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DocID028751 Rev 1
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This is information on a product in full production.
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VIPer01
Energy saving off-line high voltage converter
Datasheet - production data
Figure 1: Basic application schematic
Features
800 V avalanche-rugged power MOSFET
allowing ultra wide VAC input range to be
covered
Embedded HV startup and sense-FET
Current mode PWM controller
Drain current limit protection (OCP)
Wide supply voltage range: 4.5 V to 30 V
Self-supply option allows the auxiliary
winding or bias components to be removed
Minimized system input power consumption:
Less than 10 mW @ 230 VAC in no-load
condition
Less than 400 mW @ 230 VAC with
250 mW load
Jittered switching frequency reduces the
EMI filter cost:
30 kHz ± 7% (type X)
60 kHz ± 7% (type L)
120 kHz ± 7% (type H)
Embedded E/A with 1.2 V reference
Protections with automatic restart:
overload/short-circuit (OLP), line or output
OVP, max. duty cycle counter, VCC clamp
Pulse-skip protection to prevent
flux-runaway
Embedded thermal shutdown
Built-in soft-start for improved system
reliability
Applications
Low power SMPS for home appliances,
building and home control, small industrial,
consumers, lighting, motion control
Low power adapters
Description
The device is a high voltage converter smartly
integrating an 800 V avalanche-rugged power
MOSFET with PWM current mode control. The
power MOSFET with 800 V breakdown voltage
allows the extended input voltage range to be
applied, as well as the size of the DRAIN snubber
circuit to be reduced. This IC meets the most
stringent energy-saving standards as it has very
low consumption and operates in pulse frequency
modulation under light load. The design of
flyback, buck and buck boost converters is
supported. The integrated HV startup, sense-
FET, error amplifier and oscillator with jitter allow
a complete application to be designed with the
minimum number of components.
Contents
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DocID028751 Rev 1
Contents
1 Pin setting ........................................................................................ 5
2 Electrical and thermal ratings ........................................................ 6
2.1 Electrical characteristics .................................................................... 8
3 Typical electrical characteristics.................................................. 12
4 General description ....................................................................... 16
4.1 Block diagram ................................................................................. 16
4.2 Typical power capability .................................................................. 16
4.3 Primary MOSFET ............................................................................ 17
4.4 High voltage startup ........................................................................ 17
4.5 Soft-start ......................................................................................... 19
4.6 Oscillator ......................................................................................... 19
4.7 Pulse-skipping ................................................................................. 19
4.8 Direct feedback ............................................................................... 21
4.9 Secondary feedback ....................................................................... 21
4.10 Pulse frequency modulation ............................................................ 21
4.11 Overload protection ......................................................................... 22
4.12 Max. duty cycle counter protection .................................................. 22
4.13 VCC clamp protection ..................................................................... 23
4.14 Disable function ............................................................................... 23
4.15 Thermal shutdown ........................................................................... 25
5 Application information ................................................................ 26
5.1 Typical schematics .......................................................................... 26
5.3 Energy saving performance ............................................................ 29
5.4 Layout guidelines and design recommendations ............................ 30
6 Package information ..................................................................... 32
6.1 SSOP10 package information ......................................................... 32
7 Ordering information ..................................................................... 34
8 Revision history ............................................................................ 35
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List of tables
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List of tables
Table 1: Pin description .............................................................................................................................. 5
Table 2: Absolute maximum ratings ........................................................................................................... 6
Table 3: Thermal data ................................................................................................................................. 6
Table 4: Avalanche characteristics ............................................................................................................. 7
Table 5: Power section ............................................................................................................................... 8
Table 6: Supply section............................................................................................................................... 8
Table 7: Controller section .......................................................................................................................... 9
Table 8: Typical power .............................................................................................................................. 16
Table 9: Power supply efficiency, VOUT = 5 V ........................................................................................... 29
Table 10: SSOP10 mechanical data ......................................................................................................... 33
Table 11: Order code ................................................................................................................................ 34
Table 12: Document revision history ........................................................................................................ 35
List of figures
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List of figures
Figure 1: Basic application schematic ........................................................................................................ 1
Figure 2: Connection diagram .................................................................................................................... 5
Figure 3: RthJA/(RthJA@A=100 mm²) ............................................................................................................ 7
Figure 4: IDLIM vs TJ ................................................................................................................................... 12
Figure 5: FOSC vs TJ................................................................................................................................... 12
Figure 6: VHV_START vs TJ ........................................................................................................................... 12
Figure 7: VFB_REF vs TJ .............................................................................................................................. 12
Figure 8: Quiescent current Iq vs TJ ......................................................................................................... 12
Figure 9: Operating current ICC vs TJ ........................................................................................................ 12
Figure 10: ICH1 vs TJ .................................................................................................................................. 13
Figure 11: ICH1 vs VDRAIN ............................................................................................................................ 13
Figure 12: ICH2 vs TJ .................................................................................................................................. 13
Figure 13: ICH2 vs VDRAIN ............................................................................................................................ 13
Figure 14: ICH3 vs TJ .................................................................................................................................. 13
Figure 15: ICH3 vs VDRAIN ............................................................................................................................ 13
Figure 16: GM vs TJ ................................................................................................................................... 14
Figure 17: ICOMP vs TJ ................................................................................................................................ 14
Figure 18: RDS(on) vs TJ .............................................................................................................................. 14
Figure 19: Static drain-source on-resistance ............................................................................................ 14
Figure 20: VBVDSS vs TJ ............................................................................................................................. 14
Figure 21: Output characteristic ................................................................................................................ 14
Figure 22: SOA SSOP10 package ........................................................................................................... 15
Figure 23: Maximum avalanche energy vs TJ........................................................................................... 15
Figure 24: Block diagram .......................................................................................................................... 16
Figure 25: IC supply modes: self-supply and external supply .................................................................. 17
Figure 26: Power-ON and power-OFF ...................................................................................................... 18
Figure 27: Soft startup .............................................................................................................................. 19
Figure 28: Pulse-skipping during startup .................................................................................................. 20
Figure 29: Short-circuit condition .............................................................................................................. 22
Figure 30: Connection for input overvoltage protection (isolated or non-isolated topologies) ................. 23
Figure 31: Connection for output overvoltage protection (non-isolated topologies) ................................. 24
Figure 32: Thermal shutdown timing diagram .......................................................................................... 25
Figure 33: Flyback converter (non-isolated) ............................................................................................. 26
Figure 34: Flyback converter with line OVP (non-isolated) ...................................................................... 26
Figure 35: Flyback converter (isolated) .................................................................................................... 27
Figure 36: Primary side regulation isolated flyback converter .................................................................. 27
Figure 37: Buck converter (positive output) .............................................................................................. 28
Figure 38: Buck-boost converter (negative output) .................................................................................. 28
Figure 39: PIN versus VIN in no-load, VOUT = 5 V ....................................................................................... 29
Figure 40: PIN versus VIN in light load, VOUT = 5 V .................................................................................... 29
Figure 41: Recommended routing for flyback converter ........................................................................... 31
Figure 42: Recommended routing for buck converter .............................................................................. 31
Figure 43: SSOP10 package outline ........................................................................................................ 32
Figure 44: SSOP10 recommended footprint............................................................................................. 33
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Pin setting
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1 Pin setting
Figure 2: Connection diagram
Table 1: Pin description
SSOP10
Name
Function
1
GND
Ground and MOSFET source. Connection of source of the internal MOSFET
and the return of the bias current of the device. All groundings of bias
components must be tied to a trace going to this pin and kept separate from the
pulsed current return.
2
VCC
Controller supply. An external storage capacitor has to be connected across
this pin and GND. The pin, internally connected to the high voltage current
source, provides the VCC capacitor charging current at startup and during
steady-state operation, if the self-supply mode is selected. A small bypass
capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also
recommended, for noise filtering purpose.
3
DIS
Disable. If its voltage exceeds the internal threshold VDIS_th (1.2 V typ.) for more
than tDEB time (1 ms, typ.), the PWM is disabled in auto-restart mode. An input
overvoltage protection can be built by connecting a voltage divider between DIS
pin and the rectified mains. In case of non-isolated topologies, with the same
principle an output overvoltage protection can be implemented. If the disable
function is not required, DIS pin must be soldered to GND, which excludes the
function.
4
FB
Direct feedback. It is the inverting input of the internal transconductance E/A,
which is internally referenced to 1.2 V with respect to GND. In case of non-
isolated converter, the output voltage information is directly fed into the pin
through a voltage divider. In case of primary regulation, the FB voltage divider is
connected to the VCC. The E/A is disabled soldering FB to GND.
5
COMP
Compensation. It is the output of the internal E/A. A compensation network is
placed between this pin and GND to achieve stability and good dynamic
performance of the control loop. In case of secondary feedback, the internal E/A
must be disabled and the COMP directly driven by the optocoupler to control the
DRAIN peak current setpoint.
6 to 10
DRAIN
MOSFET drain. The internal high voltage current source sinks current from this
pin to charge the VCC capacitor at startup and during steady-state operation.
These pins are mechanically connected to the internal metal PAD of the
MOSFET in order to facilitate heat dissipation. On the PCB, copper area must
be placed under these pins in order to decrease the total junction-to-ambient
thermal resistance thus facilitating the power dissipation.
Electrical and thermal ratings
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DocID028751 Rev 1
2 Electrical and thermal ratings
Table 2: Absolute maximum ratings
Symbol
Pin
Parameter (1)(2)
Min.
Max.
Unit
VDS
6 to 10
Drain-to-source (ground) voltage
-0.3
800
V
IDRAIN
6 to 10
Pulsed drain current (pulse-width limited by
SOA)
2
A
VCC
2
VCC voltage
-0.3
Internally
limited
V
ICC
2
VCC internal Zener current (pulsed)
45 (3)
mA
VDIS
3
DIS voltage
-0.3
4.25 (4)
V
VFB
4
FB voltage
-0.3
4.25 (4)
V
VCOMP
5
COMP voltage
-0.3
5.25 (4)
V
PTOT
Power dissipation @ Tamb < 50 °C
1 (5)
W
TJ
Junction temperature operating range
-40
150
°C
TSTG
Storage temperature
-55
150
°C
Notes:
(1)Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
(2)Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.
(3) Pulse-width limited by maximum power dissipation, PTOT.
(4) The AMR value is intended when VCC ≥ 5 V, otherwise the value VCC + 0.3 V has to be considered.
(5) When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 μm thick).
Table 3: Thermal data
Symbol
Parameter
Max. value
Unit
SSOP10
RthJP
Thermal resistance junction-pin
35
°C/W
RthJA(1)
Thermal resistance junction-ambient (dissipated power 1 W)
145
Thermal resistance junction-ambient (dissipated power 1 W) (2)
90
Notes:
(1)Derived by characterization.
(2)When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 µm thick).
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Electrical and thermal ratings
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Figure 3: RthJA/(RthJA@A=100 mm²)
Table 4: Avalanche characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IAR
Avalanche current
Repetitive and non-repetitive
Pulse-width limited by TJmax
0.8
A
EAS
Single pulse avalanche
energy (1)
L = 1 mH
IAS = 0.8 A
VDS = 50 V
RG = 47 Ω
Starting TJ = 25 °C
1
mJ
Notes:
(1)Parameter derived by characterization.
Electrical and thermal ratings
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DocID028751 Rev 1
2.1 Electrical characteristics
Tj = -40 to 125 °C, VCC = 9 V (unless otherwise specified).
Table 5: Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VBVDSS
Breakdown voltage
IDRAIN = 1 mA
VCOMP = GND
TJ = 25 °C
800
V
IDSS
Drain-source leakage
current
VDS = 400 V
VCOMP = GND
TJ = 25 °C
1
µA
IOFF
OFF-state drain current
VDRAIN = max.
rating
VCOMP = GND
TJ = 25 °C
45
RDS(on)
Static drain-source
ON-resistance
IDRAIN = 360 mA
TJ = 25 °C
30
Ω
IDRAIN = 360 mA
TJ = 125 °C
60
COSS EQ
Equivalent output
capacitance
VGS = 0
VDS = 0 to 640 V
TJ = 25 °C
10
pF
Table 6: Supply section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
High voltage start-up current source
VBVDSS_SU
Breakdown voltage of
start-up MOSFET
TJ = 25 °C
800
V
VHV_START
Drain-source start-up
voltage
18
V
RG
Start-up resistor
VFB > VFB_REF
VDRAIN = 400 V
VDRAIN = 600 V
22
30
38
MΩ
ICH1
VCC charging current at
startup
VDRAIN = 100 V
VCC = 0 V
1.4
1.9
2.4
mA
ICH2
VCC charging current at
startup
VFB > VFB_REF
VDRAIN = 100 V
VCC = 6 V
3.5
4.5
5.5
ICH3(1)
Max. VCC charging
current in self-supply
VFB > VFB_REF
VDRAIN =100 V
VCC = 6 V
7.6
8.8
10
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IC supply and consumptions
VCC
Operating voltage range
VGND = 0 V
4.5
30
V
VCCclamp
Clamp voltage
ICC = Iclamp_max
30
32.5
35
V
Iclamp max
Clamp shutdown current
(2)
30
mA
tclamp max
Clamp time before
shutdown
325
500
675
µs
VCCon
VCC start-up threshold
VFB = 1.2 V
VDRAIN = 400 V
7.5
8
8.5
V
VCSon
HV current source
turn-on threshold
VCC falling
4
4.25
4.5
V
VCCoff
UVLO
VFB = 1.2 V
VDRAIN = 400 V
3.75
4
4.25
V
Iq
Quiescent current
Not switching
VFB > VFB_REF
0.3
0.45
mA
ICC
Operating supply
current, switching
VDS = 150 V
VCOMP = 1.2 V
FOSC = 30 kHz
0.75
1.1
mA
VDS = 150 V
VCOMP = 1.2 V
FOSC = 60 kHz
0.85
1.25
VDS = 150 V
VCOMP = 1.2 V
FOSC = 120 kHz
1
1.5
Notes:
(1)Current supplied during the main MOSFET OFF time only.
(2) Parameter assured by design and characterization.
Table 7: Controller section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
E/A
VFB_REF
Reference voltage
1.175
1.2
1.225
V
VFB_DIS
E/A disable voltage
150
180
210
mV
IFB PULL UP
Pull-up current
0.9
1
1.1
µA
GM
Transconductance
VCOMP = 1.5 V
VFB > VFB_REF
350
500
650
µA/V
ICOMP1
Max. source current
VCOMP = 1.5 V
VFB = 0.5 V
65
100
135
µA
ICOMP2
Max. sink current
VFB = 2 V
VCOMP = 1.5 V
70
105
140
µA
RCOMP(DYN)
Dynamic resistance
VCOMP = 2.7 V
VFB = GND
50
58
66
kΩ
VCOMPH
Current limitation
threshold
3
V
VCOMPL
PFM threshold
0.8
V
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DocID028751 Rev 1
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
OLP and timing
IDLIM
Drain current limitation
TJ = 25 °C
VIPer011*
114
120
126
mA
TJ = 25 °C
VIPer012*
228
240
252
TJ = 25 °C
VIPer013*
342
360
378
I2f
Power coefficient
IDLIM_TYP2x
FOSC_TYP
0.9 ·I2f
I2f
1.1 ·I2f
A2·kHz
IDLIM_PFM
Drain current limitation at
light load
TJ = 25 °C
VCOMP = VCOMPL(1)
VIPer011*
23
35
47
mA
TJ = 25 °C
VCOMP = VCOMPL(1)
VIPer012*
45
65
85
TJ = 25 °C
VCOMP = VCOMPL(1)
VIPer013*
60
80
100
VDISth
Disable threshold voltage
VCC = 9 V
VCOMP = 1 V
VFB = VFB_REF
1.15
1.2
1.25
V
tDIS
Debounce time before
DIS protection tripping
0.65
1
1.35
ms
tDIS_RESTART
Restart time after DIS
protection tripping
325
500
675
ms
tOVL
Overload delay time
45
50
55
ms
tOVL_MAX
Max. overload delay time
VIPer01*X
FOSC = FOSC MIN
90
100
110
ms
VIPer01*L
FOSC = FOSC MIN
180
200
220
VIPer01*H
FOSC = FOSC MIN
360
400
440
tSS
Soft-start time
5
8
11
ms
tON_MIN
Minimum turn-on time
VCC = 9 V
VCOMP = 1 V
VFB = VFB_REF
250
360
ns
tRESTART
Restart time after fault
0.65
1
1.35
s
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Electrical and thermal ratings
DocID028751 Rev 1
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Oscillator
FOSC
Switching frequency
TJ = 25 °C
VIPer01*X
27
30
33
kHz
TJ = 25 °C
VIPer01*L
54
60
66
TJ = 25 °C
VIPer01*H
108
120
132
FOSC_MIN
Minimum switching
frequency
TJ = 25 °C (2)
13.5
15
16.5
kHz
FD
Modulation depth
(3)
±7
FOSC
%
FM
Modulation frequency
(3)
260
Hz
DMAX
Max. duty cycle
(3)
70
80
%
Thermal shutdown
TSD
Thermal shutdown
temperature
(3)
150
160
°C
Notes:
(1) See Section 5.10: "Pulse frequency modulation".
(2) See Section 5.7: "Pulse-skipping".
(3) Parameter assured by design and characterization.
Typical electrical characteristics
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3 Typical electrical characteristics
Figure 4: IDLIM vs TJ
Figure 5: FOSC vs TJ
Figure 6: VHV_START vs TJ
Figure 7: VFB_REF vs TJ
Figure 8: Quiescent current Iq vs TJ
Figure 9: Operating current ICC vs TJ
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Typical electrical characteristics
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Figure 10: ICH1 vs TJ
Figure 11: ICH1 vs VDRAIN
Figure 12: ICH2 vs TJ
Figure 13: ICH2 vs VDRAIN
Figure 14: ICH3 vs TJ
Figure 15: ICH3 vs VDRAIN
Typical electrical characteristics
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Figure 16: GM vs TJ
Figure 17: ICOMP vs TJ
Figure 18: RDS(on) vs TJ
Figure 19: Static drain-source on-resistance
Figure 20: VBVDSS vs TJ
Figure 21: Output characteristic
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Typical electrical characteristics
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Figure 22: SOA SSOP10 package
* When mounted on a standard single side FR4 board
with 50 mm2 (0.077 sq in) of Cu (35 μm thick).
Figure 23: Maximum avalanche energy vs TJ
General description
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4 General description
4.1 Block diagram
Figure 24: Block diagram
4.2 Typical power capability
Table 8: Typical power
Vin: 230 VAC
Vin: 85-265 VAC
Adapter (1)
Open frame (2)
Adapter (1)
Open frame (2)
7 W
8 W
4 W
4.5 W
Notes:
(1) Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
(2) Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat-sinking.
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General description
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4.3 Primary MOSFET
The primary switch is implemented with an avalanche-rugged N-channel MOSFET with
minimum breakdown voltage 800 V, VBVDSS, and maximum on-resistance of 30 Ω, RDS(on).
The sense-FET is embedded and it allows a virtually lossless current sensing. The
MOSFET is embedded and it allows the HV voltage start-up operation.
The MOSFET gate driver controls the gate current during both turn-on and turn-off in order
to minimize EMI. Under UVLO conditions the embedded pull-down circuit holds the gate
low in order to ensure that the MOSFET cannot be turned on accidentally.
4.4 High voltage startup
The embedded high voltage startup includes both the 800 V start-up FET, whose gate is
biased through the resistor RG, and the switchable HV current source, delivering the current
IHV. The major portion of IHV, (ICH), charges the capacitor connected to VCC. A minor
portion is sunk by the controller block.
At startup, as the voltage across the DRAIN pin exceeds the VHV_START threshold, the HV
current source is turned on, charging linearly the CS capacitor. At the very beginning of the
startup, when Cs is fully discharged, the charging current is low, ICH1, in order to avoid IC
damaging in case VCC is accidentally shorted to GND. As VCC exceeds 1 V, ICH is increased
to ICH2 in order to speed up the charging of CS.
As VCC reaches the start-up threshold VCCon (8 V typ.) the chip starts operating, the primary
MOSFET is enabled to switch, the HV current source is disabled and the device is powered
by the energy stored in the CS capacitor.
In steady-state the IC supports two different kind of supplies: self-supply and external
supply, as shown in Figure 25: "IC supply modes: self-supply and external supply".
Figure 25: IC supply modes: self-supply and external supply
In self-supply only one capacitor CS is connected to the VCC and the device is supplied by
the energy stored in CS. After the IC startup, due to its internal consumption, the VCC
decays to VCCson (4.25 V, typ.) and the HV current source is turned on delivering the current
ICH3 until VCC is recharged to VCCon. The HV current source is reactivated when VCC decays
to VCCson again. The ICH3 is supplied during the switching OFF time only. In external supply
the HV current source is always kept off by maintaining the VCC above VCSon. This can be
GIPD160720151024MT
ICH
VCC
Self-supply External supply
from the output from auxiliary winding
VOUT
ICH VCC ICH VCC
VAux
CSCSCS
General description
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obtained through a transformer auxiliary winding or a connection from the output, the latter
in case of non-isolated topology only. In this case the residual consumption is given by the
power dissipated on RG, calculated as follows:
At the nominal input voltage, 230 VAC, the typical consumption (RG = 30 MΩ) is 3.5 mW and
the worst-case consumption (RG = 22 MΩ) is 4.8 mW.
When the IC is disconnected from the mains, or there is a mains interruption, for some time
the converter keeps on working, powered by the energy stored in the input bulk capacitor.
When it is discharged below a critical value, the converter is no longer able to keep the
output voltage regulated. During the power down, when the DRAIN voltage becomes too
low, the HV current source (IHV) remains off and the IC is stopped as soon as the VCC drops
below the UVLO threshold, VCCoff.
Figure 26: Power-ON and power-OFF
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General description
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4.5 Soft-start
The internal soft-start function of the device progressively increases the cycle-by-cycle
current limitation set point from zero up to IDLIM in 8 steps. The soft-start time, tSS, is
internally set at 8 ms. This function is activated at any attempt of converter startup and at
any restart after a fault event. The feature protects the system at the startup when the
output load occurs like a short-circuit and the converter works at its maximum drain current
limitation.
Figure 27: Soft startup
4.6 Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is
modulated by approximately ± 7% kHz FOSC at 260 Hz rate. The purpose of the jittering is
to get a spread-spectrum action that distributes the energy of each harmonic of the
switching frequency over a number of frequency bands, having the same energy on the
whole but smaller amplitudes. This helps to reduce the conducted emissions, especially
when measured with the average detection method or, which is the same, to pass the EMI
tests with an input filter of smaller size than that needed in absence of jittering feature.
Three options with different switching frequencies, FOSC, are available: 30 (X type), 60 (L
type) and 120 kHz (H type).
4.7 Pulse-skipping
The IC embeds a pulse-skip circuit that operates in the following ways:
each time the DRAIN peak current exceeds IDLIM level within tON_MIN, the switching
cycle is skipped. The cycles can be skipped until the minimum switching frequency is
reached, FOSC_MIN (15 kHz).
each time the DRAIN peak current does not exceed IDLIM within tON_MIN, a switching
cycle is restored. The cycles can be restored until the nominal switching frequency is
reached, FOSC (30 or 60 or 120 kHz).
General description
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If the converter is operated at FOSC_MIN, the IC is turned off after the time tOVL_MAX (100 ms or
200 ms or 400 ms typ., depending on FOSC) and then automatically restarted with soft-start
phase, after the time tRESTART (1 s, typ.).
The protection is intended to avoid the so called "flux-runaway" condition often present at
converter startup and due to the fact that the primary MOSFET, which is turned on by the
internal oscillator, cannot be turned off before than the minimum on-time.
During the on-time, the inductor is charged by the input voltage and if it cannot be
discharged by the same amount during the off-time, in every switching cycle there is an
increase of the average inductor current, that can reach dangerously high values until the
output capacitor is not charged enough to ensure the inductor discharge rate needed for
the volt-second balance. This condition may happen at converter startup, because of the
low output voltage.
In the following Figure 28: "Pulse-skipping during startup" the effect of pulse-skipping
feature on the DRAIN peak current shape is shown (solid line), compared with the DRAIN
peak current shape when pulse-skipping feature is not implemented (dashed line).
Providing more time for cycle-by-cycle inductor discharge when needed, this feature is
effective by keeping low the maximum DRAIN peak current avoiding the flux-runaway
condition.
Figure 28: Pulse-skipping during startup
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4.8 Direct feedback
The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground
reference and output are FB and COMP, respectively. The internal reference voltage of the
E/A is VFB_REF (1.2 V typical value referred to GND). In non-isolated topologies this tightly
regulates positive output voltages through a simple voltage divider applied to the output
voltage terminal, FB and GND.
The E/A output is scaled down and fed into the PWM comparator, where it is compared to
the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by-
cycle drain current limitation.
An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the
overall control loop.
The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is
accidentally left floating.
The E/A is disabled if the FB voltage is lower than VFB_DIS (200 mV, typ.).
4.9 Secondary feedback
When a secondary feedback is required, the internal E/A has to be disabled shorting FB to
GND (VFB < VFB_DIS). With this setting, COMP is internally connected to a pre-regulated
voltage through the pull-up resistor RCOMP(DYN), (60 kΩ, typ.) and the voltage across COMP
is set by the current sunk.
This allows the output voltage value to be set through an external error amplifier (TL431 or
similar) placed on the secondary side, whose error signal is used to set the DRAIN peak
current setpoint corresponding to the output power demand. If isolation is required, the
error signal must be transferred through an optocoupler, with the phototransistor collector
connected across COMP and GND.
4.10 Pulse frequency modulation
If the output load is decreased, the feedback loop reacts lowering the VCOMP voltage, which
reduces the DRAIN peak current setpoint, down to the minimum value of IDLIM_PFM when the
VCOMPL threshold is reached.
If the load is furtherly decreased, the DRAIN peak current value is maintained at IDLIM_PFM
and some PWM cycles are skipped. This kind of operation is referred to as “pulse
frequency modulation” (PFM), the number of the skipped cycles depends on the balance
between the output power demand and the power transferred from the input. The result is
an equivalent switching frequency which can go down to some hundreds Hz, thus reducing
all the frequency-related losses.
This kind of operation, together with the extremely low IC quiescent current, allows very low
input power consumption in no-load and light load, while the low DRAIN peak current
value, IDLIM_PFM, prevents any audible noise which could arise from low switching frequency
values. When the load is increased, VCOMP increases and PFM is exited. VCOMP reaches its
maximum at VCOMPH and corresponding to that value, the DRAIN current limitation (IDLIM) is
reached.
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4.11 Overload protection
To manage the overload condition, the IC embeds the following main blocks: the OCP
comparator to turn off the power MOSFET when the drain current reaches its limit (IDLIM) ,
the up and down OCP counter to define the turn-off delay time in case of continuous
overload (tOVL = 50 ms typ.) and the timer to define the restart time after protection tripping
(tRESTART = 1 s typ.).
In case of short-circuit or overload, the control level on the inverting input of the PWM
comparator is greater than the reference level fed into the inverting input of the OCP
comparator. As a result, the cycle-by-cycle turn-off of the power switch is triggered by the
OCP comparator instead of PWM comparator. Every cycle where this condition is met, the
OCP counter is incremented and if the fault condition lasts longer than tOVL (corresponding
to the counter end-of-count), the protection is tripped, the PWM is disabled for tRESTART,
then it resumes switching with soft-start and, if the fault is still present, it is disabled again
after tOVL. The OLP management prevents IC from operating indefinitely at IDLIM and the low
repetition rate of the restart attempts of the converter avoids IC overheating in case of
repeated fault events.
After the fault removal, the IC resumes working normally. If the fault is removed earlier than
the protection tripping (before tOVL), the tOVL-counter is decremented on a cycle-by-cycle
basis down to zero and the protection is not tripped. If the fault is removed during tRESTART,
the IC waits for the tRESTART period has elapsed before resuming switching.
In fault condition the VCC ranges between VCSon and VCCon levels, due to the periodical
activation of the HV current source recharging the VCC capacitor.
Figure 29: Short-circuit condition
4.12 Max. duty cycle counter protection
The IC embeds a max. duty cycle counter, which disables the PWM if the MOSFET is
turned off by max. duty cycle (70% min., 80% max.) for ten consecutive switching cycles.
After protection tripping, the PWM is stopped for tRESTART and then activated again with soft-
start phase until the fault condition is removed.
In some cases (i.e. breaking of the loop) even if VCOMP is saturated high, the OLP cannot be
triggered because at every switching cycle the PWM is turned off by maximum duty cycle
before than DRAIN peak current reaches the IDLIM setpoint. As a result, the output voltage
VOUT can increase without control by keeping a value much higher than the nominal one
with the risk for the output capacitor, the output diode and the IC itself. The max. duty cycle
counter protection avoids this kind of failures.
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4.13 VCC clamp protection
This protection can occur when the IC is supplied by auxiliary winding or diode from the
output voltage, when an output overvoltage produces an increase of VCC.
If VCC reaches the clamp level VCCclamp (30 V, min. referred to GND) the current injected
into the pin is monitored and if it exceeds the internal threshold Iclamp_max (30 mA, typ.) for
more than tclamp_max (500 µs, typ.), the PWM is disabled for tRESTART (1 s, typ.) and then
activated again in soft-start phase. The protection is disabled during the soft-start time.
4.14 Disable function
When the voltage across the pin is externally pulled above VDIS_th (1.2 V typ.) for more than
tDEB (for instance by a voltage divider connected to some higher voltages), the PWM is
disabled. If the voltage divider on the DIS pin is connected to the rectified mains, as shown
in Figure 30: "Connection for input overvoltage protection (isolated or non-isolated
topologies)", an input overvoltage protection can be built.
Figure 30: Connection for input overvoltage protection (isolated or non-isolated topologies)
In case of non-isolated topologies, by following the same principle an output overvoltage
protection can be built, as shown in Figure 31: "Connection for output overvoltage
protection (non-isolated topologies)".
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Figure 31: Connection for output overvoltage protection (non-isolated topologies)
If VOVP is the desired input/output overvoltage threshold, the resistors RH and RL of the
voltage divider are to be selected according to the following formula:
The power dissipation associated to the DIS network is:
in case of connection for the input overvoltage detection and
in case of connection for the output overvoltage detection.
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4.15 Thermal shutdown
If the junction temperature becomes higher than the internal threshold TSD (160 °C, typ.),
the PWM is disabled. After tRESTART time, a single switching cycle is performed, during
which the temperature sensor embedded in the power MOSFET section is checked. If a
junction temperature above TSD is still measured, the PWM is maintained disabled for
tRESTART time, otherwise it resumes switching with soft-start phase.
During tRESTART VCC is maintained between VCSon and VCCon levels by the HV current source
periodical activation. Such a behavior is summarized in below figure:
Figure 32: Thermal shutdown timing diagram
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5 Application information
5.1 Typical schematics
Figure 33: Flyback converter (non-isolated)
Figure 34: Flyback converter with line OVP (non-isolated)
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Figure 35: Flyback converter (isolated)
Figure 36: Primary side regulation isolated flyback converter
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Figure 37: Buck converter (positive output)
Figure 38: Buck-boost converter (negative output)
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5.3 Energy saving performance
The device allows designing applications to be compliant with the most stringent energy
saving regulations. In order to show the typical performance is achievable, the active mode
average efficiency and the efficiency at 10% of the rated output power of a single output
flyback converter have been measured and are reported in Table 9: "Power supply
efficiency, VOUT = 5 V". In addition, no-load and light load consumptions are shown in
Figure 39: "PIN versus VIN in no-load, VOUT = 5 V" and Figure 40: "PIN versus VIN in light
load, VOUT = 5 V".
Table 9: Power supply efficiency, VOUT = 5 V
VIN
10 % output load
efficiency [%]
Active mode average
efficiency [%]
Pin @ no-load [mW]
115 VAC
72.2
74.6
4.5
230 VAC
65.1
75.1
8.6
Figure 39: PIN versus VIN in no-load, VOUT = 5 V
Figure 40: PIN versus VIN in light load, VOUT = 5 V
Application information
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5.4 Layout guidelines and design recommendations
A proper printed circuit board layout ensures the correct operation of any switch-mode
converter and this is true for the VIPer as well. The main reasons to have a proper PCB
layout are:
Providing clean signals to the IC, ensuring good immunity against external and
switching noises.
Reducing the electromagnetic interferences, both radiated and conducted, to pass the
EMC tests more easily.
If the VIPer is used to design a SMPS, the following basic rules should be considered:
Separating signal from power tracks. Generally, traces carrying signal currents
should run far from others carrying pulsed currents or with fast swinging voltages.
Signal ground traces should be connected to the IC signal ground, GND, using a
single "star point", placed close to the IC. Power ground traces should be connected
to the IC power ground, GND. The compensation network should be connected to the
COMP, maintaining the trace to GND as short as possible. In case of two-layer PCB, it
is a good practice to route signal traces on one PCB side and power traces on the
other side.
Filtering sensitive pins. Some crucial points of the circuit need or may need filtering.
A small high-frequency bypass capacitor to GND might be useful to get a clean bias
voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A
low ESL ceramic capacitor (a few hundreds pF up to 0.1 μF) should be connected
across VCC and GND, placed as close as possible to the IC. With flyback topologies,
when the auxiliary winding is used, it is suggested to connect the VCC capacitor on
the auxiliary return and then to the main GND using a single track.
Keeping power loops as confined as possible. The area circumscribed by current
loops where high pulsed current flow should be minimized to reduce its parasitic self-
inductance and the radiated electromagnetic field. As a consequence, the
electromagnetic interferences produced by the power supply during the switching are
highly reduced. In a flyback converter the most critical loops are: the one including the
input bulk capacitor, the power switch, the power transformer, the one including the
snubber, the one including the secondary winding, the output rectifier and the output
capacitor. In a buck converter the most critical loop is the one including the input bulk
capacitor, the power switch, the power inductor, the output capacitor and the free-
wheeling diode.
Reducing line lengths. Any wire acts as an antenna. With the very short rise times
exhibited by EFT pulses, any antenna can receive high voltage spikes. By reducing
line lengths, the level of received radiated energy is reduced, and the resulting spikes
from electrostatic discharges are lower. This also keeps both resistive and inductive
effects to a minimum. In particular, all traces carrying high currents, especially if
pulsed (tracks of the power loops) should be as short and wide as possible.
Optimizing track routing. As levels of pickup from static discharges are likely greater
near the edges of the board, it is wise to keep any sensitive lines away from these
areas. Input and output lines often need to reach the PCB edge at some stage, but
they can be routed away from the edge as soon as possible where applicable. Since
vias are to be considered inductive elements, it is recommended to minimize their
number in the signal path and avoid them in the power path.
Improving thermal dissipation. An adequate copper area has to be provided under
the DRAIN pins as heatsink, while it is not recommended to place large copper areas
on the GND.
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Figure 41: Recommended routing for flyback converter
Figure 42: Recommended routing for buck converter
Package information
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6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1 SSOP10 package information
Figure 43: SSOP10 package outline
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Table 10: SSOP10 mechanical data
Dim.
mm
Min.
Typ.
Max.
A
1.75
A1
0.10
0.25
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
4.80
4.90
5
E
5.80
6
6.20
E1
3.80
3.90
4
e
1
h
0.25
0.50
L
0.40
0.90
K
0°
8°
Figure 44: SSOP10 recommended footprint
Ordering information
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7 Ordering information
Table 11: Order code
Order code
IDLIM (OCP)
FOSC ± jitter
Package
VIPer011XS(TR)
120 mA
30 kHz ± 7%
SSOP10 tube (tape and reel)
VIPer012XS(TR)
240 mA
VIPer013XS(TR)
360 mA
VIPer011LS(TR)
120 mA
60 kHz ± 7%
VIPer012LS(TR)
240 mA
VIPer013LS(TR)
360 mA
VIPer012HS(TR)
240 mA
120 kHz ± 7%
VIPer013HS(TR)
360 mA
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8 Revision history
Table 12: Document revision history
Date
Revision
Changes
09-Mar-2016
1
Initial release
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