DM93S62 9-Input Parity Checker/Generator October 1988 Revised May 2000 DM93S62 9-Input Parity Checker/Generator General Description The DM93S62 is a very high speed 9-input parity checker/ generator for use in error detection and error correction applications. The DM93S62 provides odd and even parity for up to nine data bits. The even parity output (PE) is HIGH if an even number of inputs are HIGH and E is LOW. The odd parity output (PO) will be HIGH if an odd number of inputs are HIGH and E is LOW. A HIGH level on the Enable (E) input forces both outputs LOW. Ordering Code: Order Number Package Number DM93S62N N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol Connection Diagram VCC = Pin 14 GND = Pin 7 Pin Descriptions Pin Name I0-I8 E Truth Table (E = LOW) Description Data Inputs Number of Inputs Output Enable (Active LOW) Outputs I0-I8 that are HIGH PO PE PO Odd Parity Output 1, 3, 5, 7, 9 H L PE Even Parity Output 0, 2, 4, 6, 8 L H H = HIGH Voltage Level L = LOW Voltage Level (c) 2000 Fairchild Semiconductor Corporation DS009809 www.fairchildsemi.com DM93S62 Functional Description I0-I7 represent one section which will generate a parity bit in 16 ns to 20 ns. The ninth input (I8) bypasses three levels of logic and switches the outputs in 6.0 ns to 9.0 ns. This feature may be used to compensate for delayed arrival of the parity bit, allowing faster system cycle times (Figure 1). The fast I8 input is also useful when more than nine bits are to be checked. The output of one DM93S62 drives the I8 input of a second DM93S62, providing a 17-bit parity check in 29 ns (typ). The DM93S62 is a very high speed 9-input parity checker or generator. It is intended primarily for error detection in systems which transmit data in 8-bit bytes, but it can be expanded to any number of data inputs. Both even and odd parity outputs are available to allow maximum flexibility for both parity generation and parity checking. When the device is enabled (E = LOW), the Even Parity output (PE) is HIGH when an even number of inputs is HIGH, and the Odd Parity output (PO) is HIGH when an odd number of inputs is HIGH. The active LOW Enable (E) controls the state of both outputs; when the Enable (E) is HIGH, both outputs will be LOW. The Enable may be used to strobe the outputs at very high speeds to synchronize or inhibit the parity data. When some inputs of the DM93S62 are not used, such as for words of less than nine bits or when using parallel expansion techniques, there is an optimum delay scheme for termination of the unused inputs (see Table 1). In essence, if one of the inputs of any Exclusive-NOR stays HIGH, the delay from the other input to the output is minimized. The DM93S62 has been designed with two sections using Exclusive-NOR comparison techniques. Eight data inputs TABLE 1. Termination Recommendations for Less than Nine Bits Number of I0 I1 I2 I3 I4 I5 I6 I7 I8 3 D0 L D1 L D2 L L L L 4 D0 L D1 L D2 L D3 L L 5 D0 L D1 L D2 L D3 L D4 6 D0 D1 D2 D3 D4 L D5 L L 7 D0 D1 D2 D3 D4 L D5 L D6 8 D0 D1 D2 D3 D4 D5 D6 D7 L Data Inputs FIGURE 1. Fast Input I8 allows Higher System Speed www.fairchildsemi.com 2 DM93S62 Logic Diagram 3 www.fairchildsemi.com DM93S62 Absolute Maximum Ratings(Note 1) Supply Voltage Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0C to +70C Operating Free Air Temperature Range -65C to +150C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current -1 mA IOL LOW Level Output Current 20 mA TA Free Air Operating Temperature 70 C V 2 V 0 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = -18 mA VOH HIGH Level VCC = Min, IOH = Max VOL Output Voltage VIL = Max LOW Level Output VCC = Min, IOL = Max Min 2.7 Typ (Note 2) Max Units -1.2 V 3.4 0.35 V 0.5 V 1 mA 50 A Voltage VIH = Min II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V IIH HIGH Level Input Current VCC = Max, VI = 2.7V IIL LOW Level Input Current VCC = Max, VI = 0.5V, I0-I8 -1.6 VCC = Max, VI = 0.5V, E Only -3.2 IOS Short Circuit Output Current VCC = Max (Note 3) ICC Supply Current VCC = Max -40 mA -100 mA 65 mA Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC = +5.0V, TA = +25C Symbol CL = 15 pF Parameter Min Max tPLH Propagation Delay 26 tPHL I0-I7 to PE 22 tPLH Propagation Delay 12 tPHL I8 to PE 9.0 tPLH Propagation Delay 26 tPHL I0-I7 to PO 26 13 tPLH Propagation Delay tPHL I8 to PO 13 tPLH Propagation Delay 7.0 tPHL E to PE 7.0 tPLH Propagation Delay 7.0 tPHL E to PO 7.0 www.fairchildsemi.com 4 Units ns ns ns ns ns ns DM93S62 9-Input Parity Checker/Generator Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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