DM93S62 - Fairchild Semiconductor

October 1988

Revised May 2000

DM93S62 9-Input Parity Checker/Generator

DM93S62

9-Input Parity Checker/Generator

General Description

The DM 93S62 is a ve ry high speed 9 -input parity ch ecker/

generator for use in error detection and error correction

applications. The DM93S62 provides odd and even parity

for up to nine data bits. The even parity output (PE) is

HIGH if an even num be r of input s are HIGH and E is LOW.

The odd parity o utput (PO) will be HIG H if an odd numb er

of inputs are HIGH and E is LOW. A HIGH level on the

Enable (E) input forces both outputs LOW.

Ordering Code:

Logic Symbol

VCC = Pin 14

GND = Pin 7

Connection Diagram

Pin Descriptions Truth Table

(E = LOW)

H = HIGH Voltage Level

L = LOW Voltage Level

Order Number Package Number Package Description

DM93S62N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Name Description

I0–I8 Data Inputs

EOutput Enable (Active LOW)

PO Odd Parity Outp ut

PE Even Parity Outpu t

Num be r of Inp u ts Outpu ts

I0–I8 that are HIGH PO PE

1, 3, 5, 7, 9 H L

0, 2, 4, 6, 8 L H

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DM93S62

Functional Description

The DM9 3S62 is a very h igh speed 9-input parity ch ecker

or generator. It is intended primarily for error detection in

systems which transmit data in 8-bit bytes, but it can be

expanded to any number of data inputs. Both even and odd

parity outp uts are availa ble to allow maximu m flexibilit y for

both parity generation and parity checking. When the

device i s enabled (E = LO W), the Even Par ity output (PE )

is HIG H when an even number of in puts is HI GH, and the

Odd Parity output (PO) is HIGH when an odd number of

inputs is HIGH. The active LOW Enable (E) controls the

state of both outputs; when the Enable (E) is HIGH, both

outputs will be LOW . The Enable may be used to strobe the

outputs at very high speeds to synchronize or inhibit the

parity data.

The DM93S62 has been designed with two sections using

Exclusive-NOR comparison techniques. Eight data inputs

I0–I7 represent one se ction which will generate a p arity bit

in 16 ns to 20 ns. The ninth input (I8) bypasses three levels

of logic and switches the outputs in 6.0 ns to 9. 0 ns. This

feature may be used to compe nsate for delayed arrival of

the parity bit, a llowing faste r system cycle times (Figure 1).

The fast I8 input is also useful when more than nine bits

are to b e checke d. Th e outp ut of o ne D M93S62 drives the

I8 input of a second DM93S62, providing a 17-bit parity

check in 29 ns (typ).

When som e inputs of the DM93 S62 are not us ed, such as

for words of less than nine bits or when using parallel

expansion techniques, there is an optimum delay scheme

for termination of the unused inputs (see Table 1). In

essence, if one of the inputs of any Exclusive-NOR stays

HIGH, the d elay from the other input to the output is mini -

mized.

TABLE 1. Termination Recommendations for Less than Nine Bits

FIGURE 1. Fast Input I8 allows Higher System Speed

Number of I0 I1 I2 I3 I4 I5 I6 I7 I8

Data Inputs

3 D0LD1LD2L L L L

4 D0LD1LD2LD3L L

5 D0LD1LD2LD3LD4

6 D0D1D2D3D4 L D5 L L

7 D0D1D2D3D4 L D5 L D6

8 D0D1D2D3D4D5D6D7 L

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DM93S62

Logic Diagram

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DM93S62

Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typical s are at VCC = 5V, TA = 25°C.

Note 3: Not more tha n one out put shoul d be shorte d at a t im e, and the duration sh ould not ex c eed one s ec ond.

Switching Characteri stics

VCC = +5.0V, TA = +25°C

Supply Voltage 7V

Input Voltag e 5.5 V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −1mA

IOL LOW Level Output Current 20 mA

TAFree Air Ope rat ing Temper atu re 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.2 V

VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V

Output Voltage VIL = Max

VOL LOW Level Output VCC = Min, IOL = Max 0.35 0.5 V

Voltage VIH = Min

IIInput Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 50 µA

IIL LOW Level Input Current VCC = Max, VI = 0.5V, I0–I8 −1.6 mA

VCC = Max, VI = 0.5V, E Only −3.2

IOS Short Circuit Output Current VCC = Max (Note 3) −40 −100 mA

ICC Supply Current VCC = Max 65 mA

Symbol Parameter CL = 15 pF Units

Min Max

tPLH Propagation Delay 26 ns

tPHL I0–I7 to PE 22

tPLH Propagation Delay 12 ns

tPHL I8 to PE 9.0

tPLH Propagation Delay 26 ns

tPHL I0–I7 to PO 26

tPLH Propagation Delay 13 ns

tPHL I8 to PO 13

tPLH Propagation Delay 7.0 ns

tPHL E to PE 7.0

tPLH Propagation Delay 7.0 ns

tPHL E to PO 7.0

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DM93S62 9-Input Parity Checker/Generator

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

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sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.