W83320G Nuvoton N-Channel FET Synchronous Buck Regulator Controller W83320G W83320G W83320G Data Sheet Revision History VERSION PAGES DATES VERSION 1 N.A. N.A. 0.50 N.A. All version before 0.5 are for internal use only. 2 N.A. N.A. 0.51 N.A. Add Pb-free part no :W83320G 3 9,10. Oct./05 0.52 N.A. To modify the application circuit. 4. N.A Oct./06 1.0 1.0 2. All versions before 1.0 are preliminary versions. 5. 10 Apr./08 1.1 1.1 Add Absolute Maximum Rating ON WEB MAIN CONTENTS 1.Remove non Pb-free part no:W83320S Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. -1- Publication Release Date: Apr., 2008 Revision 1.1 W83320G Table of Content1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. APPLICATIONS .......................................................................................................................... 3 4. PIN-OUT ..................................................................................................................................... 4 5. PIN DESCRIPTION..................................................................................................................... 5 6. INTERNAL BLOCK DIAGRAM ................................................................................................... 6 7. APPLICATION CIRCUIT............................................................................................................. 8 8. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 10 9. ELECTRICAL CHARACTERISTICS......................................................................................... 11 10. TYPICAL PERFORMANCE CHARACTERISTICS................................................................... 12 11. PACKAGE DIMENSION OUTLINE........................................................................................... 17 TAPING SPECIFICATION ........................................................................................................ 18 12. ORDERING INSTRUCTION ..................................................................................................... 18 13. TOP MARKING SPECIFICATION ............................................................................................ 18 -2- - Publication Release Date: Apr., 2008 Revision 1.1 W83320G 1. GENERAL DESCRIPTION The W83320G is a high-speed, N-Channel synchronous buck regulator controller optimized for wide reference input range. The W83320G employs adjustable frequency ranging from 100 KHz to 400 KHz voltage-mode PWM control architecture. The regulator is biased from a 5V rail and the power for the high-side MOSFET can be supplied by a separate 12V rail or supplied from the internal charge pump. A Current limit protection is implemented by monitoring the voltage drop across the switch ON resistance of the low-side MOSFET. This method can eliminate the requirement of extra current sensing resistor and avoids false trigger of OC protection when VIN varies efficiently. The adaptive non-overlapping MOSFET gate drivers help avoid potential shoot-through problems while maintaining high efficiency. All these together with Power-good flag, enable and soft start features make power sequencing easy. 2. FEATURES y 1.8V to 5V power stage input voltage y Providing +/-1.5% reference voltage y Power Good flag y Current limit without sense resistor y Soft start y Switching frequency from 100 kHz to 400 kHz y Tiny plastic SOP-14 package 3. APPLICATIONS y DDR SDRAM and AGP core power for Desktop PC y Set-Top Boxes/ Home Gateways y Core Logic Regulators y High-Efficiency Buck Regulation -3- Publication Release Date: Apr., 2008 Revision 1.1 W83320G 4. PIN-OUT LGATE 1 14 ISEN VDD 2 13 GND VDDA 3 12 UGATE PWOK 4 11 BOOT GNDA 5 10 BG_REF SS 6 9 VREF COMP 7 8 FB W83320G W83320G (Top View) Figure1. W83320G Pin-out -4- - Publication Release Date: Apr., 2008 Revision 1.1 W83320G 5. PIN DESCRIPTION PIN NAME FUNCTION 1 LGATE Low-Side N-Channel MOSFET Gate Drive Pin. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET turned off. 2 VDD 3 VDDA 4 PWROK 5 GNDA 6 SS 7 COMP 8 FB 9 VREF 10 BG_REF 11 BOOT 12 UGATE 13 GND 14 ISEN +5V supply rail for the lower gate driver and control logic circuit. VDDA: +5V supply rail for the chip. Power OK. Open drain output. This pin will be opened in following conditions: 1. No over-current detected; 2. VREF_IN >0.6V; 3. FB > 75% of VREF_IN; 4. SS >3V. Ground for analog circuit. Connect it to system ground. Soft Start Pin. A capacitor should be attached in this pin to ground for soft start output clamping. This capacitor, along with an internal 12uA current source, set the output clamp ramp up speed. Internal Error Amplifier Output Pin. This pin is available for compensation of the control loop. Inverting Input of the Error Amplifier. This pin is available for compensation of the control loop. Non-inverting Input of the Error Amplifier. Voltage on this pin provides reference input to the PWM control loop. When the VREF_IN voltage is less than 0.27V, the PWM is shut-down and the UGATE and LGAET are driven low. Due to its wide input range (0 ~ 3.6V), the VREF_IN voltage can be raised slowly to perform the input clamp function. Besides, a special function is implemented in this IC to inform the reference provider of over current alarm. Each time as the OC occurs, VREF_IN will be short to GND (through 170 ohms) for about 5~10uS. The reference provider can be aware of the OC condition by detecting this pulse. Internal Band gap Reference Voltage Output. Supply rail for the high-side MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage or a separate 12V supply can be used. High-Side N-Channel MOSFET Gate Drive Pin. This pin is also monitored by the adaptive shoot through protection circuitry to determine when the high-side MOSFET has turned off. Ground for signal level circuit. Connect it to system ground. Current limit threshold setting. Connect a resistor (ROCSET) between this pin and the drain of the low-side MOSFET. An internal 72uA current source will flow through RISEN and cause a fixed voltage drop on it while the low-side MOSFET is turned on. In the mean while, the W83320G compares the voltage drop with the voltage across the low-side MOSFET and determines whether the current limit has been reached. The equation for over-current limit is: ILIM = (72uA * RISEN)/RDSON -5- Publication Release Date: Apr., 2008 Revision 1.1 W83320G 6. INTERNAL BLOCK DIAGRAM VDDA . SS POR 72A 12A Soft Start Logic 0.6V .. FB + - EA Output Clamp COMP BG_REF . ISEN Control Logic X0.7 VREF VDD IREF & VREF . Gate Control + Logic - Oscillator GND VDD . . BOOT UGATE LGATE GNDA Figure2. W83320G Block Diagram -6- - Publication Release Date: Apr., 2008 Revision 1.1 W83320G Soft-Start When VDDA and VDD ramp over 4.3V and the voltage at pin VREF ramps over 0.27V; the soft start capacitor begins to charge through an internal 12uA (IREF/2) current source. The error amplifier (and the PWM duty) is both output clamped by the voltage on soft-start pin VSS and input clamped by the voltage on VREF. There are two ways to soft start the power that's following the rising of the slower one between VSS or VREF; during soft-start, PWOK is forced to low and the internal Over-Current Protection is triggered to work. 0.4V to 1.9V of VSS is roughly mapping to 0 to 100% pulse-width. Smaller than 0.27V on VREF will disable the PWM controller and discharge CSS. MOSFET Gate Drivers The power for the high-side driver is flowing through the BOOT pin. This voltage can be supplied by a separate, higher voltage source, or supplied from a local charge pump structure or combination of the two. Since the voltage of the low-side MOSFET gate and the high-side MOSFET gate are being monitored to determine the state of the MOSFET, it should be taken carefully to add external components between the gate drivers and their respective MOSFET gates. Doing so may interfere with the shootthrough protection. Current Limit Current limit is implemented by sensing the voltage across the low-side MOSFET while it is ON. This method enhances the converter's efficiency and reduces total cost by eliminating a current sensing resistor. While low-side MOSFET is turned on, a constant current of 72uA (IREF X 3) is forced through ROCSET which is an external resistor connected between phase and ISEN, causing a fixed voltage drop. This fixed voltage is compared against VDS and if the latter is higher, the chip enters current limit mode. In the current limit mode both the high-side and low-side MOSFETS are turned off and the soft start capacitor CSS will be discharged immediately. The VREF is shorted to GND for 5~10uS to indicate the over current condition. After a 5mS delay, a soft-start cycle is initiated. If the cause of the over-current is still present after the delay interval, the current limit would be triggered again. The shut down - delay - soft start cycle will be repeated indefinitely until the over-current event been removed. Input Tracking When the VREF voltage is less than 0.3V, the PWM is shut-down and the UGATE and LGATE are driven low. Due to its wide input range (0 ~ 3.6V), this chip is suitable for reference input tracking application. But note that the chip will be shut-down when VREF <0.27V, a proper setting of CSS is needed to clamp the output at initiation of start up and avoid output voltage step-up (and so a large inrush current). IREF and PWM Clock The Internal reference current (IREF) is determined by the resistor between pin BG_REF pin and GND (RSET) according to the following equation: IREF = 1.19V/ RSET The nominal 200 kHz PWM clock can be adjusted ranging form 100 kHz to 400 kHz by changing IREF according to the following equation: Freq = 200 KHz * IREF / 24uA; -7- Publication Release Date: Apr., 2008 Revision 1.1 W83320G 7. APPLICATION CIRCUIT z Standalone mode with internal 1.19V VREF NMOS/TO252 Q1 VCC5/5VDUAL R1 10 VCC R3 4.7K C1 C2 2.2U 2.2U R2 5.6K L1 3.3U C8 0.22U 1 2 3 4 5 6 7 C3 0.1U U1 ISEN LGATE GND VDD UGATE VDDA BOOT PWROK GNDA BG_REF VREF SS FB COMP C9 2.2U D1 Schottky 14 13 12 11 10 9 8 (OPT) R6 R7 100K 49.9K R10 (OPT) R3 4.7K C2 2.2U 2.2U U1 LGATE ISEN VDD GND VDDA UGATE PWROK BOOT GNDA BG_REF SS VREF COMP FB C11 0.22U VCC5/5VDUAL C12 2000U C13 1000U C6 (OPT) R9 5.1k C4 L1 3.3U VOUT R4 2.2 14 13 12 11 10 9 8 C14 2000U C15 2000U C10 6.8n VCC12 NMOS/TO252 Q2 C8 2.2U R5 30K W83320S/G C5 2.2n L2 3.3U R2 5.6K 1 2 3 4 5 6 7 C3 0.1U C10 6.8n NMOS/TO252 Q1 VCC5/5VDUAL R1 10 C1 C15 2000U NMOS/TO252 Q2 R8 (OPT) VCC C14 2000U R5 30K C7 0.1U C5 2.2n R4 2.2 VCC5/5VDUAL W83320S/G C4 VOUT C7 0.1U (OPT) R6 R7 100K 49.9K R8 (OPT) R10 (OPT) L2 3.3U C11 0.22U C12 2000U VCC5/5VDUAL C13 1000U C6 (OPT) R9 5.1k -8- - Publication Release Date: Apr., 2008 Revision 1.1 W83320G z Tracking mode with external VREF VCC R3 4.7K NMOS/TO252 Q1 VCC5/5VDUAL R1 10 C1 C2 2.2U 2.2U R2 5.6K L1 3.3U C8 0.22U 1 2 3 4 5 6 7 C3 0.1U U1 ISEN LGATE GND VDD UGATE VDDA BOOT PWROK GNDA BG_REF VREF SS FB COMP 14 13 12 11 10 9 8 C15 2000U C10 6.8n R6 C7 0.1U 49.9K R7 100K C11 0.22U R8 (OPT) R10 (OPT) C14 2000U NMOS/TO252 Q2 VREF R5 33 (OPT) C5 2.2n R4 2.2 VCC5/5VDUAL W83320S/G C4 C9 2.2U D1 Schottky VOUT L2 3.3U VCC5/5VDUAL C12 2000U C13 1000U C6 (OPT) R9 5.1k NMOS/TO252 Q1 VCC5/5VDUAL R1 10 VCC R3 4.7K C1 C2 2.2U 2.2U R2 5.6K 1 2 3 4 5 6 7 C3 0.1U L1 3.3U R4 2.2 U1 14 LGATE ISEN 13 VDD GND 12 VDDA UGATE 11 PWROK BOOT 10 GNDA BG_REF 9 SS VREF 8 COMP FB W83320S/G C5 2.2n C14 2000U C15 2000U C10 6.8n VCC12 VREF NMOS/TO252 Q2 C8 2.2U R5 33 C7 0.1U C4 VOUT (OPT) R6 R7 100K 49.9K R8 (OPT) R10 (OPT) L2 3.3U C11 0.22U C12 2000U VCC5/5VDUAL C13 1000U C6 (OPT) R9 5.1k -9- Publication Release Date: Apr., 2008 Revision 1.1 W83320G 8. ABSOLUTE MAXIMUM RATINGS z Supply Voltage VDD/VDDA --------------------------------------------------------- 6V z BOOT & UGATE to GND ------------------------------------------------------------ 15V z Package Thermal Resistance SOP-14, JA ------------------------------------ 128C/W z Ambient Temperature Range ------------------------------------------------------ 0C~+70C z Junction Temperature Range ------------------------------------------------------ -40C~+125C z Storage Temperature Range ------------------------------------------------------- -65C~+150C z Electrostatic discharge protection (ESD) Human Body Mode ------------------------- 2KV - 10 - - Publication Release Date: Apr., 2008 Revision 1.1 W83320G 9. ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS EN=VCC; UGATE and LGATE Open - 3 - mA Rising VDD Threshold - 4.3 - V Falling VDD Threshold - 3.7 - V VREF Enable - 0.27 - V RSET=49.6K 160 200 240 kHz RSET=49.6K - 1.5 - VP-P -1.5 - 1.5 % - 1.19 - V DC Gain - 80 - dB Gain-Bandwidth - 5 - MHz Slew Rate - 4 - V/S VCC SUPPLY CURRENT Nominal Supply ICC POWER-ON RESET OSCILLATOR Free Running Frequency Ramp Amplitude VOSC REFERENCE Reference Voltage Tolerance VREF Reference Voltage ERROR AMPLIFIER GATE DRIVERS High-side Gate Source IHGATE-SRC VBOOT=12V,VUGATE=6V 250 - - mA High-side Gate Sink IHGATE-SNK VBOOT=12V,VUGATE=6V 600 - - mA Low-side Gate Source ILGATE-SRC VCC=5V, VLGATE=2.5V 250 - - mA Low-side Gate Sink ILGATE-SNK VCC=5V, VLGATE=2.5V 300 - - mA PROTECTION ISEN Current Source ISEN 64 72 80 A Soft-Start Current ISS 10 12 14 A - 11 - Publication Release Date: Apr., 2008 Revision 1.1 W83320G 10. TYPICAL PERFORMANCE CHARACTERISTICS - Power start up with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz. Ch1: VCC Ch2: VREF Ch3: VOUT Ch4: PWROK - Power shut down with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz. Ch1: VCC Ch2: VREF Ch3: VOUT Ch4: PWROK - 12 - - Publication Release Date: Apr., 2008 Revision 1.1 W83320G - High gate switch off with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz. Ch1: UGATE Ch2: LGATE Ch3: Phase - High gate switch off with condition: 2Amp loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz. Ch1: UGATE Ch2: LGATE Ch3: Phase - 13 - Publication Release Date: Apr., 2008 Revision 1.1 W83320G - High gate switch on with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz. Ch1: UGATE Ch2: LGATE Ch3: Phase - High gate switch on with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz. Ch1: UGATE Ch2: LGATE Ch3: Phase - 14 - - Publication Release Date: Apr., 2008 Revision 1.1 W83320G - Load transient response with condition: 0.5Amp to 5.5Amp; CSS=0.1uF; VIN=5V; VOUT=2.5V; f = 200 KHz. Ch1: IOUT Ch4: VOUT - Load transient response with condition: 5.5Amp to 0.5Amp; CSS=0.1uF; VIN=5V; VOUT=2.5V; f = 200 KHz. Ch1: VOUT Ch4: IOUT - 15 - Publication Release Date: Apr., 2008 Revision 1.1 W83320G - Output load transient response with condition: IOUT=2Amp; CSS=0.1uF; VIN=5V; VOUT=2.5V; f = 200 KHz. Ch1: VOUT Ch4: IOUT Regulation efficiency with various loading Efficiency(Vin=5V,Vout=2.5V) 96 Efficiency(%) - 94.34 94.34 93.9 93.28 92.59 92.59 91.62 94 92 90.9 90 90 88 86 1 2 3 4 5 6 7 8 9 Output current(A) - 16 - - Publication Release Date: Apr., 2008 Revision 1.1 W83320G 11. PACKAGE DIMENSION OUTLINE 14L SOP (150mil) 8 14 c E HE L 7 1 D 0.25 O A Y SEATING PLANE e GAUGE PLANE A1 b Control demensions are in milmeters . SYMBOL A A1 b c E D e HE Y L DIMENSION IN MM MIN. MAX. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 3.80 4.00 8.75 8.55 1.27 BSC 6.20 5.80 0.10 1.27 0.40 0 8 DIMENSION IN INCH MIN. MAX. 0.053 0.069 0.010 0.004 0.013 0.020 0.008 0.010 0.150 0.157 0.344 0.337 0.050 BSC 0.228 0.016 0 - 17 - 0.244 0.004 0.050 8 Publication Release Date: Apr., 2008 Revision 1.1 W83320G 3/4 TAPING SPECIFICATION 14 Pin SOP Package 12. ORDERING INSTRUCTION PART NUMBER W83320G SUPPLIED AS PACKAGE TYPE 14PIN SOP (Pb-free package) E Shape: 56 units/Tube T Shape: 2,500 units/T&R PRODUCTION FLOW Commercial, 0 to +70 13. TOP MARKING SPECIFICATION W83320G 2322906Z-N 523GA Left Line: Nuvoton Logo 1st Line: Part No - W83320G is for Pb-free package. 2nd Line: IC Tracking Code 3rd Line: Manufacturing Date Code (X XX) + Assembly Code (X) + IC Version (X) 523: packages assembled in Year 05', week 23 G: assembly house ID; G means GR, O means OSE, etc. A: the IC version (A means A, B means B and C means C...etc.) - 18 - - Publication Release Date: Apr., 2008 Revision 1.1 W83320G Important Notice Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. - 19 - Publication Release Date: Apr., 2008 Revision 1.1