PIC16HV54X EPROM/ROM Memory Programming/Verify Specification This document includes the programming specifications for the following devices: Pin Diagrams PDIP, SOIC, Windowed CERDIP * PIC16HV540 Overview The PIC16HV54X Series is a family of field-programmable, single-chip CMOS microcontrollers with on-chip EPROM for program storage. Due to the special architecture of these microcontrollers (12-bit wide instruction word) and the low pin counts (starting at 18 pins), the EPROM programming methodology is different from that of standard (bytewide) EPROMs (e.g., 27C256). *1 18 RA1 RA3 2 17 RA0 T0CKI 3 16 OSC1/CLKIN MCLR/VPP 4 15 OSC2/CLKOUT VSS 5 14 VDD RB0 6 13 RB7 RB1 7 12 RB6 RB2 8 11 RB5 RB3 9 10 RB4 *1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PIC16HV540 INTRODUCTION RA2 SSOP The PIC16HV54X Series can be programmed by applying the 12-bit wide data word to the 12 available I/ O pins while the address is generated by the on-chip Program Counter. The MCLR/VPP pin provides the programming supply voltage (VPP). Programming/verify chip enable is controlled by the T0CKI pin while the OSC1 pin controls the Program Counter. PIC16HV540 RA2 RA3 T0CKI MCLR/VPP VSS VSS RB0 RB1 RB2 RB3 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4 This document describes all the programming details of the PIC16HV54X Series and the requirements for programming equipment to be used from programming prototypes in the engineering lab up to high volume programming on the factory floor. PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16HV540 During Programming Pin Name Pin Name Pin Type Pin Description T0CKI PROG/VER I RA0 - RA3 D0 - D3 I/O Data input/output RB0 - RB7 D4 - D11 I/O Data input/output Program pulse input/verify pulse input OSC1 INCPC I Increment Program Counter input MCLR/VPP VPP P Programming Power VDD VDD P Power Supply VSS VSS P Ground Legend: I = Input, O = Output, P = Power 1999 Microchip Technology Inc. DS30467A-page 1 PIC16HV54X 1.0 PROGRAM/VERIFY MODES The PIC16HV54X Series uses the internal Program Counter (PC) to generate the EPROM address. VPP is supplied through the MCLR pin. The T0CKI pin acts as chip enable, alternating between programming and verifying. The OSC1 pin is used for incrementing the PC. Data is applied to, or can be read on PORTA and PORTB (MSB on RB7, LSB on RA0). The programming/verify mode is entered by raising the level on the MCLR pin from VIL to VHH (= VPP) while the T0CKI pin is held at VIH and the OSC1 pin is held at VIL. The Program Counter now has the value "0x7FF", because MCLR was at VIL before. This condition selects the configuration word as the very first EPROM location to be accessed after entering the program/verify mode. Since the MCLR pin was initially at VIL, the device is in the reset state (the I/O pins are in the reset state). Incrementing the PC once (by pulsing the OSC1 pin) selects location "0x000" of the user program memory. Afterwards all other memory locations from 001h through end of memory can be addressed by incrementing the PC. If the Program Counter has reached the last address of the user memory area ("0x1FF" for the PIC16HV5404), and is incremented again, the on-chip special EPROM area will be addressed. (See Figure 1-2 to determine where the special EPROM area is located for the various PIC16HV54X devices). 1.1 Program/Verify Without PC Increment After entering the program/verify mode, pulsing the T0CKI pin LOW programs the data present on PORTA and PORTB into the memory location selected by the Program Counter. The duration of the T0CKI LOW time determines the length of the programming pulse. 1.2 Verify with PC Increment If a verification cycle shows that programming was successful, the Program Counter can be incremented by keeping the T0CKI input at a HIGH level while pulsing the OSC1 input HIGH. When both T0CKI and OSC1 are HIGH, the contents of the selected memory location is put out on Ports A and B (= Verify). The falling edge of OSC1 will increment the Program Counter. A fast VERIFY- ONLY with automatic increment of the PC can be performed by entering the program/verify mode as described above and then clocking the OSC1 input. If OSC1 is HIGH, the selected memory location is output on Ports A and B, while the falling edge of OSC1 will increment the Program Counter. Thus, the first memory location to be verified after entering the program/verify mode, is the configuration word. The next location is 000h followed by 001h and so on. The program memory location "N" can be reached by generating "N + 1" falling edges on OSC1. When OSC1 is brought HIGH again, the contents of address "N" are output on Ports A and B as long as OSC1 stays HIGH. 1.3 Programming/Verifying Configuration Word The configuration word is logically mapped at program memory location "0x7FF". The PC points to the configuration word after MCLR pin goes from LOW to VHH (HIGH). The configuration word can be programmed or verified using the techniques described in Section 1.1 and Section 1.2. If PC is incremented, the next location it will point to is "0x000" in user memory. Incrementing PC 2048 times will not allow the user to point to the configuration word. The only way to point to it again is to reset and re-enter program mode. Pulsing the T0CKI pin LOW again without changing the signals on MCLR and OSC1 puts the contents of the selected memory location out on PORTA and PORTB for verification of a successful programming cycle. This verification pulse on T0CKI can be much shorter than the programming pulse. If the programming was not successful, T0CKI can be pulsed LOW again to apply another programming pulse, followed again by a shorter T0CKI LOW pulse for another verification cycle. This sequence can be repeated as many times as required until the programming is successful. DS30467A-page 2 1999 Microchip Technology Inc. PIC16HV54X 1.4 Programming Method The programming technique is described in the following section. It is designed to guarantee good programming margins. It does, however, require a variable power supply for VCC. 1.4.1 PROGRAMMING METHOD DETAILS Essentially, this technique includes the following steps: 1. 2. a) Perform blank check at VDD = VDDmin. Report failure. The device may not be properly erased. Program location with pulses and verify after each pulse at VDD = VDDP: where VDDP = VDD range required during programming (4.5V - 5.5V). Programming condition: VPP = 13.0V to 13.25V VDD = VDDP = 4.5V to 5.5V VPP must be VDD + 7.25V to keep "programming mode" active. b) 1.4.2 Clearly, to implement this technique, the most stringent requirements will be that of the power supplies: VPP: VPP can be a fixed 13.0V to 13.25V supply. It must not exceed 14.0V to avoid damage to the pin and should be current limited to approximately 100mA. VDD: 2.0V to 6.5V with 0.25V granularity. Since this method calls for verification at different VDD values, a programmable VDD power supply is needed. Current Requirement: 40mA maximum Microchip may release PIC16HV54Xs in the future with different VDD ranges which make it necessary to have a programmable VDD. It is important to verify an EPROM at the voltages specified in this method to remain consistent with Microchip's test screening. For example, a PIC16HV54X specified for 4.5V to 5.5V should be tested for proper programming from 4.5V to 5.5V. Note: Verify condition: VDD = VDDP VPP VDD + 7.5V but not to exceed 13.25V If location fails to program after "N" pulses, (suggested maximum program pulses of 8) then report error as a programming failure. Note: 3. 4. 5. 6. Device must be verified at minimum and maximum specified operating voltages as specified in the data sheet. Once location passes "Step 2", apply 3X overprogramming, i.e., apply three times the number of pulses that were required to program the location. This will guarantee a solid programming margin. The overprogramming should be made "software programmable" for easy updates. Program all locations. Verify all locations (using speed verify mode) at VDD = VDDmin Verify all locations at VDD = VDDmax VDDmin is the minimum operating voltage spec. for the part. VDDmax is the maximum operating voltage spec. for the part. SYSTEM REQUIREMENTS 1.4.3 Any programmer not meeting the programmable VDD requirement and the verify at VDDmax and VDDmin requirement may only be classified as "prototype" or "development" programmer but not a production programmer. SOFTWARE REQUIREMENTS Certain parameters should be programmable (and therefore easily modified) for easy upgrade. a) b) c) 1.5 Pulse width Maximum number of pulses, current limit 8. Number of over-programming pulses: should be = (A * N) + B, where N = number of pulses required in regular programming. In our current algorithm A = 11, B = 0. Programming Pulse Width Program Memory Cells: When programming one word of EPROM, a programming pulse width (TPW) of 100 s is recommended. The maximum number of programming attempts should be limited to 8 per word. After the first successful verify, the same location should be over-programmed with 11X over-programming. Configuration Word: The configuration word for oscillator selection, WDT (watchdog timer) disable and code protection, requires a programming pulse width (TPWF) of 10 ms. A series of 100 s pulses is preferred over a single 10 ms pulse. 1999 Microchip Technology Inc. DS30467A-page 3 PIC16HV54X FIGURE 1-1: PROGRAMMING METHOD FLOWCHART Start Blank Check @ VDD = VDDmin Report Possible Erase Failure Continue Programming at user's option No Pass? Report Programming Failure Yes Yes Program 1 Location @ VPP = 13.0V to 13.25V VDD = VDDP No Pass? No N > 8? N=N+1 (N = # of program pulses) Yes Increment PC to point to next location, N = 0 Apply 11N additional program pulses No All locations done? Yes Verify all locations @ VDD = VDDmin No Pass? Report verify failure @ VDDmin Yes Verify all locations =V =DD VDD max. max @ VDD VDD No Pass? Report verify failure @ VDDmax Yes Now program Configuration Word Verify Configuration Word @ VDDmax & VDDmin Done DS30467A-page 4 1999 Microchip Technology Inc. PIC16HV54X FIGURE 1-2: PIC16HV54X SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE Address 11 (Hex) 000 NNN Bit Number 0 User Program Memory (NNN + 1) x 12 bit TTT 0 0 ID0 TTT + 1 0 0 0 0 ID1 ID2 0 0 ID3 TTT + 2 TTT + 3 For Customer Use (4 x 4 bit usable) For Factory Use TTT + 3F (FFF) Configuration Word 4 bit NNN Highest normal EPROM memory address. NNN = 0x1FF for PIC16HV540. TTT Start address of special EPROM area and ID Locations. 1.6 Special Memory Locations EXAMPLE 1: CUSTOMER CODE 0xD1E2 The ID Locations area is only enabled if the device is in a test or programming/verify mode. Thus, in normal operation mode only the memory location 0x000 to 0xNNN will be accessed and the Program Counter will just roll over from address 0xNNN to 0x000 when incremented. The Customer ID code "0xD1E2" should be stored in the ID locations 200-203 like this: The configuration word can only be accessed immediately after MCLR going from VIL to VHH. The Program Counter will be set to all '1's upon MCLR = VIL. Thus, it has the value "0x7FF" when accessing the configuration EPROM. Incrementing the Program Counter once by pulsing OSC1 causes the Program Counter to roll over to all '0's. Incrementing the Program Counter 4K times after reset (MCLR = VIL) does not allow access to the configuration EPROM. Reading these four memory locations, even with the code protection bit programmed would still output on Port A the bit sequence "1101", "0001", "1110", "0010" which is "0xD1E2". 1.6.1 200: 201: 202: 203: Note: 0000 0000 0000 0000 0000 0000 0000 0000 1101 0001 1110 0010 Microchip will assign a unique pattern number for QTP and SQTP requests and for ROM devices. This pattern number will be unique and traceable to the submitted code. CUSTOMER ID CODE LOCATIONS Per definition, the first four words (address TTT to TTT + 3) are reserved for customer use. It is recommended that the customer use only the four lower order bits (bits 0 through 3) of each word and filling the eight higher order bits with '0's. A user may want to store an identification code (ID) in the ID locations and still be able to read this code after the code protection bit was programmed. This is possible if the ID code is only four bits long per memory location, is located in the least significant nibble boundary of the 12-bit word, and the remaining eight bits are all '0's. 1999 Microchip Technology Inc. DS30467A-page 5 PIC16HV54X 2.0 CONFIGURATION WORD The configuration word is the very first memory location which is accessed after entering the program/verify mode of the PIC16HV54X. It contains the two bits for the selection of the oscillator type, the watchdog timer enable bit, and the code protection bit. All other bits (4 through 11) are read as '1's. FIGURE 2-1: CONFIGURATION WORD BIT MAP bit Number: 11 10 9 8 7 6 5 4 PIC16HV540 - TABLE 2-1: - - - - - - - 3 2 CP WDTE RA3 RA2 1 0 FOSC1 FOSC0 RA1 RA0 CONFIGURATION BIT FUNCTIONALITY (PIC16HV540) RA3-RA11 CP RA2 WDTE RA1 FOSC1 RA0 FOSC2 1 x x x Memory unprotected 0 x x x Memory protected x 1 x x Watchdog Timer enabled x 0 x x Watchdog Timer disabled x x 1 1 RC - Oscillator x x 1 0 HS - High Speed Crystal x x 0 1 XT - Standard Crystal x x 0 0 LP - Low Frequency Crystal Function Remarks Default Default Default Legend: 1= Erased (apply HIGH Level to I/O pin during program) 0 = Written (apply LOW Level to I/O pin during program) x = Don't Care DS30467A-page 6 1999 Microchip Technology Inc. PIC16HV54X 3.0 CODE PROTECTION The program code written into the EPROM can be protected by writing to the "CP" bit of the configuration word. All memory locations starting at 0x40 and above are protected against programming. It is still possible to program locations 0x00 through 0x3F, the ID locations, and the configuration word. Note: 3.1 Locations [0x000 : 0x03F] are not secure after code protection. Programming Locations 0x000 to 0x03F after Code Protection In a code protected part, these locations can still be programmed. They will read back scrambled data. In any event, the programmer cannot verify the device once it is code protected. In code protected parts, the contents of the program memory cannot be read out in a way that the program code can be reconstructed. A location when read out will read as: 0000 0000 xxxx where xxxx is the XOR of the three nibbles. 3.2 For example, if the memory location contains 0xC04 (movlw 4), after code protection the output will be 0x008. In addition, all memory locations starting at 0x40 and above are protected against programming. It is still possible to program locations 0x000 through 0x03F and the configuration word. However, performing a verify with activated code protection logic puts a 4-bit wide "checksum" on PORTA while the 8-bits of PORTB are read as '0's. The checksum is computed as follows: The four high order bits of an instruction word are "XOR'ed" with the four middle and the four low order bits, and the result is transferred to PORTA. All memory locations are affected. To program location 0x000 to 0x03F in a code protected part, the programmer should program one nibble at a time and verify the result through the XOR'ed output. For example, to program a location with 0xA93, first program the location with 0xFF3, verify checksum to be 0x003; then program the location with 0xF93 and verify the XOR'ed output to be 0x00C and finally program the location with 0xA93 and verify the read-out to be 0x006. Embedding Configuration Word and ID Information in the Hex File To allow portability of code, a PIC16HV54X programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, all configuration word and ID information must be included. Configuration word should have the address of 0xFFF. ID locations are mapped at addresses described in Section 1.6.1 and Table 3-1. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 1999 Microchip Technology Inc. DS30467A-page 7 PIC16HV54X 3.3 Checksum 3.3.1 CHECKSUM CALCULATIONS The least significant 16 bits of this sum is the checksum. Checksum is calculated by reading the contents of the PIC16HV54X memory locations and adding up the opcodes up to the maximum user addressable location, 0x1FF for the PIC16HV540. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16HV54X devices is shown in Table . The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) TABLE 3-1: Device PIC16HV540 The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Code Protect OFF ON Checksum* SUM[0x000:0x1FF] + CFGW & 0x00F + 0x0FF0 SUM_XOR4[0x000:0x1FF] + CFGW & 0x00F Blank Value 0x723 at 0 and max address 0x0DFF 0x1E07 0xFC47 0x1DF5 Legend: CFGW = Configuration Word SUM[a:b] = Sum of locations a through b inclusive SUM_XOR4[a:b] = XOR of the four high order bits with the four middle and the four low of memory location order bits summed over the locations a through b inclusive. For example, location_a = 0x123 and location_b = 0x456, then SUM_XOR [location_a: location_b] = 0x0007. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234. *Checksum = Sum of all individual expressions modulo [0xFFFF] + = Addition & = Bitwise AND DS30467A-page 8 1999 Microchip Technology Inc. PIC16HV54X 4.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS 4.1 DC Program Characteristics) TABLE 4-1: DC CHARACTERISTICS (TA = +10C TO +40C) (25C IS RECOMMENDED Parameter Symbol No. PD1 Characteristics VDDP Supply voltage during programming Min. Typ. Max. Units 4.75 5.0 5.25 V PD2 IDDP Supply Current (from VDD) 25.0 mA PD3 VDDV Supply Voltage during verify VDDmin 5.75 V PD4 VHH1 Voltage on MCLR to stay in Program/Verify Modes VDD + 3 VDD+7.25 V PD5 VHH2 Voltage on MCLR during programming 12.5 13.5 V PD6 IHH Supply current from programming voltage source 100 mA PD7 IHH2 Current into MCLR pin during programming (T0CKI=0) 25.0 mA 0.15VDD V VDD V PD8 VIL Input Low Voltage PD9 VIH Input High Voltage 10.0 VSS 0.85VDD 5.0 Conditions Note 1 VDD = 5.0V, Fosc1 = 5MHz VHH = 13.5V, VDD = 6.0V Note 1: Device must be verified at minimum and maximum operating voltages specified in the data sheet. 4.2 AC Program and Test Mode Characteristics ) TABLE 4-1: AC CHARACTERISTICS (TA = +10C TO +40C, VDD = 5.0V 5%) (25C IS RECOMMENDED Parameter Symbol No. Characteristics Min Typ Max Units P1 TR MCLR Rise Time 0.15 1.0 8 s P2 TF MCLR Fall Time 0.5 2.0 8 s P3 TPS Program Mode Setup Time 1.0 P4 TACC Data Access Time P5 TDS Data Setup Time 1.0 s P6 TDH Data Hold Time 1.0 s P7 TOE Output Enable Time 0 100 ns P8 TOZ Output Disable Time 0 100 ns P9 TPW Programming Pulse Width P10 TPWF Programming Pulse Width P11 TRC P12 FOSC Recovery Time 10.0 Frequency on OSC1 DC 1999 Microchip Technology Inc. s 250 10.0 Conditions ns 100 s 10,000 s Configuration Word only s 5 MHz For incrementing of the PC DS30467A-page 9 PIC16HV54X FIGURE 4-1: PROGRAMMING AND VERIFY TIMING WAVEFORM P2 P1 VHH1/VHH2 MCLR/VPP P3 P10 P9 P11 T0CKI OSC1 P4 P4 P4 P4 DATA (RB7:0, RA3:0) P5 P7 P6 P8 Data out (Config) Data in (Config) P7 P8 P5 Data out (Config) P6 0xFFF PC (Internal) P7 Data in (LOC 0x000) P8 P7 Data out (LOC 0x000) P8 Data out (LOC0x000) 0x000 0x001 (PC pointing to Configuration Word) FIGURE 4-2: SPEED VERIFY TIMING WAVEFORM VHH1 MCLR/VPP T0CKI OSC1 Data out (0x000) Data out (Config) DATA (RB7:0, RA3:0) P7 Data out (0x001) Data out (0x002) Data out (0x003) 0x002 0x003 '1' P8 P4 PC (Internal) DS30467A-page 10 0xFFF 0x000 0x001 1999 Microchip Technology Inc. PIC16HV54X NOTES: 1999 Microchip Technology Inc. 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The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30467A-page 12 1999 Microchip Technology Inc.