TL/F/9486
54F/74F161A #54F/74F163A Synchronous Presettable Binary Counter
November 1994
54F/74F161A #54F/74F163A
Synchronous Presettable Binary Counter
General Description
The ’F161A and ’F163A are high-speed synchronous modu-
lo-16 binary counters. They are synchronously presettable
for application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multi-stage counters. The
’F161A has an asynchronous Master-Reset input that over-
rides all other inputs and forces the outputs LOW. The
’F163A has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock. The
’F161A and ’F163A are high-speed versions of the ’F161
and ’F163.
Features
YSynchronous counting and loading
YHigh-speed synchronous expansion
YTypical count frequency of 120 MHz
YGuaranteed 4000V minimum ESD protection
Commercial Military Package Package Description
Number
74F161APC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F161ADM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F161ASC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
74F161ASJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F161AFM (Note 2) W16A 16-Lead Cerpack
54F161ALM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
74F163APC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F163ADM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F163ASC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
74F163ASJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F163AFM (Note 2) W16A 16-Lead Cerpack
54F163ALM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffix eSCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix eDMQB, FMQB and LMQB.
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
’F161A
TL/F/9486–1
Pin Assignment
for LCC
’F161A
TL/F/9486–2
Pin Assignment
for DIP, SOIC and Flatpak
’F163A
TL/F/9486–7
Pin Assignment
for LCC
’F163A
TL/F/9486–8
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Obsolete
Logic Symbols
’F161A
TL/F/9486–3
IEEE/IEC
’F161A
TL/F/9486–6
’F163A
TL/F/9486–9
IEEE/IEC
’F163A
TL/F/9486–10
Unit Loading/Fan Out
54F/74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
CEP Count Enable Parallel Input 1.0/1.0 20 mA/b0.6 mA
CET Count Enable Trickle Input 1.0/2.0 20 mA/b1.2 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA
MR (’F161A) Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
SR (’F163A) Synchronous Reset Input (Active LOW) 1.0/2.0 20 mA/b1.2 mA
P0–P3Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA
PE Parallel Enable Input (Active LOW) 1.0/2.0 20 mA/b1.2 mA
Q0–Q3Flip-Flop Outputs 50/33.3 b1 mA/20 mA
TC Terminal Count Output 50/33.3 b1 mA/20 mA
2
Obsolete
Functional Description
The ’F161A and ’F163A count in modulo-16 binary se-
quence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the ’F161A) occur as a re-
sult of, and synchronous with, the LOW-to-HIGH transition
of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous
reset (’F161A), synchronous reset (’F163A), parallel load,
count-up and hold. Five control inputsÐMaster Reset (MR,
’F161A), Synchronous Reset (SR, ’F163A), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable Trickle
(CET)Ðdetermine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP.
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (Pn) inputs to be loaded into the
flip-flops on the next rising edge of CP. With PE and MR
(’F161A) or SR (’F163A) HIGH, CEP and CET permit count-
ing when both are HIGH. Conversely, a LOW signal on ei-
ther CEP or CET inhibits counting.
The ’F161A and ’F163A use D-type edge triggered flip-flops
and changing the SR,PE, CEP and CET inputs when the CP
is in either state does not cause errors, provided that the
recommended setup and hold times, with respect to the ris-
ing edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in state 15. To implement synchronous
multi-stage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the ’F568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers.
Logic Equations: Count Enable eCEP #CET #PE
TC eQ0#Q1#Q2#Q3#CET
Mode Select Table
*SR PE CET CEP Action on the Rising
Clock Edge (L)
L X X X Reset (Clear)
H L X X Load (Pn
x
Qn)
H H H H Count (Increment)
H H L X No Change (Hold)
H H X L No Change (Hold)
*For ’F163A only
HeHIGH Voltage Level
LeLOW Voltage Level
XeImmaterial
State Diagram
TL/F/9486–5
3
Obsolete
Block Diagram
TL/F/9486–4
4
Obsolete
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature b65§Ctoa
150§C
Ambient Temperature under Bias b55§Ctoa
125§C
Junction Temperature under Bias b55§Ctoa
175§C
Plastic b55§Cto
a
150§C
VCC Pin Potential to
Ground Pin b0.5V to a7.0V
Input Voltage (Note 2) b0.5V to a7.0V
Input Current (Note 2) b30 mA to a5.0 mA
Voltage Applied to Output
in HIGH State (with VCC e0V)
Standard Output b0.5V to VCC
TRI-STATEÉOutput b0.5V to a5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
ESD Last Passing Voltage (Min) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military b55§Ctoa
125§C
Commercial 0§Ctoa
70§C
Supply Voltage
Military a4.5V to a5.5V
Commercial a4.5V to a5.5V
DC Electrical Characteristics
Symbol Parameter 54F/74F Units VCC Conditions
Min Typ Max
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage b1.2 V Min IIN eb
18 mA
VOH Output HIGH 54F 10% VCC 2.5 IOH eb
1mA
Voltage 74F 10% VCC 2.5 V Min
74F 5% VCC 2.7
VOL Output LOW 54F 10% VCC 0.5 V Min IOL e20 mA
Voltage 74F 10% VCC 0.5
IIH Input HIGH 54F 20.0
mA Max VIN e2.7V
Current 74F 5.0
IBVI Input HIGH Current 54F 100
mA Max VIN e7.0V
Breakdown Test 74F 7.0
ICEX Output HIGH 54F 250
mA Max VOUT eVCC
Leakage Current 74F 50
VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA
Test All Other Pins Grounded
IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current b0.6 mA Max VIN e0.5V (CEP, CP, MR,P
0
–P3)
b1.2 mA Max VIN e0.5V (CET, PE,SR)
I
OS Output Short-Circuit Current b60 b150 mA Max VOUT e0V
ICC Power Supply Current 37 55 mA Max
5
Obsolete
AC Electrical Characteristics
74F 54F 74F
TAea
25§CTA,V
CC eMil TA,V
CC eCom
Symbol Parameter VCC ea
5.0V CLe50 pF CLe50 pF Units
CLe50 pF
Min Typ Max Min Max Min Max
fmax Maximum Count Frequency 100 120 75 90 MHz
tPLH Propagation Delay 3.5 5.5 7.5 3.5 9.0 3.5 8.5
tPHL CP to Qn(PE Input HIGH) 3.5 7.5 10.0 3.5 11.5 3.5 11.0 ns
tPLH Propagation Delay 4.0 6.0 8.5 4.0 10.0 4.0 9.5
tPHL CP to Qn(PE Input LOW) 4.0 6.0 8.5 4.0 10.0 4.0 9.5
tPLH Propagation Delay 5.0 10.0 14.0 5.0 16.5 5.0 15.0 ns
tPHL CP to TC 5.0 10.0 14.0 5.0 15.5 5.0 15.0
tPLH Propagation Delay 2.5 4.5 7.5 2.5 9.0 2.5 8.5 ns
tPHL CET to TC 2.5 4.5 7.5 2.5 9.0 2.5 8.5
tPHL Propagation Delay 5.5 9.0 12.0 5.5 14.0 5.5 13.0 ns
MR to Qn(’F161A)
tPHL Propagation Delay 4.5 8.0 10.5 4.5 12.5 4.5 11.5 ns
MR to TC (’F161A)
AC Operating Requirements
74F 54F 74F
Symbol Parameter TAea
25§CTA,V
CC eMil TA,V
CC eCom Units
VCC ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 5.0 5.5 5.0
ts(L) Pnto CP 5.0 5.5 5.0 ns
th(H) Hold Time, HIGH or LOW 2.0 2.5 2.0
th(L) Pnto CP 2.0 2.5 2.0
ts(H) Setup Time, HIGH or LOW 11.0 13.5 11.5
ts(L) PE or SR to CP 8.5 10.5 9.5 ns
th(H) Hold Time, HIGH or LOW 2.0 3.6 2.0
th(L) PE or SR to CP 0 0 0
ts(H) Setup Time, HIGH or LOW 11.0 13.0 11.5
ts(L) CEP or CET to CP 5.0 6.0 5.0 ns
th(H) Hold Time, HIGH or LOW 0 0 0
th(L) CEP or CET to CP 0 0 0
tw(H) Clock Pulse Width (Load) 5.0 5.0 5.0 ns
tw(L) HIGH or LOW 5.0 5.0 5.0
tw(H) Clock Pulse Width (Count) 4.0 5.0 4.0 ns
tw(L) HIGH or LOW 6.0 8.0 7.0
tw(L) MR Pulse Width, LOW 5.0 5.0 5.0 ns
(’F161A)
trec Recovery Time 6.0 6.0 6.0 ns
MR to CP (’F161A)
6
Obsolete
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 161A/163A S C X
Temperature Range Family Special Variations
74FeCommercial QR eCommercial grade device
54FeMilitary with burn-in
QB eMilitary grade device with
Device Type environmental and burn-in
processing
Package Code XeDevices shipped in 13×reel
PePlastic DIP
DeCeramic DIP Temperature Range
FeFlatpak CeCommercial (0§Ctoa
70§C)
LeLeadless Chip Carrier (LCC) MeMilitary (b55§Ctoa
125§C)
SeSmall Outline Package SOIC JEDEC
SJ eSmall Outline Package SOIC EIAJ
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
7
Obsolete
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
16-Lead (0.150×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M16A
8
Obsolete
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M16D
16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N16E
9
Obsolete
54F/74F161A #54F/74F163A Synchronous Presettable Binary Counter
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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with instructions for use provided in the labeling, can effectiveness.
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Obsolete
