[AK1573/AK1573B/AK1573C] AK1573/AK1573B/AK1573C Frequency Synthesizer with Integrated VCO 1. General Description AK1573 is the Integer-N frequency synthesizer with integrated VCO (Voltage Controlled Oscillator). It is composed of programmable charge pump, reference divider, programmable divider, dual modulus prescaler (P / P + 1). With the feature of high-performance, low noise and small size, it can be used as a local signal source of a variety of frequency conversion. By combining with an external loop filter, AK1573 form a complete Phase Locked Loop. Access to the register is controlled by the serial interface of the 3-wire and Power supply voltage is 2.7V to 3.3V. 2. Features Normalized Phase Noise Low Noise Integrated VCO Operating Supply Voltage Low Current Comsumption@0dBm Output -223dBc/Hz -86dBc/Hz@10kHz -112dBc/Hz@100kHz 2.7 to 3.3V AK1573 AK1573B AK1573C Programmable to Divide by Programmable Output Power Fast Lock-up Function Analog or Digital Lock Detect Function Output Mute Function Package Operating Temperature Range Frequency Coverage Options VCO Frequency [MHz] Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 43mA 44mA 46mA 1, 2, 4, 8, 16, 32, 64 -12dBm to +6dBm 24pin QFN (0.5mm pitch 4x4mm) -40 C to 85 C AK1573 1480 to 2240 1480 to 2240 740 to 1120 370 to 560 185 to 280 92.5 to 140 46.25 to 70 30 to 35 AK1573B 1728 to 2600 1728 to 2600 864 to 1300 432 to 650 216 to 325 108 to 162.5 54 to 81.25 30 to 40.625 015009351-E-00 AK1573C 2100 to 3000 2100 to 3000 1050 to 1500 525 to 750 262.5 to 375 131.25 to 187.5 65.625 to 93.75 32.8125 to 46.875 2015/8 -1- [AK1573/AK1573B/AK1573C] 3. - AK1573 - AK1573B - AK1573C - AKD1573 - AKD1573B - AKD1573C 24-pin QFN (4.0mm x 4.0mm, 0.5mm pitch) 24-pin QFN (4.0mm x 4.0mm, 0.5mm pitch) 24-pin QFN (4.0mm x 4.0mm, 0.5mm pitch) AK1573 Evaluation Board AK1573B Evaluation Board AK1573C Evaluation Board 4. Ordering Guide Applications Public safety and Community/Emergency Wireless System Wireless applications Cellular BTS 015009351-E-00 2015/8 -2- [AK1573/AK1573B/AK1573C] 5. Table of Contents 1. 2. 3. 4. 5. 6. General Description ............................................................................................................................ 1 Features .............................................................................................................................................. 1 Ordering Guide.................................................................................................................................... 2 Applications ......................................................................................................................................... 2 Table of Contents ................................................................................................................................ 3 Block Diagram and Functions ............................................................................................................. 4 6.1. Block Diagram.............................................................................................................................. 4 6.2. Functions ..................................................................................................................................... 4 7. Pin Configurations and Functions ....................................................................................................... 5 8. Absolute Maximum Ratings ................................................................................................................ 6 9. Recommended Operating Conditions................................................................................................. 7 10. Electrical Characteristics ................................................................................................................. 7 10.1. Digital DC Characteristics ........................................................................................................ 7 10.2. Serial Interface Timing ............................................................................................................. 7 10.3. Analog Circuit Characteristics .................................................................................................. 8 10.4. Loop filter................................................................................................................................ 10 11. Typical Characteristics .................................................................................................................. 11 12. Register Map ................................................................................................................................. 21 13. Function Descriptions .................................................................................................................... 28 13.1. Lock detect ............................................................................................................................. 28 13.2. Frequency Setting .................................................................................................................. 30 13.3. Fast Lock-up mode ................................................................................................................ 32 13.4. VCO ........................................................................................................................................ 33 14. Power on sequence....................................................................................................................... 34 15. Recommended External Circuits................................................................................................... 35 16. Application Note ............................................................................................................................ 36 17. Interface circuit .............................................................................................................................. 37 18. Package ......................................................................................................................................... 39 18.1. Outline Dimensions ................................................................................................................ 39 18.2. Marking................................................................................................................................... 40 19. Revision History............................................................................................................................. 41 015009351-E-00 2015/8 -3- [AK1573/AK1573B/AK1573C] 6. Block Diagram and Functions 6.1. Block Diagram REFIN Buffer BIAS R COUNTER 14 bit REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP LOCK DETECT LD FAST COUNTER SWALLOW COUNTER 6 bit Loop Filter PROGRAMMABLE COUNTER 13 bit TANK PRESCALER 8/9, 16/17, 32/33, 64/65 VCNT N COUNTER SCAP LE VBG RFOUT_P TEST2 TEST1 OAVSS CPVSS CPVDD PVSS PVDD PDN2 RFOUT_N VREF2 PDN1 VREF1 LDO 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 VCOVSS DATA Digital Control Interface VCOVDD CLK Figure.1 Block Diagram 6.2. Functions Block Function N counter It is composed of prescaler, Swallow Counter and Programmable Counter. VCO output signal is divided by N and passed to phase frequency detector (PFD). VCO Divider It divides VCO output signal and passes it to output buffer. Dividing ratio of 1, 2, 4, 8, 16, 32 and 64 can be selected. R counter It divides a reference signal by R and passes it to phase frequency detector (PFD). VCO (Voltage Controlled Oscillator) It generates a signal of the frequency corresponding to a voltage inputted to VCNT pin. PFD(Phase Frequency Detector) Charge Pump It outputs a signal corresponding to phase difference between N counter and R counter. Sweep or pull-in a current corresponding to a signal from PFD. 015009351-E-00 2015/8 -4- [AK1573/AK1573B/AK1573C] 7. Pin Configurations and Functions Power Down No. Pin Name I/O Pin function 1 BIAS AI Charge pump current setting pin 2 VREF2 AO Internal reference voltage output pin 3 VCNT AI VCO control voltage input pin 4 SCAP AO VCO Bias stabilizing connection pin 5 6 VCOVSS VCOVDD G P 7 TEST1 DI 8 TEST2 9 Description Connect a 27k resistor to the ground "L" Connect a 470nF capacitor to the ground "L" Connect a 100pF capacitor to the ground Ground of VCO block Power supply of VCO block TEST1 pin Connect to the ground Pull Down Schmitt trigger input DI TEST2 pin Connect to the ground Pull Down Schmitt trigger input PDN1 DI Power down 1 pin. When PDN1 = "L", device is powered down and the registers are not retained. Schmitt trigger input 10 11 OAVSS RFOUT_P G AO 12 RFOUT_N AO 13 14 PVDD PVSS P G 15 VREF1 AO Output pin of LDO 16 REFIN DI Reference signal input pin Ground of Local buffer Local signal output pin Local signal complementary output pin Power supply of Prescaler and LDO Ground of Prescaler and LDO "L" 17 PDN2 DI Power down 2 pin. When PDN2 = "L", all blocks except LDO and VBG are powered down but the registers are retained 18 19 20 21 22 23 24 CLK DATA LE LD CVPSS CP CPVDD DI DI DI DO G AO P Serial clock input pin. Serial data input pin. Load enable input pin. Lock detect output pin Ground of Charge Pump CP signal output pin Power supply of Charge Pump AI: Analog input pin DI: Digital input pin Open collector Connect a inductor and a register to VDD AO: Analog output pin DO: Digital output pin Connect a 220nF capacitor to the ground Schmitt trigger input Schmitt trigger input Schmitt trigger input "L" Tri-State AIO: Analog I/O pin P: Power supply pin G: Ground pin * "Power Down" means the state in which power supply is applied and PDN1 / PDN2 pins = "L". * The exposed pad at the center of the backside should be connected to the ground 015009351-E-00 2015/8 -5- 19 DATA 20 LE 21 LD 22 CPVSS 23 CP 24 CPVDD [AK1573/AK1573B/AK1573C] 4 15 VREF1 VCOVSS 5 14 PVSS VCOVDD 6 13 PVDD RFOUT_N 12 SCAP RFOUT_P 11 16 REFIN 10 3 OAVSS VCNT 9 17 PDN2 PDN1 2 8 VREF2 TEST2 18 CLK 7 1 TEST1 BIAS 24-pin QFN (0.5mm pitch, 4mm 4mm) Figure.2 Package pin layout (Top view) 8. Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Description Supply Voltage VDD -0.3 3.6 V * 1, 2 Ground Level VSS 0 0 V *3 Analog input voltage VAIN VSS-0.3 VDD+0.3 V * 1, 4, 6 Digital input voltage VDIN VSS-0.3 VDD+0.3 V * 1, 5, 6 Input current IIN -10 10 mA Storage Temperature Tstg -55 125 C Note * 1. All voltage reference ground level: 0V * 2. Applied to the VCOVDD / PVDD / CPVDD pins * 3. Applied to the CPVSS / PVSS / VCOVSS / OAVSS pins * 4. Applied to the VCNT / REFIN pins * 5. Applied to the CLK / DATA / LE / PDN1 / PDN2 / TEST1 / TEST2 pins * 6. The maximum value must not exceed the absolute maximum rating of 3.6V. Exceeding these maximum ratings may result in damage to the AK1573. Normal operation is not guaranteed at these extremes. 015009351-E-00 2015/8 -6- [AK1573/AK1573B/AK1573C] 9. Parameter Operating Temperature Supply Voltage Recommended Operating Conditions Symbol Min. Ta -40 VDD 2.7 Typ. 3.0 Max. Unit 85 C 3.3 V Description Applied to the VCOVDD / PVDD / CPVDD pins 10. Electrical Characteristics 10.1. Digital DC Characteristics Parameter Symbol Conditions Min. High level input Vih 0.8VDD voltage Low level input Vil voltage High level input Iih1 Vih = VDD=3.3V -1 current 1 High level input Iih2 Vih = VDD=3.3V 16.5 current 2 Low level input Vil = 0V, Iil -1 current VDD=3.3V High level output Voh VDD-0.4 Ioh = -500A voltage Low level output Vol Iol = 500A voltage Note * 1. Applied to the CLK / DATA / LE / PDN1 / PDN2 pins * 2. Applied to the CLK / DATA / LE / PDN1 / PDN2 pins * 3. Applied to the TEST1 / TEST2 pins * 4. Applied to the LD pin Typ. 33 Max. Unit Description V * 1. 0.2VDD V * 1. 1 A *2 66 A *3 1 A *1 V *4 V *4 0.4 10.2. Serial Interface Timing <Write-In Timing> Tcsu Tlesu Tle LE (Input) Tch Tcl CLK (Input) Tsu DATA (Input) D19 Thd D18 6 D0 A3 A2 A1 A0 Max. Unit ns ns ns ns ns ns ns Figure.3 Serial Interface Timing Parameter Clock L level hold time Clock H level hold time Clock setup time Data setup time Data hold time LE setup time LE pulse width Symbol Tcl Tch Tcsu Tsu Thd Tlesu Tle Min. 25 25 10 10 10 10 25 015009351-E-00 Typ. Description 2015/8 -7- [AK1573/AK1573B/AK1573C] 10.3. Analog Circuit Characteristics VDD=2.7 to 3.3V, -40C<Ta<85C, BIAS resistance =27k unless otherwise specified. The exposed pad at the center of the backside should be connected to the ground Parameter Input sensitivity Input Frequency Range Maximum available prescaler output Frequency PFD Frequency Maximum Charge Pump current Minimum Charge pump current Min. Max. Unit Description VDD 2 300 Vpp Vpp MHz REFIN frequency < 200MHz REFIN frequency 200MHz 300 MHz Design guarantee value Typ. REFIN 0.4 0.4 10 Phase Frequency Detector(PFD) 104 MHz Charge Pump 2800 A 350 A Icp TRI-STATE leak current 1 Sink / Source current mismatch * 1 Icp vs. Vcpo * 2 nA 1 10 % 3 15 % 2240 2600 3000 MHz MHz MHz MHz/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Design guarantee value Ta = 25C, Vcpo = VDD / 2 Vcpo : CP pin voltage Vcpo = VDD / 2, Ta = 25C Vcpo : CP pin voltage 0.5 Vcpo VDD - 0.5 Ta = 25C VCO Operating Frequency Range 1480 1728 2100 VCO tuning Sensitivity Phase Noise @ 1.6GHz (AK1573) @ 1.8GHz (AK1573B) @ 2.1GHz (AK1573C) OUTLV[2:0] bits "011" fvcox0.02 -86 -112 -133 -151 -223 Output Buffer 6 3 1 -5 10kHz offset 100kHz offset 1MHz offset 10MHz offset Normalized Phase Noise OUTPUT Power @1GHz Output Frequency dBm dBm dBm dBm MHz 30 AK1573 AK1573B AK1573C fvco : Oscillation Frequency VCOI bit = "1" VCOI bit = "1" VCOI bit = "1" VCOI bit = "1" Note 3 OUTLV[2:0] bits = "111" OUTLV[2:0] bits = "101" OUTLV[2:0] bits = "011" OUTLV[2:0] bits = "001" Design guarantee value Regulator VREF1 start-up time 10 ms Note * 1. Sink/Source current mismatch [(|Isink|-|Isource|)/{(|Isink|+|Isource|)/2}] * 100 [%] * 2. Icp v.s.Vcpo[{1/2*(|I1|-|I2|)}/{1/2*(|I1|+|I2|)}]*100 [%] * 3. Measured in-band phase noise with the loop locked. Normalized Phase Noise is calculated from following equation. REFIN frequency = 120MHz, FPFD = 10MHz. (PNtotal = PNsynth -10 Log FPFD- 20 Log N) PNtotal : Normalized Phase Noise PNsynth : In-band Phase Noise FPFD : PFD Frequency 015009351-E-00 2015/8 -8- [AK1573/AK1573B/AK1573C] Parameter Min. Typ. Max. Unit Description Current Consumption IDD1 10 A PDN1 pin = PDN2 pin = "L" (Full power down) IDD2 @1.6GHz (AK1573) @ OUTLV[2:0] bits = "001" VCOI bits = "0" @ OUTLV[2:0] bits = "011" VCOI bits = "0" @ OUTLV[2:0] bits = "111" VCOI bits = "0" @ OUTLV[2:0] bits = "111" VCOI bits = "1" 33 43 mA 62 66 93 IDD2 @1.8GHz (AK1573B) @ OUTLV[2:0] bits = "001" VCOI bits = "0" @ OUTLV[2:0] bits = "011" VCOI bits = "0" @ OUTLV[2:0] bits = "111" VCOI bits = "0" @ OUTLV[2:0] bits = "111" VCOI bits = "1" 34 44 mA 62 66 PDN1 pin = PDN2 pin = "H" DIV[2:0] bits = "000" PRE[1:0] bits = "00" 93 IDD2 @2.1GHz (AK1573C) @ OUTLV[2:0] bits = "001" VCOI bits = "0" @ OUTLV[2:0] bits = "011" VCOI bits = "0" @ OUTLV[2:0] bits = "111" VCOI bits = "0" @ OUTLV[2:0] bits = "111" VCOI bits = "1" 37 46 mA 64 68 93 IDD3 @1.6GHz (AK1573) @1.8GHz (AK1573B) @2.1GHz (AK1573C) DIV[2:0} bits "100" 75 105 mA PDN1 pin = PDN2 pin = "H" DIV[2:0] bits "000" PRE[1:0] bits = "00" IDD4 0.5 1 mA PDN1 pin = "H", PDN2 pin = "L" (power down except VBG / LDO) CP current adjusting resistance 22 27 33 k BIAS resistance Connect to BIAS pin Icp I1 I2 I2 I1 Isink Isource 0.5 CPVDD/2 CPVDD-0.5 Vcpo Figure.4 Charge Pump Characteristics - Voltage vs Current 015009351-E-00 2015/8 -9- [AK1573/AK1573B/AK1573C] 10.4. Loop filter Figure.5 shows loop filter topology used to evaluate AK1573, AK1573B and AK1573C. PFD Loop filter Up R3 CP R2 Down C1 C3 C2 Timer VCNT Figure.5 Loop Filter Schematic 015009351-E-00 2015/8 - 10 - [AK1573/AK1573B/AK1573C] 11. Typical Characteristics VDD=3.0V, Ta=25C, BIAS resistance =27k. 1. Analog Characteristics AK1573 Figure.6 Output power vs. Output frequency (a) VCOI bit = "0", DIV[2:0] bits = "000" (b) VCOI bit = "1", DIV[2:0] bits = "000" (c) Output frequency=1600MHz, VCOI bit="1" (d) Output frequency=2000MHz, VCOI bit="1" Figure.7 Current vs. OUTLV[2:0] bits 015009351-E-00 2015/8 - 11 - [AK1573/AK1573B/AK1573C] REFIN frequency = 100MHz, R counter = 100, CP1[2:0] bits = "111" (a) VCOI bit = "0" (b) VCOI bit = "1" Figure.8 Current vs. Output frequency REFIN frequency = 100MHz, R counter = 100, CP1[2:0] bits = "111", DIV[2:0] bits = "000" (a) VCOI bit = "0", DIV[2:0] bits = "000" (b) VCOI bit = "1", DIV[2:0] bits = "000" (c) VCOI bit = "1", DIV[2:0] bits = "001" (d) VCOI bit = "1", DIV[2:0] bits = "010" 015009351-E-00 2015/8 - 12 - [AK1573/AK1573B/AK1573C] (e) VCOI bit = "1", DIV[2:0] bits = "011" (f) VCOI bit = "1", DIV[2:0] bits = "100" (g) VCOI bit = "1", DIV[2:0] bits = "101" Figure.9 VCO Phase Noise vs. Output frequency OUTLV[2:0] bits = "111" Figure.10 VCO Phase Noise vs. Offset frequency Output frequency = 1602.8MHz, VCOI bit = "1", OUTLV[2:0] bits = "111" 015009351-E-00 2015/8 - 13 - [AK1573/AK1573B/AK1573C] Figure.11 VCO Tuning Sensitivity Figure.12 VCO Tuning Sensitivity (a) Output frequency = 1500MHz (b) Output frequency = 1600MHz (c) Output frequency = 2100MHz Figure.13 Closed loop Phase Noise REFIN frequency = 120MHz, R counter = 12, Prescaler = 8/9 Loop Filter : C1 = 33pF, C2 = 1500pF, C3 = N/A, R2 = 10k, R3 = 0 015009351-E-00 2015/8 - 14 - [AK1573/AK1573B/AK1573C] AK1573B Figure.14 Output power vs. Output frequency (a) VCOI bit = "0", DIV[2:0] bits = "000" (b) VCOI bit = "1" , DIV[2:0] bits = "000" (c) Output frequency=1800MHz, VCOI bit="1" (d) Output frequency=2600MHz, VCOI bit="1" Figure.15 Current vs. OUTLV[2:0] bits REFIN frequency = 100MHz, R counter = 100, CP1[2:0] bits = "111" 015009351-E-00 2015/8 - 15 - [AK1573/AK1573B/AK1573C] (a) VCOI bit = "0" (b) VCOI bit = "1" Figure.16 Current vs. Output frequency REFIN frequency = 100MHz, R counter = 100, CP1[2:0] bits = "111", DIV[2:0] bits = "000" (a) VCOI bit = "0", DIV[2:0] bits = "000" (b) VCOI bit = "1", DIV[2:0] bits = "000" (c) VCOI bit = "1", DIV[2:0] bits = "001" (d) VCOI bit = "1", DIV[2:0] bits = "010" 015009351-E-00 2015/8 - 16 - [AK1573/AK1573B/AK1573C] (e) VCOI bit = "1", DIV[2:0] bits = "011" (f) VCOI bit = "1", DIV[2:0] bits = "100" (g) VCOI bit = "1", DIV[2:0] bits = "101" (h) VCOI bit = "1", DIV[2:0] bits = "110" Figure.17 VCO Phase Noise vs. Output frequency OUTLV[2:0] bits = "111" Figure.18 VCO Tuning Sensitivity Figure.19 VCO Tuning Sensitivity 015009351-E-00 2015/8 - 17 - [AK1573/AK1573B/AK1573C] AK1573C Figure.20 Output power vs. Output frequency (a) VCOI bit = "0", DIV[2:0] bits = "000" (b) VCOI bit = "1" , DIV[2:0] bits = "000" (c) Output frequency=2100MHz, VCOI bit="1" (d) Output frequency=3000MHz, VCOI bit="1" Figure.21 Current vs. OUTLV[2:0] bits REFIN frequency = 100MHz, R counter = 100, CP1[2:0] bits = "111" 015009351-E-00 2015/8 - 18 - [AK1573/AK1573B/AK1573C] (a) VCOI bit = "0" (b) VCOI bit = "1" Figure.22 Current vs. Output frequency REFIN frequency = 100MHz, R counter = 100, CP1[2:0] bits = "111", DIV[2:0] bits = "000" (a) VCOI bit = "0", DIV[2:0] bits = "000" (b) VCOI bit = "1", DIV[2:0] bits = "000" (c) VCOI bit = "1", DIV[2:0] bits = "001" (d) VCOI bit = "1", DIV[2:0] bits = "010" 015009351-E-00 2015/8 - 19 - [AK1573/AK1573B/AK1573C] (e) VCOI bit = "1", DIV[2:0] bits = "011" (f) VCOI bit = "1", DIV[2:0] bits = "100" (g) VCOI bit = "1", DIV[2:0] bits = "101" (h) VCOI bit = "1", DIV[2:0] bits = "110" Figure.23 VCO Phase Noise vs. Output frequency OUTLV[2:0] bits = "111" Figure.24 VCO Tuning Sensitivity Figure.25 VCO Tuning Sensitivity 015009351-E-00 2015/8 - 20 - [AK1573/AK1573B/AK1573C] 12. Register Map Name A/B C/P Ref/Pres Function Data D19 to D0 0 0 0 0 Address 0 0 0 1 0 1 1 0 1 0 1 0 N D19 a D18 m e D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address A/B Don't care B [12] B [11] B [10] B [9] B [8] B [7] B [6] B [5] B [4] B [3] B [2] B [1] B [0] A [5] A [4] A [3] A [2] A [] A [] 0x01 C/P Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care CP2 [2] CP2 [1] CP2 [0] Don't care Don't care Don't care CP1 [2] CP1 [1] CP1 [0] 0x02 CALTM CALTM CALTM CALTM PRE [3] [2] [1] [1] [1] PRE [0] R [13] R [12] R [11] R [10] R [9] R [8] R [7] R [6] R [5] R [4] R [3] R [2] R [1] R [0] 0x03 Don't care VCOI FAST [3] FAST [2] FAST [1] FAST [0] 0x04 Ref/Pres Function Don't care Don't LDCNT FAST CPHiZ care SEL EN Software Reset LD DIV[2] DIV[1] DIV[0] MTLD OUTLV OUTLV OUTLV Don't [2] [1] [0] care Don't care 015009351-E-00 0x05 2015/8 - 21 - [AK1573/AK1573B/AK1573C] Notes on writing registers 1. When PDN1 pin = "H" and LDO (VREF1 pin) is active, access to the register is available 2. The setting of <Address0x02> and <Address0x03> will be reflected to the behavior of AK1573 when the register <Address0x01> is written 3. <Address0x04> can be written independently. 4. After PDN1 pin turns to "H", all of the register values are indefinite. It is needed to write the data to all the registers to confirm. Examples of the register setting Ex.1 Power on setting 1. Set PDN1 pin = "L" and PDN2 pin = "L" 2. Power on VCOVDD, PVDD and CPVDD Note) All VDD should be powered on simultaneously 3. Set PDN1 pin = "H" and PDN2 pin = "L" (VBG / LDO are powered on) 4. Write the data to the register <Address0x04> 5. Set PDN1 pin = "H" and PDN2 pin = "H" (All blocks are powered on) 6. Write the data to the register <Address0x01> and <Address0x02> 7. Write the data to the register <Address0x01> Ex.2 Change frequency settings 1. Write the data to the register <Address0x01> Ex.3 Change Charge Pump settings 1. Write the data to the register <Address0x02> 2. Write the data to the register <Address0x01> Ex.4 Change Reference dividing ratio 1. Write the data to the register <Address0x03> 2. Write the data to the register <Address0x01> 015009351-E-00 2015/8 - 22 - [AK1573/AK1573B/AK1573C] < Address0x01 : N counter > D[18:6] B[12:0] : B (Programmable) counter setting Set the dividing ratio of B (Programmable) counter. The setting range is shown in the following table. B[12:0] 0 1 2 3 : 8191 Programmable counter dividing ratio 3 : 8191 Remark Prohibited Prohibited Prohibited D[5:0] A[5:0] : A (Swallow) counter setting Set the dividing ratio of A (Swallow) counter. The setting range is shown in the following table. A[5:0] 0 1 2 : 63 Swallow counter dividing ratio 0 1 2 : 63 Remark The data at A[5:0] bits and B[12:0] bits must meet the following requirements: B[12:0] bits 3, B[12:0] bits A[5:0] bits See "13. Frequency Setting" for details of the relationship between a frequency dividing ratio N and the data at A[5:0] bits and B[12:0] bits. It is prohibited to set frequency once again until VCO calibration and Fast lock-up mode is completed. < Address0x02 : C/P > D[8: 6] CP2[2:0] : Charge pump current setting for Fast Lockup operation D[2:0] CP1[2:0] : Charge pump current setting for normal operation AK1573 provides two settings for charge pump current. CP1[2:0] bits are for normal operation and CP2[2:0] bits are for Fast Lockup mode. The following formula shows the relationship among the resistance value, the register setting and the electric current. Charge pump current (Icp) [A] = Icp_min [A] x [(CP1[2:0] bits or CP2[2:0] bits setting) + 1] Charge pump minimum current (Icp_min) [A] = 9.45 / BIAS Resistance [] 015009351-E-00 2015/8 - 23 - [AK1573/AK1573B/AK1573C] The following table shows the typical Icp for each status. Icp (typ.) unit : A CP1[2:0], CP2[2:0] 0 1 2 3 4 5 6 7 33k BIAS 27k 22k 286 573 859 1146 1432 1718 2005 2291 350 700 1050 1400 1750 2100 2450 2800 430 859 1289 1718 2148 2577 3007 3436 < Address0x03 : Ref/Pres > D[19:16] CALTM[3:0] Set the calibration precision of VCO The register CALTM[3:0] bits set the calibration precision and time. The larger CALTM[3:0] bits are set, the higher calibration precision becomes, but the longer calibration time is required as trade-off. Set the value calculated by the following formula to get enough calibration precision. However, CALTM[3:0] bits should be set from 0 to 10. Over 11 are prohibited. See "15. VCO" for details of the VCO calibration. CALTM[3:0] bits 10 - log (B[12:0] bits) / log(2) The calibration time can be estimated as following formula; Calibration time = 1 /FPFD x 11 x 2 ^ CALTM[3:0] bits D[15:14] PRE[1:0] : Selects a dividing ratio for the prescaler 00: P=8 01: P=16 10: P=32 11: P=64 The prescaler value should be selected so that the prescaler output frequency is less than or equal to 300MHz. 015009351-E-00 2015/8 - 24 - [AK1573/AK1573B/AK1573C] D[13:0] R[13:0] : 14bit Reference Counter The following settings can be selected for the reference clock division. The allowed range is 1 (1/1 division) to 16383 (1/16383 division). 0 cannot be set. The maximum PFD frequency is 104MHz. R[13:0] 0 1 2 3 4 : : : 16381 16382 16383 Dividing Ratio Prohibited 1 2 3 4 : : : 16381 16382 16383 < Address0x04 : Function > D[17] LDCNTSEL : Lock Detect Precision Set the counter value for digital lock detect. LDCNTSEL 0 1 Function 15 times Count 3 times Count 31 times Count 7 times Count unlocked to locked locked to unlocked unlocked to locked locked to unlocked D[16] FASTEN : Enables the Fast Lock mode See "14. Fast Lock-up mode" for details of the Fast Lock-up function. 0: Fast Lockup disable 1: Fast Lockup enable D[15] CPHIZ : TRI-STATE output setting for charge pump 0: Charge pumps are activated 1: Tri-State D[14] LD : Selects output from LD pin See "12. Lock detect" for details of the Lock detect function. 0: Digital lock detect 1: Analog lock detect 015009351-E-00 2015/8 - 25 - [AK1573/AK1573B/AK1573C] D[13:11] DIV[2:0] : Selects Divide of Output Select the dividing ratio in accordance with the used frequency. 0: 1: 2: 3: 4: 5: 6: 7: Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Prohibited D[10] MTLD : Local signal mute 0: Disable to mute local signal in unlock state. 1: Enable to Mute local signal in unlock state. Set MTLD bit = "0" when LD bit = "1". D[9:7] OUTLV[2:0] : Select output power level Adjust bias current of output buffer OUTLV[2:0] Bias current (mA) 0 1 2 3 4 5 6 7 4 8 12 16 20 24 28 32 D[4] VCOI : VCO core current setting 0: Low current mode 1: Normal 015009351-E-00 2015/8 - 26 - [AK1573/AK1573B/AK1573C] D[3:0] FAST[3:0] : FAST counter timer Set the effective time of fast lock-up mode. Counter value = 3 + FAST[3:0] bits x 4 FAST[3:0] Counter value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 < Address0x05 : Software Reset > When writing a <Address0x05>, all of the internal flip-flops, except for the register and calibration results, are initialized. Internal flip-flops except for the register and the calibration results is initialized in the state of PDN1 pin = PDN2 pin = "H". When standing up PDN1 pin and PDN2 pin at the same time or PDN1 pin and PDN2 pin are fixed to "H", internal flip-flops are not initialized. In this case, it is needed to initialize internal flip-flops using the Software Reset. 015009351-E-00 2015/8 - 27 - [AK1573/AK1573B/AK1573C] 13. Function Descriptions 13.1. Lock detect Lock detect output can be selected by LD bit in <Address0x04>. When LD bit = "1", LD pin outputs a phase comparison result which is from phase detector directly (This is called "analog lock detect"). When LD bit = "0", the output is the lock detect signal according to the on-chip logic (This is called "digital lock detect"). The digital lock detect can be done as following : The LD pin is in unlocked state (which outputs "L") when a frequency setup is made. In the digital lock detect, the LD pin outputs "H" (which means the locked state) when a phase error smaller than a cycle of [REFIN] clock (T) is detected for N times consecutively. When a phase error larger than T is detected for N times consecutively while the LD pin outputs "H", then the LD pin outputs "L" (which means the unlocked state). The counter value N can be set by LDCNTSEL bit in <Address0x04>. The N is different between "unlocked to locked" and "locked to unlocked". LDCNTSEL bit 0 1 unlocked to locked N=15 N=31 locked to unlocked N=3 N=7 The lock detect signal is shown below Reference clock Phase Comparison signal T/2 Divided VCO signal Phase detector output signal This is ignored because it cannot be sampled. Valid ignore ignore d Valid ignore The LD pin outputs HIGH when a phase error which is smaller than T/2 is detected for N times consecutively. LD pin output Case of R counter = 1 (Note) Reference clock Phase Comparison signal T Divided signal of RF signal PFD output signal This is ignored because it cannot be sampled. LD pin output Valid This is ignored because it cannot be sampled. Valid ignore The LD pin outputs will be HIGH when a phase error which is smaller than T is detected for N times consecutively. Case of R counter > 1 (Note) * R counter can be set by R[13:0] bits in Address0x03 Figure.26 Digital Lock Detect Operations 015009351-E-00 2015/8 - 28 - [AK1573/AK1573B/AK1573C] Unlock -> Lock Unlock(LD pin= "L") Flag=0 No Phase Error < T Yes Flag=Flag+1 No Flag>N Yes Lock(LD pin= "H") Lock -> Unlock Lock(LD pin= "H") Address2 write Flag=0 No Phase Error > T Yes Flag=Flag+1 No Flag>N Yes Unlock(LD pin= "L") 015009351-E-00 2015/8 - 29 - [AK1573/AK1573B/AK1573C] 13.2. Frequency Setting The following formula is used to calculate the frequency setting for the AK1573. Frequency Setting FPFD x ( P x B + A) FPFD : PFD frequency P : Prescalor value (refer to Address0x02 : Pre[1:0] ) B : B (Programmable) counter (refer to Address0x01 : B[12:0] ) A : A (Swallow)counter (refer to Address0x01 : A[5:0] ) Example Set the AK1573 as follows to obtain Frequency setting =2100MHz with FPFD = 200kHz P=8 ( Address0x02 : Pre[1:0] bits = 0 ) B = 1312 ( Address0x01 : B[12:0] bits = 1312 ) A=4 ( Address0x01 : A[5:0] bits = 4 ) Frequency setting = 200k x (8 x 1312 + 4) = 2100MHz Note) Lower limit for setting consecutive dividing numbers For the AK1573, it is not possible to set consecutive dividing ratio below the lower limit (The lower limit is determined by a dividing ratio set for the prescaler). The following table shows an example where consecutive dividing numbers below the lower limit cannot be set. The consecutive dividing ratio can be set when B P-1. *P=8 (Dual modulus prescaler 8/9) P B[12:0] A[5:0] Dividing ratio 8 6 6 54 8 7 0 56 8 : 8 8 : 7 : 7 8 : 1 : 7 0 : 57 : 63 64 : 55 cannot be set as an N divider. This is the lower limit. 56 or over can consecutively be set as an N divider. 015009351-E-00 2015/8 - 30 - [AK1573/AK1573B/AK1573C] *P=16 (Dual modulus prescaler 16/17) P B A N 16 14 14 238 16 15 0 240 16 : 16 16 : 15 : 15 16 : 1 : 15 0 : 241 : 255 256 : *P=32 (Dual modulus prescaler 32/33) P B A N 32 30 30 990 32 31 0 992 32 : 32 32 : 31 : 31 32 : 1 : 31 0 : 993 : 1023 1024 : *P=64 (Dual modulus prescaler 64/65) P B A 239 cannot be set as an N divider. This is the lower limit. 240 or over can consecutively be set as an N divider. 991 cannot be set as an N divider. This is the lower limit. 992 or over can consecutively be set as an N divider. N 64 62 62 4030 64 63 0 4032 64 : 64 64 : 63 : 63 64 : 1 : 63 0 : 4033 : 4095 4096 : 015009351-E-00 4031 cannot be set as an N divider. This is the lower limit. 4032 or over can consecutively be set as an N divider. 2015/8 - 31 - [AK1573/AK1573B/AK1573C] 13.3. Fast Lock-up mode The AK1573 goes into Fast Lock Up mode by setting FASTEN bit in <Address0x04> to "1". When A and B counter setting is finished (writing in <Address0x01>), Fast Lock Up mode starts after calibration. The Fast Lock Up mode is enabled only during the time period set by the timer according to the counter value in FAST[3:0] bits in <Address0x04>. The charge pump current is set to the value specified by CP2[2:0] bits. When the specified time period elapses, the Fast Lock Up mode operation is switched to the normal operation, and the charge pump current returns to CP1[2:0] bits setting. FAST[3:0] bits in <Address0x04> is used to set the time period for this mode. The following formula is used to calculate the time period : Switchover time = 1 / FPFD x Counter Value Counter Value = 3 + 4 x ( FAST[3:0] bits setting ) Fast Lock Up time specified by the timer Operation mode Charge pump current Normal Calibration Fast Lock Up Normal CP1[2:0] bits Hi-Z CP2[2:0] bits CP1[2:0] bits Frequency setting (Write in <Address0x01>) Figure.27 Fast Lock-up Mode Timing Chart 015009351-E-00 2015/8 - 32 - [AK1573/AK1573B/AK1573C] 13.4. VCO Calibration The VCO core in AK1573 uses several overlapping bands to achieve low Phase Noise, low VCO sensitivity (KVCO) and wide frequency range. The correct band is chosen automatically at frequency setting by VCO calibration. The calibration starts when A counter and B counter in <Address0x01> are set. During the calibration, VCO VCNT is disconnected from the external loop filter and connected to an internal reference voltage. The charge pump output is Tri-State. The internal reference voltage must be stable so that the calibration is done correctly. Therefore, it is necessary to wait 10sec at least until <Address0x01> is set after PDN2 pin rises up to "1" (when 100pF is connected to SCAP pin). The register CALTM[3:0] bits set the calibration precision and time. The larger CALTM[3:0] bits are set, the higher calibration precision becomes, but the longer calibration time is required as trade-off. Set the value calculated by the following formula to get enough calibration precision. However, CALTM[3:0] bits should be set from 0 to 10. Over 11 are prohibited. CALTM[3:0] bits 10 - log( B[12:0] ) / log(2) The calibration time can be estimated as following formula; Calibration time = 1 /FPFD x 11 x 2 ^ CALTM[3:0] bits It is prohibited to set frequency once again until VCO calibration and Fast lock-up mode is completed. Low Current Mode The AK1573 goes into low current mode by setting VCOI bit in <Address0x04> to "0". This mode decreases VCO core current but Phase Noise gets worse compared to normal mode. 015009351-E-00 2015/8 - 33 - [AK1573/AK1573B/AK1573C] 14. Power on sequence 1. Recommended sequence PVDDAVDD CPVDD PDN1 Register Writing available LDO 10s ON OFF 10ms <0x04> Register Writing <0x03> <0x02> <0x01> <0x01> PDN2 Synth /VCO Unstable PDN Active 2. The sequence when PDN1 pin and PDN2 pin are powered on simultaneously PVDDAVDD CPVDD PDN1 Register Writing available LDO ON OFF 10ms <0x05> Register Writing <0x04> <0x03> <0x02> <0x01> PDN2 Synthe VCO PDN Un-stable Active Figure.28 Power on sequence * After powering on AK1573, the initial register's values are not defined. It is required to write the data to all the registers. * It takes about 10msec from PDN1 pin rise-up to LDO rise-up. * If PDN1 pin and PDN2 pin are powered on simultaneously, the operation of AK1573 is not defined until the registers are set. 015009351-E-00 2015/8 - 34 - [AK1573/AK1573B/AK1573C] 15. Recommended External Circuits Figure.29. Evaluation Board Schematic Ref. C1 C2 C3 C4 C5 C6 Value Loop Filter Loop Filter Loop Filter 470nF 100pF 10nF Ref. C7 C8 C9 C10 C11 C12 Value 100pF 100pF 100pF 100pF 10nF 220nF Table.1 Ref. C13 C14 C15 L1 L2 R2 Value 100pF 100pF 10nF 2.2H 2.2H Loop Filter Ref. R3 R1 R5 R6 R7 R8 Value Loop Filter 27k 100 100 51 51 * The exposed pad at the center of the backside should be connected to the ground. * TEST1 / TEST2 pins should be connected to the ground. * RFOUT_P / RFOUT_N pins must be connected an inductor and a register to VDD. * In the case of single-ended output operation, unused output pin is terminated through 50 after 100pF capacitance. 015009351-E-00 2015/8 - 35 - [AK1573/AK1573B/AK1573C] 16. Application Note Differential to single-ended circuit AK1573 has differential output ports. "15 Recommended External Circuits" shows single-ended output but users can convert differential output to single output using lumped element balun. By doing this, AK1573 outputs higher signal level compared to single-ended output with the same current consumption. Lumped element balun shows frequency dependence, so users need to populate optimized elements in order to obtain good matching characteristics. Table.2 shows the reference values of lumped element balun. VDD AK1573 R10 C21 RFOUT_N L11 C22 Signal Output C20 L12 RFOUT_P R11 L10 VDD Figure 30 Lumped Element Balun Circuit Table.2 Reference values of lumped element balun Frequency Range [MHz] C20 [pF] C21 [pF] C22 [pF] L10 [nH] L11 [nH] L12 [nH] R10 [] R11 [] 2150 to 2250 2000 to 2150 1900 to 2000 1770 to 1900 1600 to 1770 1450 to 1600 1280 to 1450 1050 to 1280 800 to 1050 550 to 800 350 to 550 200 to 350 100 to 200 60 to 100 40 to 60 30 to 40 1 1 1 1 1 1 1 1 1 1 1.6 4.7 8 15 27 39 1 1 1 1 1 1 1 1 1 1 1.6 4.7 8 15 27 39 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1 1.5 2 2.4 3.3 4.3 5.1 7.5 10 15 22 47 82 150 270 390 1 1.5 2 2.4 3.3 4.3 5.1 7.5 10 15 22 47 82 150 270 390 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 015009351-E-00 2015/8 - 36 - [AK1573/AK1573B/AK1573C] 17. Interface circuit Pin No. 9 17 18 19 20 7 8 Pin name I/O PDN1 PDN2 CLK DATA LE I I I I I R0 () 300 300 300 300 300 TEST1 TEST2 I I 300 300 Current (A) Function Digital input pin R0 Digital input (Pull-Down) R0 100k 21 LD O 3 16 VCNT REFIN I I Digital output pin 100 300 Analog input pin R0 015009351-E-00 2015/8 - 37 - [AK1573/AK1573B/AK1573C] Pin No. 1 2 4 15 R0 () 300 300 100 300 Current (A) Pin Name I/O Function BIAS VREF2 SCAP VREF1 IO IO IO IO 23 CP O Analog output pin 11 12 RFOUT_P RFOUT_N O O Open-collector output pin Analog input/output pin R0 015009351-E-00 2015/8 - 38 - [AK1573/AK1573B/AK1573C] 18. Package 18.1. Outline Dimensions * The exposed pad at the center of the backside should be connected to ground. 015009351-E-00 2015/8 - 39 - [AK1573/AK1573B/AK1573C] 18.2. Marking (a) Style (b) Number of pins (c) 1 pin marking (d) Product number AK1573 AK1573B AK1573C : QFN : 24-pin : : XXXX (4 or 5 digits) : AK1573 : AK1573B : AK1573C (e) Date code : YWWL (4 digits) Y: Lower 1 digit of calendar year (Year 2015 5, 2016 6 ...) WW: Week L: Lot identification, given to each product lot which is made in a week LOT ID is given in alphabetical order (A, B, C...) XXXX YWWL (d) (e) (c) 015009351-E-00 2015/8 - 40 - [AK1573/AK1573B/AK1573C] 19. Revision History Date (Y/M/D) 15/08/03 Revision 00 Reason First Edition Page 015009351-E-00 Contents 2015/8 - 41 - [AK1573/AK1573B/AK1573C] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 015009351-E-00 2015/8 - 42 -