TDA5103AHTMA1 - INFINEON TECHNOLOGIES AG

Wireless Components

ASK Transmitter 345 MHz

TDA 5103A Version 1.0

Specification March 2001

preliminary

Edition 15.02.2001

Published by Infineon Technologies AG,

Balanstraße 73,

81541 München

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Revision History

Current Version: 1.0, March 2001

Previous Version: 0.1, February 2000

Page

(in previous

Version)

Page

(in current

Version)

Subjects (major changes since last revision)

3-3 ... 3-5 Interface schematics inserted

3-4, 3-5 4-5, 4-6 Hints on the crystal oszillator revised and moved to paragraph applications

3-5, 3-6 3-8, 3-9 Tables adapted, description of power modes revised

3-10 Timing diagram added

4-1, 4-2 4-1 ... 4-6 new

5-3, 5-4 5-3 ... 5-5 Table corrected for pin1: „V > 1.4 V“ replaced by „pin open“

VCO frequency range added, some limits adapted

5-6 ... 5-6 Table inserted: AC/DC characteristics over full supply- and temperature range

Product Info

Wireless Components

Specification, March 2001

Package

TDA 5103A

preliminary

Product Info

General Description The TDA 5103A is a single chip ASK

transmitter for the frequency band 344-

347 MHz. The IC offers a high level of

integration and needs only a few exter-

nal components. The device contains a

fully integrated PLL synthesizer and a

high efficiency power amplifier to drive

a loop antenna. A special circuit design

and an unique power amplifier design

are used to save current consumption

and therefore to save battery life. Addi-

tionally features like a power down

mode, a low power detect and a divided

clock output are implemented.

Features



fully integrated

frequency synthesizer



VCO without external components



high efficiency power amplifier



frequency range 344-347 MHz



ASK modulation



low supply current (typically 7mA)



voltage supply range 2.1 - 4 V



power down mode



low voltage sensor



clock output for µC



low external component count

Applications



Keyless entry systems



Remote control systems



Alarm systems



Communication systems

Ordering Information

Type Ordering Code Package

TDA 5103A Q67036-A1121 P-TSSOP-10

available on tape and reel

1Table of Contents

1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i

2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

4.1 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.4 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

2Product Description

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Contents of this Chapter

Product Description

2 - 2

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

2.1 Overview

The TDA 5103A is a single chip ASK transmitter for the frequency band 344-

347 MHz. The IC offers a high level of integration and needs only a few external

components. The device contains a fully integrated PLL synthesizer and a high

efficiency power amplifier to drive a loop antenna. A special circuit design and

an unique power amplifier design are used to save current consumption and

therefore to save battery life. Additional features like a power down mode, a low

power detect and a divided clock output are implemented.

2.2 Applications



Keyless entry systems



Remote control systems



Alarm systems



Communication systems

2.3 Features



fully integrated frequency synthesizer



VCO without external components



high efficiency power amplifier



frequency range 344-347 MHz



ASK modulation



low supply current (typically 7 mA)



voltage supply range 2.1 - 4 V



power down mode



low voltage sensor



clock output for µC



low external component count

Product Description

2 - 3

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

2.4 Package Outlines

Figure 2-1 P-TSSOP-10

0.09

±0.1

0.42 -0.1

+0.15

+0.08

-0.05

0.125

6 max.

0.1

4.9 M

0.25 ABC

3±0.1

0.08 M

0.22±0.05

0.15 max.

±0.1

0.85

1.1 max.

0.5

Index Marking

3Functional Description

3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.4 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.1 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.3 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4.4 Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4.5 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4.5.1 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4.5.2 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4.5.3 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4.5.4 Power mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4.6 Recommended timing diagram for ASK-Modulation . . . . . . . . . . . 3-10

Contents of this Chapter

Functional Description

3 - 2

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

3.1 Pin Configuration

Pin_config.wmf

Figure 3-1 IC Pin Configuration

Table 3-1Pin Configuration

Pin No. Symbol Function

1PDWN Power Down Mode Control

2VS Voltage Supply

3GND Ground

4LF Loop Filter

5DATA Amplitude Shift Keying Data Input

6CLKOUT Clock Driver Output

7COSC Crystal Oscillator Input

8PAGND Power Amplifier Ground

9PAOUT Power Amplifier Output

10 LPD Low Power Detect Output

LPD

PAOUT

PAGND

COSC

CLKOUT

PDWN

GND

DATA

TDA 5103A

Functional Description

3 - 3

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

3.2 Pin Definitions and Functions

Table 3-2

No.

Symbol Interface Schematic Function

1PDWN Disable pin for the complete transmitter cir-

cuit.

A logic low (PDWN < 0.7 V) turns off all

transmitter functions.

A logic high (PDWN > 1.5 V) gives access to

all transmitter functions.

PDWN input will be pulled up by 40 µA inter-

nally by setting DATA to a logic high-state.

2VS This pin is the positive supply of the trans-

mitter electronics.

An RF bypass capacitor should be con-

nected directly to this pin and returned to

GND (pin 3) as short as possible.

3GND General ground connection.

4LF Output of the charge pump and input of the

VCO control voltage.

The loop bandwidth of the PLL is 150 kHz

when only the internal loop filter is used.

The loop bandwidth may be reduced by

applying an external RC network referencing

to the positive supply VS (pin 2).

150 k

Ω

5 k

Ω

250 k

Ω

"ON"

∗

DATA

10 k

Ω

35 k

Ω

15 pF

140 pF

Functional Description

3 - 4

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

5DATA Digital amplitude modulation can be

imparted to the Power Amplifier through this

pin.

A logic high (DATA > 1.5 V or open) enables

the Power Amplifier.

A logic low (DATA < 0.5 V)

disables the Power Amplifier.

6CLKOUT Clock output to supply an external device.

An external pull-up resistor has to be added

in accordance to the driving requirements of

the external device.

The clock output frequency is 2.7 MHz when

a crystal of 10.78 MHz is used.

7COSC This pin is connected to the reference oscil-

lator circuit.

The reference oscillator is working as a neg-

ative impedance converter. It presents a

negative resistance in series to an induc-

tance at the COSC pin.

The resonance frequency of the crystal

should be 10.78 MHz to achieve an output

frequency of 345 MHz.

+1.2 V

90 k

Ω

50 pF 30



60 k

Ω

+1.1 V

300

Ω

6 k



100



Functional Description

3 - 5

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

8PAG N D Ground connection of the power amplifier.

The RF ground return path of the power

amplifier output PAOUT (pin 9) has to be

concentrated to this pin.

9PAO U T RF output pin of the transmitter.

A DC path to the positive supply VS has to

be supplied by the antenna matching net-

work.

10 LPD This pin provides an output indicating the

low-voltage state of the supply voltage VS.

VS < 2.15 V will set LPD to the low-state.

An internal pull-up current of 40 µA gives the

output a high-state at supply voltages above

2.15 V.

300

Ω

40 µA

Functional Description

3 - 6

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

3.3 Functional Block diagram

Block_diagram.wmf

Figure 3-2 Functional Block diagram

XTAL PD :64 VCO :2 Power

AMP

Low voltage

Sensor

Power

Supply

Crystal

Oscillator

Input

Clock

Output

Power Down

Control

Positive

Supply

Low Power

Detect Output

Power

Am plifier

Ground

Power

Am plifier

Output

DATA

Input

Loop

Filter

Ground

GND

Functional Description

3 - 7

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

3.4 Functional Blocks

3.4.1 PLL Synthesizer

The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator

(VCO), an asynchronous divider chain, a phase detector, a charge pump and a

loop filter. It is fully implemented on chip. The tuning circuit of the VCO consist-

ing of spiral inductors and varactor diodes is on chip, too. Therefore no addi-

tional external components are necessary. The nominal center frequency of the

VCO is 690 MHz. The oscillator signal is fed both, to the synthesizer divider

chain and to the power amplifier. The overall division ratio of the asynchronous

divider chain is 64, a 10.78 MHz crystal should be used. The phase detector is

a Type IV PD with charge pump. The passive loop filter is realized on chip.

3.4.2 Crystal Oscillator

The crystal oscillator operates at 10.78 MHz.

The output frequency at CLKOUT (pin 6) is 2.7 MHz, this is the crystal fre-

quency divided by 4.

3.4.3 Power Amplifier

The VCO frequency 688-694 MHz is divided by 2 and fed to the power amplifier.

The Power Amplifier can be switched on and off

by the signal at DATA (pin 5).

The Power Amplifier has an Open Collector output at PAOUT (pin 9) and

requires an external pull-up coil to provide bias. The coil is part of the tuning and

matching LC circuitry to get best performance with the external loop antenna.

To achieve the best power amplifier efficiency, the high frequency voltage swing

at PAOUT (pin 9) should be twice the supply voltage.

The power amplifier has its own ground pin PAGND (pin 8) in order to reduce

the amount of coupling to the other circuits.

Table 3-3

DATA (pin 5) Power Amplifier

Low1)

1) Low: Voltage at pin < 0.5 V

OFF

Open2), High3)

2) Open: Pin open

3) High: Voltage at pin > 1.5 V

Functional Description

3 - 8

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

3.4.4 Low Power Detect

The supply voltage is sensed by a low power detector. When the supply voltage

drops below 2.15 V, the output LPD (pin 10) switches to the low-state. To min-

imize the external component count, an internal pull-up current of 40 µA gives

the output a high-state at supply voltages above 2.15 V.

The output LPD (pin 10) can either be connected to DATA (pin 5) to switch off

the PA as soon as the supply voltage drops below 2.15 V or it can be used to

inform a micro-controller to stop the transmission after the current data packet.

3.4.5 Power Modes

The IC provides three power modes, the POWER DOWN MODE, the PLL

ENABLE MODE and the TRANSMIT MODE.

3.4.5.1 Power Down Mode

In the POWER DOWN MODE the complete chip is switched off.

The current consumption is less than 100nA.

3.4.5.2 PLL Enable Mode

In the PLL ENABLE MODE the PLL is switched on but the power amplifier is

turned off to avoid undesired power radiation during the time the PLL needs to

settle. The turn on time of the PLL is determined mainly by the turn on time of

the crystal oscillator and is typically less than 1 msec, depending on the crystal.

The current consumption is typically 3.5 mA.

3.4.5.3 Transmit Mode

In the TRANSMIT MODE the PLL is switched on and the power amplifier is

turned on too.

The current consumption of the IC is typically 7 mA when using a proper trans-

forming network at PAOUT, see Figure 4-1.

3.4.5.4 Power mode control

The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1).

When the bias circuitry is powered up, the pin DATA is pulled up internally.

Forcing the voltage at the pin DATA low overrides the internally set state.

The principle schematic of the power mode control circuitry is shown in

Figure 3-5.

Functional Description

3 - 9

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

Power_Mode.wmf

Figure 3-5 Power mode control circuitry

Table 3-4 provides a listing of how to get into the different power modes

Other combinations of the control pins PDWN and DATA are not recom-

mended.

Table 3-4

PDWN DATA MODE

Low1)

1) Low: Voltage at pin < 0.7 V (PDWN)

Voltage at pin < 0.5 V (DATA)

Low, Open2)

2) Open: Pin open

POWER DOWN

High3)

3) High: Voltage at pin > 1.5 V

Low PLL ENABLE

High Open, High TRANSMIT

Bias

Source

DATA

PDWN

PAOUT

Bias Voltage

120 k



PLL 345

MHz

Functional Description

3 - 10

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

3.4.6 Recommended timing diagram for ASK-Modulation

ASK_mod.wmf

Figure 3-6 Recommended Timing Diagram for ASK Modulation

PDWN

High

Low

DATA

min. 1 msec.

DATA

Open, High

Low

Modes: TransmitPLL EnablePower Down

4Applications

4.1 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 4-4

4.4 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Contents of this Chapter

Applications

4 - 2

TDA 5103 A

preliminary

Wireless Components

Specification, March 2001

4.1 50 Ohm-Output Testboard Schematic

50ohm_test_v5.wmf

Figure 4-1 50 Ω-Output testboard schematic

VCC

TDA5103A

R1 C5

X1SMA

X2SMA

VCC

CLKOUT

Applications

4 - 3

TDA 5103 A

preliminary

Wireless Components

Specification, March 2001

4.2 50 Ohm-Output Testboard Layout

Figure 4-2 Top Side of TDA 5103A-Testboard with 50 Ω-Output

It is the same testboard as for an other product

Figure 4-3 Bottom Side of TDA 5103A-Testboard with 50 Ω-Output

It is the same testboard as for an other product

Applications

4 - 4

TDA 5103 A

preliminary

Wireless Components

Specification, March 2001

4.3 Bill of material (50 Ohm-Output Testboard)

Table 4-1 Bill of material

Part Value Specification

R1 4.7 kΩ0805, ± 5%

R4 open 0805, ± 5%

R5 open 0805, ± 5%

C1 47 nF 0805, X7R, ± 10%

C2 330 pF 0805, COG, ± 5%

C3 3.9 pF 0805, COG, ± 0.1 pF

C4 68 pF 0805, COG, ± 5%

C5 1 nF 0805, X7R, ± 10%

C6 tbd 0805, COG, ± 0.1 pF

C8 10 pF 0805, COG, ± 5%

L1 220 nH TOKO LL2012-J

L2 56 nH TOKO LL2012-J

Q1 10.78 MHz

IC1 TDA 5103A

T1 Push-button replaced by a short

B1 Battery clip HU2031-1,RENATA

X1 SMA-S SMA standing

X2 SMA-S SMA standing

Applications

4 - 5

TDA 5103 A

preliminary

Wireless Components

Specification, March 2001

4.4 Hints

1. Application Hints on the crystal oscillator

As mentioned before, the crystal oscillator achieves a turn on time less than

1 msec. To achieve this, a NIC oscillator type is implemented in the TDA 5103A.

The input impedance of this oscillator is a negative resistance in series to an

inductance. Therefore the load capacitance of the crystal CL (specified by the

crystal supplier) is transformed to the capacitance Cv.

CL: crystal load capacitance for nominal frequency

ω: angular frequency

L: inductance of the crystal oscillator

Example:

Assume a crystal frequency of 10.78 MHz and a crystal load capacitance of CL

= 12 pF. The inductance L is specified within the electrical characteristics at

10.78 MHz to a value of 11 µH. Therefore C6 is calculated to 7.5 pF.

-R L f, CL Cv

Cv =

Formula 1)

Applications

4 - 6

TDA 5103 A

preliminary

Wireless Components

Specification, March 2001

2. Design hints on the buffered clock output (CLKOUT)

The CLKOUT pin is an open collector output. An external pull up resistor (RL)

should be connected between this pin and the positive supply voltage. The

value of RL is depending on the clock frequency and the load capacitance CLD

(PCB board plus input capacitance of the microcontroller). RL can be calculated

to:

Remark: To achieve a low current consumption and a low

spurious radiation, the largest possible RL should be chosen.

Table 4-2

fCLKOUT=

2.7 MHz

CL[pF]RL[kOhm]

58.2

10 4.7

20 2.2

CLDfCLKOUT

RL *8*

5Reference

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3.1 AC/DC Characteristics at 3V, 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -25°C ... +85°C. . . . . . . . . . 5-5

Contents of this Chapter

Reference

5 - 2

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

5.1 Absolute Maximum Ratings

The AC / DC characteristic limits are not guaranteed. The maximum ratings

must not be exceeded under any circumstances, not even momentarily and

individually, as permanent damage to the IC may result.

Ambient Temperature under bias: TA=-25°C to +85°C

5.2 Operating Range

Within the operating range the IC operates as described in the circuit

description.

Table 5-1 Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Remarks

Min Max

Junction Temperature TJ-40 150 °C

Storage Temperature Ts-40 125 °C

Thermal Resistance RthJA 220 K/W

ESD integrity, all pins VESD -1 +1 kV 100 pF, 1500 Ω

Table 5-2 Operating Range

Parameter Symbol Limit Values Unit Test Conditions

Min Max

Supply voltage VS2.1 4.0 V

Ambient temperature TA-25 85 °C

Reference

5 - 3

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

5.3 AC/DC Characteristics

5.3.1 AC/DC Characteristics at 3V, 25°C

Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C

Parameter Symbol Limit Values Unit Test Conditions

Min Typ Max

Current consumption

Power down mode IS PDWN 100 nA V (Pins 1 and 5) = 0 V

PLL enable mode IS PLL_EN 3.3 4.2 mA

Transmit mode IS TRANSM 79mA Load tank see

Figure 4-1

Power Down Mode Control (Pin 1)

Power down mode VPDWN 00.7 VV

DATA < 0.2 V

PLL enable mode VPDWN 1.5 VSVV

DATA < 0.5 V

Transmit mode VPDWN 1.5 VSVV

DATA > 1.5 V

Input bias current PDWN IPDWN 30 µA VPDWN = VS

Loop Filter (Pin 4)

VCO tuning voltage VLF VS - 1.3 VS - 0.8 Vf

VCO = 690 MHz

Output frequency range

345 MHz-band

fOUT, 345 338 345 352 MHz VS-VLF = 0.6V...1.6V

ASK Modulation Data Input (Pin 5)

Transmit disabled VDATA 00.5 V

Transmit enabled VDATA 1.5 VSV

Input bias current DATA IDATA 30 µA VDATA = VS

Input bias current DATA IDATA -20 µA VDATA = 0 V

ASK data rate fDATA 20 kHz

Reference

5 - 4

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C

Parameter Symbol Limit Values Unit Test Conditions

Min Typ Max

Clock Driver Output (Pin 6)

Output current (Low) ICLKOUT 1mA VCLKOUT = VS

Output current (High) ICLKOUT -40 µA VCLKOUT = 0 V

Saturation Voltage (Low) VSATL 0.9 VI

CLKOUT = 1 mA

Saturation Voltage (High) VSATH VS - 0.9 VI

CLKOUT = 0 mA

Crystal Oscillator Input (Pin 7)

Load capacitance CCOSCmax 5pF

Serial Resistance of the crys-

tal

100 Ωf = 10.78 MHz

Input inductance of the

COSC pin

11 µH f = 10.78 MHz

Power Amplifier Output (Pin 9)

Output Power1)

transformed to 50 Ohm

POUT345 357dBm fOUT = 345 MHz

Low Power Detect Output (Pin 10)

Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS

Input current low voltage I LPD2 1mA VS = 1.9 V ... 2.1 V

1) Power amplifier in overcritical C-operation.

Matching circuitry as used in the 50 Ohm-Output Testboard.

Reference

5 - 5

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

5.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -25°C ... +85°C

Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C

Parameter Symbol Limit Values Unit Test Conditions

Min Typ Max

Current consumption

Power down mode IS PDWN 250 nA V (Pins 1 and 5) = 0 V

PLL enable mode IS PLL_EN 3.3 4.6 mA

Transmit mode IS TRANSM 79.5mA Load tank see

Figure 4-1

Power Down Mode Control (Pin 1)

Power down mode VPDWN 00.5 VV

DATA < 0.2 V

PLL enable mode VPDWN 1.5 VSVV

DATA < 0.5 V

Transmit mode VPDWN 1.5 VSVV

DATA > 1.5 V

Input bias current PDWN IPDWN 30 µA VPDWN = VS

Loop Filter (Pin 4)

VCO tuning voltage VLF VS - 1.5 VS - 0.65 Vf

VCO = 690 MHz

Output frequency range

345 MHz-band

fOUT, 315 343.5 345 347.5 MHz VS-VLF = 0.6V...1.6V

ASK Modulation Data Input (Pin 5)

Transmit disabled VDATA 00.5 V

Transmit enabled VDATA 1.5 VSV

Input bias current DATA IDATA 30 µA VDATA = VS

Input bias current DATA IDATA -20 µA VDATA = 0 V

ASK data rate fDATA 20 kHz

Reference

5 - 6

TDA 5103A

preliminary

Wireless Components

Specification, March 2001

Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C

Parameter Symbol Limit Values Unit Test Conditions

Min Typ Max

Clock Driver Output (Pin 6)

Output current (Low) ICLKOUT 1mA VCLKOUT = VS

Output current (High) ICLKOUT -40 µA VCLKOUT = 0 V

Saturation Voltage (Low) VSATL 0.9 VI

CLKOUT = 1 mA

Saturation Voltage (High) VSATH VS - 0.9 VI

CLKOUT = 0 mA

Crystal Oscillator Input (Pin 7)

Load capacitance CCOSCmax 5pF

Serial Resistance of the crys-

tal

100 Ωf = 10.78 MHz

Input inductance of the

COSC pin

11 µH f = 10.78 MHz

Power Amplifier Output (Pin 9)

Output Power1)

transformed to 50 Ohm

POUT345 -2.5 2.5 5.5 dBm Vs = 2.2 V2)

POUT345 058dBm Vs = 3.0 V

POUT345 2710dBm Vs = 4.0 V

Low Power Detect Output (Pin 10)

Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS

Input current low voltage I LPD2 1mA VS = 1.9 V ... 2.1 V

1) Power amplifier in overcritical C-operation.

Matching circuitry as used in the 50 Ohm-Output Testboard.

Supply-voltage dependency: 2 dB / V at 3 V with reference to 3 V.

A smaller load impedance reduces the supply-voltage dependency.

Temperature dependency: +1 dB at -25°c and -3 dB at +85°C with reference to +25°C.

A higher load impedance reduces the temperature dependency.

2) Power amplifier is switched off at 2.15 V