R01DS0065EJ0120 Rev.1.20 Page 1 of 123
Feb 6, 2013
R32C/118 Group
RENESAS MCU
R01DS0065EJ0120
Rev.1.20
Feb 6, 2013
Datasheet
R32C/118 Group Datasheet
1. Overview
1.1 Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM
code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing
in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from
low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral
functions, provides support for a vast range of application fields.
The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory
space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,
multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on-
chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and watchdog timer
enables to minimize external components.
The R32C/118 Group is the standard MCU within the R32C/100 Series. This product, provided as 100-pin
and 144-pin plastic molded LQFP packages, has nine channels of serial interface, one channel of multi-
master I2C-bus interface, and two channels of CAN module.
1.1.1 Applications
Car audio, audio, printer, office/industrial equipment, etc.
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Feb 6, 2013
R32C/118 Group 1. Overview
1.1.2 Performance Overview
Tables 1.1 to 1.4 list the performance overview of the R32C/118 Group.
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
Table 1.1 Performance Overview for the 144-pin Package (1/2)
Unit Function Explanation
CPU Central
processing unit
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 compatible FPU: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional (1))
Memory Flash memory: 384 Kbytes to 1 Mbyte
RAM: 40 K/48 K/63 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for each product’s memory size
Voltage
Detector
Low voltage
detector
Optional (1)
Low voltage detection interrupt
Clock Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
External Bus
Expansion
Bus and memory
expansion
• Address space: 4 Gbytes (of which up to 64 Mbytes is user
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16/32 bits)
Interrupts Interrupt vectors: 261
External interrupt inputs: NMI, INT × 9, key input × 4
Interrupt priority levels: 7
Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output)
DMA DMAC 4 channels
• Cycle-steal transfer mode
• Request sources: 57
• 2 transfer modes: Single transfer, repeat transfer
DMAC II • Triggered by an interrupt request of any peripheral
• 3 characteristic transfer functions: Immediate data transfer,
calculation result transfer, chain transfer
I/O Ports Programmable
I/O ports
• 2 input-only ports
• 120 CMOS I/O ports (of which 32 are 5 V tolerant)
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
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Feb 6, 2013
R32C/118 Group 1. Overview
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
Table 1.2 Performance Overview for the 144-pin Package (2/2)
Unit Function Explanation
Timer Timer A 16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-
phase encoder input) × 3
Timer B 16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
Serial
Interface
UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels
•I
2C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
• IEBus (optional (1)) (UART0 to UART6)
A/D Converter 10-bit resolution × 34 channels
Sample and hold functionality integrated
D/A Converter 8-bit resolution × 2
CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter 16 bits × 16 bits
Intelligent I/O Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 24
Serial interface: Variable-length synchronous serial I/O mode, IEBus
mode (optional (1))
Multi-master I2C-bus Interface 1 channel
CAN Module 2 channels
CAN functionality compliant with ISO 11898-1
32 mailboxes
Flash Memory Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
64 MHz (high speed version)/VCC = 3.0 to 5.5 V
50 MHz (normal speed version)/VCC = 3.0 to 5.5 V
Operating Temperature -20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
Current Consumption 45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package 144-pin plastic molded LQFP (PLQP0144KA-A)
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Feb 6, 2013
R32C/118 Group 1. Overview
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
Table 1.3 Performance Overview for the 100-pin Package (1/2)
Unit Function Explanation
CPU Central
processing unit
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit
• IEEE-754 compatible FPU: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional (1))
Memory Flash memory: 384 Kbytes to 1 Mbyte
RAM: 40 K/48 K/63 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for each product’s memory size
Voltage
Detector
Low voltage
detector
Optional (1)
Low voltage detection interrupt
Clock Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
External Bus
Expansion
Bus and memory
expansion
• Address space: 4 Gbytes (of which up to 64 Mbytes is user
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16 bits)
Interrupts Interrupt vectors: 261
External interrupt inputs: NMI, INT × 6, key input × 4
Interrupt priority levels: 7
Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output)
DMA DMAC 4 channels
• Cycle-steal transfer mode
• Request sources: 51
• 2 transfer modes: Single transfer, repeat transfer
DMAC II • Triggered by an interrupt request of any peripheral
• 3 characteristic transfer functions: Immediate data transfer,
calculation result transfer, chain transfer
I/O Ports Programmable
I/O ports
• 2 input-only ports
• 84 CMOS I/O ports (of which 32 are 5 V tolerant)
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
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Feb 6, 2013
R32C/118 Group 1. Overview
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
Table 1.4 Performance Overview for the 100-pin Package (2/2)
Unit Function Explanation
Timer Timer A 16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-
phase encoder input) × 3
Timer B 16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
Serial
Interface
UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels
•I
2C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
• IEBus (optional (1)) (UART0 to UART6)
A/D Converter 10-bit resolution × 26 channels
Sample and hold functionality integrated
D/A Converter 8-bit resolution × 2
CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1)
X-Y Converter 16 bits × 16 bits
Intelligent I/O Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 19
Serial interface: Variable-length synchronous serial I/O mode, IEBus
mode (optional (1))
Multi-master I2C-bus Interface 1 channel
CAN Module 2 channels
CAN functionality compliant with ISO 11898-1
32 mailboxes
Flash Memory Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
64 MHz (high speed version)/VCC = 3.0 to 5.5 V
50 MHz (normal speed version)/VCC = 3.0 to 5.5 V
Operating Temperature -20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
Current Consumption 45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package 100-pin plastic molded LQFP (PLQP0100KB-A)
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R32C/118 Group 1. Overview
1.2 Product Information
Tables 1.5 and 1.6 list the product information and Figure 1.1 shows the details of the part number.
Notes:
1. The old package codes are as follows:
PLQP0100KB-A: 100P6Q-A; PLQP0144KA-A: 144P6Q-A
2. “8 Kbytes” in the ROM capacity indicates the data flash memory capacity.
Table 1.5 R32C/118 Group Product List for Normal Speed Version (1/2) As of February, 2013
Part Number Package Code (1) ROM Capacity (2) RAM Capacity Remarks
R5F64185NFD (P)
PLQP0144KA-A
384 Kbytes
+ 8 Kbytes
40 Kbytes
-20°C to 85°C (N version)
R5F64185DFD -40°C to 85°C (D version)
R5F64185PFD -40°C to 85°C (P version)
R5F64185NFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64185DFB -40°C to 85°C (D version)
R5F64185PFB -40°C to 85°C (P version)
R5F64186NFD (P)
PLQP0144KA-A
512 Kbytes
+ 8 Kbytes
-20°C to 85°C (N version)
R5F64186DFD -40°C to 85°C (D version)
R5F64186PFD -40°C to 85°C (P version)
R5F64186NFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64186DFB -40°C to 85°C (D version)
R5F64186PFB -40°C to 85°C (P version)
R5F64187NFD (P)
PLQP0144KA-A
640 Kbytes
+ 8 Kbytes 48 Kbytes
-20°C to 85°C (N version)
R5F64187DFD -40°C to 85°C (D version)
R5F64187PFD -40°C to 85°C (P version)
R5F64187NFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64187DFB -40°C to 85°C (D version)
R5F64187PFB -40°C to 85°C (P version)
R5F64188NFD (P)
PLQP0144KA-A
768 Kbytes
+ 8 Kbytes
63 Kbytes
-20°C to 85°C (N version)
R5F64188DFD -40°C to 85°C (D version)
R5F64188PFD -40°C to 85°C (P version)
R5F64188NFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64188DFB -40°C to 85°C (D version)
R5F64188PFB -40°C to 85°C (P version)
R5F64189NFD (P)
PLQP0144KA-A
1 Mbyte
+ 8 Kbytes
-20°C to 85°C (N version)
R5F64189DFD -40°C to 85°C (D version)
R5F64189PFD -40°C to 85°C (P version)
R5F64189NFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64189DFB -40°C to 85°C (D version)
R5F64189PFB -40°C to 85°C (P version)
(P): On planning phase
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R32C/118 Group 1. Overview
Notes:
1. The old package codes are as follows:
PLQP0100KB-A: 100P6Q-A; PLQP0144KA-A: 144P6Q-A
2. “8 Kbytes” in the ROM capacity indicates the data flash memory capacity.
Table 1.6 R32C/118 Group Product List for High Speed Version (2/2) As of February, 2013
Part Number Package Code (1) ROM Capacity (2) RAM Capacity Remarks
R5F64185HNFD (P)
PLQP0144KA-A
384 Kbytes
+ 8 Kbytes
40 Kbytes
-20°C to 85°C (N version)
R5F64185HDFD -40°C to 85°C (D version)
R5F64185HPFD -40°C to 85°C (P version)
R5F64185HNFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64185HDFB -40°C to 85°C (D version)
R5F64185HPFB -40°C to 85°C (P version)
R5F64186HNFD (P)
PLQP0144KA-A
512 Kbytes
+ 8 Kbytes
-20°C to 85°C (N version)
R5F64186HDFD -40°C to 85°C (D version)
R5F64186HPFD -40°C to 85°C (P version)
R5F64186HNFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64186HDFB -40°C to 85°C (D version)
R5F64186HPFB -40°C to 85°C (P version)
R5F64187HNFD (P)
PLQP0144KA-A
640 Kbytes
+ 8 Kbytes 48 Kbytes
-20°C to 85°C (N version)
R5F64187HDFD -40°C to 85°C (D version)
R5F64187HPFD -40°C to 85°C (P version)
R5F64187HNFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64187HDFB -40°C to 85°C (D version)
R5F64187HPFB -40°C to 85°C (P version)
R5F64188HNFD (P)
PLQP0144KA-A
768 Kbytes
+ 8 Kbytes
63 Kbytes
-20°C to 85°C (N version)
R5F64188HDFD -40°C to 85°C (D version)
R5F64188HPFD -40°C to 85°C (P version)
R5F64188HNFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64188HDFB -40°C to 85°C (D version)
R5F64188HPFB -40°C to 85°C (P version)
R5F64189HNFD (P)
PLQP0144KA-A
1 Mbyte
+ 8 Kbytes
-20°C to 85°C (N version)
R5F64189HDFD -40°C to 85°C (D version)
R5F64189HPFD -40°C to 85°C (P version)
R5F64189HNFB (P)
PLQP0100KB-A
-20°C to 85°C (N version)
R5F64189HDFB -40°C to 85°C (D version)
R5F64189HPFB -40°C to 85°C (P version)
(P): On planning phase
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Feb 6, 2013
R32C/118 Group 1. Overview
Figure 1.1 Part Numbering
Part Number
R5 F 64 18 9 H P XXX FD
Package Code
FB : PLQP0100KB-A
FD : PLQP0144KA-A
ROM Number
Omitted in the flash memory version
Temperature Code
N : -20°C to 85°C
D : -40°C to 85°C
P : -40°C to 85°C
Rated Operating Frequency
H : 64 MHz (High speed version)
None : 50 MHz (Normal speed version)
Memory Type
F : Flash memory version
R32C/118 Group
R32C/100 Series
ROM/RAM Capacity
5 : 384 KB/40 KB
6 : 512 KB/40 KB
7 : 640 KB/48 KB
8 : 768 KB/63 KB
9 : 1 MB/63 KB
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Feb 6, 2013
R32C/118 Group 1. Overview
1.3 Block Diagram
Figure 1.2 shows the block diagram for the R32C/118 Group.
Figure 1.2 R32C/118 Group Block Diagram
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6
8888888
Port P7 P8_5 Port P9 Port P10
8 7 8 (3) 8
Peripherals
Timers:
Timer A 16 bits × 5 timers
Timer B 16 bits × 6 timers
Three-phase motor
controller
Watchdog timer:
15 bits
D/A converter:
8 bits × 2 channels
A/D converter:
10 bits × 1 circuit
Standard: 10 inputs
Maximum: 34 inputs (1)
Serial interface:
9 channels X-Y converter:
16 bits × 16 bits
Clock generator:
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
DMAC
CRC calculator (CCITT)
X16 + X12 + X5 + 1
Intelligent I/O
Time measurement: 16
Wave generation: 24 (2)
Serial interface:
- Variable-length
synchronous serial I/O
- IEBus
R32C/100 Series CPU Core
R2R0
R3R1
R6R4
R7R5
A0
A1
A2
A3
FB
SB
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
R2R0
R3R1
R6R4
R7R5
A0
A1
A2
A3
FB
SB
Memory
ROM
RAM
Multiplier
Port P14 Port P14_1 Port P11Port P12Port P13
4 588
DMAC II
Floating-point unit
Port P8
Port P15
8
(Note 4)
Notes:
1. The 144-pin package has 34 inputs. The 100-pin package can have up to 26 inputs.
2. The 144-pin package has 24 outputs. The 100-pin package has 19 outputs.
3. The 144-pin package has eight ports. The 100-pin package has five I/O ports and one input-only port
(P9_1).
4. Ports P11 to P15 are only available in the 144-pin package.
Multi-master I2C-bus
interface:
1 channel
CAN module:
2 channels
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R32C/118 Group 1. Overview
1.4 Pin Assignments
Figures 1.3 and 1.4 show the pin assignments (top view) and Tables 1.7 to 1.13 list the pin characteristics.
Figure 1.3 Pin Assignment for the 144-pin Package (top view)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
87
86
85
84
83
82
81
80
79
78
77
76
75
74
88
73
RXD4 / SCL4 / STXD4 / ADTRG / P9_7 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
P6_7 / TXD1 / SDA1 / SRXD1AVCC
VREF
AN_0 / P10_0
AVSS
AN_1 / P10_1
AN_2 / P10_2
AN_3 / P10_3
KI0 / AN_4 / P10_4
KI1 / AN_5 / P10_5
KI2 / AN_6 / P10_6
KI3 / AN_7 / P10_7
VCC
IIO0_0 / TXD7 / AN15_0 / P15_0
VSS
IIO0_1 / CLK7 / AN15_1 / P15_1
IIO0_2 / RXD7 / AN15_2 / P15_2
IIO0_3 / CTS7 / RTS7 / AN15_3 / P15_3
IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4
IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5
IIO0_6 / CLK6 / AN15_6 / P15_6
IIO0_7 / CTS6 / RTS6 / SS6 / AN15_7 / P15_7
AN0_0 / D0 / P0_0
AN0_1 / D1 / P0_1
AN0_2 / D2 / P0_2
AN0_3 / D3 / P0_3
IIO1_0 / TXD8 / CS0 / P11_0
IIO1_1 / CLK8 / CS1 / P11_1
IIO1_2 / RXD8 / CS2 / P11_2
IIO1_3 / CTS8 / RTS8 / WR2 / CS3 / P11_3
WR3 / BC3 / P11_4
AN0_4 / D4 / P0_4
AN0_5 / D5 / P0_5
AN0_6 / D6 / P0_6
AN0_7 / D7 / P0_7
IIO0_0 / IIO1_0 / D8 / P1_0
VCC
P6_6 / RXD1 / SCL1 / STXD1
VSS
P6_5 / CLK1
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_3 / TXD0 / SDA0 / SRXD0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_1 / TB1IN / CLK0
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P13_7 / D31 / OUTC2_7
P13_6 / D30 / OUTC2_1 / ISCLK2
P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN
P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT
P5_7 / RDY / CS3 / CTS7 / RTS7
P5_6 / ALE / CS2 / RXD7
P5_5 / HOLD / CLK7
P5_4 / HLDA / CS1 / TXD7
P13_3 / D27 / OUTC2_3
VSS
P13_2 / D26 / OUTC2_6
VCC
P13_1 / D25 / OUTC2_5
P13_0 / D24 / OUTC2_4
P5_3 / CLKOUT / BCLK
P5_2 / RD
P5_1 / WR1 / BC1
P5_0 / WR0 / WR
P12_7 / D23
P12_6 / D22
P12_5 / D21
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_5 / CS2 / A21 / CLK6
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
CAN1OUT / TXD4 / SDA4 / SRXD4 / ANEX1 / P9_6
CAN1IN / CAN1WU / CLK4 / ANEX0 / P9_5
CTS4 / RTS4 / SS4 / TB4IN / DA1 / P9_4
OUTC2_0 / ISTXD2 / IEOUT / TXD3 / SDA3 / SRXD3 / TB2IN / P9_2
ISRXD2 / IEIN / RXD3 / SCL3 / STXD3 / TB1IN / P9_1
CLK3 / TB0IN / P9_0
INT8 / P14_6
INT7 / P14_5
INT6 / P14_4
P14_3
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC
NMI / P8_5
INT2 / P8_4
CAN0IN / CAN0WU / CAN1IN / CAN1WU / INT1 / P8_3
CAN0OUT / CAN1OUT / INT0 / P8_2
IIO1_5 / UD0B / UD1B / CTS5 / RTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
CAN0IN / CAN0WU / IIO1_4 / UD0B / UD1B / CLK5 / TA3IN / P7_7
CAN0OUT / IIO1_3 / UD0A / UD1A / CTS8 / RTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6
IIO1_2 / RXD8 / W / TA2IN / P7_5
IIO1_1 / CLK8 / W / TA2OUT / P7_4
IIO1_0 / TXD8 / CTS2 / RTS2 / SS2 / V / TA1IN / P7_3
CLK2 / V / TA1OUT / P7_2
MSCL / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / RXD2 / SCL2 / STXD2 / TA0IN / TB5IN / P7_1
CTS3 / RTS3 / SS3 / TB3IN / DA0 / P9_3
VDC0
P14_1
VDC1
P1_1 / D9 / IIO0_1 / IIO1_1
P1_2 / D10 / IIO0_2 / IIO1_2
P1_3 / D11 / IIO0_3 / IIO1_3
P1_4 / D12 / IIO0_4 / IIO1_4
P1_5 / D13 / INT3 / IIO0_5 / IIO1_5
P1_6 / D14 / INT4 / IIO0_6 / IIO1_6
P1_7 / D15 / INT5 / IIO0_7 / IIO1_7
P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0
VSS
P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A
VCC
P12_0 / D16 / TXD6 / SDA6 / SRXD6
P12_1 / D17 / CLK6
P12_2 / D18 / RXD6 / SCL6 / STXD6
P12_3 / D19 / CTS6 / RTS6 / SS6
P12_4 / D20
P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B
P3_2 / A10 / [A10/D10] / TA1OUT / V
P3_3 / A11 / [A11/D11] / TA1IN / V
P3_4 / A12 / [A12/D12] / TA2OUT / W
P3_5 / A13 / [A13/D13] / TA2IN / W
P3_6 / A14 / [A14/D14] / TA4OUT / U
P3_7 / A15 / [A15/D15] / TA4IN / U
P4_0 / A16 / CTS3 / RTS3 / SS3
P4_1 / A17 / CLK3
VSS
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN
VCC
P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT
P2_1 / A1 / [A1/D1] / BC2 / [BC2/D1] / AN2_1
P2_2 / A2 / [A2/D2] / AN2_2
P2_3 / A3 / [A3/D3] / AN2_3
P2_4 / A4 / [A4/D4] / AN2_4
P2_5 / A5 / [A5/D5] / AN2_5
P2_6 / A6 / [A6/D6] / AN2_6
P2_7 / A7 / [A7/D7] / AN2_7
PLQP0144KA-A
(144P6Q-A)
(Top view)
R32C/118 Group
(Note 3)
(Note 1)
(Note 2)
R01DS0065EJ0120 Rev.1.20 Page 11 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Table 1.7 Pin Characteristics for the 144-pin Package (1/4)
Pin
No.
Control
Pin Port Interrupt
Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog
Pin
Bus Control
Pin
1 P9_6 TXD4/SDA4/SRXD4/
CAN1OUT
ANEX1
2 P9_5 CLK4/CAN1IN/
CAN1WU
ANEX0
3P9_4TB4INCTS4/RTS4/SS4 DA1
4P9_3TB3INCTS3/RTS3/SS3 DA0
5 P9_2 TB2IN TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/
IEOUT
6 P9_1 TB1IN RXD3/SCL3/STXD3 ISRXD2/IEIN
7 P9_0 TB0IN CLK3
8 P14_6 INT8
9 P14_5 INT7
10 P14_4 INT6
11 P14_3
12 VDC0
13 P14_1
14 VDC1
15 NSD
16 CNVSS
17 XCIN P8_7
18 XCOUT P8_6
19 RESET
20 XOUT
21 VSS
22 XIN
23 VCC
24 P8_5 NMI
25 P8_4 INT2
26 P8_3 INT1 CAN0IN/CAN0WU/
CAN1IN/CAN1WU
27 P8_2 INT0 CAN0OUT/CAN1OUT
28 P8_1 TA4IN/UCTS5/RTS5/SS5 IIO1_5/UD0B/UD1B
29 P8_0 TA4OUT/U RXD5/SCL5/STXD5 UD0A/UD1A
30 P7_7 TA3IN CLK5/CAN0IN/
CAN0WU
IIO1_4/UD0B/UD1B
31 P7_6 TA3OUT TXD5/SDA5/SRXD5/
CTS8/RTS8/CAN0OUT
IIO1_3/UD0A/UD1A
32 P7_5 TA2IN/WRXD8 IIO1_2
33 P7_4 TA2OUT/W CLK8 IIO1_1
34 P7_3 TA1IN/VCTS2/RTS2/SS2/TXD8 IIO1_0
35 P7_2 TA1OUT/V CLK2
36 P7_1 TA0IN/
TB5IN
RXD2/SCL2/STXD2/
MSCL
IIO1_7/OUTC2_2/
ISRXD2/IEIN
R01DS0065EJ0120 Rev.1.20 Page 12 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Table 1.8 Pin Characteristics for the 144-pin Package (2/4)
Pin
No.
Control
Pin Port Interrupt
Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog
Pin
Bus Control
Pin
37 P7_0 TA0OUT TXD2/SDA2/SRXD2/
MSDA
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
38 P6_7 TXD1/SDA1/SRXD1
39 VCC
40 P6_6 RXD1/SCL1/STXD1
41 VSS
42 P6_5 CLK1
43 P6_4 CTS1/RTS1/SS1 OUTC2_1/ISCLK2
44 P6_3 TXD0/SDA0/SRXD0
45 P6_2 TB2IN RXD0/SCL0/STXD0
46 P6_1 TB1IN CLK0
47 P6_0 TB0IN CTS0/RTS0/SS0
48 P13_7 OUTC2_7 D31
49 P13_6 OUTC2_1/ISCLK2 D30
50 P13_5 OUTC2_2/ISRXD2/
IEIN
D29
51 P13_4 OUTC2_0/ISTXD2/
IEOUT
D28
52 P5_7 CTS7/RTS7 RDY/CS3
53 P5_6 RXD7 ALE/CS2
54 P5_5 CLK7 HOLD
55 P5_4 TXD7 HLDA/CS1
56 P13_3 OUTC2_3 D27
57 VSS
58 P13_2 OUTC2_6 D26
59 VCC
60 P13_1 OUTC2_5 D25
61 P13_0 OUTC2_4 D24
62 P5_3 CLKOUT/
BCLK
63 P5_2 RD
64 P5_1 WR1/BC1
65 P5_0 WR0/WR
66 P12_7 D23
67 P12_6 D22
68 P12_5 D21
69 P4_7 TXD6/SDA6/SRXD6 CS0/A23
70 P4_6 RXD6/SCL6/STXD6 CS1/A22
71 P4_5 CLK6 CS2/A21
72 P4_4 CTS6/RTS6/SS6 CS3/A20
73 P4_3 TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/
IEOUT
A19
74 VCC
R01DS0065EJ0120 Rev.1.20 Page 13 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Table 1.9 Pin Characteristics for the 144-pin Package (3/4)
Pin
No.
Control
Pin Port Interrupt
Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog
Pin
Bus Control
Pin
75 P4_2 RXD3/SCL3/STXD3 ISRXD2/IEIN A18
76 VSS
77 P4_1 CLK3 A17
78 P4_0 CTS3/RTS3/SS3 A16
79 P3_7 TA4IN/UA15(/D15)
80 P3_6 TA4OUT/U A14(/D14)
81 P3_5 TA2IN/WA13(/D13)
82 P3_4 TA2OUT/W A12(/D12)
83 P3_3 TA1IN/VA11(/D11)
84 P3_2 TA1OUT/V A10(/D10)
85 P3_1 TA3OUT UD0B/UD1B A9(/D9)
86 P12_4 D20
87 P12_3 CTS6/RTS6/SS6 D19
88 P12_2 RXD6/SCL6/STXD6 D18
89 P12_1 CLK6 D17
90 P12_0 TXD6/SDA6/SRXD6 D16
91 VCC
92 P3_0 TA0OUT UD0A/UD1A A8(/D8)
93 VSS
94 P2_7 AN2_7 A7(/D7)
95 P2_6 AN2_6 A6(/D6)
96 P2_5 AN2_5 A5(/D5)
97 P2_4 AN2_4 A4(/D4)
98 P2_3 AN2_3 A3(/D3)
99 P2_2 AN2_2 A2(/D2)
100 P2_1 AN2_1 A1(/D1)/
BC2(/D1)
101 P2_0 AN2_0 A0(/D0)/
BC0(/D0)
102 P1_7 INT5 IIO0_7/IIO1_7 D15
103 P1_6 INT4 IIO0_6/IIO1_6 D14
104 P1_5 INT3 IIO0_5/IIO1_5 D13
105 P1_4 IIO0_4/IIO1_4 D12
106 P1_3 IIO0_3/IIO1_3 D11
107 P1_2 IIO0_2/IIO1_2 D10
108 P1_1 IIO0_1/IIO1_1 D9
109 P1_0 IIO0_0/IIO1_0 D8
110 P0_7 AN0_7 D7
111 P0_6 AN0_6 D6
112 P0_5 AN0_5 D5
113 P0_4 AN0_4 D4
114 P11_4 BC3/WR3
R01DS0065EJ0120 Rev.1.20 Page 14 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Table 1.10 Pin Characteristics for the 144-pin Package (4/4)
Pin
No.
Control
Pin Port Interrupt
Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog
Pin
Bus Control
Pin
115 P11_3 CTS8/RTS8 IIO1_3 CS3/WR2
116 P11_2 RXD8 IIO1_2 CS2
117 P11_1 CLK8 IIO1_1 CS1
118 P11_0 TXD8 IIO1_0 CS0
119 P0_3 AN0_3 D3
120 P0_2 AN0_2 D2
121 P0_1 AN0_1 D1
122 P0_0 AN0_0 D0
123 P15_7 CTS6/RTS6/SS6 IIO0_7 AN15_7
124 P15_6 CLK6 IIO0_6 AN15_6
125 P15_5 RXD6/SCL6/STXD6 IIO0_5 AN15_5
126 P15_4 TXD6/SDA6/SRXD6 IIO0_4 AN15_4
127 P15_3 CTS7/RTS7 IIO0_3 AN15_3
128 P15_2 RXD7 IIO0_2 AN15_2
129 P15_1 CLK7 IIO0_1 AN15_1
130 VSS
131 P15_0 TXD7 IIO0_0 AN15_0
132 VCC
133 P10_7 KI3 AN_7
134 P10_6 KI2 AN_6
135 P10_5 KI1 AN_5
136 P10_4 KI0 AN_4
137 P10_3 AN_3
138 P10_2 AN_2
139 P10_1 AN_1
140 AVSS
141 P10_0 AN_0
142 VREF
143 AVCC
144 P9_7 RXD4/SCL4/STXD4 ADTRG
R01DS0065EJ0120 Rev.1.20 Page 15 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Figure 1.4 Pin Assignment for the 100-pin Package (top view)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
100
99
98
97
96
95
94
93
92
91
90
89
87
86
85
84
83
82
81
80
79
78
77
76
75
74
88
73
RXD4 / SCL4 / STXD4 / ADTRG / P9_7 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
P6_7 / TXD1 / SDA1 / SRXD1AVCC
VREF
AN_0 / P10_0
AVSS
AN_1 / P10_1
AN_2 / P10_2
AN_3 / P10_3
KI0 / AN_4 / P10_4
KI1 / AN_5 / P10_5
KI2 / AN_6 / P10_6
KI3 / AN_7 / P10_7
AN0_0 / D0 / P0_0
AN0_1 / D1 / P0_1
AN0_2 / D2 / P0_2
AN0_3 / D3 / P0_3
AN0_4 / D4 / P0_4
AN0_5 / D5 / P0_5
AN0_6 / D6 / P0_6
AN0_7 / D7 / P0_7
P6_6 / RXD1 / SCL1 / STXD1
P6_5 / CLK1
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_3 / TXD0 / SDA0 / SRXD0
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_1 / TB1IN / CLK0
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P5_7 / RDY / CS3 / CTS7 / RTS7
P5_6 / ALE / CS2 / RXD7
P5_5 / HOLD / CLK7
P5_4 / HLDA / CS1 / TXD7
P5_3 / CLKOUT / BCLK
P5_2 / RD
P5_1 / WR1 / BC1
P5_0 / WR0 / WR
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_5 / CS2 / A21 / CLK6
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
CAN1OUT / TXD4 / SDA4 / SRXD4 / ANEX1 / P9_6
CAN1IN / CAN1WU / CLK4 / ANEX0 / P9_5
CTS4 / RTS4 / SS4 / TB4IN / DA1 / P9_4
VDC0
P9_1
VDC1
NSD
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC
NMI / P8_5
INT2 / P8_4
CAN0IN / CAN0WU / CAN1IN / CAN1WU / INT1 / P8_3
CAN0OUT / CAN1OUT / INT0 / P8_2
IIO1_5 / UD0B / UD1B / CTS5 / RTS5 / SS5 / U / TA4IN / P8_1
UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0
CAN0IN / CAN0WU / IIO1_4 / UD0B / UD1B / CLK5 / TA3IN / P7_7
CAN0OUT / IIO1_3 / UD0A / UD1A / CTS8 / RTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6
IIO1_2 / RXD8 / W / TA2IN / P7_5
IIO1_1 / CLK8 / W / TA2OUT / P7_4
IIO1_0 / TXD8 / CTS2 / RTS2 / SS2 / V / TA1IN / P7_3
P7_2 / TA1OUT / V / CLK2
P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / MSCL
TB3IN / DA0 / P9_3
IIO0_1 / IIO1_1 / D9 / P1_1
IIO0_2 / IIO1_2 / D10 / P1_2
P1_3 / D11 / IIO0_3 / IIO1_3
P1_4 / D12 / IIO0_4 / IIO1_4
P1_5 / D13 / INT3 / IIO0_5 / IIO1_5
P1_6 / D14 / INT4 / IIO0_6 / IIO1_6
P1_7 / D15 / INT5 / IIO0_7 / IIO1_7
P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0
VSS
P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A
VCC
P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B
P3_2 / A10 / [A10/D10] / TA1OUT / V
P3_3 / A11 / [A11/D11] / TA1IN / V
P3_4 / A12 / [A12/D12] / TA2OUT / W
P3_5 / A13 / [A13/D13] / TA2IN / W
P3_6 / A14 / [A14/D14] / TA4OUT / U
P3_7 / A15 / [A15/D15] / TA4IN / U
P4_0 / A16 / CTS3 / RTS3 / SS3
P4_1 / A17 / CLK3
P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN
P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT
P2_1 / A1 / [A1/D1] / AN2_1
P2_2 / A2 / [A2/D2] / AN2_2
P2_3 / A3 / [A3/D3] / AN2_3
P2_4 / A4 / [A4/D4] / AN2_4
P2_5 / A5 / [A5/D5] / AN2_5
P2_6 / A6 / [A6/D6] / AN2_6
P2_7 / A7 / [A7/D7] / AN2_7
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IIO0_0 / IIO1_0 / D8 / P1_0
PLQP0100KB-A
(100P6Q-A)
(Top view)
R32C/118 Group
(Note 1)
(Note 3)
(Note 2)
R01DS0065EJ0120 Rev.1.20 Page 16 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Table 1.11 Pin Characteristics for the 100-pin Package (1/3)
Pin
No.
Control
Pin Port Interrupt
Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog
Pin
Bus Control
Pin
1P9_4TB4INCTS4/RTS4/SS4 DA1
2P9_3TB3IN DA0
3 VDC0
4P9_1
5 VDC1
6NSD
7 CNVSS
8XCINP8_7
9 XCOUT P8_6
10 RESET
11 XOUT
12 VSS
13 XIN
14 VCC
15 P8_5 NMI
16 P8_4 INT2
17 P8_3 INT1 CAN0IN/CAN0WU/
CAN1IN/CAN1WU
18 P8_2 INT0 CAN0OUT/CAN1OUT
19 P8_1 TA4IN/UCTS5/RTS5/SS5 IIO1_5/UD0B/UD1B
20 P8_0 TA4OUT/U RXD5/SCL5/STXD5 UD0A/UD1A
21 P7_7 TA3IN CLK5/CAN0IN/
CAN0WU
IIO1_4/UD0B/UD1B
22 P7_6 TA3OUT TXD5/SDA5/SRXD5/
CTS8/RTS8/CAN0OUT
IIO1_3/UD0A/UD1A
23 P7_5 TA2IN/WRXD8 IIO1_2
24 P7_4 TA2OUT/W CLK8 IIO1_1
25 P7_3 TA1IN/VCTS2/RTS2/SS2/TXD8 IIO1_0
26 P7_2 TA1OUT/V CLK2
27 P7_1 TA0IN/
TB5IN
RXD2/SCL2/STXD2/
MSCL
IIO1_7/OUTC2_2/
ISRXD2/IEIN
28 P7_0 TA0OUT TXD2/SDA2/SRXD2/
MSDA
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
29 P6_7 TXD1/SDA1/SRXD1
30 P6_6 RXD1/SCL1/STXD1
31 P6_5 CLK1
32 P6_4 CTS1/RTS1/SS1 OUTC2_1/ISCLK2
33 P6_3 TXD0/SDA0/SRXD0
34 P6_2 TB2IN RXD0/SCL0/STXD0
35 P6_1 TB1IN CLK0
36 P6_0 TB0IN CTS0/RTS0/SS0
37 P5_7 CTS7/RTS7 RDY/CS3
38 P5_6 RXD7 ALE/CS2
R01DS0065EJ0120 Rev.1.20 Page 17 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Table 1.12 Pin Characteristics for the 100-pin Package (2/3)
Pin
No.
Control
Pin Port Interrupt
Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog
Pin
Bus Control
Pin
39 P5_5 CLK7 HOLD
40 P5_4 TXD7 HLDA/CS1
41 P5_3 CLKOUT/
BCLK
42 P5_2 RD
43 P5_1 WR1/BC1
44 P5_0 WR0/WR
45 P4_7 TXD6/SDA6/SRXD6 CS0/A23
46 P4_6 RXD6/SCL6/STXD6 CS1/A22
47 P4_5 CLK6 CS2/A21
48 P4_4 CTS6/RTS6/SS6 CS3/A20
49 P4_3 TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/
IEOUT
A19
50 P4_2 RXD3/SCL3/STXD3 ISRXD2/IEIN A18
51 P4_1 CLK3 A17
52 P4_0 CTS3/RTS3/SS3 A16
53 P3_7 TA4IN/UA15(/D15)
54 P3_6 TA4OUT/U A14(/D14)
55 P3_5 TA2IN/WA13(/D13)
56 P3_4 TA2OUT/W A12(/D12)
57 P3_3 TA1IN/VA11(/D11)
58 P3_2 TA1OUT/V A10(/D10)
59 P3_1 TA3OUT UD0B/UD1B A9(/D9)
60 VCC
61 P3_0 TA0OUT UD0A/UD1A A8(/D8)
62 VSS
63 P2_7 AN2_7 A7(/D7)
64 P2_6 AN2_6 A6(/D6)
65 P2_5 AN2_5 A5(/D5)
66 P2_4 AN2_4 A4(/D4)
67 P2_3 AN2_3 A3(/D3)
68 P2_2 AN2_2 A2(/D2)
69 P2_1 AN2_1 A1(/D1)
70 P2_0 AN2_0 A0(/D0)/
BC0(/D0)
71 P1_7 INT5 IIO0_7/IIO1_7 D15
72 P1_6 INT4 IIO0_6/IIO1_6 D14
73 P1_5 INT3 IIO0_5/IIO1_5 D13
74 P1_4 IIO0_4/IIO1_4 D12
75 P1_3 IIO0_3/IIO1_3 D11
R01DS0065EJ0120 Rev.1.20 Page 18 of 123
Feb 6, 2013
R32C/118 Group 1. Overview
Table 1.13 Pin Characteristics for the 100-pin Package (3/3)
Pin
No.
Control
Pin Port Interrupt
Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog
Pin
Bus Control
Pin
76 P1_2 IIO0_2/IIO1_2 D10
77 P1_1 IIO0_1/IIO1_1 D9
78 P1_0 IIO0_0/IIO1_0 D8
79 P0_7 AN0_7 D7
80 P0_6 AN0_6 D6
81 P0_5 AN0_5 D5
82 P0_4 AN0_4 D4
83 P0_3 AN0_3 D3
84 P0_2 AN0_2 D2
85 P0_1 AN0_1 D1
86 P0_0 AN0_0 D0
87 P10_7 KI3 AN_7
88 P10_6 KI2 AN_6
89 P10_5 KI1 AN_5
90 P10_4 KI0 AN_4
91 P10_3 AN_3
92 P10_2 AN_2
93 P10_1 AN_1
94 AVSS
95 P10_0 AN_0
96 VREF
97 AVCC
98 P9_7 RXD4/SCL4/STXD4 ADTRG
99 P9_6 TXD4/SDA4/SRXD4/
CAN1OUT
ANEX1
100 P9_5 CLK4/CAN1IN/
CAN1WU
ANEX0
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R32C/118 Group 1. Overview
1.5 Pin Definitions and Functions
Tables 1.14 to 1.18 list the pin definitions and functions.
Notes:
1. Pins INT6 to INT8 are available in the 144-pin package only.
2. Pins D16 to D31 are available in the 144-pin package only.
Table 1.14 Pin Definitions and Functions (1/4)
Function Symbol I/O Description
Power supply VCC, VSS I Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V
Connecting pins
for decoupling
capacitor
VDC0, VDC1
—
A decoupling capacitor for internal voltage should be
connected between VDC0 and VDC1
Analog power
supply
AVCC, AVSS IPower supply for the A/D converter. AVCC and AVSS
should be connected to VCC and VSS, respectively
Reset input RESET I The MCU is reset when this pin is driven low
CNVSS CNVSS I This pin should be connected to VSS via a resistor
Debug port NSD I/O This pin is to communicate with a debugger. It should be
connected to VCC via a resistor of 1 to 4.7 k
Main clock input XIN IInput/output for the main clock oscillator. A crystal, or a
ceramic resonator should be connected between pins XIN
and XOUT. An external clock should be input at the XIN
while leaving the XOUT open
Main clock output XOUT O
Sub clock input XCIN IInput/output for the sub clock oscillator. A crystal oscillator
should be connected between pins XCIN and XCOUT. An
external clock should be input at the XCIN while leaving the
XCOUT open
Sub clock output XCOUT O
BCLK output BCLK O BCLK output
Clock output CLKOUT OOutput of the clock with the same frequency as low speed
clocks, f8, or f32
External interrupt
input
INT0 to INT8 (1) IInput for external interrupts
NMI input P8_5/NMI I Input for NMI
Key input interrupt KI0 to KI3 I Input for the key input interrupt
Bus control pins D0 to D7 I/O Input/output of data (D0 to D7) while accessing an external
memory space with a separate bus
D8 to D15 I/O Input/output of data (D8 to D15) while accessing an
external memory space with 16-bit or 32-bit separate bus
D16 to D31 (2) I/O Input/output of data (D16 to D31) while accessing an
external memory space with 32-bit separate bus
A0 to A23 O Output of address bits A0 to A23
A0/D0 to A7/D7
I/O
Output of address bits (A0 to A7) and input/output of data
(D0 to D7) by time-division while accessing an external
memory space with multiplexed bus
A8/D8 to
A15/D15 I/O
Output of address bits (A8 to A15) and input/output of data
(D8 to D15) by time-division while accessing an external
memory space with 16-bit or 32-bit multiplexed bus
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R32C/118 Group 1. Overview
Note:
1. Pins BC2/D1, WR2, WR3, BC2, and BC3 are available in the 144-pin package only.
Table 1.15 Pin Definitions and Functions (2/4)
Function Symbol I/O Description
Bus control pins BC0/D0, BC2/D1
(1) I/O
Output of byte control (BC0 and BC2) and input/output of
data (D0 and D1) by time-division while accessing an
external memory space with multiplexed bus
CS0 to CS3 O Chip select output
WR0/WR1/WR2/
WR3,
WR/BC0/BC1/
BC2/BC3,
RD (1)
O
Output of write, byte control, and read signals. Either WRx
or WR and BCx can be selected by a program.
Data is read when RD is low.
• When WR0, WR1, WR2, WR3, and RD are selected,
data is written to the following address:
4n+0, when WR0 is low
4n+1, when WR1 is low
4n+2, when WR2 is low
4n+3, when WR3 is low
on 32-bit external data bus
or
an even address, when WR0 is low
an odd address, when WR1 is low
on 16-bit external data bus
• When WR, BC0, BC1, BC2, BC3, and RD are selected,
data is written, when WR is low
and
the following address is accessed:
4n+0, when BC0 is low
4n+1, when BC1 is low
4n+2, when BC2 is low
4n+3, when BC3 is low
on 32-bit external data bus
or
an even address, when BC0 is low
an odd address, when BC1 is low
on 16-bit external data bus
ALE O Latch enable signal in multiplexed bus format
HOLD I The MCU is in a hold state while this pin is held low
HLDA O This pin is driven low while the MCU is held in a hold state
RDY IBus cycle is extended by the CPU if this pin is low on the
falling edge of BCLK
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R32C/118 Group 1. Overview
Notes:
1. Port P9_1 in the 100-pin package is an input-only port.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only.
Table 1.16 Pin Definitions and Functions (3/4)
Function Symbol I/O Description
I/O port (1, 2) P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P6_0 to P6_7,
P7_0 to P7_7,
P8_0 to P8_4,
P8_6, P8_7,
P9_0 to P9_7,
P10_0 to P10_7,
P11_0 to P11_4,
P12_0 to P12_7,
P13_0 to P13_7,
P14_3 to P14_6,
P15_0 to P15_7
I/O
I/O ports in CMOS. Each port can be programmed to input
or output under the control of the direction register.
Some ports are 5 V tolerant inputs.
Pull-up resistors and N-channel open drain setting can be
enabled on some ports. Refer to Table 1.18 “Pin
Specifications” for details
Input port (2) P9_1 (for 100-pin
package)
P14_1 (for 144-
pin package)
I
Input port in CMOS
Pull-up resistor is selectable.
Refer to Table 1.18 “Pin Specifications” for details
Timer A TA0OUT to
TA4OUT I/O Timers A0 to A4 input/output
TA0IN to TA4IN I Timers A0 to A4 input
Timer B TB0IN to TB5IN I Timers B0 to B5 input
Three-phase
motor control
timer output
U, U, V, V, W, W
O
Three-phase motor control timer output
Serial interface CTS0 to CTS8 I Handshake input
RTS0 to RTS8 O Handshake output
CLK0 to CLK8 I/O Transmit/receive clock input/output
RXD0 to RXD8 I Serial data input
TXD0 to TXD8 O Serial data output
I2C-bus
(simplified)
SDA0 to SDA6 I/O Serial data input/output
SCL0 to SCL6 I/O Transmit/receive clock input/output
Serial interface
special functions
STXD0 to
STXD6 OSerial data output in slave mode
SRXD0 to
SRXD6 ISerial data input in slave mode
SS0 to SS6 I Input to control serial interface special functions
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R32C/118 Group 1. Overview
Notes:
1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.
2. Pins OUTC2_3 to OUTC2_7 are available in the 144-pin package only.
Table 1.17 Pin Definitions and Functions (4/4)
Function Symbol I/O Description
A/D converter AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to
AN15_7 (1)
I
Analog input for the A/D converter
ADTRG I External trigger input for the A/D converter
ANEX0 I/O Expanded analog input for the A/D converter and output in
external op-amp connection mode
ANEX1 I Expanded analog input for the A/D converter
D/A converter DA0, DA1 O Output for the D/A converter
Reference voltage
input
VREF IReference voltage input for the A/D converter and D/A
converter
Intelligent I/O IIO0_0 to IIO0_7 I/O Input/output for Intelligent I/O group 0. Either input capture
or output compare is selectable
IIO1_0 to IIO1_7 I/O Input/output for Intelligent I/O group 1. Either input capture
or output compare is selectable
UD0A, UD0B,
UD1A, UD1B IInput for the two-phase encoder
OUTC2_0 to
OUTC2_7 (2) OOutput for OC (output compare) of Intelligent I/O group 2
ISCLK2 I/O Clock input/output for the serial interface
ISRXD2 I Receive data input for the serial interface
ISTXD2 O Transmit data output for the serial interface
IEIN I Receive data input for the serial interface
IEOUT O Transmit data output for the serial interface
Multi-master I2C-
bus
MSDA I/O Serial data input/output
MSCL I/O Transmit/receive clock input/output
CAN Module CAN0IN, CAN1IN I Receive data input for the CAN communications
CAN0OUT,
CAN1OUT OTransmit data output for the CAN communications
CAN0WU,
CAN1WU IInput for the CAN wake-up interrupt
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R32C/118 Group 1. Overview
Table 1.18 Pin Specifications
Notes:
1. Pull-up resistors are selected for the following 4-pin units: Pi_0 to Pi_3 and Pi_4 to Pi_7 (i = 0 to 15);
however, they are enabled only for the input pins.
2. N-channel open drain output can be enabled on the applicable pins on a discrete pin basis.
3. 5 V tolerant input is enabled when an applicable pin is set as an input port. When it is set as an I/O
port, to enable 5 V tolerant input, this pin should be set as N-channel open drain output.
Pin Names
Package Selectable Functions
5 V Tolerant Input (3)
144-
pin
100-
pin Pull-up resistor (1) N-channel
open drain (2)
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_3
P5_4 to P5_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_3
P8_4, P8_6, P8_7
P9_0 to P9_3 (144-pin)
P9_1, P9_3 (100-pin)
P9_4 to P9_7
P10_0 to P10_7
P11_0 to P11_3
P11_4
P12_0 to P12_3
P12_4 to P12_7
P13_0 to P13_7
P14_1, P14_3
P14_4 to P14_6
P15_0 to P15_7
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R32C/118 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
The CPU contains the registers shown below. There are two register banks each consisting of registers
R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.
Figure 2.1 CPU Registers
DDA0
DDR0
DSA0
DSR0
DDA0
DCR0
DCT0
DMD0
DDR0
DSA0
DSR0
DDA0
DCR0
DCT0
DMD0
DDR0
DSA0
DSR0
DDA0
DCR0
DCT0
DMD0
DDR0
DSA0
DSR0
DCR0
DCT0
DMD0
b0b31
VCT
SVP
SVF
PC
INTB
USP
ISP
FB
SB
A3
A2
A1
R5R7
R6 R4
R1LR1HR3LR3H
R2H R2L R0H R0L
A0
FLG
b0b31
General purpose
registers
Fast interrupt
registers
DMAC-associated
registers (2)
Notes:
1.There are two banks of these registers.
2.There are four identical sets of DMAC-associated registers.
DMA destination address reload register
Flag register
Data registers (1)
Address registers (1)
Static base register (1)
Frame base register (1)
User stack pointer
Interrupt stack pointer
Interrupt vector table base register
Program counter
Save flag register
Save PC register
Vector register
R2R0
R3R1
R6R4
R7R5
DMA source address register
DMA source address reload register
DMA terminal count reload register
DMA terminal count register
DMA mode register
CDZSBOIUIPLRND
b0b31 b8 b7b16 b15
b0b31
b23 b15 b7
DMA destination address register
Blank spaces are reserved.
FU
FO
DP
b24 b23
b23
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R32C/118 Group 2. Central Processing Unit (CPU)
2.1 General Purpose Registers
2.1.1 Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into
R2 and R0, R3R1 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and
R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).
2.1.2 Address Registers (A0, A1, A2, and A3)
These 32-bit registers have functions similar to data registers. They are also used for address register
indirect addressing and address register relative addressing.
2.1.3 Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4 Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5 Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6 Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP).
Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt
stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for
details.
To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer
(USP) or the interrupt stack pointer (ISP) to a multiple of 4.
2.1.8 Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1 Carry Flag (C flag)
This flag retains a carry, borrow, or shifted-out bit generated by the arithmetic logic unit (ALU).
2.1.8.2 Debug Flag (D flag)
This flag is only for debugging. Only set this bit to 0.
2.1.8.3 Zero Flag (Z flag)
This flag becomes 1 when the result of an operation is 0; otherwise it is 0.
2.1.8.4 Sign Flag (S flag)
This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
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R32C/118 Group 2. Central Processing Unit (CPU)
2.1.8.5 Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when register bank 0 is selected, and 1 when register
bank 1 is selected.
2.1.8.6 Overflow Flag (O flag)
This flag becomes 1 when the result of an operation overflows; otherwise it is 0.
2.1.8.7 Interrupt Enable Flag (I flag)
This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable
them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.
2.1.8.8 Stack Pointer Select Flag (U flag)
To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set
this flag to 1.
It becomes 0 when a hardware interrupt is accepted or when an INT instruction designated by a
software interrupt number from 0 to 127 is executed.
2.1.8.9 Floating-point Underflow Flag (FU flag)
This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand contains invalid numbers (subnormal numbers).
2.1.8.10 Floating-point Overflow Flag (FO flag)
This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand contains invalid numbers (subnormal numbers).
2.1.8.11 Processor Interrupt Priority Level (IPL)
The processor interrupt priority level (IPL), consisting of 3 bits, selects a processor interrupt priority
level from level 0 to 7. An interrupt is enabled when the interrupt request level is higher than the
selected IPL.
When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.
2.1.8.12 Fixed-point Radix Point Designation Bit (DP bit)
This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result
to extract. It is used for the MULX instruction.
2.1.8.13 Floating-point Rounding Mode (RND)
The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.
2.1.8.14 Reserved
Only set this bit to 0. The read value is undefined.
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R32C/118 Group 2. Central Processing Unit (CPU)
2.2 Fast Interrupt Registers
The following three registers are provided to minimize the overhead of the interrupt sequence.
2.2.1 Save Flag Register (SVF)
This 32-bit register is used to save the flag register when a fast interrupt occurs.
2.2.2 Save PC Register (SVP)
This 32-bit register is used to save the program counter when a fast interrupt occurs.
2.2.3 Vector Register (VCT)
This 32-bit register is used to indicate a jump address when a fast interrupt occurs.
2.3 DMAC-associated Registers
There are seven types of DMAC-associated registers.
2.3.1 DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)
These 32-bit registers are used to set DMA transfer mode, bit rate, etc.
2.3.2 DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)
These 24-bit registers are used to set the number of DMA transfers.
2.3.3 DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)
These 24-bit registers are used to set the reloaded values for DMA terminal count registers.
2.3.4 DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)
These 32-bit registers are used to set DMA source addresses.
2.3.5 DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)
These 32-bit registers are used to set the reloaded values for DMA source address registers.
2.3.6 DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)
These 32-bit registers are used to set DMA destination addresses.
2.3.7 DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and
DDR3)
These 32-bit registers are used to set reloaded values for DMA destination address registers.
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R32C/118 Group 3. Memory
3. Memory
Figure 3.1 shows the memory map of the R32C/118 Group.
The R32C/118 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.
The internal ROM is mapped from address FFFFFFFFh in the inferior direction. For example, the 1-Mbyte
internal ROM is mapped from FFF00000h to FFFFFFFFh.
The fixed interrupt vector table contains the start address of interrupt handlers and is mapped from
FFFFFFDCh to FFFFFFFFh.
The internal RAM is mapped from address 00000400h in the superior direction. For example, the 63-Kbyte
internal RAM is mapped from 00000400h to 0000FFFFh. Besides being used for data storage, the internal
RAM functions as a stack(s) for subroutine calls and/or interrupt handlers.
Special function registers (SFRs), which are control registers for peripheral functions, are mapped from
00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved,
and no access is allowed.
In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should
not be accessed.
Figure 3.1 Memory Map
Internal RAM
SFR1
SFR2
00000000h
FFFFFFFFh Reset
NMI
Reserved
Reserved
Reserved
BRK instruction
Overflow
Undefined instruction
Watchdog timer (5)
FFFFFFFFh
FFFFFFDCh
YYYYYYYYh
00000400h
XXXXXXXXh
Reserved
00040000h
Internal ROM
(Data space) (1)
00060000h
00062000h
00050000h Reserved
Internal RAM
Capacity XXXXXXXXh
63 Kbytes 00010000h
40 Kbytes 0000A400h
Internal ROM
Capacity YYYYYYYYh
512 Kbytes FFF80000h
640 Kbytes FFF60000h
768 Kbytes FFF40000h
1 Mbyte FFF00000h
48 Kbytes 0000C400h
External space (2)
Reserved
00080000h
Reserved (3)
FFE00000h
Internal ROM (4)
384 Kbytes FFFA0000h
Notes:
1. The flash memory version provides two additional 4-Kbyte spaces (blocks A and B) for storing data.
2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h
to FDFFFFFFh are inaccessible.
3. This space is reserved in memory expansion mode. It becomes an external space in microprocessor mode.
4. This space can be used in single-chip mode or memory expansion mode. It becomes an external space in
microprocessor mode.
5. The watchdog timer interrupt shares a vector with the oscillator stop detection interrupt and low voltage
detection interrupt.
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R32C/118 Group 4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List
(1) to Table 4.53 SFR List (53) list the SFR details.
Table 4.1 SFR List (1)
Address Register Symbol Reset Value
000000h
000001h
000002h
000003h
000004h Clock Control Register CCR 0001 1000b
000005h
000006h Flash Memory Control Register FMCR 0000 0001b
000007h Protect Release Register PRR 00h
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h External Bus Control Register 3/Flash Memory Rewrite Bus
Control Register 3
EBC3/FEBC3 0000h
000011h
000012h Chip Selects 2 and 3 Boundary Setting Register CB23 00h
000013h
000014h External Bus Control Register 2 EBC2 0000h
000015h
000016h Chip Selects 1 and 2 Boundary Setting Register CB12 00h
000017h
000018h External Bus Control Register 1 EBC1 0000h
000019h
00001Ah Chip Selects 0 and 1 Boundary Setting Register CB01 00h
00001Bh
00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus
Control Register 0
EBC0/FEBC0 0000h
00001Dh
00001Eh Peripheral Bus Control Register PBC 0504h
00001Fh
000020h to
00005Fh
X: Undefined
Blanks are reserved. No access is allowed.
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R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.2 SFR List (2)
Address Register Symbol Reset Value
000060h
000061h Timer B5 Interrupt Control Register TB5IC XXXX X000b
000062h UART5 Transmit/NACK Interrupt Control Register S5TIC XXXX X000b
000063h UART2 Receive/ACK Interrupt Control Register/I2C-bus Line
Interrupt Control Register
S2RIC/I2CLIC XXXX X000b
000064h UART6 Transmit/NACK Interrupt Control Register S6TIC XXXX X000b
000065h UART3 Receive/ACK Interrupt Control Register S3RIC XXXX X000b
000066h UART5/6 Bus Collision, START Condition/STOP Condition
Detection Interrupt Control Register
BCN5IC/BCN6IC XXXX X000b
000067h UART4 Receive/ACK Interrupt Control Register S4RIC XXXX X000b
000068h DMA0 Transfer Complete Interrupt Control Register DM0IC XXXX X000b
000069h UART0/3 Bus Collision, START Condition/STOP Condition
Detection Interrupt Control Register
BCN0IC/BCN3IC XXXX X000b
00006Ah DMA2 Transfer Complete Interrupt Control Register DM2IC XXXX X000b
00006Bh
A/D Converter 0 Convert Completion Interrupt Control Register
AD0IC XXXX X000b
00006Ch Timer A0 Interrupt Control Register TA0IC XXXX X000b
00006Dh Intelligent I/O Interrupt Control Register 0 IIO0IC XXXX X000b
00006Eh Timer A2 Interrupt Control Register TA2IC XXXX X000b
00006Fh Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X000b
000070h Timer A4 Interrupt Control Register TA4IC XXXX X000b
000071h Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X000b
000072h UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X000b
000073h Intelligent I/O Interrupt Control Register 6 IIO6IC XXXX X000b
000074h UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X000b
000075h Intelligent I/O Interrupt Control Register 8 IIO8IC XXXX X000b
000076h Timer B1 Interrupt Control Register TB1IC XXXX X000b
000077h Intelligent I/O Interrupt Control Register 10 IIO10IC XXXX X000b
000078h Timer B3 Interrupt Control Register TB3IC XXXX X000b
000079h
00007Ah INT5 Interrupt Control Register INT5IC XX00 X000b
00007Bh CAN0 Wake-up Interrupt Control Register C0WIC XXXX X000b
00007Ch INT3 Interrupt Control Register INT3IC XX00 X000b
00007Dh
00007Eh INT1 Interrupt Control Register INT1IC XX00 X000b
00007Fh
000080h
000081h UART2 Transmit/NACK Interrupt Control Register/I2C-bus
Interrupt Control Register
S2TIC/I2CIC XXXX X000b
000082h UART5 Receive/ACK Interrupt Control Register S5RIC XXXX X000b
000083h UART3 Transmit/NACK Interrupt Control Register S3TIC XXXX X000b
000084h UART6 Receive/ACK Interrupt Control Register S6RIC XXXX X000b
000085h UART4 Transmit/NACK Interrupt Control Register S4TIC XXXX X000b
000086h
000087h UART2 Bus Collision, START Condition/STOP Condition
Detection Interrupt Control Register
BCN2IC XXXX X000b
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 31 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.3 SFR List (3)
Address Register Symbol Reset Value
000088h DMA1 Transfer Complete Interrupt Control Register DM1IC XXXX X000b
000089h UART1/4 Bus Collision, START Condition/STOP Condition
Detection Interrupt Control Register
BCN1IC/BCN4IC XXXX X000b
00008Ah DMA3 Transfer Complete Interrupt Control Register DM3IC XXXX X000b
00008Bh Key Input Interrupt Control Register KUPIC XXXX X000b
00008Ch Timer A1 Interrupt Control Register TA1IC XXXX X000b
00008Dh Intelligent I/O Interrupt Control Register 1 IIO1IC XXXX X000b
00008Eh Timer A3 Interrupt Control Register TA3IC XXXX X000b
00008Fh Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X000b
000090h UART0 Transmit/NACK Interrupt Control Register S0TIC XXXX X000b
000091h Intelligent I/O Interrupt Control Register 5 IIO5IC XXXX X000b
000092h UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X000b
000093h Intelligent I/O Interrupt Control Register 7 IIO7IC XXXX X000b
000094h Timer B0 Interrupt Control Register TB0IC XXXX X000b
000095h Intelligent I/O Interrupt Control Register 9 IIO9IC XXXX X000b
000096h Timer B2 Interrupt Control Register TB2IC XXXX X000b
000097h Intelligent I/O Interrupt Control Register 11 IIO11IC XXXX X000b
000098h Timer B4 Interrupt Control Register TB4IC XXXX X000b
000099h
00009Ah INT4 Interrupt Control Register INT4IC XX00 X000b
00009Bh CAN1 Wake-up Interrupt Control Register C1WIC XXXX X000b
00009Ch INT2 Interrupt Control Register INT2IC XX00 X000b
00009Dh
00009Eh INT0 Interrupt Control Register INT0IC XX00 X000b
00009Fh
0000A0h Intelligent I/O Interrupt Request Register 0 IIO0IR 0000 0XX1b
0000A1h Intelligent I/O Interrupt Request Register 1 IIO1IR 0000 0XX1b
0000A2h Intelligent I/O Interrupt Request Register 2 IIO2IR 0000 0X01b
0000A3h Intelligent I/O Interrupt Request Register 3 IIO3IR 0000 XXX1b
0000A4h Intelligent I/O Interrupt Request Register 4 IIO4IR 000X 0XX1b
0000A5h Intelligent I/O Interrupt Request Register 5 IIO5IR 000X 0XX1b
0000A6h Intelligent I/O Interrupt Request Register 6 IIO6IR 000X 0XX1b
0000A7h Intelligent I/O Interrupt Request Register 7 IIO7IR X00X 0XX1b
0000A8h Intelligent I/O Interrupt Request Register 8 IIO8IR XX0X 0XX1b
0000A9h Intelligent I/O Interrupt Request Register 9 IIO9IR 0X00 0XX1b
0000AAh Intelligent I/O Interrupt Request Register 10 IIO10IR 0X00 0XX1b
0000ABh Intelligent I/O Interrupt Request Register 11 IIO11IR 0X00 0XX1b
0000ACh
0000ADh
0000AEh
0000AFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 32 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.4 SFR List (4)
Address Register Symbol Reset Value
0000B0h Intelligent I/O Interrupt Enable Register 0 IIO0IE 00h
0000B1h Intelligent I/O Interrupt Enable Register 1 IIO1IE 00h
0000B2h Intelligent I/O Interrupt Enable Register 2 IIO2IE 00h
0000B3h Intelligent I/O Interrupt Enable Register 3 IIO3IE 00h
0000B4h Intelligent I/O Interrupt Enable Register 4 IIO4IE 00h
0000B5h Intelligent I/O Interrupt Enable Register 5 IIO5IE 00h
0000B6h Intelligent I/O Interrupt Enable Register 6 IIO6IE 00h
0000B7h Intelligent I/O Interrupt Enable Register 7 IIO7IE 00h
0000B8h Intelligent I/O Interrupt Enable Register 8 IIO8IE 00h
0000B9h Intelligent I/O Interrupt Enable Register 9 IIO9IE 00h
0000BAh Intelligent I/O Interrupt Enable Register 10 IIO10IE 00h
0000BBh Intelligent I/O Interrupt Enable Register 11 IIO11IE 00h
0000BCh
0000BDh
0000BEh
0000BFh
0000C0h
0000C1h CAN0 Transmit Interrupt Control Register C0TIC XXXX X000b
0000C2h
0000C3h CAN0 Error Interrupt Control Register C0EIC XXXX X000b
0000C4h
0000C5h CAN1 Receive Interrupt Control Register C1RIC XXXX X000b
0000C6h
0000C7h
0000C8h
0000C9h
0000CAh
0000CBh
0000CCh
0000CDh
0000CEh
0000CFh
0000D0h CAN0 Transmit FIFO Interrupt Control Register C0FTIC XXXX X000b
0000D1h
0000D2h CAN1 Transmit FIFO Interrupt Control Register C1FTIC XXXX X000b
0000D3h
0000D4h
0000D5h
0000D6h
0000D7h
0000D8h
0000D9h
0000DAh
0000DBh
0000DCh
0000DDh UART7 Transmit Interrupt Control Register S7TIC XXXX X000b
0000DEh INT7 Interrupt Control Register INT7IC XX00 X000b
0000DFh UART8 Transmit Interrupt Control Register S8TIC XXXX X000b
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 33 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.5 SFR List (5)
Address Register Symbol Reset Value
0000E0h
0000E1h CAN0 Receive Interrupt Control Register C0RIC XXXX X000b
0000E2h
0000E3h CAN1 Transmit Interrupt Control Register C1TIC XXXX X000b
0000E4h
0000E5h CAN1 Error Interrupt Control Register C1EIC XXXX X000b
0000E6h
0000E7h
0000E8h
0000E9h
0000EAh
0000EBh
0000ECh
0000EDh
0000EEh
0000EFh
0000F0h CAN0 Receive FIFO Interrupt Control Register C0FRIC XXXX X000b
0000F1h
0000F2h CAN1 Receive FIFO Interrupt Control Register C1FRIC XXXX X000b
0000F3h
0000F4h
0000F5h
0000F6h
0000F7h
0000F8h
0000F9h
0000FAh
0000FBh
0000FCh INT8 Interrupt Control Register INT8IC XX00 X000b
0000FDh UART7 Receive Interrupt Control Register S7RIC XXXX X000b
0000FEh INT6 Interrupt Control Register INT6IC XX00 X000b
0000FFh UART8 Receive Interrupt Control Register S8RIC XXXX X000b
000100h Group 1 Time Measurement/Waveform Generation Register 0 G1TM0/G1PO0 XXXXh
000101h
000102h Group 1 Time Measurement/Waveform Generation Register 1 G1TM1/G1PO1 XXXXh
000103h
000104h Group 1 Time Measurement/Waveform Generation Register 2 G1TM2/G1PO2 XXXXh
000105h
000106h Group 1 Time Measurement/Waveform Generation Register 3 G1TM3/G1PO3 XXXXh
000107h
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 34 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.6 SFR List (6)
Address Register Symbol Reset Value
000108h Group 1 Time Measurement/Waveform Generation Register 4 G1TM4/G1PO4 XXXXh
000109h
00010Ah Group 1 Time Measurement/Waveform Generation Register 5 G1TM5/G1PO5 XXXXh
00010Bh
00010Ch Group 1 Time Measurement/Waveform Generation Register 6 G1TM6/G1PO6 XXXXh
00010Dh
00010Eh Group 1 Time Measurement/Waveform Generation Register 7 G1TM7/G1PO7 XXXXh
00010Fh
000110h Group 1 Waveform Generation Control Register 0 G1POCR0 0000 X000b
000111h Group 1 Waveform Generation Control Register 1 G1POCR1 0X00 X000b
000112h Group 1 Waveform Generation Control Register 2 G1POCR2 0X00 X000b
000113h Group 1 Waveform Generation Control Register 3 G1POCR3 0X00 X000b
000114h Group 1 Waveform Generation Control Register 4 G1POCR4 0X00 X000b
000115h Group 1 Waveform Generation Control Register 5 G1POCR5 0X00 X000b
000116h Group 1 Waveform Generation Control Register 6 G1POCR6 0X00 X000b
000117h Group 1 Waveform Generation Control Register 7 G1POCR7 0X00 X000b
000118h Group 1 Time Measurement Control Register 0 G1TMCR0 00h
000119h Group 1 Time Measurement Control Register 1 G1TMCR1 00h
00011Ah Group 1 Time Measurement Control Register 2 G1TMCR2 00h
00011Bh Group 1 Time Measurement Control Register 3 G1TMCR3 00h
00011Ch Group 1 Time Measurement Control Register 4 G1TMCR4 00h
00011Dh Group 1 Time Measurement Control Register 5 G1TMCR5 00h
00011Eh Group 1 Time Measurement Control Register 6 G1TMCR6 00h
00011Fh Group 1 Time Measurement Control Register 7 G1TMCR7 00h
000120h Group 1 Base Timer Register G1BT XXXXh
000121h
000122h Group 1 Base Timer Control Register 0 G1BCR0 0000 0000b
000123h Group 1 Base Timer Control Register 1 G1BCR1 0000 0000b
000124h Group 1 Time Measurement Prescaler Register 6 G1TPR6 00h
000125h Group 1 Time Measurement Prescaler Register 7 G1TPR7 00h
000126h Group 1 Function Enable Register G1FE 00h
000127h Group 1 Function Select Register G1FS 00h
000128h
000129h
00012Ah
00012Bh
00012Ch
00012Dh
00012Eh
00012Fh
000130h to
00013Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 35 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.7 SFR List (7)
Address Register Symbol Reset Value
000140h Group 2 Waveform Generation Register 0 G2PO0 XXXXh
000141h
000142h Group 2 Waveform Generation Register 1 G2PO1 XXXXh
000143h
000144h Group 2 Waveform Generation Register 2 G2PO2 XXXXh
000145h
000146h Group 2 Waveform Generation Register 3 G2PO3 XXXXh
000147h
000148h Group 2 Waveform Generation Register 4 G2PO4 XXXXh
000149h
00014Ah Group 2 Waveform Generation Register 5 G2PO5 XXXXh
00014Bh
00014Ch Group 2 Waveform Generation Register 6 G2PO6 XXXXh
00014Dh
00014Eh Group 2 Waveform Generation Register 7 G2PO7 XXXXh
00014Fh
000150h Group 2 Waveform Generation Control Register 0 G2POCR0 0000 0000b
000151h Group 2 Waveform Generation Control Register 1 G2POCR1 0000 0000b
000152h Group 2 Waveform Generation Control Register 2 G2POCR2 0000 0000b
000153h Group 2 Waveform Generation Control Register 3 G2POCR3 0000 0000b
000154h Group 2 Waveform Generation Control Register 4 G2POCR4 0000 0000b
000155h Group 2 Waveform Generation Control Register 5 G2POCR5 0000 0000b
000156h Group 2 Waveform Generation Control Register 6 G2POCR6 0000 0000b
000157h Group 2 Waveform Generation Control Register 7 G2POCR7 0000 0000b
000158h
000159h
00015Ah
00015Bh
00015Ch
00015Dh
00015Eh
00015Fh
000160h Group 2 Base Timer Register G2BT XXXXh
000161h
000162h Group 2 Base Timer Control Register 0 G2BCR0 0000 0000b
000163h Group 2 Base Timer Control Register 1 G2BCR1 0000 0000b
000164h Base Timer Start Register BTSR XXXX 0000b
000165h
000166h Group 2 Function Enable Register G2FE 00h
000167h Group 2 RTP Output Buffer Register G2RTP 00h
000168h
000169h
00016Ah Group 2 Serial Interface Mode Register G2MR 00XX X000b
00016Bh Group 2 Serial Interface Control Register G2CR 0000 X110b
00016Ch Group 2 SI/O Transmit Buffer Register G2TB XXXXh
00016Dh
00016Eh Group 2 SI/O Receive Buffer Register G2RB XXXXh
00016Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 36 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.8 SFR List (8)
Address Register Symbol Reset Value
000170h Group 2 IEBus Address Register IEAR XXXXh
000171h
000172h Group 2 IEBus Control Register IECR 00XX X000b
000173h Group 2 IEBus Transmit Interrupt Source Detect Register IETIF XXX0 0000b
000174h Group 2 IEBus Receive Interrupt Source Detect Register IERIF XXX0 0000b
000175h
000176h
000177h
000178h
000179h
00017Ah
00017Bh
00017Ch
00017Dh
00017Eh
00017Fh
000180h Group 0 Time Measurement/Waveform Generation Register 0 G0TM0/G0PO0 XXXXh
000181h
000182h Group 0 Time Measurement/Waveform Generation Register 1 G0TM1/G0PO1 XXXXh
000183h
000184h Group 0 Time Measurement/Waveform Generation Register 2 G0TM2/G0PO2 XXXXh
000185h
000186h Group 0 Time Measurement/Waveform Generation Register 3 G0TM3/G0PO3 XXXXh
000187h
000188h Group 0 Time Measurement/Waveform Generation Register 4 G0TM4/G0PO4 XXXXh
000189h
00018Ah Group 0 Time Measurement/Waveform Generation Register 5 G0TM5/G0PO5 XXXXh
00018Bh
00018Ch Group 0 Time Measurement/Waveform Generation Register 6 G0TM6/G0PO6 XXXXh
00018Dh
00018Eh Group 0 Time Measurement/Waveform Generation Register 7 G0TM7/G0PO7 XXXXh
00018Fh
000190h Group 0 Waveform Generation Control Register 0 G0POCR0 0000 X000b
000191h Group 0 Waveform Generation Control Register 1 G0POCR1 0X00 X000b
000192h Group 0 Waveform Generation Control Register 2 G0POCR2 0X00 X000b
000193h Group 0 Waveform Generation Control Register 3 G0POCR3 0X00 X000b
000194h Group 0 Waveform Generation Control Register 4 G0POCR4 0X00 X000b
000195h Group 0 Waveform Generation Control Register 5 G0POCR5 0X00 X000b
000196h Group 0 Waveform Generation Control Register 6 G0POCR6 0X00 X000b
000197h Group 0 Waveform Generation Control Register 7 G0POCR7 0X00 X000b
000198h Group 0 Time Measurement Control Register 0 G0TMCR0 00h
000199h Group 0 Time Measurement Control Register 1 G0TMCR1 00h
00019Ah Group 0 Time Measurement Control Register 2 G0TMCR2 00h
00019Bh Group 0 Time Measurement Control Register 3 G0TMCR3 00h
00019Ch Group 0 Time Measurement Control Register 4 G0TMCR4 00h
00019Dh Group 0 Time Measurement Control Register 5 G0TMCR5 00h
00019Eh Group 0 Time Measurement Control Register 6 G0TMCR6 00h
00019Fh Group 0 Time Measurement Control Register 7 G0TMCR7 00h
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 37 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.9 SFR List (9)
Address Register Symbol Reset Value
0001A0h Group 0 Base Timer Register G0BT XXXXh
0001A1h
0001A2h Group 0 Base Timer Control Register 0 G0BCR0 0000 0000b
0001A3h Group 0 Base Timer Control Register 1 G0BCR1 0000 0000b
0001A4h Group 0 Time Measurement Prescaler Register 6 G0TPR6 00h
0001A5h Group 0 Time Measurement Prescaler Register 7 G0TPR7 00h
0001A6h Group 0 Function Enable Register G0FE 00h
0001A7h Group 0 Function Select Register G0FS 00h
0001A8h
0001A9h
0001AAh
0001ABh
0001ACh
0001ADh
0001AEh
0001AFh
0001B0h
0001B1h
0001B2h
0001B3h
0001B4h
0001B5h
0001B6h
0001B7h
0001B8h
0001B9h
0001BAh
0001BBh
0001BCh
0001BDh
0001BEh
0001BFh
0001C0h
0001C1h
0001C2h
0001C3h
0001C4h UART5 Special Mode Register 4 U5SMR4 00h
0001C5h UART5 Special Mode Register 3 U5SMR3 00h
0001C6h UART5 Special Mode Register 2 U5SMR2 00h
0001C7h UART5 Special Mode Register U5SMR 00h
0001C8h UART5 Transmit/Receive Mode Register U5MR 00h
0001C9h UART5 Bit Rate Register U5BRG XXh
0001CAh UART5 Transmit Buffer Register U5TB XXXXh
0001CBh
0001CCh UART5 Transmit/Receive Control Register 0 U5C0 0000 1000b
0001CDh UART5 Transmit/Receive Control Register 1 U5C1 0000 0010b
0001CEh UART5 Receive Buffer Register U5RB XXXXh
0001CFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 38 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.10 SFR List (10)
Address Register Symbol Reset Value
0001D0h
0001D1h
0001D2h
0001D3h
0001D4h UART6 Special Mode Register 4 U6SMR4 00h
0001D5h UART6 Special Mode Register 3 U6SMR3 00h
0001D6h UART6 Special Mode Register 2 U6SMR2 00h
0001D7h UART6 Special Mode Register U6SMR 00h
0001D8h UART6 Transmit/Receive Mode Register U6MR 00h
0001D9h UART6 Bit Rate Register U6BRG XXh
0001DAh UART6 Transmit Buffer Register U6TB XXXXh
0001DBh
0001DCh UART6 Transmit/Receive Control Register 0 U6C0 0000 1000b
0001DDh UART6 Transmit/Receive Control Register 1 U6C1 0000 0010b
0001DEh UART6 Receive Buffer Register U6RB XXXXh
0001DFh
0001E0h UART7 Transmit/Receive Mode Register U7MR 00h
0001E1h UART7 Bit Rate Register U7BRG XXh
0001E2h UART7 Transmit Buffer Register U7TB XXXXh
0001E3h
0001E4h UART7 Transmit/Receive Control Register 0 U7C0 00X0 1000b
0001E5h UART7 Transmit/Receive Control Register 1 U7C1 XXXX 0010b
0001E6h UART7 Receive Buffer Register U7RB XXXXh
0001E7h
0001E8h UART8 Transmit/Receive Mode Register U8MR 00h
0001E9h UART8 Bit Rate Register U8BRG XXh
0001EAh UART8 Transmit Buffer Register U8TB XXXXh
0001EBh
0001ECh UART8 Transmit/Receive Control Register 0 U8C0 00X0 1000b
0001EDh UART8 Transmit/Receive Control Register 1 U8C1 XXXX 0010b
0001EEh UART8 Receive Buffer Register U8RB XXXXh
0001EFh
0001F0h UART7, UART8 Transmit/Receive Control Register 2 U78CON X000 0000b
0001F1h
0001F2h
0001F3h
0001F4h
0001F5h
0001F6h
0001F7h
0001F8h
0001F9h
0001FAh
0001FBh
0001FCh
0001FDh
0001FEh
0001FFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 39 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.11 SFR List (11)
Address Register Symbol Reset Value
000200h to
0002BFh
0002C0h X0 Register/Y0 Register X0R/Y0R XXXXh
0002C1h
0002C2h X1 Register/Y1 Register X1R/Y1R XXXXh
0002C3h
0002C4h X2 Register/Y2 Register X2R/Y2R XXXXh
0002C5h
0002C6h X3 Register/Y3 Register X3R/Y3R XXXXh
0002C7h
0002C8h X4 Register/Y4 Register X4R/Y4R XXXXh
0002C9h
0002CAh X5 Register/Y5 Register X5R/Y5R XXXXh
0002CBh
0002CCh X6 Register/Y6 Register X6R/Y6R XXXXh
0002CDh
0002CEh X7 Register/Y7 Register X7R/Y7R XXXXh
0002CFh
0002D0h X8 Register/Y8 Register X8R/Y8R XXXXh
0002D1h
0002D2h X9 Register/Y9 Register X9R/Y9R XXXXh
0002D3h
0002D4h X10 Register/Y10 Register X10R/Y10R XXXXh
0002D5h
0002D6h X11 Register/Y11 Register X11R/Y11R XXXXh
0002D7h
0002D8h X12 Register/Y12 Register X12R/Y12R XXXXh
0002D9h
0002DAh X13 Register/Y13 Register X13R/Y13R XXXXh
0002DBh
0002DCh X14 Register/Y14 Register X14R/Y14R XXXXh
0002DDh
0002DEh X15 Register/Y15 Register X15R/Y15R XXXXh
0002DFh
0002E0h X-Y Control Register XYC XXXX XX00b
0002E1h
0002E2h
0002E3h
0002E4h UART1 Special Mode Register 4 U1SMR4 00h
0002E5h UART1 Special Mode Register 3 U1SMR3 00h
0002E6h UART1 Special Mode Register 2 U1SMR2 00h
0002E7h UART1 Special Mode Register U1SMR 00h
0002E8h UART1 Transmit/Receive Mode Register U1MR 00h
0002E9h UART1 Bit Rate Register U1BRG XXh
0002EAh UART1 Transmit Buffer Register U1TB XXXXh
0002EBh
0002ECh UART1 Transmit/Receive Control Register 0 U1C0 0000 1000b
0002EDh UART1 Transmit/Receive Control Register 1 U1C1 0000 0010b
0002EEh UART1 Receive Buffer Register U1RB XXXXh
0002EFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 40 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.12 SFR List (12)
Address Register Symbol Reset Value
0002F0h
0002F1h
0002F2h
0002F3h
0002F4h UART4 Special Mode Register 4 U4SMR4 00h
0002F5h UART4 Special Mode Register 3 U4SMR3 00h
0002F6h UART4 Special Mode Register 2 U4SMR2 00h
0002F7h UART4 Special Mode Register U4SMR 00h
0002F8h UART4 Transmit/Receive Mode Register U4MR 00h
0002F9h UART4 Bit Rate Register U4BRG XXh
0002FAh UART4 Transmit Buffer Register U4TB XXXXh
0002FBh
0002FCh UART4 Transmit/Receive Control Register 0 U4C0 0000 1000b
0002FDh UART4 Transmit/Receive Control Register 1 U4C1 0000 0010b
0002FEh UART4 Receive Buffer Register U4RB XXXXh
0002FFh
000300h Count Start Register for Timers B3, B4, and B5 TBSR 000X XXXXb
000301h
000302h Timer A1-1 Register TA11 XXXXh
000303h
000304h Timer A2-1 Register TA21 XXXXh
000305h
000306h Timer A4-1 Register TA41 XXXXh
000307h
000308h Three-phase PWM Control Register 0 INVC0 00h
000309h Three-phase PWM Control Register 1 INVC1 00h
00030Ah Three-phase Output Buffer Register 0 IDB0 XX11 1111b
00030Bh Three-phase Output Buffer Register 1 IDB1 XX11 1111b
00030Ch Dead Time Timer DTT XXh
00030Dh Timer B2 Interrupt Generating Frequency Set Counter ICTB2 XXh
00030Eh
00030Fh
000310h Timer B3 Register TB3 XXXXh
000311h
000312h Timer B4 Register TB4 XXXXh
000313h
000314h Timer B5 Register TB5 XXXXh
000315h
000316h
000317h
000318h
000319h
00031Ah
00031Bh Timer B3 Mode Register TB3MR 00XX 0000b
00031Ch Timer B4 Mode Register TB4MR 00XX 0000b
00031Dh Timer B5 Mode Register TB5MR 00XX 0000b
00031Eh
00031Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 41 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.13 SFR List (13)
Address Register Symbol Reset Value
000320h
000321h
000322h
000323h
000324h UART3 Special Mode Register 4 U3SMR4 00h
000325h UART3 Special Mode Register 3 U3SMR3 00h
000326h UART3 Special Mode Register 2 U3SMR2 00h
000327h UART3 Special Mode Register U3SMR 00h
000328h UART3 Transmit/Receive Mode Register U3MR 00h
000329h UART3 Bit Rate Register U3BRG XXh
00032Ah UART3 Transmit Buffer Register U3TB XXXXh
00032Bh
00032Ch UART3 Transmit/Receive Control Register 0 U3C0 0000 1000b
00032Dh UART3 Transmit/Receive Control Register 1 U3C1 0000 0010b
00032Eh UART3 Receive Buffer Register U3RB XXXXh
00032Fh
000330h
000331h
000332h
000333h
000334h UART2 Special Mode Register 4 U2SMR4 00h
000335h UART2 Special Mode Register 3 U2SMR3 00h
000336h UART2 Special Mode Register 2 U2SMR2 00h
000337h UART2 Special Mode Register U2SMR 00h
000338h UART2 Transmit/Receive Mode Register U2MR 00h
000339h UART2 Bit Rate Register U2BRG XXh
00033Ah UART2 Transmit Buffer Register U2TB XXXXh
00033Bh
00033Ch UART2 Transmit/Receive Control Register 0 U2C0 0000 1000b
00033Dh UART2 Transmit/Receive Control Register 1 U2C1 0000 0010b
00033Eh UART2 Receive Buffer Register U2RB XXXXh
00033Fh
000340h Count Start Register TABSR 0000 0000b
000341h Clock Prescaler Reset Register CPSRF 0XXX XXXXb
000342h One-shot Start Register ONSF 0000 0000b
000343h Trigger Select Register TRGSR 0000 0000b
000344h Increment/Decrement Select Register UDF 0000 0000b
000345h
000346h Timer A0 Register TA0 XXXXh
000347h
000348h Timer A1 Register TA1 XXXXh
000349h
00034Ah Timer A2 Register TA2 XXXXh
00034Bh
00034Ch Timer A3 Register TA3 XXXXh
00034Dh
00034Eh Timer A4 Register TA4 XXXXh
00034Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 42 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.14 SFR List (14)
Address Register Symbol Reset Value
000350h Timer B0 Register TB0 XXXXh
000351h
000352h Timer B1 Register TB1 XXXXh
000353h
000354h Timer B2 Register TB2 XXXXh
000355h
000356h Timer A0 Mode Register TA0MR 0000 0000b
000357h Timer A1 Mode Register TA1MR 0000 0000b
000358h Timer A2 Mode Register TA2MR 0000 0000b
000359h Timer A3 Mode Register TA3MR 0000 0000b
00035Ah Timer A4 Mode Register TA4MR 0000 0000b
00035Bh Timer B0 Mode Register TB0MR 00XX 0000b
00035Ch Timer B1 Mode Register TB1MR 00XX 0000b
00035Dh Timer B2 Mode Register TB2MR 00XX 0000b
00035Eh Timer B2 Special Mode Register TB2SC XXXX XXX0b
00035Fh Count Source Prescaler Register TCSPR 0000 0000b
000360h
000361h
000362h
000363h
000364h UART0 Special Mode Register 4 U0SMR4 00h
000365h UART0 Special Mode Register 3 U0SMR3 00h
000366h UART0 Special Mode Register 2 U0SMR2 00h
000367h UART0 Special Mode Register U0SMR 00h
000368h UART0 Transmit/Receive Mode Register U0MR 00h
000369h UART0 Bit Rate Register U0BRG XXh
00036Ah UART0 Transmit Buffer Register U0TB XXXXh
00036Bh
00036Ch UART0 Transmit/Receive Control Register 0 U0C0 0000 1000b
00036Dh UART0 Transmit/Receive Control Register 1 U0C1 0000 0010b
00036Eh UART0 Receive Buffer Register U0RB XXXXh
00036Fh
000370h
000371h
000372h
000373h
000374h
000375h
000376h
000377h
000378h
000379h
00037Ah
00037Bh
00037Ch CRC Data Register CRCD XXXXh
00037Dh
00037Eh CRC Input Register CRCIN XXh
00037Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 43 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.15 SFR List (15)
Address Register Symbol Reset Value
000380h A/D0 Register 0 AD00 00XXh
000381h
000382h A/D0 Register 1 AD01 00XXh
000383h
000384h A/D0 Register 2 AD02 00XXh
000385h
000386h A/D0 Register 3 AD03 00XXh
000387h
000388h A/D0 Register 4 AD04 00XXh
000389h
00038Ah A/D0 Register 5 AD05 00XXh
00038Bh
00038Ch A/D0 Register 6 AD06 00XXh
00038Dh
00038Eh A/D0 Register 7 AD07 00XXh
00038Fh
000390h
000391h
000392h A/D0 Control Register 4 AD0CON4 XXXX 00XXb
000393h
000394h A/D0 Control Register 2 AD0CON2 XX0X X000b
000395h A/D0 Control Register 3 AD0CON3 XXXX X000b
000396h A/D0 Control Register 0 AD0CON0 00h
000397h A/D0 Control Register 1 AD0CON1 00h
000398h D/A Register 0 DA0 XXh
000399h
00039Ah D/A Register 1 DA1 XXh
00039Bh
00039Ch D/A Control Register DACON XXXX XX00b
00039Dh
00039Eh
00039Fh
0003A0h
0003A1h
0003A2h
0003A3h
0003A4h
0003A5h
0003A6h
0003A7h
0003A8h
0003A9h
0003AAh
0003ABh
0003ACh
0003ADh
0003AEh
0003AFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 44 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.16 SFR List (16)
Address Register Symbol Reset Value
0003B0h
0003B1h
0003B2h
0003B3h
0003B4h
0003B5h
0003B6h
0003B7h
0003B8h
0003B9h
0003BAh
0003BBh
0003BCh
0003BDh
0003BEh
0003BFh
0003C0h Port P0 Register P0 XXh
0003C1h Port P1 Register P1 XXh
0003C2h Port P0 Direction Register PD0 0000 0000b
0003C3h Port P1 Direction Register PD1 0000 0000b
0003C4h Port P2 Register P2 XXh
0003C5h Port P3 Register P3 XXh
0003C6h Port P2 Direction Register PD2 0000 0000b
0003C7h Port P3 Direction Register PD3 0000 0000b
0003C8h Port P4 Register P4 XXh
0003C9h Port P5 Register P5 XXh
0003CAh Port P4 Direction Register PD4 0000 0000b
0003CBh Port P5 Direction Register PD5 0000 0000b
0003CCh Port P6 Register P6 XXh
0003CDh Port P7 Register P7 XXh
0003CEh Port P6 Direction Register PD6 0000 0000b
0003CFh Port P7 Direction Register PD7 0000 0000b
0003D0h Port P8 Register P8 XXh
0003D1h Port P9 Register P9 XXh
0003D2h Port P8 Direction Register PD8 00X0 0000b
0003D3h Port P9 Direction Register PD9 0000 0000b
0003D4h Port P10 Register P10 XXh
0003D5h Port P11 Register P11 XXh
0003D6h Port P10 Direction Register PD10 0000 0000b
0003D7h Port P11 Direction Register PD11 XXX0 0000b
0003D8h Port P12 Register P12 XXh
0003D9h Port P13 Register P13 XXh
0003DAh Port P12 Direction Register PD12 0000 0000b
0003DBh Port P13 Direction Register PD13 0000 0000b
0003DCh Port P14 Register P14 XXh
0003DDh Port P15 Register P15 XXh
0003DEh Port P14 Direction Register PD14 X000 0000b
0003DFh Port P15 Direction Register PD15 0000 0000b
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 45 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.17 SFR List (17)
Address Register Symbol Reset Value
0003E0h
0003E1h
0003E2h
0003E3h
0003E4h
0003E5h
0003E6h
0003E7h
0003E8h
0003E9h
0003EAh
0003EBh
0003ECh
0003EDh
0003EEh
0003EFh
0003F0h Pull-up Control Register 0 PUR0 0000 0000b
0003F1h Pull-up Control Register 1 PUR1 XXXX X0XXb
0003F2h Pull-up Control Register 2 PUR2 000X XXXXb
0003F3h Pull-up Control Register 3 PUR3 0000 0000b
0003F4h Pull-up Control Register 4 PUR4 XXXX 0000b
0003F5h
0003F6h
0003F7h
0003F8h
0003F9h
0003FAh
0003FBh
0003FCh
0003FDh
0003FEh
0003FFh Port Control Register PCR 0XXX XXX0b
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 46 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Note:
1. The reset value reflects the value of the protect bit for each block in the flash memory.
Table 4.18 SFR List (18)
Address Register Symbol Reset Value
040000h Flash Memory Control Register 0 FMR0 0X01 XX00b
040001h Flash Memory Status Register 0 FMSR0 1000 0000b
040002h
040003h
040004h
040005h
040006h
040007h
040008h Flash Register Protection Unlock Register 0 FPR0 00h
040009h Flash Memory Control Register 1 FMR1 0000 0010b
04000Ah Block Protect Bit Monitor Register 0 FBPM0 ??X? ????b (1)
04000Bh Block Protect Bit Monitor Register 1 FBPM1 XXX? ????b (1)
04000Ch
04000Dh
04000Eh
04000Fh
040010h
040011h Block Protect Bit Monitor Register 2 FBPM2 ???? ????b (1)
040012h
040013h
040014h
040015h
040016h
040017h
040018h
040019h
04001Ah
04001Bh
04001Ch
04001Dh
04001Eh
04001Fh
040020h PLL Control Register 0 PLC0 0000 0001b
040021h PLL Control Register 1 PLC1 0001 1111b
040022h
040023h
040024h
040025h
040026h
040027h
040028h
040029h
04002Ah
04002Bh
04002Ch
04002Dh
04002Eh
04002Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 47 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Note:
1. The value in the PM0 register is retained even after a software reset or watchdog timer reset.
Table 4.19 SFR List (19)
Address Register Symbol Reset Value
040030h to
04003Fh
040040h
040041h
040042h
040043h
040044h Processor Mode Register 0 (1) PM0 1000 0000b
(CNVSS pin = Low)
0000 0011b
(CNVSS pin = High)
040045h
040046h System Clock Control Register 0 CM0 0000 1000b
040047h System Clock Control Register 1 CM1 0010 0000b
040048h Processor Mode Register 3 PM3 00h
040049h
04004Ah Protect Register PRCR XXXX X000b
04004Bh
04004Ch Protect Register 3 PRCR3 0000 0000b
04004Dh Oscillator Stop Detection Register CM2 00h
04004Eh
04004Fh
040050h
040051h
040052h
040053h Processor Mode Register 2 PM2 00h
040054h Chip Select Output Pin Setting Register 0 CSOP0 1000 XXXXb
040055h Chip Select Output Pin Setting Register 1 CSOP1 01X0 XXXXb
040056h Chip Select Output Pin Setting Register 2 CSOP2 XXXX 0000b
040057h
040058h
040059h
04005Ah Low Speed Mode Clock Control Register CM3 XXXX XX00b
04005Bh
04005Ch
04005Dh
04005Eh
04005Fh
040060h Voltage Regulator Control Register VRCR 0000 0000b
040061h
040062h Low Voltage Detector Control Register LVDC 0000 XX00b
040063h
040064h Detection Voltage Configuration Register DVCR 0000 XXXXb
040065h
040066h
040067h
040068h to
040093h
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 48 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.20 SFR List (20)
Address Register Symbol Reset Value
040094h
040095h
040096h
040097h Three-phase Output Buffer Control Register IOBC 0XXX XXXXb
040098h Input Function Select Register 0 IFS0 X000 0000b
040099h Input Function Select Register 1 IFS1 XXXX X0X0b
04009Ah Input Function Select Register 2 IFS2 0000 00X0b
04009Bh Input Function Select Register 3 IFS3 XXXX XX00b
04009Ch
04009Dh
04009Eh
04009Fh
0400A0h Port P0_0 Function Select Register P0_0S 0XXX X000b
0400A1h Port P1_0 Function Select Register P1_0S XXXX X000b
0400A2h Port P0_1 Function Select Register P0_1S 0XXX X000b
0400A3h Port P1_1 Function Select Register P1_1S XXXX X000b
0400A4h Port P0_2 Function Select Register P0_2S 0XXX X000b
0400A5h Port P1_2 Function Select Register P1_2S XXXX X000b
0400A6h Port P0_3 Function Select Register P0_3S 0XXX X000b
0400A7h Port P1_3 Function Select Register P1_3S XXXX X000b
0400A8h Port P0_4 Function Select Register P0_4S 0XXX X000b
0400A9h Port P1_4 Function Select Register P1_4S XXXX X000b
0400AAh Port P0_5 Function Select Register P0_5S 0XXX X000b
0400ABh Port P1_5 Function Select Register P1_5S XXXX X000b
0400ACh Port P0_6 Function Select Register P0_6S 0XXX X000b
0400ADh Port P1_6 Function Select Register P1_6S XXXX X000b
0400AEh Port P0_7 Function Select Register P0_7S 0XXX X000b
0400AFh Port P1_7 Function Select Register P1_7S XXXX X000b
0400B0h Port P2_0 Function Select Register P2_0S 0XXX X000b
0400B1h Port P3_0 Function Select Register P3_0S XXXX X000b
0400B2h Port P2_1 Function Select Register P2_1S 0XXX X000b
0400B3h Port P3_1 Function Select Register P3_1S XXXX X000b
0400B4h Port P2_2 Function Select Register P2_2S 0XXX X000b
0400B5h Port P3_2 Function Select Register P3_2S XXXX X000b
0400B6h Port P2_3 Function Select Register P2_3S 0XXX X000b
0400B7h Port P3_3 Function Select Register P3_3S XXXX X000b
0400B8h Port P2_4 Function Select Register P2_4S 0XXX X000b
0400B9h Port P3_4 Function Select Register P3_4S XXXX X000b
0400BAh Port P2_5 Function Select Register P2_5S 0XXX X000b
0400BBh Port P3_5 Function Select Register P3_5S XXXX X000b
0400BCh Port P2_6 Function Select Register P2_6S 0XXX X000b
0400BDh Port P3_6 Function Select Register P3_6S XXXX X000b
0400BEh Port P2_7 Function Select Register P2_7S 0XXX X000b
0400BFh Port P3_7 Function Select Register P3_7S XXXX X000b
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 49 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.21 SFR List (21)
Address Register Symbol Reset Value
0400C0h Port P4_0 Function Select Register P4_0S X0XX X000b
0400C1h Port P5_0 Function Select Register P5_0S XXXX X000b
0400C2h Port P4_1 Function Select Register P4_1S X0XX X000b
0400C3h Port P5_1 Function Select Register P5_1S XXXX X000b
0400C4h Port P4_2 Function Select Register P4_2S X0XX X000b
0400C5h Port P5_2 Function Select Register P5_2S XXXX X000b
0400C6h Port P4_3 Function Select Register P4_3S X0XX X000b
0400C7h Port P5_3 Function Select Register P5_3S XXXX X000b
0400C8h Port P4_4 Function Select Register P4_4S X0XX X000b
0400C9h Port P5_4 Function Select Register P5_4S X0XX X000b
0400CAh Port P4_5 Function Select Register P4_5S X0XX X000b
0400CBh Port P5_5 Function Select Register P5_5S X0XX X000b
0400CCh Port P4_6 Function Select Register P4_6S X0XX X000b
0400CDh Port P5_6 Function Select Register P5_6S X0XX X000b
0400CEh Port P4_7 Function Select Register P4_7S X0XX X000b
0400CFh Port P5_7 Function Select Register P5_7S X0XX X000b
0400D0h Port P6_0 Function Select Register P6_0S X0XX X000b
0400D1h Port P7_0 Function Select Register P7_0S X0XX X000b
0400D2h Port P6_1 Function Select Register P6_1S X0XX X000b
0400D3h Port P7_1 Function Select Register P7_1S X0XX X000b
0400D4h Port P6_2 Function Select Register P6_2S X0XX X000b
0400D5h Port P7_2 Function Select Register P7_2S X0XX X000b
0400D6h Port P6_3 Function Select Register P6_3S X0XX X000b
0400D7h Port P7_3 Function Select Register P7_3S X0XX X000b
0400D8h Port P6_4 Function Select Register P6_4S X0XX X000b
0400D9h Port P7_4 Function Select Register P7_4S X0XX X000b
0400DAh Port P6_5 Function Select Register P6_5S X0XX X000b
0400DBh Port P7_5 Function Select Register P7_5S X0XX X000b
0400DCh Port P6_6 Function Select Register P6_6S X0XX X000b
0400DDh Port P7_6 Function Select Register P7_6S X0XX X000b
0400DEh Port P6_7 Function Select Register P6_7S X0XX X000b
0400DFh Port P7_7 Function Select Register P7_7S X0XX X000b
0400E0h Port P8_0 Function Select Register P8_0S X0XX X000b
0400E1h Port P9_0 Function Select Register P9_0S X0XX X000b
0400E2h Port P8_1 Function Select Register P8_1S X0XX X000b
0400E3h Port P9_1 Function Select Register P9_1S X0XX X000b
0400E4h Port P8_2 Function Select Register P8_2S X0XX X000b
0400E5h Port P9_2 Function Select Register P9_2S X0XX X000b
0400E6h Port P8_3 Function Select Register P8_3S X0XX X000b
0400E7h Port P9_3 Function Select Register P9_3S 00XX X000b
0400E8h Port P8_4 Function Select Register P8_4S XXXX X000b
0400E9h Port P9_4 Function Select Register P9_4S 00XX X000b
0400EAh
0400EBh Port P9_5 Function Select Register P9_5S 00XX X000b
0400ECh Port P8_6 Function Select Register P8_6S XXXX X000b
0400EDh Port P9_6 Function Select Register P9_6S 00XX X000b
0400EEh Port P8_7 Function Select Register P8_7S XXXX X000b
0400EFh Port P9_7 Function Select Register P9_7S X0XX X000b
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 50 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.22 SFR List (22)
Address Register Symbol Reset Value
0400F0h Port P10_0 Function Select Register P10_0S 0XXX X000b
0400F1h Port P11_0 Function Select Register P11_0S X0XX X000b
0400F2h Port P10_1 Function Select Register P10_1S 0XXX X000b
0400F3h Port P11_1 Function Select Register P11_1S X0XX X000b
0400F4h Port P10_2 Function Select Register P10_2S 0XXX X000b
0400F5h Port P11_2 Function Select Register P11_2S X0XX X000b
0400F6h Port P10_3 Function Select Register P10_3S 0XXX X000b
0400F7h Port P11_3 Function Select Register P11_3S X0XX X000b
0400F8h Port P10_4 Function Select Register P10_4S 0XXX X000b
0400F9h Port P11_4 Function Select Register P11_4S XXXX X000b
0400FAh Port P10_5 Function Select Register P10_5S 0XXX X000b
0400FBh
0400FCh Port P10_6 Function Select Register P10_6S 0XXX X000b
0400FDh
0400FEh Port P10_7 Function Select Register P10_7S 0XXX X000b
0400FFh
040100h Port P12_0 Function Select Register P12_0S X0XX X000b
040101h Port P13_0 Function Select Register P13_0S XXXX X000b
040102h Port P12_1 Function Select Register P12_1S X0XX X000b
040103h Port P13_1 Function Select Register P13_1S XXXX X000b
040104h Port P12_2 Function Select Register P12_2S X0XX X000b
040105h Port P13_2 Function Select Register P13_2S XXXX X000b
040106h Port P12_3 Function Select Register P12_3S X0XX X000b
040107h Port P13_3 Function Select Register P13_3S XXXX X000b
040108h Port P12_4 Function Select Register P12_4S XXXX X000b
040109h Port P13_4 Function Select Register P13_4S XXXX X000b
04010Ah Port P12_5 Function Select Register P12_5S XXXX X000b
04010Bh Port P13_5 Function Select Register P13_5S XXXX X000b
04010Ch Port P12_6 Function Select Register P12_6S XXXX X000b
04010Dh Port P13_6 Function Select Register P13_6S XXXX X000b
04010Eh Port P12_7 Function Select Register P12_7S XXXX X000b
04010Fh Port P13_7 Function Select Register P13_7S XXXX X000b
040110h
040111h Port P15_0 Function Select Register P15_0S 00XX X000b
040112h
040113h Port P15_1 Function Select Register P15_1S 00XX X000b
040114h
040115h Port P15_2 Function Select Register P15_2S 00XX X000b
040116h Port P14_3 Function Select Register P14_3S XXXX X000b
040117h Port P15_3 Function Select Register P15_3S 00XX X000b
040118h Port P14_4 Function Select Register P14_4S XXXX X000b
040119h Port P15_4 Function Select Register P15_4S 00XX X000b
04011Ah Port P14_5 Function Select Register P14_5S XXXX X000b
04011Bh Port P15_5 Function Select Register P15_5S 00XX X000b
04011Ch Port P14_6 Function Select Register P14_6S XXXX X000b
04011Dh Port P15_6 Function Select Register P15_6S 00XX X000b
04011Eh
04011Fh Port P15_7 Function Select Register P15_7S 00XX X000b
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 51 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.23 SFR List (23)
Address Register Symbol Reset Value
040120h to
04403Fh
044040h
044041h
044042h
044043h
044044h
044045h
044046h
044047h
044048h
044049h
04404Ah
04404Bh
04404Ch
04404Dh
04404Eh Watchdog Timer Start Register WDTS XXXX XXXXb
04404Fh Watchdog Timer Control Register WDC 000X XXXXb
044050h
044051h
044052h
044053h
044054h
044055h
044056h
044057h
044058h
044059h
04405Ah
04405Bh
04405Ch
04405Dh
04405Eh
04405Fh Protect Register 2 PRCR2 0XXX XXXXb
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 52 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.24 SFR List (24)
Address Register Symbol Reset Value
044060h
044061h
044062h
044063h
044064h
044065h
044066h
044067h
044068h
044069h
04406Ah
04406Bh
04406Ch
04406Dh External Interrupt Request Source Select Register 1 IFSR1 X0XX X000b
04406Eh
04406Fh External Interrupt Request Source Select Register 0 IFSR0 0000 0000b
044070h DMA0 Request Source Select Register 2 DM0SL2 XX00 0000b
044071h DMA1 Request Source Select Register 2 DM1SL2 XX00 0000b
044072h DMA2 Request Source Select Register 2 DM2SL2 XX00 0000b
044073h DMA3 Request Source Select Register 2 DM3SL2 XX00 0000b
044074h
044075h
044076h
044077h
044078h DMA0 Request Source Select Register DM0SL XXX0 0000b
044079h DMA1 Request Source Select Register DM1SL XXX0 0000b
04407Ah DMA2 Request Source Select Register DM2SL XXX0 0000b
04407Bh DMA3 Request Source Select Register DM3SL XXX0 0000b
04407Ch
04407Dh Wake-up IPL Setting Register 2 RIPL2 XX0X 0000b
04407Eh
04407Fh Wake-up IPL Setting Register 1 RIPL1 XX0X 0000b
044080h
044081h
044082h
044083h
044084h
044085h
044086h
044087h
044088h
044089h
04408Ah
04408Bh
04408Ch
04408Dh
04408Eh
04408Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 53 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.25 SFR List (25)
Address Register Symbol Reset Value
044090h to
0443FFh
044400h I2C-bus Transmit/Receive Shift Register I2CTRSR XXh
044401h
044402h I2C-bus Slave Address Register I2CSAR 00h
044403h I2C-bus Control Register 0 I2CCR0 0000 0000b
044404h I2C-bus Clock Control Register I2CCCR 0000 0000b
044405h I2C-bus START and STOP Conditions Control Register I2CSSCR 0001 1010b
044406h I2C-bus Control Register 1 I2CCR1 0011 0000b
044407h I2C-bus Control Register 2 I2CCR2 0X00 0000b
044408h I2C-bus Status Register I2CSR 0001 000Xb
044409h
04440Ah
04440Bh
04440Ch
04440Dh
04440Eh
04440Fh
044410h I2C-bus Mode Register I2CMR XXXX 0000b
044411h
044412h
044413h
044414h
044415h
044416h
044417h
044418h
044419h
04441Ah
04441Bh
04441Ch
04441Dh
04441Eh
04441Fh
044420h to
0467FFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 54 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.26 SFR List (26)
Address Register Symbol Reset Value
046800h to
0477FFh
047800h CAN1 Mailbox 0: Message Identifier C1MB0 XXXX XXXXh
047801h
047802h
047803h
047804h
047805h CAN1 Mailbox 0: Data Length XXh
047806h CAN1 Mailbox 0: Data Field XXXX XXXX
XXXX XXXXh
047807h
047808h
047809h
04780Ah
04780Bh
04780Ch
04780Dh
04780Eh CAN1 Mailbox 0: Time Stamp XXXXh
04780Fh
047810h CAN1 Mailbox 1: Message Identifier C1MB1 XXXX XXXXh
047811h
047812h
047813h
047814h
047815h CAN1 Mailbox 1: Data Length XXh
047816h CAN1 Mailbox 1: Data Field XXXX XXXX
XXXX XXXXh
047817h
047818h
047819h
04781Ah
04781Bh
04781Ch
04781Dh
04781Eh CAN1 Mailbox 1: Time Stamp XXXXh
04781Fh
047820h CAN1 Mailbox 2: Message Identifier C1MB2 XXXX XXXXh
047821h
047822h
047823h
047824h
047825h CAN1 Mailbox 2: Data Length XXh
047826h CAN1 Mailbox 2: Data Field XXXX XXXX
XXXX XXXXh
047827h
047828h
047829h
04782Ah
04782Bh
04782Ch
04782Dh
04782Eh CAN1 Mailbox 2: Time Stamp XXXXh
04782Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 55 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.27 SFR List (27)
Address Register Symbol Reset Value
047830h CAN1 Mailbox 3: Message Identifier C1MB3 XXXX XXXXh
047831h
047832h
047833h
047834h
047835h CAN1 Mailbox 3: Data Length XXh
047836h CAN1 Mailbox 3: Data Field XXXX XXXX
XXXX XXXXh
047837h
047838h
047839h
04783Ah
04783Bh
04783Ch
04783Dh
04783Eh CAN1 Mailbox 3: Time Stamp XXXXh
04783Fh
047840h CAN1 Mailbox 4: Message Identifier C1MB4 XXXX XXXXh
047841h
047842h
047843h
047844h
047845h CAN1 Mailbox 4: Data Length XXh
047846h CAN1 Mailbox 4: Data Field XXXX XXXX
XXXX XXXXh
047847h
047848h
047849h
04784Ah
04784Bh
04784Ch
04784Dh
04784Eh CAN1 Mailbox 4: Time Stamp XXXXh
04784Fh
047850h CAN1 Mailbox 5: Message Identifier C1MB5 XXXX XXXXh
047851h
047852h
047853h
047854h
047855h CAN1 Mailbox 5: Data Length XXh
047856h CAN1 Mailbox 5: Data Field XXXX XXXX
XXXX XXXXh
047857h
047858h
047859h
04785Ah
04785Bh
04785Ch
04785Dh
04785Eh CAN1 Mailbox 5: Time Stamp XXXXh
04785Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 56 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.28 SFR List (28)
Address Register Symbol Reset Value
047860h CAN1 Mailbox 6: Message Identifier C1MB6 XXXX XXXXh
047861h
047862h
047863h
047864h
047865h CAN1 Mailbox 6: Data Length XXh
047866h CAN1 Mailbox 6: Data Field XXXX XXXX
XXXX XXXXh
047867h
047868h
047869h
04786Ah
04786Bh
04786Ch
04786Dh
04786Eh CAN1 Mailbox 6: Time Stamp XXXXh
04786Fh
047870h CAN1 Mailbox 7: Message Identifier C1MB7 XXXX XXXXh
047871h
047872h
047873h
047874h
047875h CAN1 Mailbox 7: Data Length XXh
047876h CAN1 Mailbox 7: Data Field XXXX XXXX
XXXX XXXXh
047877h
047878h
047879h
04787Ah
04787Bh
04787Ch
04787Dh
04787Eh CAN1 Mailbox 7: Time Stamp XXXXh
04787Fh
047880h CAN1 Mailbox 8: Message Identifier C1MB8 XXXX XXXXh
047881h
047882h
047883h
047884h
047885h CAN1 Mailbox 8: Data Length XXh
047886h CAN1 Mailbox 8: Data Field XXXX XXXX
XXXX XXXXh
047887h
047888h
047889h
04788Ah
04788Bh
04788Ch
04788Dh
04788Eh CAN1 Mailbox 8: Time Stamp XXXXh
04788Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 57 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.29 SFR List (29)
Address Register Symbol Reset Value
047890h CAN1 Mailbox 9: Message Identifier C1MB9 XXXX XXXXh
047891h
047892h
047893h
047894h
047895h CAN1 Mailbox 9: Data Length XXh
047896h CAN1 Mailbox 9: Data Field XXXX XXXX
XXXX XXXXh
047897h
047898h
047899h
04789Ah
04789Bh
04789Ch
04789Dh
04789Eh CAN1 Mailbox 9: Time Stamp XXXXh
04789Fh
0478A0h CAN1 Mailbox 10: Message Identifier C1MB10 XXXX XXXXh
0478A1h
0478A2h
0478A3h
0478A4h
0478A5h CAN1 Mailbox 10: Data Length XXh
0478A6h CAN1 Mailbox 10: Data Field XXXX XXXX
XXXX XXXXh
0478A7h
0478A8h
0478A9h
0478AAh
0478ABh
0478ACh
0478ADh
0478AEh CAN1 Mailbox 10: Time Stamp XXXXh
0478AFh
0478B0h CAN1 Mailbox 11: Message Identifier C1MB11 XXXX XXXXh
0478B1h
0478B2h
0478B3h
0478B4h
0478B5h CAN1 Mailbox 11: Data Length XXh
0478B6h CAN1 Mailbox 11: Data Field XXXX XXXX
XXXX XXXXh
0478B7h
0478B8h
0478B9h
0478BAh
0478BBh
0478BCh
0478BDh
0478BEh CAN1 Mailbox 11: Time Stamp XXXXh
0478BFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 58 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.30 SFR List (30)
Address Register Symbol Reset Value
0478C0h CAN1 Mailbox 12: Message Identifier C1MB12 XXXX XXXXh
0478C1h
0478C2h
0478C3h
0478C4h
0478C5h CAN1 Mailbox 12: Data Length XXh
0478C6h CAN1 Mailbox 12: Data Field XXXX XXXX
XXXX XXXXh
0478C7h
0478C8h
0478C9h
0478CAh
0478CBh
0478CCh
0478CDh
0478CEh CAN1 Mailbox 12: Time Stamp XXXXh
0478CFh
0478D0h CAN1 Mailbox 13: Message Identifier C1MB13 XXXX XXXXh
0478D1h
0478D2h
0478D3h
0478D4h
0478D5h CAN1 Mailbox 13: Data Length XXh
0478D6h CAN1 Mailbox 13: Data Field XXXX XXXX
XXXX XXXXh
0478D7h
0478D8h
0478D9h
0478DAh
0478DBh
0478DCh
0478DDh
0478DEh CAN1 Mailbox 13: Time Stamp XXXXh
0478DFh
0478E0h CAN1 Mailbox 14: Message Identifier C1MB14 XXXX XXXXh
0478E1h
0478E2h
0478E3h
0478E4h
0478E5h CAN1 Mailbox 14: Data Length XXh
0478E6h CAN1 Mailbox 14: Data Field XXXX XXXX
XXXX XXXXh
0478E7h
0478E8h
0478E9h
0478EAh
0478EBh
0478ECh
0478EDh
0478EEh CAN1 Mailbox 14: Time Stamp XXXXh
0478EFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 59 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.31 SFR List (31)
Address Register Symbol Reset Value
0478F0h CAN1 Mailbox 15: Message Identifier C1MB15 XXXX XXXXh
0478F1h
0478F2h
0478F3h
0478F4h
0478F5h CAN1 Mailbox 15: Data Length XXh
0478F6h CAN1 Mailbox 15: Data Field XXXX XXXX
XXXX XXXXh
0478F7h
0478F8h
0478F9h
0478FAh
0478FBh
0478FCh
0478FDh
0478FEh CAN1 Mailbox 15: Time Stamp XXXXh
0478FFh
047900h CAN1 Mailbox 16: Message Identifier C1MB16 XXXX XXXXh
047901h
047902h
047903h
047904h
047905h CAN1 Mailbox 16: Data Length XXh
047906h CAN1 Mailbox 16: Data Field XXXX XXXX
XXXX XXXXh
047907h
047908h
047909h
04790Ah
04790Bh
04790Ch
04790Dh
04790Eh CAN1 Mailbox 16: Time Stamp XXXXh
04790Fh
047910h CAN1 Mailbox 17: Message Identifier C1MB17 XXXX XXXXh
047911h
047912h
047913h
047914h
047915h CAN1 Mailbox 17: Data Length XXh
047916h CAN1 Mailbox 17: Data Field XXXX XXXX
XXXX XXXXh
047917h
047918h
047919h
04791Ah
04791Bh
04791Ch
04791Dh
04791Eh CAN1 Mailbox 17: Time Stamp XXXXh
04791Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 60 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.32 SFR List (32)
Address Register Symbol Reset Value
047920h CAN1 Mailbox 18: Message Identifier C1MB18 XXXX XXXXh
047921h
047922h
047923h
047924h
047925h CAN1 Mailbox 18: Data Length XXh
047926h CAN1 Mailbox 18: Data Field XXXX XXXX
XXXX XXXXh
047927h
047928h
047929h
04792Ah
04792Bh
04792Ch
04792Dh
04792Eh CAN1 Mailbox18: Time Stamp XXXXh
04792Fh
047930h CAN1 Mailbox 19: Message Identifier C1MB19 XXXX XXXXh
047931h
047932h
047933h
047934h
047935h CAN1 Mailbox 19: Data Length XXh
047936h CAN1 Mailbox 19: Data Field XXXX XXXX
XXXX XXXXh
047937h
047938h
047939h
04793Ah
04793Bh
04793Ch
04793Dh
04793Eh CAN1 Mailbox 19: Time Stamp XXXXh
04793Fh
047940h CAN1 Mailbox 20: Message Identifier C1MB20 XXXX XXXXh
047941h
047942h
047943h
047944h
047945h CAN1 Mailbox 20: Data Length XXh
047946h CAN1 Mailbox 20: Data Field XXXX XXXX
XXXX XXXXh
047947h
047948h
047949h
04794Ah
04794Bh
04794Ch
04794Dh
04794Eh CAN1 Mailbox 20: Time Stamp XXXXh
04794Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 61 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.33 SFR List (33)
Address Register Symbol Reset Value
047950h CAN1 Mailbox 21: Message Identifier C1MB21 XXXX XXXXh
047951h
047952h
047953h
047954h
047955h CAN1 Mailbox 21: Data Length XXh
047956h CAN1 Mailbox 21: Data Field XXXX XXXX
XXXX XXXXh
047957h
047958h
047959h
04795Ah
04795Bh
04795Ch
04795Dh
04795Eh CAN1 Mailbox 21: Time Stamp XXXXh
04795Fh
047960h CAN1 Mailbox 22: Identifier C1MB22 XXXX XXXXh
047961h
047962h
047963h
047964h
047965h CAN1 Mailbox 22: Data Length XXh
047966h CAN1 Mailbox 22: Data Field XXXX XXXX
XXXX XXXXh
047967h
047968h
047969h
04796Ah
04796Bh
04796Ch
04796Dh
04796Eh CAN1 Mailbox 22: Time Stamp XXXXh
04796Fh
047970h CAN1 Mailbox 23: Message Identifier C1MB23 XXXX XXXXh
047971h
047972h
047973h
047974h
047975h CAN1 Mailbox 23: Data Length XXh
047976h CAN1 Mailbox 23: Data Field XXXX XXXX
XXXX XXXXh
047977h
047978h
047979h
04797Ah
04797Bh
04797Ch
04797Dh
04797Eh CAN1 Mailbox 23: Time Stamp XXXXh
04797Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 62 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.34 SFR List (34)
Address Register Symbol Reset Value
047980h CAN1 Mailbox 24: Message Identifier C1MB24 XXXX XXXXh
047981h
047982h
047983h
047984h
047985h CAN1 Mailbox 24: Data Length XXh
047986h CAN1 Mailbox 24: Data Field XXXX XXXX
XXXX XXXXh
047987h
047988h
047989h
04798Ah
04798Bh
04798Ch
04798Dh
04798Eh CAN1 Mailbox 24: Time Stamp XXXXh
04798Fh
047990h CAN1 Mailbox 25: Message Identifier C1MB25 XXXX XXXXh
047991h
047992h
047993h
047994h
047995h CAN1 Mailbox 25: Data Length XXh
047996h CAN1 Mailbox 25: Data Field XXXX XXXX
XXXX XXXXh
047997h
047998h
047999h
04799Ah
04799Bh
04799Ch
04799Dh
04799Eh CAN1 Mailbox 25: Time Stamp XXXXh
04799Fh
0479A0h CAN1 Mailbox 26: Message Identifier C1MB26 XXXX XXXXh
0479A1h
0479A2h
0479A3h
0479A4h
0479A5h CAN1 Mailbox 26: Data Length XXh
0479A6h CAN1 Mailbox 26: Data Field XXXX XXXX
XXXX XXXXh
0479A7h
0479A8h
0479A9h
0479AAh
0479ABh
0479ACh
0479ADh
0479AEh CAN1 Mailbox 26: Time Stamp XXXXh
0479AFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 63 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.35 SFR List (35)
Address Register Symbol Reset Value
0479B0h CAN1 Mailbox 27: Message Identifier C1MB27 XXXX XXXXh
0479B1h
0479B2h
0479B3h
0479B4h
0479B5h CAN1 Mailbox 27: Data Length XXh
0479B6h CAN1 Mailbox 27: Data Field XXXX XXXX
XXXX XXXXh
0479B7h
0479B8h
0479B9h
0479BAh
0479BBh
0479BCh
0479BDh
0479BEh CAN1 Mailbox 27: Time Stamp XXXXh
0479BFh
0479C0h CAN1 Mailbox 28: Message Identifier C1MB28 XXXX XXXXh
0479C1h
0479C2h
0479C3h
0479C4h
0479C5h CAN1 Mailbox 28: Data Length XXh
0479C6h CAN1 Mailbox 28: Data Field XXXX XXXX
XXXX XXXXh
0479C7h
0479C8h
0479C9h
0479CAh
0479CBh
0479CCh
0479CDh
0479CEh CAN1 Mailbox 28: Time Stamp XXXXh
0479CFh
0479D0h CAN1 Mailbox 29: Message Identifier C1MB29 XXXX XXXXh
0479D1h
0479D2h
0479D3h
0479D4h
0479D5h CAN1 Mailbox 29: Data Length XXh
0479D6h CAN1 Mailbox 29: Data Field XXXX XXXX
XXXX XXXXh
0479D7h
0479D8h
0479D9h
0479DAh
0479DBh
0479DCh
0479DDh
0479DEh CAN1 Mailbox 29: Time Stamp XXXXh
0479DFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 64 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.36 SFR List (36)
Address Register Symbol Reset Value
0479E0h CAN1 Mailbox 30: Message Identifier C1MB30 XXXX XXXXh
0479E1h
0479E2h
0479E3h
0479E4h
0479E5h CAN1 Mailbox 30: Data Length XXh
0479E6h CAN1 Mailbox 30: Data Field XXXX XXXX
XXXX XXXXh
0479E7h
0479E8h
0479E9h
0479EAh
0479EBh
0479ECh
0479EDh
0479EEh CAN1 Mailbox 30: Time Stamp XXXXh
0479EFh
0479F0h CAN1 Mailbox 31: Message Identifier C1MB31 XXXX XXXXh
0479F1h
0479F2h
0479F3h
0479F4h
0479F5h CAN1 Mailbox 31: Data Length XXh
0479F6h CAN1 Mailbox 31: Data Field XXXX XXXX
XXXX XXXXh
0479F7h
0479F8h
0479F9h
0479FAh
0479FBh
0479FCh
0479FDh
0479FEh CAN1 Mailbox 31: Time Stamp XXXXh
0479FFh
047A00h CAN1 Mask Register 0 C1MKR0 XXXX XXXXh
047A01h
047A02h
047A03h
047A04h CAN1 Mask Register 1 C1MKR1 XXXX XXXXh
047A05h
047A06h
047A07h
047A08h CAN1 Mask Register 2 C1MKR2 XXXX XXXXh
047A09h
047A0Ah
047A0Bh
047A0Ch CAN1 Mask Register 3 C1MKR3 XXXX XXXXh
047A0Dh
047A0Eh
047A0Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 65 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.37 SFR List (37)
Address Register Symbol Reset Value
047A10h CAN1 Mask Register 4 C1MKR4 XXXX XXXXh
047A11h
047A12h
047A13h
047A14h CAN1 Mask Register 5 C1MKR5 XXXX XXXXh
047A15h
047A16h
047A17h
047A18h CAN1 Mask Register 6 C1MKR6 XXXX XXXXh
047A19h
047A1Ah
047A1Bh
047A1Ch CAN1 Mask Register 7 C1MKR7 XXXX XXXXh
047A1Dh
047A1Eh
047A1Fh
047A20h CAN1 FIFO Received ID Compare Register 0 C1FIDCR0 XXXX XXXXh
047A21h
047A22h
047A23h
047A24h CAN1 FIFO Received ID Compare Register 1 C1FIDCR1 XXXX XXXXh
047A25h
047A26h
047A27h
047A28h CAN1 Mask Invalid Register C1MKIVLR XXXX XXXXh
047A29h
047A2Ah
047A2Bh
047A2Ch CAN1 Mailbox Interrupt Enable Register C1MIER XXXX XXXXh
047A2Dh
047A2Eh
047A2Fh
047A30h
047A31h
047A32h
047A33h
047A34h
047A35h
047A36h
047A37h
047A38h
047A39h
047A3Ah
047A3Bh
047A3Ch
047A3Dh
047A3Eh
047A3Fh
047A40h to
047B1Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 66 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.38 SFR List (38)
Address Register Symbol Reset Value
047B20h CAN1 Message Control Register 0 C1MCTL0 00h
047B21h CAN1 Message Control Register 1 C1MCTL1 00h
047B22h CAN1 Message Control Register 2 C1MCTL2 00h
047B23h CAN1 Message Control Register 3 C1MCTL3 00h
047B24h CAN1 Message Control Register 4 C1MCTL4 00h
047B25h CAN1 Message Control Register 5 C1MCTL5 00h
047B26h CAN1 Message Control Register 6 C1MCTL6 00h
047B27h CAN1 Message Control Register 7 C1MCTL7 00h
047B28h CAN1 Message Control Register 8 C1MCTL8 00h
047B29h CAN1 Message Control Register 9 C1MCTL9 00h
047B2Ah CAN1 Message Control Register 10 C1MCTL10 00h
047B2Bh CAN1 Message Control Register 11 C1MCTL11 00h
047B2Ch CAN1 Message Control Register 12 C1MCTL12 00h
047B2Dh CAN1 Message Control Register 13 C1MCTL13 00h
047B2Eh CAN1 Message Control Register 14 C1MCTL14 00h
047B2Fh CAN1 Message Control Register 15 C1MCTL15 00h
047B30h CAN1 Message Control Register 16 C1MCTL16 00h
047B31h CAN1 Message Control Register 17 C1MCTL17 00h
047B32h CAN1 Message Control Register 18 C1MCTL18 00h
047B33h CAN1 Message Control Register 19 C1MCTL19 00h
047B34h CAN1 Message Control Register 20 C1MCTL20 00h
047B35h CAN1 Message Control Register 21 C1MCTL21 00h
047B36h CAN1 Message Control Register 22 C1MCTL22 00h
047B37h CAN1 Message Control Register 23 C1MCTL23 00h
047B38h CAN1 Message Control Register 24 C1MCTL24 00h
047B39h CAN1 Message Control Register 25 C1MCTL25 00h
047B3Ah CAN1 Message Control Register 26 C1MCTL26 00h
047B3Bh CAN1 Message Control Register 27 C1MCTL27 00h
047B3Ch CAN1 Message Control Register 28 C1MCTL28 00h
047B3Dh CAN1 Message Control Register 29 C1MCTL29 00h
047B3Eh CAN1 Message Control Register 30 C1MCTL30 00h
047B3Fh CAN1 Message Control Register 31 C1MCTL31 00h
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 67 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.39 SFR List (39)
Address Register Symbol Reset Value
047B40h CAN1 Control Register C1CTLR 0000 0101b
047B41h 0000 0000b
047B42h CAN1 Status Register C1STR 0000 0101b
047B43h 0000 0000b
047B44h CAN1 Bit Configuration Register C1BCR 00 0000h
047B45h
047B46h
047B47h CAN1 Clock Select Register C1CLKR 000X 0000b
047B48h CAN1 Receive FIFO Control Register C1RFCR 1000 0000b
047B49h CAN1 Receive FIFO Pointer Control Register C1RFPCR XXh
047B4Ah CAN1 Transmit FIFO Control Register C1TFCR 1000 0000b
047B4Bh CAN1 Transmit FIFO Pointer Control Register C1TFPCR XXh
047B4Ch CAN1 Error Interrupt Enable Register C1EIER 00h
047B4Dh CAN1 Error Interrupt Factor Judge Register C1EIFR 00h
047B4Eh CAN1 Receive Error Count Register C1RECR 00h
047B4Fh CAN1 Transmit Error Count Register C1TECR 00h
047B50h CAN1 Error Code Store Register C1ECSR 00h
047B51h CAN1 Channel Search Support Register C1CSSR XXh
047B52h CAN1 Mailbox Search Status Register C1MSSR 1000 0000b
047B53h CAN1 Mailbox Search Mode Register C1MSMR 0000 0000b
047B54h CAN1 Time Stamp Register C1TSR 0000h
047B55h
047B56h CAN1 Acceptance Filter Support Register C1AFSR XXXXh
047B57h
047B58h CAN1 Test Control Register C1TCR 00h
047B59h
047B5Ah
047B5Bh
047B5Ch
047B5Dh
047B5Eh
047B5Fh
047B60h to
047BFFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 68 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.40 SFR List (40)
Address Register Symbol Reset Value
047C00h CAN0 Mailbox 0: Message Identifier C0MB0 XXXX XXXXh
047C01h
047C02h
047C03h
047C04h
047C05h CAN0 Mailbox 0: Data Length XXh
047C06h CAN0 Mailbox 0: Data Field XXXX XXXX
XXXX XXXXh
047C07h
047C08h
047C09h
047C0Ah
047C0Bh
047C0Ch
047C0Dh
047C0Eh CAN0 Mailbox 0: Time Stamp XXXXh
047C0Fh
047C10h CAN0 Mailbox 1: Message Identifier C0MB1 XXXX XXXXh
047C11h
047C12h
047C13h
047C14h
047C15h CAN0 Mailbox 1: Data Length XXh
047C16h CAN0 Mailbox 1: Data Field XXXX XXXX
XXXX XXXXh
047C17h
047C18h
047C19h
047C1Ah
047C1Bh
047C1Ch
047C1Dh
047C1Eh CAN0 Mailbox 1: Time Stamp XXXXh
047C1Fh
047C20h CAN0 Mailbox 2: Message Identifier C0MB2 XXXX XXXXh
047C21h
047C22h
047C23h
047C24h
047C25h CAN0 Mailbox 2: Data Length XXh
047C26h CAN0 Mailbox 2: Data Field XXXX XXXX
XXXX XXXXh
047C27h
047C28h
047C29h
047C2Ah
047C2Bh
047C2Ch
047C2Dh
047C2Eh CAN0 Mailbox 2: Time Stamp XXXXh
047C2Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 69 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.41 SFR List (41)
Address Register Symbol Reset Value
047C30h CAN0 Mailbox 3: Message Identifier C0MB3 XXXX XXXXh
047C31h
047C32h
047C33h
047C34h
047C35h CAN0 Mailbox 3: Data Length XXh
047C36h CAN0 Mailbox 3: Data Field XXXX XXXX
XXXX XXXXh
047C37h
047C38h
047C39h
047C3Ah
047C3Bh
047C3Ch
047C3Dh
047C3Eh CAN0 Mailbox 3: Time Stamp XXXXh
047C3Fh
047C40h CAN0 Mailbox 4: Message Identifier C0MB4 XXXX XXXXh
047C41h
047C42h
047C43h
047C44h
047C45h CAN0 Mailbox 4: Data Length XXh
047C46h CAN0 Mailbox 4: Data Field XXXX XXXX
XXXX XXXXh
047C47h
047C48h
047C49h
047C4Ah
047C4Bh
047C4Ch
047C4Dh
047C4Eh CAN0 Mailbox 4: Time Stamp XXXXh
047C4Fh
047C50h CAN0 Mailbox 5: Message Identifier C0MB5 XXXX XXXXh
047C51h
047C52h
047C53h
047C54h
047C55h CAN0 Mailbox 5: Data Length XXh
047C56h CAN0 Mailbox 5: Data Field XXXX XXXX
XXXX XXXXh
047C57h
047C58h
047C59h
047C5Ah
047C5Bh
047C5Ch
047C5Dh
047C5Eh CAN0 Mailbox 5: Time Stamp XXXXh
047C5Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 70 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.42 SFR List (42)
Address Register Symbol Reset Value
047C60h CAN0 Mailbox 6: Message Identifier C0MB6 XXXX XXXXh
047C61h
047C62h
047C63h
047C64h
047C65h CAN0 Mailbox 6: Data Length XXh
047C66h CAN0 Mailbox 6: Data Field XXXX XXXX
XXXX XXXXh
047C67h
047C68h
047C69h
047C6Ah
047C6Bh
047C6Ch
047C6Dh
047C6Eh CAN0 Mailbox 6: Time Stamp XXXXh
047C6Fh
047C70h CAN0 Mailbox 7: Message Identifier C0MB7 XXXX XXXXh
047C71h
047C72h
047C73h
047C74h
047C75h CAN0 Mailbox 7: Data Length XXh
047C76h CAN0 Mailbox 7: Data Field XXXX XXXX
XXXX XXXXh
047C77h
047C78h
047C79h
047C7Ah
047C7Bh
047C7Ch
047C7Dh
047C7Eh CAN0 Mailbox 7: Time Stamp XXXXh
047C7Fh
047C80h CAN0 Mailbox 8: Message Identifier C0MB8 XXXX XXXXh
047C81h
047C82h
047C83h
047C84h
047C85h CAN0 Mailbox 8: Data Length XXh
047C86h CAN0 Mailbox 8: Data Field XXXX XXXX
XXXX XXXXh
047C87h
047C88h
047C89h
047C8Ah
047C8Bh
047C8Ch
047C8Dh
047C8Eh CAN0 Mailbox 8: Time Stamp XXXXh
047C8Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 71 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.43 SFR List (43)
Address Register Symbol Reset Value
047C90h CAN0 Mailbox 9: Message Identifier C0MB9 XXXX XXXXh
047C91h
047C92h
047C93h
047C94h
047C95h CAN0 Mailbox 9: Data Length XXh
047C96h CAN0 Mailbox 9: Data Field XXXX XXXX
XXXX XXXXh
047C97h
047C98h
047C99h
047C9Ah
047C9Bh
047C9Ch
047C9Dh
047C9Eh CAN0 Mailbox 9: Time Stamp XXXXh
047C9Fh
047CA0h CAN0 Mailbox 10: Message Identifier C0MB10 XXXX XXXXh
047CA1h
047CA2h
047CA3h
047CA4h
047CA5h CAN0 Mailbox 10: Data Length XXh
047CA6h CAN0 Mailbox 10: Data Field XXXX XXXX
XXXX XXXXh
047CA7h
047CA8h
047CA9h
047CAAh
047CABh
047CACh
047CADh
047CAEh CAN0 Mailbox 10: Time Stamp XXXXh
047CAFh
047CB0h CAN0 Mailbox 11: Message Identifier C0MB11 XXXX XXXXh
047CB1h
047CB2h
047CB3h
047CB4h
047CB5h CAN0 Mailbox 11: Data Length XXh
047CB6h CAN0 Mailbox 11: Data Field XXXX XXXX
XXXX XXXXh
047CB7h
047CB8h
047CB9h
047CBAh
047CBBh
047CBCh
047CBDh
047CBEh CAN0 Mailbox 11: Time Stamp XXXXh
047CBFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 72 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.44 SFR List (44)
Address Register Symbol Reset Value
047CC0h CAN0 Mailbox 12: Message Identifier C0MB12 XXXX XXXXh
047CC1h
047CC2h
047CC3h
047CC4h
047CC5h CAN0 Mailbox 12: Data Length XXh
047CC6h CAN0 Mailbox 12: Data Field XXXX XXXX
XXXX XXXXh
047CC7h
047CC8h
047CC9h
047CCAh
047CCBh
047CCCh
047CCDh
047CCEh CAN0 Mailbox 12: Time Stamp XXXXh
047CCFh
047CD0h CAN0 Mailbox 13: Message Identifier C0MB13 XXXX XXXXh
047CD1h
047CD2h
047CD3h
047CD4h
047CD5h CAN0 Mailbox 13: Data Length XXh
047CD6h CAN0 Mailbox 13: Data Field XXXX XXXX
XXXX XXXXh
047CD7h
047CD8h
047CD9h
047CDAh
047CDBh
047CDCh
047CDDh
047CDEh CAN0 Mailbox 13: Time Stamp XXXXh
047CDFh
047CE0h CAN0 Mailbox 14: Message Identifier C0MB14 XXXX XXXXh
047CE1h
047CE2h
047CE3h
047CE4h
047CE5h CAN0 Mailbox 14: Data Length XXh
047CE6h CAN0 Mailbox 14: Data Field XXXX XXXX
XXXX XXXXh
047CE7h
047CE8h
047CE9h
047CEAh
047CEBh
047CECh
047CEDh
047CEEh CAN0 Mailbox 14: Time Stamp XXXXh
047CEFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 73 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.45 SFR List (45)
Address Register Symbol Reset Value
047CF0h CAN0 Mailbox 15: Message Identifier C0MB15 XXXX XXXXh
047CF1h
047CF2h
047CF3h
047CF4h
047CF5h CAN0 Mailbox 15: Data Length XXh
047CF6h CAN0 Mailbox 15: Data Field XXXX XXXX
XXXX XXXXh
047CF7h
047CF8h
047CF9h
047CFAh
047CFBh
047CFCh
047CFDh
047CFEh CAN0 Mailbox 15: Time Stamp XXXXh
047CFFh
047D00h CAN0 Mailbox 16: Message Identifier C0MB16 XXXX XXXXh
047D01h
047D02h
047D03h
047D04h
047D05h CAN0 Mailbox 16: Data Length XXh
047D06h CAN0 Mailbox 16: Data Field XXXX XXXX
XXXX XXXXh
047D07h
047D08h
047D09h
047D0Ah
047D0Bh
047D0Ch
047D0Dh
047D0Eh CAN0 Mailbox 16: Time Stamp XXXXh
047D0Fh
047D10h CAN0 Mailbox 17: Message Identifier C0MB17 XXXX XXXXh
047D11h
047D12h
047D13h
047D14h
047D15h CAN0 Mailbox 17: Data Length XXh
047D16h CAN0 Mailbox 17: Data Field XXXX XXXX
XXXX XXXXh
047D17h
047D18h
047D19h
047D1Ah
047D1Bh
047D1Ch
047D1Dh
047D1Eh CAN0 Mailbox 17: Time Stamp XXXXh
047D1Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 74 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.46 SFR List (46)
Address Register Symbol Reset Value
047D20h CAN0 Mailbox 18: Message Identifier C0MB18 XXXX XXXXh
047D21h
047D22h
047D23h
047D24h
047D25h CAN0 Mailbox 18: Data Length XXh
047D26h CAN0 Mailbox 18: Data Field XXXX XXXX
XXXX XXXXh
047D27h
047D28h
047D29h
047D2Ah
047D2Bh
047D2Ch
047D2Dh
047D2Eh CAN0 Mailbox 18: Time Stamp XXXXh
047D2Fh
047D30h CAN0 Mailbox 19: Message Identifier C0MB19 XXXX XXXXh
047D31h
047D32h
047D33h
047D34h
047D35h CAN0 Mailbox 19: Data Length XXh
047D36h CAN0 Mailbox 19: Data Field XXXX XXXX
XXXX XXXXh
047D37h
047D38h
047D39h
047D3Ah
047D3Bh
047D3Ch
047D3Dh
047D3Eh CAN0 Mailbox 19: Time Stamp XXXXh
047D3Fh
047D40h CAN0 Mailbox 20: Message Identifier C0MB20 XXXX XXXXh
047D41h
047D42h
047D43h
047D44h
047D45h CAN0 Mailbox 20: Data Length XXh
047D46h CAN0 Mailbox 20: Data Field XXXX XXXX
XXXX XXXXh
047D47h
047D48h
047D49h
047D4Ah
047D4Bh
047D4Ch
047D4Dh
047D4Eh CAN0 Mailbox 20: Time Stamp XXXXh
047D4Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 75 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.47 SFR List (47)
Address Register Symbol Reset Value
047D50h CAN0 Mailbox 21: Message Identifier C0MB21 XXXX XXXXh
047D51h
047D52h
047D53h
047D54h
047D55h CAN0 Mailbox 21: Data Length XXh
047D56h CAN0 Mailbox 21: Data Field XXXX XXXX
XXXX XXXXh
047D57h
047D58h
047D59h
047D5Ah
047D5Bh
047D5Ch
047D5Dh
047D5Eh CAN0 Mailbox 21: Time Stamp XXXXh
047D5Fh
047D60h CAN0 Mailbox 22: Message Identifier C0MB22 XXXX XXXXh
047D61h
047D62h
047D63h
047D64h
047D65h CAN0 Mailbox 22: Data Length XXh
047D66h CAN0 Mailbox 22: Data Field XXXX XXXX
XXXX XXXXh
047D67h
047D68h
047D69h
047D6Ah
047D6Bh
047D6Ch
047D6Dh
047D6Eh CAN0 Mailbox 22: Time Stamp XXXXh
047D6Fh
047D70h CAN0 Mailbox 23: Message Identifier C0MB23 XXXX XXXXh
047D71h
047D72h
047D73h
047D74h
047D75h CAN0 Mailbox 23: Data Length XXh
047D76h CAN0 Mailbox 23: Data Field XXXX XXXX
XXXX XXXXh
047D77h
047D78h
047D79h
047D7Ah
047D7Bh
047D7Ch
047D7Dh
047D7Eh CAN0 Mailbox 23: Time Stamp XXXXh
047D7Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 76 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.48 SFR List (48)
Address Register Symbol Reset Value
047D80h CAN0 Mailbox 24: Message Identifier C0MB24 XXXX XXXXh
047D81h
047D82h
047D83h
047D84h
047D85h CAN0 Mailbox 24: Data Length XXh
047D86h CAN0 Mailbox 24: Data Field XXXX XXXX
XXXX XXXXh
047D87h
047D88h
047D89h
047D8Ah
047D8Bh
047D8Ch
047D8Dh
047D8Eh CAN0 Mailbox 24: Time Stamp XXXXh
047D8Fh
047D90h CAN0 Mailbox 25: Message Identifier C0MB25 XXXX XXXXh
047D91h
047D92h
047D93h
047D94h
047D95h CAN0 Mailbox 25: Data Length XXh
047D96h CAN0 Mailbox 25: Data Field XXXX XXXX
XXXX XXXXh
047D97h
047D98h
047D99h
047D9Ah
047D9Bh
047D9Ch
047D9Dh
047D9Eh CAN0 Mailbox 25: Time Stamp XXXXh
047D9Fh
047DA0h CAN0 Mailbox 26: Message Identifier C0MB26 XXXX XXXXh
047DA1h
047DA2h
047DA3h
047DA4h
047DA5h CAN0 Mailbox 26: Data Length XXh
047DA6h CAN0 Mailbox 26: Data Field XXXX XXXX
XXXX XXXXh
047DA7h
047DA8h
047DA9h
047DAAh
047DABh
047DACh
047DADh
047DAEh CAN0 Mailbox 26: Time Stamp XXXXh
047DAFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 77 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.49 SFR List (49)
Address Register Symbol Reset Value
047DB0h CAN0 Mailbox 27: Message Identifier C0MB27 XXXX XXXXh
047DB1h
047DB2h
047DB3h
047DB4h
047DB5h CAN0 Mailbox 27: Data Length XXh
047DB6h CAN0 Mailbox 27: Data Field XXXX XXXX
XXXX XXXXh
047DB7h
047DB8h
047DB9h
047DBAh
047DBBh
047DBCh
047DBDh
047DBEh CAN0 Mailbox 27: Time Stamp XXXXh
047DBFh
047DC0h CAN0 Mailbox 28: Message Identifier C0MB28 XXXX XXXXh
047DC1h
047DC2h
047DC3h
047DC4h
047DC5h CAN0 Mailbox 28: Data Length XXh
047DC6h CAN0 Mailbox 28: Data Field XXXX XXXX
XXXX XXXXh
047DC7h
047DC8h
047DC9h
047DCAh
047DCBh
047DCCh
047DCDh
047DCEh CAN0 Mailbox 28: Time Stamp XXXXh
047DCFh
047DD0h CAN0 Mailbox 29: Message Identifier C0MB29 XXXX XXXXh
047DD1h
047DD2h
047DD3h
047DD4h
047DD5h CAN0 Mailbox 29: Data Length XXh
047DD6h CAN0 Mailbox 29: Data Field XXXX XXXX
XXXX XXXXh
047DD7h
047DD8h
047DD9h
047DDAh
047DDBh
047DDCh
047DDDh
047DDEh CAN0 Mailbox 29: Time Stamp XXXXh
047DDFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 78 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.50 SFR List (50)
Address Register Symbol Reset Value
047DE0h CAN0 Mailbox 30: Message Identifier C0MB30 XXXX XXXXh
047DE1h
047DE2h
047DE3h
047DE4h
047DE5h CAN0 Mailbox 30: Data Length XXh
047DE6h CAN0 Mailbox 30: Data Field XXXX XXXX
XXXX XXXXh
047DE7h
047DE8h
047DE9h
047DEAh
047DEBh
047DECh
047DEDh
047DEEh CAN0 Mailbox 30: Time Stamp XXXXh
047DEFh
047DF0h CAN0 Mailbox 31: Message Identifier C0MB31 XXXX XXXXh
047DF1h
047DF2h
047DF3h
047DF4h
047DF5h CAN0 Mailbox 31: Data Length XXh
047DF6h CAN0 Mailbox 31: Data Field XXXX XXXX
XXXX XXXXh
047DF7h
047DF8h
047DF9h
047DFAh
047DFBh
047DFCh
047DFDh
047DFEh CAN0 Mailbox 31: Time Stamp XXXXh
047DFFh
047E00h CAN0 Mask Register 0 C0MKR0 XXXX XXXXh
047E01h
047E02h
047E03h
047E04h CAN0 Mask Register 1 C0MKR1 XXXX XXXXh
047E05h
047E06h
047E07h
047E08h CAN0 Mask Register 2 C0MKR2 XXXX XXXXh
047E09h
047E0Ah
047E0Bh
047E0Ch CAN0 Mask Register 3 C0MKR3 XXXX XXXXh
047E0Dh
047E0Eh
047E0Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 79 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.51 SFR List (51)
Address Register Symbol Reset Value
047E10h CAN0 Mask Register 4 C0MKR4 XXXX XXXXh
047E11h
047E12h
047E13h
047E14h CAN0 Mask Register 5 C0MKR5 XXXX XXXXh
047E15h
047E16h
047E17h
047E18h CAN0 Mask Register 6 C0MKR6 XXXX XXXXh
047E19h
047E1Ah
047E1Bh
047E1Ch CAN0 Mask Register 7 C0MKR7 XXXX XXXXh
047E1Dh
047E1Eh
047E1Fh
047E20h CAN0 FIFO Receive ID Compare Register 0 C0FIDCR0 XXXX XXXXh
047E21h
047E22h
047E23h
047E24h CAN0 FIFO Receive ID Compare Register 1 C0FIDCR1 XXXX XXXXh
047E25h
047E26h
047E27h
047E28h CAN0 Mask Invalid Register C0MKIVLR XXXX XXXXh
047E29h
047E2Ah
047E2Bh
047E2Ch CAN0 Mailbox Interrupt Enable Register C0MIER XXXX XXXXh
047E2Dh
047E2Eh
047E2Fh
047E30h
047E31h
047E32h
047E33h
047E34h
047E35h
047E36h
047E37h
047E38h
047E39h
047E3Ah
047E3Bh
047E3Ch
047E3Dh
047E3Eh
047E3Fh
047E40h to
047F1Fh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 80 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.52 SFR List (52)
Address Register Symbol Reset Value
047F20h CAN0 Message Control Register 0 C0MCTL0 00h
047F21h CAN0 Message Control Register 1 C0MCTL1 00h
047F22h CAN0 Message Control Register 2 C0MCTL2 00h
047F23h CAN0 Message Control Register 3 C0MCTL3 00h
047F24h CAN0 Message Control Register 4 C0MCTL4 00h
047F25h CAN0 Message Control Register 5 C0MCTL5 00h
047F26h CAN0 Message Control Register 6 C0MCTL6 00h
047F27h CAN0 Message Control Register 7 C0MCTL7 00h
047F28h CAN0 Message Control Register 8 C0MCTL8 00h
047F29h CAN0 Message Control Register 9 C0MCTL9 00h
047F2Ah CAN0 Message Control Register 10 C0MCTL10 00h
047F2Bh CAN0 Message Control Register 11 C0MCTL11 00h
047F2Ch CAN0 Message Control Register 12 C0MCTL12 00h
047F2Dh CAN0 Message Control Register 13 C0MCTL13 00h
047F2Eh CAN0 Message Control Register 14 C0MCTL14 00h
047F2Fh CAN0 Message Control Register 15 C0MCTL15 00h
047F30h CAN0 Message Control Register 16 C0MCTL16 00h
047F31h CAN0 Message Control Register 17 C0MCTL17 00h
047F32h CAN0 Message Control Register 18 C0MCTL18 00h
047F33h CAN0 Message Control Register 19 C0MCTL19 00h
047F34h CAN0 Message Control Register 20 C0MCTL20 00h
047F35h CAN0 Message Control Register 21 C0MCTL21 00h
047F36h CAN0 Message Control Register 22 C0MCTL22 00h
047F37h CAN0 Message Control Register 23 C0MCTL23 00h
047F38h CAN0 Message Control Register 24 C0MCTL24 00h
047F39h CAN0 Message Control Register 25 C0MCTL25 00h
047F3Ah CAN0 Message Control Register 26 C0MCTL26 00h
047F3Bh CAN0 Message Control Register 27 C0MCTL27 00h
047F3Ch CAN0 Message Control Register 28 C0MCTL28 00h
047F3Dh CAN0 Message Control Register 29 C0MCTL29 00h
047F3Eh CAN0 Message Control Register 30 C0MCTL30 00h
047F3Fh CAN0 Message Control Register 31 C0MCTL31 00h
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 81 of 123
Feb 6, 2013
R32C/118 Group 4. Special Function Registers (SFRs)
Table 4.53 SFR List (53)
Address Register Symbol Reset Value
047F40h CAN0 Control Register C0CTLR 0000 0101b
047F41h 0000 0000b
047F42h CAN0 Status Register C0STR 0000 0101b
047F43h 0000 0000b
047F44h CAN0 Bit Configuration Register C0BCR 00 0000h
047F45h
047F46h
047F47h CAN0 Clock Select Register C0CLKR 000X 0000b
047F48h CAN0 Receive FIFO Control Register C0RFCR 1000 0000b
047F49h CAN0 Receive FIFO Pointer Control Register C0RFPCR XXh
047F4Ah CAN0 Transmit FIFO Control Register C0TFCR 1000 0000b
047F4Bh CAN0 Transmit FIFO Pointer Control Register C0TFPCR XXh
047F4Ch CAN0 Error Interrupt Enable Register C0EIER 00h
047F4Dh CAN0 Error Interrupt Factor Judge Register C0EIFR 00h
047F4Eh CAN0 Receive Error Count Register C0RECR 00h
047F4Fh CAN0 Transmit Error Count Register C0TECR 00h
047F50h CAN0 Error Code Store Register C0ECSR 00h
047F51h CAN0 Channel Search Support Register C0CSSR XXh
047F52h CAN0 Mailbox Search Status Register C0MSSR 1000 0000b
047F53h CAN0 Mailbox Search Mode Register C0MSMR 0000 0000b
047F54h CAN0 Time Stamp Register C0TSR 0000h
047F55h
047F56h CAN0 Acceptance Filter Support Register C0AFSR XXXXh
047F57h
047F58h CAN0 Test Control Register C0TCR 00h
047F59h
047F5Ah
047F5Bh
047F5Ch
047F5Dh
047F5Eh
047F5Fh
047F60h to
047FFFh
048000h to
04FFFFh
X: Undefined
Blanks are reserved. No access is allowed.
R01DS0065EJ0120 Rev.1.20 Page 82 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
5. Electrical Characteristics
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
Table 5.1 Absolute Maximum Ratings (1)
Symbol Characteristic Condition Value Unit
VCC Supply voltage VCC = AVCC -0.3 to 6.0 V
AVCC Analog supply voltage VCC = AVCC -0.3 to 6.0 V
VIInput
voltage
XIN, RESET, CNVSS, NSD, VREF
,
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P5_0 to P5_3, P8_4 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0toP11_4, P12_0toP12_7,
P13_0 to P13_7, P14_1,
P14_3 to P14_6, P15_0 to P15_7 (2)
-0.3 to VCC + 0.3 V
P4_0 to P4_7, P5_4 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_3
-0.3 to 6.0 V
VOOutput
voltage
XOUT, P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0toP11_4, P12_0toP12_7,
P13_0 to P13_7, P14_3 to P14_6,
P15_0 to P15_7 (2)
-0.3 to VCC + 0.3 V
PdPower consumption Ta = 25°C 500 mW
— Operating temperature range -40 to 85 °C
Tstg Storage temperature range -65 to 150 °C
R01DS0065EJ0120 Rev.1.20 Page 83 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable
for P8_7 as XCIN.
3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
Table 5.2 Operating Conditions (1/5) (1)
Symbol Characteristic Value Unit
Min. Typ. Max.
VCC Digital supply voltage 3.0 5.0 5.5 V
AVCC Analog supply voltage VCC V
VREF Reference voltage 3.0 VCC V
VSS Digital ground voltage 0V
AVSS Analog ground voltage 0V
dVCC/dt VCC ramp up rate (VCC < 2.0 V) 0.05 V/ms
VIH High level
input
voltage
XIN, RESET, CNVSS, NSD, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7 (2),
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (3)
0.8 × VCC VCC V
P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_3 0.8 × VCC 6.0 V
P0_0 to P0_7,
P1_0 to P1_7,
P12_0 to P12_7,
P13_0 to P13_7
(3)
in single-chip mode 0.8 × VCC VCC V
in memory expansion mode
or microprocessor mode 0.5 × VCC VCC V
VIL Low level
input
voltage
XIN, RESET, CNVSS, NSD, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7 (2),
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (3)
00.2 × VCC V
P0_0 to P0_7,
P1_0 to P1_7,
P12_0 to P12_7,
P13_0 to P13_7
(3)
in single-chip mode 00.2 × VCC V
in memory expansion mode
or microprocessor mode 00.16 × VCC V
Topr Operating
temperature
range
N version -20 85 °C
D version -40 85 °C
P version -40 85 °C
R01DS0065EJ0120 Rev.1.20 Page 84 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. This value should be met with due consideration to the following conditions: operating temperature,
DC bias, aging, etc.
Table 5.3 Operating Conditions (2/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted) (1)
Symbol Characteristic Value (2)
Unit
Min. Typ. Max.
CVDC Decoupling capacitance for voltage
regulator
Inter-pin voltage: 1.5 V 2.4 10.0 µF
R01DS0065EJ0120 Rev.1.20 Page 85 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. The following conditions should be satisfied:
• The sum of IOL(peak) of ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 is 80 mA or less.
• The sum of IOL(peak) of ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 is 80 mA or less.
• The sum of IOH(peak) of ports P0, P1, P2, and P11 is -40 mA or less.
• The sum of IOH(peak) of ports P8_6, P8_7, P9, P10, P14, and P15 is -40 mA or less.
• The sum of IOH(peak) of ports P3, P4, P5, P12, and P13 is -40 mA or less.
• The sum of IOH(peak) of ports P6, P7, and P8_0 to P8_4 is -40 mA or less.
3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
4. Average value within 100 ms.
Table 5.4 Operating Conditions (3/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted) (1)
Symbol Characteristic Value Unit
Min. Typ. Max.
IOH(peak) High level
peak
output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
-10.0 mA
IOH(avg) High level
average
output
current (4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
-5.0 mA
IOL(peak) Low level
peak
output
current (2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
10.0 mA
IOL(avg) Low level
average
output
current (4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (3)
5.0 mA
R01DS0065EJ0120 Rev.1.20 Page 86 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Note:
1. The device is operationally guaranteed under these operating conditions.
Figure 5.1 Clock Cycle Time
Table 5.5 Operating Conditions (4/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted) (1)
Symbol Characteristic Value Unit
Min. Typ. Max.
f(XIN) Main clock oscillator frequency 416MHz
f(XRef) Reference clock frequency 24MHz
f(PLL) PLL clock oscillator frequency 96 128 MHz
f(Base) Base clock frequency High speed version 64 MHz
Normal speed version 50 MHz
tc(Base) Base clock cycle time High speed version 15.625 ns
Normal speed version 20 ns
f(CPU) CPU operating frequency High speed version 64 MHz
Normal speed version 50 MHz
tc(CPU) CPU clock cycle time High speed version 15.625 ns
Normal speed version 20 ns
f(BCLK) Peripheral bus clock operating
frequency
High speed version 32 MHz
Normal speed version 25 MHz
tc(BCLK) Peripheral bus clock cycle time High speed version 31.25 ns
Normal speed version 40 ns
f(PER) Peripheral clock source frequency 32 MHz
f(XCIN) Sub clock oscillator frequency 32.768 62.5 kHz
Base clock
(internal signal)
t
c(Base)
Peripheral bus clock
(internal signal)
t
c(BCLK)
CPU clock
(internal signal)
t
c(CPU)
R01DS0065EJ0120 Rev.1.20 Page 87 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Note:
1. The device is operationally guaranteed under these operating conditions.
Figure 5.2 Ripple Waveform
Table 5.6 Operating Conditions (5/5)
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted) (1)
Symbol Characteristic Value Unit
Min. Typ. Max.
Vr(VCC) Allowable ripple voltage VCC = 5.0 V 0.5 Vp-p
VCC = 3.0 V 0.3 Vp-p
dVr(VCC)/dt Ripple voltage gradient VCC = 5.0 V ±0.3 V/ms
VCC = 3.0 V ±0.3 V/ms
fr(VCC) Allowable ripple frequency 10 kHz
VCC
1 / fr(VCC)
Vr(VCC)
R01DS0065EJ0120 Rev.1.20 Page 88 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Notes:
1. Program/erase definition
This value represents the number of erasures per block.
When the number of program/erase cycles is n, each block can be erased n times.
For example, if a 4-word write is performed in 512 different addresses in the 4-Kbyte block A and
then the block is erased, this is counted as a single program/erase operation.
However, the same address cannot be written to more than once per erasure (overwrite disabled).
2. Data retention includes periods when no supply voltage is applied and no clock is provided.
3. Contact a Renesas Electronics sales office for data retention times other than the above condition.
Table 5.7 Electrical Characteristics of RAM
(VCC = 3.0 to 5.5 V, VSS =0V, and Ta=T
opr, unless otherwise noted)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Typ. Max.
VRDR RAM data retention voltage In stop mode 2.0 V
Table 5.8 Electrical Characteristics of Flash Memory
(VCC = 3.0 to 5.5 V, VSS =0V, and Ta=T
opr, unless otherwise noted)
Symbol Characteristic Value Unit
Min. Typ. Max.
—Program/erase cycles (1) Program area 1000 Cycles
Data area 10000 Cycles
— 4-word program time Program area 150 900 µs
Data area 300 1700 µs
— Lock bit program time Program area 70 500 µs
Data area 140 1000 µs
— Block erasure time 4-Kbyte block 0.12 3.0 s
32-Kbyte block 0.17 3.0 s
64-Kbyte block 0.20 3.0 s
—Data retention (2) Ta = 55°C (3) 10 Years
R01DS0065EJ0120 Rev.1.20 Page 89 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Figure 5.3 Power Supply Circuit Timing
Table 5.9 Power Supply Circuit Timing Characteristics
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Typ. Max.
td(P-R) Internal power supply start-up stabilization
time after the main power supply is turned on 2ms
Table 5.10 Electrical Characteristics of Voltage Regulator for Internal Logic
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Symbol Characteristics Measurement
Condition
Value Unit
Min. Typ. Max.
VVDC1 Output voltage 1.5 V
Table 5.11 Electrical Characteristics of Low Voltage Detector
(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Symbol Characteristics Measurement
Condition
Value Unit
Min. Typ. Max.
Vdet Detected voltage error ±0.3 V
Vdet(R)-Vdet(F) Hysteresis width 0 V
—Self-consuming current VCC = 5.0 V, low voltage
detector enabled 4µA
td(E-A) Operation start time of low voltage detector 150 µs
t
d(P-R)
VCC
PLL oscillator-
output waveform
Internal power supply start-up
stabilization time after the main
power supply is turned on
Recommended
operating voltage
t
d(P-R)
Supply voltage for
internal logic
R01DS0065EJ0120 Rev.1.20 Page 90 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Note:
1. This value is applicable only when the main clock oscillation is stable.
Note:
1. The recovery time from stop mode does not include the main clock oscillation stabilization time. The
CPU starts operating before the oscillator is stabilized.
Figure 5.4 Clock Circuit Timing
Table 5.12 Electrical Characteristics of Oscillator
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Symbol Characteristics Measurement
Condition
Value Unit
Min. Typ. Max.
fSO(PLL) PLL clock self-oscillation frequency 35 50 65 MHz
tLOCK(PLL) PLL lock time (1) 1ms
tjitter(p-p) PLL jitter period (p-p) 2.0 ns
f(OCO) On-chip oscillator frequency 62.5 125 250 kHz
Table 5.13 Electrical Characteristics of Clock Circuitry
(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Symbol Characteristics Measurement
Condition
Value Unit
Min. Typ. Max.
trec(WAIT) Recovery time from wait mode to low power mode 225 µs
trec(STOP) Recovery time from stop mode (1) 225 µs
t
rec(STOP)
Interrupt for exiting
stop mode
CPU clock
Main clock oscillator
output
On-chip oscillator
output
Sub clock oscillator
output
On-chip oscillator
output
t
rec(WAIT)
Interrupt for exiting
wait mode
CPU clock
Recovery time from stop mode
t
rec(STOP)
Recovery time from wait mode
to low power mode
t
rec(WAIT)
R01DS0065EJ0120 Rev.1.20 Page 91 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)
Figure 5.5 Flash Memory CPU Rewrite Mode Timing
Table 5.14 Flash Memory CPU Rewrite Mode Timing
Symbol Characteristics Value Unit
Min. Max.
tcR Read cycle time 200 ns
tsu(S-R) Chip-select setup time before read 200 ns
th(R-S) Chip-select hold time after read 0ns
tsu(A-R) Address setup time before read 200 ns
th(R-A) Address hold time after read 0ns
tw(R) Read pulse width 100 ns
tcW Write cycle time 200 ns
tsu(S-W) Chip-select setup time before write 0ns
th(W-S) Chip-select hold time after write 30 ns
tsu(A-W) Address setup time before write 0ns
th(W-A) Address hold time after write 30 ns
tw(W) Write pulse width 50 ns
Chip select
Address
RD
t
h(R-S)
Read cycle
t
w(R)
t
su(S-R)
t
h(R-A)
t
su(A-R)
Write cycle
Chip select
Address
WR
t
h(W-S)
t
w(W)
t
su(S-W)
t
h(W-A)
t
su(A-W)
t
cW
t
cR
R01DS0065EJ0120 Rev.1.20 Page 92 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Note:
1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
Table 5.15 Electrical Characteristics (1/3)
(VCC = 4.2 to 5.5 V, VSS =0V, T
a=T
opr, and f(CPU) = 64 MHz, unless otherwise noted)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Typ. Max.
VOH High
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0toP10_7, P11_0toP11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOH = -5 mA VCC - 2.0 VCC V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0toP10_7, P11_0toP11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOH = -200 µA VCC - 0.3 VCC V
VOL Low
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0toP10_7, P11_0toP11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOL = 5 mA 2.0 V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0toP10_7, P11_0toP11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOL = 200 µA 0.45 V
R01DS0065EJ0120 Rev.1.20 Page 93 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Notes:
1. Pins INT6 to INT8 are available in the 144-pin package only.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
Table 5.16 Electrical Characteristics (2/3)
(VCC = 4.2 to 5.5 V, VSS =0V, T
a=T
opr, and f(CPU) = 64 MHz, unless otherwise noted)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Typ. Max.
VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS8,
CLK0 to CLK8, RXD0 to RXD8,
SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,
SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7,
IIO1_0 to IIO1_7, UD0A, UD0B, UD1A,
UD1B, ISCLK2, ISRXD2, IEIN, MSCL,
MSDA, CAN0IN, CAN1IN, CAN0WU,
CAN1WU (1)
0.2 1.0 V
RESET 0.2 1.8 V
IIH High level
input
current
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 5 V 5.0 µA
IIL Low level
input
current
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 0 V -5.0 µA
RPULLUP Pull-up
resistor
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 0 V 30 50 170 k
RfXIN Feedback
resistor
XIN 1.5 M
RfXCIN Feedback
resistor
XCIN 15 M
R01DS0065EJ0120 Rev.1.20 Page 94 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Table 5.17 Electrical Characteristics (3/3)
(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Symbol Characterist
ic Measurement Condition Value Unit
Min. Typ. Max.
ICC Power supply
current
In single-chip mode,
output pins are left open
and others are
connected to VSS
XIN-XOUT
Drive strength: low
XCIN-XCOUT
Drive strength: low
f(CPU) =64MHz, f
(BCLK) =32MHz,
f(XIN) =8MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
45 60 mA
f(CPU) = 50 MHz, f(BCLK) = 25 MHz,
f(XIN) =8MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
35 50 mA
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
12 mA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) =8MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
1.2 mA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
220 µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
230 µA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) =8MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
960 1600 µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8140µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10 150 µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
570µA
R01DS0065EJ0120 Rev.1.20 Page 95 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Note:
1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.
Table 5.18 A/D Conversion Characteristics (VCC =AV
CC =V
REF =4.2to5.5V, V
SS =AV
SS =0V,
Ta=T
opr, and f(BCLK) = 32 MHz, unless otherwise noted)
Symbol Characteristic Measurement Condition Value Unit
Min. Typ. Max.
—Resolution VREF = VCC 10 Bits
—
Absolute error VREF = VCC = 5 V AN_0toAN_7,
AN0_0toAN0_7,
AN2_0toAN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
±3 LSB
External op-amp
connection mode ±7 LSB
INL Integral non-linearity
error
VREF = VCC = 5 V AN_0toAN_7,
AN0_0toAN0_7,
AN2_0toAN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
±3 LSB
External op-amp
connection mode ±7 LSB
DNL Differential non-linearity
error ±1 LSB
— Offset error ±3 LSB
— Gain error ±3 LSB
RLADDER Resistor ladder VREF = VCC 420k
tCONV Conversion time
(10 bits)
AD = 16 MHz, with sample and hold
function 2.06 µs
AD = 16 MHz, without sample and hold
function 3.69 µs
tCONV Conversion time
(8 bits)
AD = 16 MHz, with sample and hold
function 1.75 µs
AD = 16 MHz, without sample and hold
function 3.06 µs
tSAMP Sampling time AD = 16 MHz 0.188 µs
VIA Analog input voltage 0VREF V
AD Operating clock
frequency
Without sample and hold function 0.25 16 MHz
With sample and hold function 1 16 MHz
R01DS0065EJ0120 Rev.1.20 Page 96 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for the A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
Table 5.19 D/A Conversion Characteristics (VCC =AV
CC =V
REF =4.2to5.5V, V
SS =AV
SS =0V,
and Ta=T
opr, unless otherwise noted)
Symbol Characteristic Measurement Condition Value Unit
Min. Typ. Max.
— Resolution 8Bits
— Absolute precision 1.0 %
tSSettling time 3µs
ROOutput resistance 41020k
IVREF Reference input current See Note 1 1.5 mA
R01DS0065EJ0120 Rev.1.20 Page 97 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.20 External Clock Input
Symbol Characteristic Value Unit
Min. Max.
tc(X) External clock input period 62.5 250 ns
tw(XH) External clock input high level pulse width 25 ns
tw(XL) External clock input low level pulse width 25 ns
tr(X) External clock input rise time 5ns
tf(X) External clock input fall time 5ns
tw / tcExternal clock input duty 40 60 %
Table 5.21 External Bus Timing
Symbol Characteristic Value Unit
Min. Max.
tsu(D-R) Data setup time before read 40 ns
th(R-D) Data hold time after read 0ns
tdis(R-D) Data disable time after read 0.5 × tc(Base) + 10 ns
R01DS0065EJ0120 Rev.1.20 Page 98 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.22 Timer A Input (counting input in event counter mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TA) TAiIN input clock cycle time 200 ns
tw(TAH) TAiIN input high level pulse width 80 ns
tw(TAL) TAiIN input low level pulse width 80 ns
Table 5.23 Timer A Input (gating input in timer mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TA) TAiIN input clock cycle time 400 ns
tw(TAH) TAiIN input high level pulse width 180 ns
tw(TAL) TAiIN input low level pulse width 180 ns
Table 5.24 Timer A Input (external trigger input in one-shot timer mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TA) TAiIN input clock cycle time 200 ns
tw(TAH) TAiIN input high level pulse width 80 ns
tw(TAL) TAiIN input low level pulse width 80 ns
Table 5.25 Timer A Input (external trigger input in pulse-width modulation mode)
Symbol Characteristic Value Unit
Min. Max.
tw(TAH) TAiIN input high level pulse width 80 ns
tw(TAL) TAiIN input low level pulse width 80 ns
Table 5.26 Timer A Input (increment/decrement switching input in event counter mode)
Symbol Characteristic Value Unit
Min. Max.
tc(UP) TAiOUT input clock cycle time 2000 ns
tw(UPH) TAiOUT input high level pulse width 1000 ns
tw(UPL) TAiOUT input low level pulse width 1000 ns
tsu(UP-TIN) TAiOUT input setup time 400 ns
th(TIN-UP) TAiOUT input hold time 400 ns
R01DS0065EJ0120 Rev.1.20 Page 99 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.27 Timer B Input (counting input in event counter mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TB) TBiIN input clock cycle time (one edge counting) 200 ns
tw(TBH) TBiIN input high level pulse width (one edge counting) 80 ns
tw(TBL) TBiIN input low level pulse width (one edge counting) 80 ns
tc(TB) TBiIN input clock cycle time (both edges counting) 200 ns
tw(TBH) TBiIN input high level pulse width (both edges counting) 80 ns
tw(TBL) TBiIN input low level pulse width (both edges counting) 80 ns
Table 5.28 Timer B Input (pulse period measure mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TB) TBiIN input clock cycle time 400 ns
tw(TBH) TBiIN input high level pulse width 180 ns
tw(TBL) TBiIN input low level pulse width 180 ns
Table 5.29 Timer B Input (pulse-width measure mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TB) TBiIN input clock cycle time 400 ns
tw(TBH) TBiIN input high level pulse width 180 ns
tw(TBL) TBiIN input low level pulse width 180 ns
R01DS0065EJ0120 Rev.1.20 Page 100 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.30 Serial Interface
Symbol Characteristic Value Unit
Min. Max.
tc(CK) CLKi input clock cycle time 200 ns
tw(CKH) CLKi input high level pulse width 80 ns
tw(CKL) CLKi input low level pulse width 80 ns
tsu(D-C) RXDi input setup time 80 ns
th(C-D) RXDi input hold time 90 ns
Table 5.31 A/D Trigger Input
Symbol Characteristic Value Unit
Min. Max.
tw(ADH) ADTRG input high level pulse width
Hardware trigger input high level pulse width ns
tw(ADL) ADTRG input low level pulse width
Hardware trigger input high level pulse width 125 ns
Table 5.32 External Interrupt INTi Input
Symbol Characteristic Value Unit
Min. Max.
tw(INH) INTi input high level pulse width Edge sensitive 250 ns
Level sensitive tc(CPU) + 200 ns
tw(INL) INTi input low level pulse width Edge sensitive 250 ns
Level sensitive tc(CPU) + 200 ns
Table 5.33 Intelligent I/O
Symbol Characteristic Value Unit
Min. Max.
tc(ISCLK2) ISCLK2 input clock cycle time 600 ns
tw(ISCLK2H) ISCLK2 input high level pulse width 270 ns
tw(ISCLK2L) ISCLK2 input low level pulse width 270 ns
tsu(RXD-ISCLK2) ISRXD2 input setup time 150 ns
th(ISCLK2-RXD) ISRXD2 input hold time 100 ns
3
AD
----------
R01DS0065EJ0120 Rev.1.20 Page 101 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. The value is calculated by the following formulas based on a value SSC by setting bits SSC4 to
SSC0 in the I2CSSCR register:
th(SDA-SCL)S = SSC ÷ 2 × tc(IIC) + 40 [ns]
tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(IIC) + 40 [ns]
tw(SDAH)P = (SSC + 1) × tc(IIC) + 40 [ns]
Table 5.34 Multi-master I2C-bus Interface
Symbol Characteristic
Value
UnitStandard-mode Fast-mode
Min. Max. Min. Max.
tw(SCLH) MSCL input high level pulse width 600 600 ns
tw(SCLL) MSCL input low level pulse width 600 600 ns
tr(SCL) MSCL input rise time 1000 300 ns
tf(SCL) MSCL input fall time 300 300 ns
tr(SDA) MSDA input rise time 1000 300 ns
tf(SDA) MSDA input fall time 300 300 ns
th(SDA-SCL)S MSCL high level hold time after
START condition/repeated START
condition
(1) 2 × tc(IIC) + 40 ns
tsu(SCL-SDA)P MSCL high level setup time for
repeated START condition/STOP
condition
(1) 2 × tc(IIC) + 40 ns
tw(SDAH)P MSDA high level pulse width after
STOP condition (1) 4 × tc(IIC) + 40 ns
tsu(SDA-SCL) MSDA input setup time 100 100 ns
th(SCL-SDA) MSDA input hold time 00ns
R01DS0065EJ0120 Rev.1.20 Page 102 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For details on how to set values,
refer to the User’s manual.
tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
tw(R) = Tw(R) × tc(Base) - 10 [ns]
tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
Table 5.35 External Bus Timing (separate bus)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tsu(S-R) Chip-select setup time before
read
Refer to
Figure 5.6
(1) ns
th(R-S) Chip-select hold time after read tc(Base) - 15 ns
tsu(A-R) Address setup time before read (1) ns
th(R-A) Address hold time after read tc(Base) - 15 ns
tw(R) Read pulse width (1) ns
tsu(S-W) Chip-select setup time before
write (1) ns
th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns
tsu(A-W) Address setup time before write (1) ns
th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns
tw(W) Write pulse width (1) ns
tsu(D-W) Data setup time before write (1) ns
th(W-D) Data hold time after write 0ns
R01DS0065EJ0120 Rev.1.20 Page 103 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For details on how to set values,
refer to the User’s manual.
tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]
tw(R) = Tw(R) × tc(Base) -10 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]
Table 5.36 External Bus Timing (multiplexed bus)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tsu(S-ALE) Chip-select setup time before
ALE
Refer to
Figure 5.6
(1) ns
th(R-S) Chip-select hold time after read 1.5 × tc(Base) - 15 ns
tsu(A-ALE) Address setup time before ALE (1) ns
th(ALE-A) Address hold time after ALE 0.5 × tc(Base) - 5 ns
th(R-A) Address hold time after read 1.5 × tc(Base) - 15 ns
td(ALE-R) ALE-read delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(ALE) ALE pulse width (1) ns
tdis(R-A) Address disable time after read 8ns
tw(R) Read pulse width (1) ns
th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns
th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns
td(ALE-W) ALE-write delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(W) Write pulse width (1) ns
tsu(D-W) Data setup time before write (1) ns
th(W-D) Data hold time after write 0.5 × tc(Base) ns
R01DS0065EJ0120 Rev.1.20 Page 104 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =5V
Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. External circuits are required to satisfy the I2C-bus specification.
Table 5.37 Serial Interface
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
td(C-Q) TXDi output delay time Refer to
Figure 5.6
80 ns
th(C-Q) TXDi output hold time 0ns
Table 5.38 Intelligent I/O
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
td(ISCLK2-TXD) ISTXD2 output delay time Refer to
Figure 5.6
180 ns
th(ISCLK2-RXD) ISTXD2 output hold time 0ns
Table 5.39 Multi-master I2C-bus Interface (standard-mode)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tf(SCL) MSCL output fall time
Refer to
Figure 5.6
2ns
tf(SDA) MSDA output fall time 2ns
td(SDA-SCL)S MSCL output delay time after START
condition/repeated START condition 20 × tc(IIC) - 120 52 × tc(IIC) - 40 ns
td(SCL-SDA)P Repeated START condition/STOP
condition output delay time after
MSCL becomes high
20 × tc(IIC) + 40 52 × tc(IIC) + 120 ns
td(SCL-SDA) MSDA output delay time 2 × tc(IIC) + 40 3 × tc(IIC) + 120 ns
Table 5.40 Multi-master I2C-bus Interface (fast-mode)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tf(SCL) MSCL output fall time
Refer to
Figure 5.6
2 (1) ns
tf(SDA) MSDA output fall time 2 (1) ns
td(SDA-SCL)S MSCL output delay time after START
condition/repeated START condition 10 × tc(IIC) - 120 26 × tc(IIC) - 40 ns
td(SCL-SDA)P Repeated START condition/STOP
condition output delay time after
MSCL becomes high
10 × tc(IIC) + 40 26 × tc(IIC) + 120 ns
td(SCL-SDA) MSDA output delay time 2 × tc(IIC) + 40 3 × tc(IIC) + 120 ns
R01DS0065EJ0120 Rev.1.20 Page 105 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Note:
1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
Table 5.41 Electrical Characteristics (1/3) (VCC = 3.0 to 3.6 V, VSS =0V, T
a=T
opr, and
f(CPU) = 64 MHz, unless otherwise noted)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Typ. Max.
VOH High
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0toP10_7, P11_0toP11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOH = -1 mA VCC - 0.6 VCC V
VOL Low
level
output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0toP10_7, P11_0toP11_4,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_6, P15_0 to P15_7 (1)
IOL = 1 mA 0.5 V
R01DS0065EJ0120 Rev.1.20 Page 106 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Notes:
1. Pins INT6 to INT8 are available in the 144-pin package only.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated
as input pin in the 100-pin package.
Table 5.42 Electrical Characteristics (2/3) (VCC = 3.0 to 3.6 V, VSS =0V, T
a=T
opr, and
f(CPU) = 64 MHz, unless otherwise noted)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Typ. Max.
VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS8,
CLK0 to CLK8, RXD0 to RXD8,
SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,
SRXD0toSRXD6,
ADTRG,
IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,
UD0B, UD1A, UD1B, ISCLK2, ISRXD2,
IEIN, MSCL, MSDA, CAN0IN, CAN1IN,
CAN0WU, CAN1WU (1)
0.2 1.0 V
RESET 0.2 1.8 V
IIH High level
input
current
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 3.3 V 4.0 µA
IIL Low level
input
current
XIN, RESET, CNVSS, NSD,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 0 V -4.0 µA
RPULLUP Pull-up
resistor
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_6,
P15_0 to P15_7 (2)
VI = 0 V 50 100 500 k
RfXIN Feedback
resistor
XIN 3M
RfXCIN Feedback
resistor
XCIN 25 M
R01DS0065EJ0120 Rev.1.20 Page 107 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Table 5.43 Electrical Characteristics (3/3)
(VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Symbol Characte
ristic Measurement Condition Value Unit
Min. Typ. Max.
ICC Power
supply
current
In single-chip mode,
output pins are left open
and others are
connected to VSS
XIN-XOUT
Drive strength: low
XCIN-XCOUT
Drive strength: low
f(CPU) =64MHz, f
(BCLK) =32MHz,
f(XIN) =8MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
40 55 mA
f(CPU) = 50 MHz, f(BCLK) = 25 MHz,
f(XIN) =8MHz,
Active: XIN, PLL,
Stopped: XCIN, OCO
32 45 mA
f(CPU) = fSO(PLL)/24 MHz,
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
9mA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) =8MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO
670 µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
180 µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
190 µA
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
500 900 µA
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8 140 µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10 150 µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
570µA
R01DS0065EJ0120 Rev.1.20 Page 108 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Note:
1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.
Table 5.44 A/D Conversion Characteristics (VCC =AV
CC =V
REF =3.0to3.6V, V
SS =AV
SS =0V,
Ta=T
opr, and f(BCLK) = 32 MHz, unless otherwise noted)
Symbol Characteristic Measurement Condition Value Unit
Min. Typ. Max.
—Resolution VREF = VCC 10 Bits
—
Absolute error VREF = VCC = 3.3 V AN_0toAN_7,
AN0_0toAN0_7,
AN2_0toAN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
±5 LSB
External op-amp
connection mode ±7 LSB
INL Integral non-linearity
error
VREF = VCC = 3.3 V AN_0toAN_7,
AN0_0toAN0_7,
AN2_0toAN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1 (1)
±5 LSB
External op-amp
connection mode ±7 LSB
DNL Differential non-
linearity error
VREF = VCC = 3.3 V ±1 LSB
— Offset error ±3 LSB
— Gain error ±3 LSB
RLADDER Resistor ladder VREF = VCC 420k
tCONV Conversion time
(10 bits)
AD = 10 MHz,
with sample and hold function 3.3 µs
tCONV Conversion time
(8 bits)
AD = 10 MHz,
with sample and hold function 2.8 µs
tSAMP Sampling time AD = 10 MHz 0.3 µs
VIA Analog input voltage 0VREF V
AD Operating clock
frequency
Without sample and hold function 0.25 10 MHz
With sample and hold function 1 10 MHz
R01DS0065EJ0120 Rev.1.20 Page 109 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for the A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.
Table 5.45 D/A Conversion Characteristics (VCC =AV
CC =V
REF =3.0to3.6V, V
SS =AV
SS =0V,
and Ta=T
opr, unless otherwise noted)
Symbol Characteristic Measurement Condition Value Unit
Min. Typ. Max.
— Resolution 8Bits
— Absolute precision 1.0 %
tSSettling time 3µs
ROOutput resistance 41020k
IVREF Reference input current See Note 1 1.0 mA
R01DS0065EJ0120 Rev.1.20 Page 110 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.46 External Clock Input
Symbol Characteristic Value Unit
Min. Max.
tc(X) External clock input period 62.5 250 ns
tw(XH) External clock input high level pulse width 25 ns
tw(XL) External clock input low level pulse width 25 ns
tr(X) External clock input rise time 5ns
tf(X) External clock input fall time 5ns
tw / tcExternal clock input duty 40 60 %
Table 5.47 External Bus Timing
Symbol Characteristic Value Unit
Min. Max.
tsu(D-R) Data setup time before read 40 ns
th(R-D) Data hold time after read 0ns
tdis(R-D) Data disable time after read 0.5 × tc(Base) + 10 ns
R01DS0065EJ0120 Rev.1.20 Page 111 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.48 Timer A Input (counting input in event counter mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TA) TAiIN input clock cycle time 200 ns
tw(TAH) TAiIN input high level pulse width 80 ns
tw(TAL) TAiIN input low level pulse width 80 ns
Table 5.49 Timer A Input (gating input in timer mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TA) TAiIN input clock cycle time 400 ns
tw(TAH) TAiIN input high level pulse width 180 ns
tw(TAL) TAiIN input low level pulse width 180 ns
Table 5.50 Timer A Input (external trigger input in one-shot timer mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TA) TAiIN input clock cycle time 200 ns
tw(TAH) TAiIN input high level pulse width 80 ns
tw(TAL) TAiIN input low level pulse width 80 ns
Table 5.51 Timer A Input (external trigger input in pulse-width modulation mode)
Symbol Characteristic Value Unit
Min. Max.
tw(TAH) TAiIN input high level pulse width 80 ns
tw(TAL) TAiIN input low level pulse width 80 ns
Table 5.52 Timer A Input (increment/decrement switching input in event counter mode)
Symbol Characteristic Value Unit
Min. Max.
tc(UP) TAiOUT input clock cycle time 2000 ns
tw(UPH) TAiOUT input high level pulse width 1000 ns
tw(UPL) TAiOUT input low level pulse width 1000 ns
tsu(UP-TIN) TAiOUT input setup time 400 ns
th(TIN-UP) TAiOUT input hold time 400 ns
R01DS0065EJ0120 Rev.1.20 Page 112 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.53 Timer B Input (counting input in event counter mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TB) TBiIN input clock cycle time (one edge counting) 200 ns
tw(TBH) TBiIN input high level pulse width (one edge counting) 80 ns
tw(TBL) TBiIN input low level pulse width (one edge counting) 80 ns
tc(TB) TBiIN input clock cycle time (both edges counting) 200 ns
tw(TBH) TBiIN input high level pulse width (both edges counting) 80 ns
tw(TBL) TBiIN input low level pulse width (both edges counting) 80 ns
Table 5.54 Timer B Input (pulse period measure mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TB) TBiIN input clock cycle time 400 ns
tw(TBH) TBiIN input high level pulse width 180 ns
tw(TBL) TBiIN input low level pulse width 180 ns
Table 5.55 Timer B Input (pulse-width measure mode)
Symbol Characteristic Value Unit
Min. Max.
tc(TB) TBiIN input clock cycle time 400 ns
tw(TBH) TBiIN input high level pulse width 180 ns
tw(TBL) TBiIN input low level pulse width 180 ns
R01DS0065EJ0120 Rev.1.20 Page 113 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Table 5.56 Serial Interface
Symbol Characteristic Value Unit
Min. Max.
tc(CK) CLKi input clock cycle time 200 ns
tw(CKH) CLKi input high level pulse width 80 ns
tw(CKL) CLKi input low level pulse width 80 ns
tsu(D-C) RXDi input setup time 80 ns
th(C-D) RXDi input hold time 90 ns
Table 5.57 A/D Trigger Input
Symbol Characteristic Value Unit
Min. Max.
tw(ADH) ADTRG input high level pulse width
Hardware trigger input high level pulse width ns
tw(ADL) ADTRG input low level pulse width
Hardware trigger input high level pulse width 125 ns
Table 5.58 External Interrupt INTi Input
Symbol Characteristic Value Unit
Min. Max.
tw(INH) INTi input high level pulse width Edge sensitive 250 ns
Level sensitive tc(CPU) + 200 ns
tw(INL) INTi input low level pulse width Edge sensitive 250 ns
Level sensitive tc(CPU) + 200 ns
Table 5.59 Intelligent I/O
Symbol Characteristic Value Unit
Min. Max.
tc(ISCLK2) ISCLK2 input clock cycle time 600 ns
tw(ISCLK2H) ISCLK2 input high level pulse width 270 ns
tw(ISCLK2L) ISCLK2 input low level pulse width 270 ns
tsu(RXD-ISCLK2) ISRXD2 input setup time 150 ns
th(ISCLK2-RXD) ISRXD2 input hold time 100 ns
3
AD
----------
R01DS0065EJ0120 Rev.1.20 Page 114 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. The value is calculated using the formulas below based on a value SSC set by bits SSC4 to SSC0 in
the I2CSSCR register:
th(SDA-SCL)S = SSC ÷ 2 × tc(IIC) + 40 [ns]
tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(IIC) + 40 [ns]
tw(SDAH)P = (SSC + 1) × tc(IIC) + 40 [ns]
Table 5.60 Multi-master I2C-bus Interface
Symbol Characteristic
Value
UnitStandard-mode Fast-mode
Min. Max. Min. Max.
tw(SCLH) MSCL input high level pulse width 600 600 ns
tw(SCLL) MSCL input low level pulse width 600 600 ns
tr(SCL) MSCL input rise time 1000 300 ns
tf(SCL) MSCL input fall time 300 300 ns
tr(SDA) MSDA input rise time 1000 300 ns
tf(SDA) MSDA input fall time 300 300 ns
th(SDA-SCL)S MSCL high level hold time after
START condition/repeated START
condition
(1) 2 × tc(IIC) + 40 ns
tsu(SCL-SDA)P MSCL high level setup time for
repeated START condition/STOP
condition
(1) 2 × tc(IIC) + 40 ns
tw(SDAH)P MSDA high level pulse width after
STOP condition (1) 4 × tc(IIC) + 40 ns
tsu(SDA-SCL) MSDA input setup time 100 100 ns
th(SCL-SDA) MSDA input hold time 00ns
R01DS0065EJ0120 Rev.1.20 Page 115 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For details on how to set values,
refer to the User’s manual.
tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
tw(R) = Tw(R) × tc(Base) - 10 [ns]
tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
Table 5.61 External Bus Timing (separate bus)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tsu(S-R) Chip-select setup time before
read
Refer to
Figure 5.6
(1) ns
th(R-S) Chip-select hold time after read tc(Base) - 15 ns
tsu(A-R) Address setup time before read (1) ns
th(R-A) Address hold time after read tc(Base) - 15 ns
tw(R) Read pulse width (1) ns
tsu(S-W) Chip-select setup time before
write (1) ns
th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns
tsu(A-W) Address setup time before write (1) ns
th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns
tw(W) Write pulse width (1) ns
tsu(D-W) Data setup time before write (1) ns
th(W-D) Data hold time after write 0ns
R01DS0065EJ0120 Rev.1.20 Page 116 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For details on how to set values,
refer to the User’s manual.
tsu(S-ALE) = tsu(A-ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]
tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) - 20 [ns]
tw(R) = Tw(R) × tc(Base) -10 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]
Table 5.62 External Bus Timing (multiplexed bus)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tsu(S-ALE) Chip-select setup time before
ALE
Refer to
Figure 5.6
(1) ns
th(R-S) Chip-select hold time after read 1.5 × tc(Base) - 15 ns
tsu(A-ALE) Address setup time before ALE (1) ns
th(ALE-A) Address hold time after ALE 0.5 × tc(Base) - 5 ns
th(R-A) Address hold time after read 1.5 × tc(Base) - 15 ns
td(ALE-R) ALE-read delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(ALE) ALE pulse width (1) ns
tdis(R-A) Address disable time after read 8ns
tw(R) Read pulse width (1) ns
th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns
th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns
td(ALE-W) ALE-write delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns
tw(W) Write pulse width (1) ns
tsu(D-W) Data setup time before write (1) ns
th(W-D) Data hold time after write 0.5 × tc(Base) ns
R01DS0065EJ0120 Rev.1.20 Page 117 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
VCC =3.3V
Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T
opr, unless otherwise noted)
Note:
1. External circuits are required to satisfy the I2C-bus specification.
Table 5.63 Serial Interface
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
td(C-Q) TXDi output delay time Refer to
Figure 5.6
80 ns
th(C-Q) TXDi output hold time 0ns
Table 5.64 Intelligent I/O
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
td(ISCLK2-TXD) ISTXD2 output delay time Refer to
Figure 5.6
180 ns
th(ISCLK2-RXD) ISTXD2 output hold time 0ns
Table 5.65 Multi-master I2C-bus Interface (Standard-mode)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tf(SCL) MSCL output fall time
Refer to
Figure 5.6
2ns
tf(SDA) MSDA output fall time 2ns
td(SDA-SCL)S MSCL output delay time after START
condition/repeated START condition 20 × tc(IIC) - 120 52 × tc(IIC) - 40 ns
td(SCL-SDA)P Repeated START condition/STOP
condition output delay time after
MSCL becomes high
20 × tc(IIC) + 40 52 × tc(IIC) + 120 ns
td(SCL-SDA) MSDA output delay time 2 ×tc(IIC) + 40 3 × tc(IIC) + 120 ns
Table 5.66 Multi-master I2C-bus Interface (Fast-mode)
Symbol Characteristic Measurement
Condition
Value Unit
Min. Max.
tf(SCL) MSCL output fall time
Refer to
Figure 5.6
2 (1) ns
tf(SDA) MSDA output fall time 2 (1) ns
td(SDA-SCL)S MSCL output delay time after START
condition/repeated START condition 10 × tc(IIC) - 120 26 × tc(IIC) - 40 ns
td(SCL-SDA)P Repeated START condition/STOP
condition output delay time after
MSCL becomes high
10 × tc(IIC) + 40 26 × tc(IIC) + 120 ns
td(SCL-SDA) MSDA output delay time 2 × tc(IIC) + 40 3 × tc(IIC) + 120 ns
R01DS0065EJ0120 Rev.1.20 Page 118 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Figure 5.6 Switching Characteristic Measurement Circuit
Figure 5.7 External Clock Input Timing
30 pF
Pin to be
measured
MCU
XIN
t
w(XH) t
w(XL)
t
r(X) t
f(X)
t
c(X)
R01DS0065EJ0120 Rev.1.20 Page 119 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Figure 5.8 External Bus Timing for Separate Bus
CS0 to CS3
A23 to A0, BC0 to BC3
RD
D31 to D0
t
h(R-D)
t
h(R-S)
External bus timing (separate bus)
Read cycle
t
w(R)
t
su(S-R)
t
h(R-A)
t
su(A-R)
Write cycle
CS0 to CS3
A23 to A0, BC0 to BC3
WR, WR0 to WR3
D31 to D0
t
su(D-W) t
h(W-D)
t
su(D-R)
t
h(W-S)
t
w(W)
t
su(S-W)
t
h(W-A)
t
su(A-W)
Measurement conditions
Criterion for
input voltage
Criterion for
output voltage
V
IH
V
IL
V
OH
V
OL
2.5 V
0.8 V
2.0 V
0.8 V
1.5 V
0.5 V
2.4 V
0.5 V
Item V = 4.2 to 5.5 V
CC
t
cR
t
cW
V = 3.0 to 3.6 V
CC
R01DS0065EJ0120 Rev.1.20 Page 120 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Figure 5.9 External Bus Timing for Multiplexed Bus
CS0 to CS3
A23 to A8, BC0 to BC3
RD
D31 to D8
t
h(R-D)
t
h(R-S)
External bus timing (multiplexed bus)
Read cycle
t
w(R)
t
su(S-ALE)
t
h(R-A)
t
su(A-ALE)
Write cycle
WR, WR0 to WR3
t
su(D-R)
Measurement conditions
Criterion for
input voltage
Criterion for
output voltage
V
IH
V
IL
V
OH
V
OL
2.5 V
0.8 V
2.0 V
0.8 V
1.5 V
0.5 V
2.4 V
0.5 V
Item
ALE
t
w(ALE)
Address
t
su(A-ALE)
A15/D15 to A0/D0,
BC0/D0, BC2/D1 Data
t
h(ALE-A)
t
d(ALE-R)
t
h(R-D)
t
su(D-R)
CS0 to CS3
A23 to A8, BC0 to BC3
D31 to D8
t
h(W-D)
t
h(W-S)
t
w(W)
t
su(S-ALE)
t
h(W-A)
t
su(A-ALE)
t
su(D-W)
ALE
t
w(ALE)
Address
t
su(A-ALE)
A15/D15 to A0/D0,
BC0/D0, BC2/D1 Data
t
h(ALE-A)
t
d(ALE-W)
t
h(W-D)
t
su(D-W)
t
dis(R-A)
t
dis(R-D)
t
cR
t
cW
V = 4.2 to 5.5 V
CC V = 3.0 to 3.6 V
CC
R01DS0065EJ0120 Rev.1.20 Page 121 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Figure 5.10 Timing of Peripherals
TAiIN input
TAiOUT input
t
c(TA)
t
w(TAH) t
w(TAL)
t
c(UP)
t
w(UPH) t
w(UPL)
TAiIN input (in falling edge counting)
TAiOUT input (input for increment/
decrement switching)
In event counter mode
TAiIN input (in rising edge counting)
t
h(TIN-UP)
TBiIN input
ADTRG input
t
c(TB)
t
w(TBH) t
w(TBL)
t
w(ADL)
CLKi
t
c(CK)
t
w(CKH) t
w(CKL)
TXDi
t
d(C-Q) t
h(C-Q)
RXDi
t
su(D-C) t
h(C-D)
INTi input
t
w(INL) t
w(INH)
NMI input
Two CPU clock cycles +
300 ns or more
Two CPU clock cycles +
300 ns or more
t
su(UP-TIN)
t
w(ADH)
R01DS0065EJ0120 Rev.1.20 Page 122 of 123
Feb 6, 2013
R32C/118 Group 5. Electrical Characteristics
Figure 5.11 Timing of Multi-master I2C-bus Interface
MSCL
t
h(SDA-SCL)S
MSDA (input)
MSCL
t
w(SCLH) t
w(SCLL)
t
c(SCL)
t
r(SCL) t
f(SCL)
MSDA
t
r(SDA) t
f(SDA)
t
su(SCL-SDA)P
t
h(SDA-SCL)S
t
su(SCL-SDA)P
MSDA (output)
MSCL
t
d(SDA-SCL)S t
d(SCL-SDA)P
t
d(SDA-SCL)S
t
d(SCL-SDA)P
MSCL
MSDA (input)
t
su(SDA-SCL) t
h(SCL-SDA)
MSCL
MSDA (output)
t
d(SCL-SDA)
t
w(SDAH)P
R01DS0065EJ0120 Rev.1.20 Page 123 of 123
Feb 6, 2013
R32C/118 Group Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Terminal cross section
b1
c1
bp
c
1.0
0.125
0.20
1.25
1.25
0.08
0.20
0.145
0.09
0.270.220.17
MaxNomMin
Dimension in Millimeters
Symbol
Reference
20.120.019.9
D
20.120.019.9
E
1.4
A
2
22.222.021.8
22.222.021.8
1.7
A
0.15
0.1
0.05
0.65
0.5
0.35
L
x
8°0°
c
0.5
e
0.10
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
P-LQFP144-20x20-0.50 1.2g
MASS[Typ.]
144P6Q-A / FP-144L / FP-144LVPLQP0144KA-A
RENESAS CodeJEITA Package Code Previous Code
F
136
37
72
73
108
109
144
*1
*2
*3
x
Index mark
HE
E
D
HD
bp
ZD
ZE
Detail F
c
A
L
A1A2
L1
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
eyS
S
Terminal cross section
b1
c
1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Index mark
x
125
26
50
51
75
76
100
F
*1
*3
*2
Z
E
ZD
E
D
HD
H
E
bp
Detail F
L1
A
2
A
1
L
A
c
L1
ZE
ZD
c1
b1
bp
A1
HE
HD
y0.08
e0.5
c
0° 8°
x
L0.35 0.5 0.65
0.05 0.1 0.15
A1.7
15.8 16.0 16.2
15.8 16.0 16.2
A21.4
E13.9 14.0 14.1
D13.9 14.0 14.1
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.15 0.20 0.25
0.09 0.145 0.20
0.08
1.0
1.0
0.18
0.125
1.0
Previous CodeJEITA Package Code RENESAS Code
PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6gP-LQFP100-14x14-0.50
e
yS
S
A- 1
Revision History R32C/118 Group Datasheet
Rev. Date Description
Page Summary
1.00 Nov 19, 2009 — Initial release
1.10 Jun 23, 2010 — Second edition released
This manual in general
— • Applied new Renesas templates and formats to the manual
• Changed company name to “Renesas Electronics Corporation” and
changed related descriptions due to business merger of Renesas
Technology Corporation and NEC Electronics Corporation (under
Chapters 1 and 5)
• Added specifications of 64 MHz version
Chapter 1. Overview
3, 5 • Deleted Note 1 from Tables 1.2 and 1.4
9 • Deleted Note 4 from Figure 1.2
19 • Modified expression “fC” in Table 1.14 to “low speed clocks”
Chapter 4. SFRs
34, 37 • Changed register name “Group i Timer Measurement Prescaler
Register” in Tables 4.6 and 4.9 to “Group i Time Measurement
Prescaler Register”
39 • Modified expression “XY Control Register” in Table 4.11 to “X-Y
Control Register”
41 • Changed register name “UART2 Transmission/Receive Mode
Register” in Table 4.13 to “UART2 Transmit/Receive Mode Register”;
Changed hexadecimal format of reset values for registers TABSR,
ONSF, and TRGSR to binary
52 • Changed register name “External Interrupt Source Select Register i” in
Table 4.24 to “External Interrupt Request Source Select Register i”
67, 81 • Modified register names “CANi Reception Error Count Register” and
“CANi Transmission Error Count Register” in Tables 4.39 and 4.53 to
“CANi Receive Error Count Register” and “CANi Transmit Error Count
Register”, respectively
Chapter 5. Electrical Characteristics
91 • Changed expressions “CS0” and “A23 to A0, BC3 to BC0” in Figure
5.5 to “Chip select” and “Address”, respectively
Appendix 1. Package Dimensions
123 • Added a seating plane to the drawing of package dimension
1.20 Feb 6, 2013 — Third edition released
This manual in general
— • Changed document number “REJ03B0255-0110” to
“R01DS0065EJ0120”
• Modified expressions “version N”, “version D”, and “version P” to “N
version”, “D version”, and “P version”, respectively (under Chapters 1
and 5)
Chapter 1. Overview
— • Modified wording and enhanced description in this chapter
A- 2
2, 4 • Modified expressions “Main clock oscillator stop/re-oscillation
detection”, “calculation transfer”, “chained transfer”, and “inputs/
outputs” in Tables 1.1 and 1.3 to “Main clock oscillator stop/restart
detection”, “calculation result transfer”, “chain transfer”, and “I/O ports”,
respectively
7 • Completed “under development” phase of versions D and P products
in Table 1.6
10, 15 • Changed order of signals in Figures 1.3 and 1.4
11, 16 • Changed order of timer pins “TB5IN/TA0IN” in Tables 1.7 and 1.11 to
“TA0IN/TB5IN”
21 • Changed expression “I2C bus” in Table 1.16 to “I2C-bus”
23 • Modified Note 1 of Table 1.18
Chapter 2. CPU
— • Modified wording and enhanced description in this chapter
25 • Corrected a typo “R3R0” in line 3 of 2.1.1 to “R3R1”
Chapter 3. Memory
— • Modified wording and enhanced description in this chapter
Chapter 4. SFRs
—• Changed expressions “I2C Bus” and “I2C-Bus” to “I2C-bus”
34, 35, 37 • Changed hexadecimal format of reset values for registers G1BCR0,
G2BCR0, and G0BCR0 in Tables 4.6, 4.7, and 4.9 to binary
41 • Changed register name “Increment/Decrement Counting Select
Register” in Table 4.13 to “Increment/Decrement Select Register”
43 • Corrected reset value “X00X X000b” for AD0CON2 register in Table
4.15 to “XX0X X000b”
53 • Modified register name “I2C Bus START Condition/STOP Condition
Control Register” in Table 4.25 to “I2C-bus START and STOP
Conditions Control Register”; Corrected reset values for the following
registers in: I2CSSCR, I2CCR1, I2CCR2, I2CSR, and I2CMR
64, 65, 78,
79
• Changed register name “CANi Acceptance Mask Register k” in Tables
4.36, 4.37, 4.50, and 4.51 to “CANi Mask Register k”
67, 81 • Corrected reset value “XXXX XX00b” for CiMSMR register in Tables
4.39 and 4.53 to “0000 0000b”
Chapter 5. Electrical Characteristics
— • Modified wording and enhanced description in this chapter
88 • Changed expression “Programming and erasure endurance of flash
memory” in Table 5.8 to “Program/erase cycles”; Changed its unit
“times” to “Cycles”
93, 106 • Added “MSCL” and “MSDA” to Tables 5.16 and 5.42
94, 107 • Modified description “Drive power” in Tables 5.17 and 5.43 to “Drive
strength”
100, 113 • Corrected “INTi” in the title of Tables 5.32 and 5.58 to “INTi”
101, 104,
114, 117
• Changed expression “restart condition” in Tables 5.34, 5.39, 5.40,
5.60, 5.65, and 5.66 to “repeated START condition”
All trademarks and registered trademarks are the property of their respective owners.
Revision History R32C/118 Group Datasheet
Rev. Date Description
Page Summary
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pi ns
Handle unused pins in acc ord with the directions given under Hand ling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the ope n-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. U nused
pins should be handle d as described under Handlin g of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is suppli ed.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal i s applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which res etting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are pr ovided for the possible future expa nsion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has bec ome
stable. When switching the clock sign al during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an e xternal
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock sig na l produced with an external
resonator (or by an external oscillator) while program execution is in progr ess, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but ha ving different part numbers may
differ because of the differences in internal memory capacity and layo ut pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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R
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2880 Scott Boulevard Santa Clara
,
CA 95050-2554
,
U.S.A
.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Mala
y
sia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petalin
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Jaya, Selan
g
or Darul Ehsan, Malaysi
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Tel: +60-3-7955-9390
,
Fax: +60-3-7955-951
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Renesas Electronics Korea Co.
,
Ltd
.
11F., Samik Lavied' or Bld
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., 720-2 Yeoksam-Don
g
, Kan
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nam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737
,
Fax: +82-2-558-514
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2013 Renesas Electronics Corporation. All ri
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