2014 Microchip Technology Inc. DS20005350A-page 1
Synchronous Buck Features:
• Input Voltage: 4.5V to 40V
• Output Voltage: 0.5V to 3.6V
- Greater than 3.6V requires external divider
• Switching Frequency: 100 kHz to 1.6 MHz
• Quiescent Current: 5 mA Ty pical
• High-Drive:
- +5V Gate Drive
- 1A/2A Source Current
- 1A/2A Sink Current
• Low-Drive:
- +5V Gate Drive
- 2A Source Current
- 4A Sink Current
• Peak Cur rent Mode Control
• Differential Remote Output Sense
• QEC-100 Qualified
• Multiple Output Systems:
- Master or Slave
- Frequency Synchronized
• Configurable Parameters:
- Overcurrent Limit
- Input Undervoltage Lockout
- Output Overvoltage
- Output Und ervoltage
- Internal Analog Compensation
- Soft Start Profile
- Synchronous Dr iver Dead Time
- Switching Frequency
• Thermal Shutdown
Microcontroller Features:
• Precision 8 MHz Internal Oscillator Block:
- Factory Calibrated
• Inter rupt Capable
-Firmware
- Interrupt-on-Change Pins
• Only 35 Instructions to Learn
• 4096 Words On-Chip Program Memory
• High-Endurance Flash:
- 100,000 Write Flash Endurance
- Flash Retention: >40 years
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Programmable Code Protection
• In-Circuit De bug (ICD) vi a Two Pins (MCP19119)
• In-Circuit Serial Programming™ (ICSP™) v ia T wo
Pins
• 11 I/O Pins and One Input-Only Pin (MCP19118)
- Three Open- Dr ain Pins
• 14 I/O Pins and One Input-Only Pin (MCP19119)
- Three Open- Dr ain Pins
• Analog-to-Digital Converter (ADC):
- 10-Bit Resolution
- 12 Internal Channels
- Eight External Channels
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-Bit T im er/Counte r with Pres c ale r
- Two Selectable Clock Sources
• Timer2: 8-Bit Timer/Counter with Prescaler
- 8-Bit Period Register
• I
2CTM Communication:
- 7-Bit Address Masking
- Two Dedicated Address Registers
- SMBus/PMBusTM Compatibility
MCP19118/19
Digitally-Enhanced Power Analog Controller
with Integrated Synchr onous Driver
MCP19118/19
DS20005350A-page 2 2014 Microchip Technology Inc.
Pin Diagram – 24-Pin QFN (MCP19118)
MCP19118
GPA2
GPA4
GPB0
GPA1
GPA0
GPA3
GPA7
VIN
GPB2
GPA5/MCLR
PGND
LDRV
VDR
PHASE
HDRV
BOOT
VDD
GPB1
-VSEN
+VSEN
+ISEN
-ISEN
GPA6
GND
1
2
3
4
5
613
7
8
9
10
11
12
14
15
16
17
18
23
22
21
20
19
24
EXP-25
2014 Microchip Technology Inc. DS20005350A-page 3
MCP19118/19
TABLE 1: 24-PIN SUMMARY
I/O
24-Pin QFN
ANSEL
A/D
Timers
MSSP
Interrupt
Pull-Up
Basic Additional
GPA0 1 Y AN0 — — IOC Y — Analog Debug Output (1)
GPA1 2 Y AN1 — — IOC Y — Sync. Signal In/Out (2, 3)
GPA2 3 Y AN2 T0CKI —IOC
INT Y — —
GPA3 5 Y AN3 —IOC Y — —
GPA4 8 N — — — IOC N — —
GPA5 7 N — — — IOC(4)Y(5)MCLR —
GPA6 6 N — — — IOC NICSPDAT —
GPA7 5 N — — SCL IOC NICSPCLK —
GPB0 9 N — — SDA IOC N — —
GPB1 23 YAN4 — — IOC Y — Error Signal In/Out (3)
GPB2 24 YAN5 — — IOC Y — —
VIN 11 N — — — — — VIN Device Input Voltage
VDR 14 N — — — — — VDR Gate Drive Supply Input
Voltage
VDD 18 N — — — — — VDD Internal Regulator Output
GND 10 N — — — — — GND Small Signal Ground
PGND 12 N — — — — — — Large Signal Ground
LDRV 13 N — — — — — — Low-Si de MOSFET
Connection
HDRV 16 N — — — — — — High-Side MOSFET
Connection
PHASE 15 N — — — — — — Switch Node
BOOT 17 N — — — — — — Floating Bootstrap Supply
+VSEN 21 N — — — — — — Output Voltage
Dif fere nti al Sens e
-VSEN 22 N — — — — — — Output Voltage
Dif fere nti al Sens e
+ISEN 20 N — — — — — — Current Sens e Inpu t
-ISEN 19 N — — — — — — Current Sens e Inpu t
Note 1: The Analog Debug Output is selected when the ATST CON<BNCHEN> bit is set.
2: Selected when the device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0>
bits in the BUFFCON register.
3: Selected when the device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits
in the BUFFCON register.
4: The IOC is disabled when MCLR is enabled.
5: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
MCP19118/19
DS20005350A-page 4 2014 Microchip Technology Inc.
Pin Diagram – 28-Pin QFN (MCP19119)
MCP19119
GPA2
GPB4
GPA4
GPB7
GPB0
GPA1
GPA0
GPA3
GPA7
VIN
GPB2
GPA5/MCLR
PGND
LDRV
VDR
PHASE
HDRV
BOOT
VDD
GPB1
-VSEN
+VSEN
+ISEN
-ISEN
GPA6
GND
GPB6
GPB5
1
2
3
4
5
6
715
8
9
10
11
12
13
14
16
17
18
19
20
21
26
25
24
23
22
28
27
EXP-29
2014 Microchip Technology Inc. DS20005350A-page 5
MCP19118/19
TABLE 2: 28-PIN SUMMARY
I/O
28-Pin QFN
ANSEL
A/D
Timers
MSSP
Interrupt
Pull-Up
Basic Additional
GPA0 1 Y AN0 — — IOC Y — Analog Debug Output (1)
GPA1 2 Y AN1 — — IOC Y — Sync. Signal In/Out (2, 3)
GPA2 3 Y AN2 T0CKI —IOC
INT Y — —
GPA3 5 Y AN3 —IOC Y — —
GPA4 9 N — — — IOC N — —
GPA5 8 N — — — IOC(4)Y(5)MCLR —
GPA6 7 N — — — IOC N — —
GPA7 6 N — — SCL IOC N — —
GPB0 10 N — — SDA IOC N — —
GPB1 26 YAN4 — — IOC Y — Error Signal In/Out (3)
GPB2 28 YAN5 — — IOC Y — —
GPB4 4 Y AN6 — — IOC YICSPDAT
ICDDAT —
GPB5 27 YAN7 — — IOC YICSPCLK
ICDCLK Alternate Sync
Signal In/Out (2, 3)
GPB6 21 N — — — IOC Y — —
GPB7 11 N — — — IOC Y — —
VIN 13 N — — — — — VIN Device Input Voltage
VDR 16 N — — — — — VDR Gate Drive Supply Input
Voltage
VDD 20 N — — — — — VDD Internal Regulator Output
GND 12 N — — — — — GND Small Signal Ground
PGND 14 N — — — — — — Large Signal Ground
LDRV 15 N — — — — — — Low-Si de MOSFET
Connection
HDRV 18 N — — — — — — High-Side MOSFET
Connection
PHASE 17 N — — — — — — Switch Node
BOOT 19 N — — — — — — Floating Bootstrap Supply
+VSEN 24 N — — — — — — Output Voltage
Dif fere nti al Sens e
-VSEN 25 N — — — — — — Output Voltage
Dif fere nti al Sens e
+ISEN 23 N — — — — — — Current Sens e Inpu t
-ISEN 22 N — — — — — — Current Sens e Inpu t
Note 1: The Analog Debug Output is selected when the ATST CON<BNCHEN> bit is set.
2: Selected when the device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0>
bits in the BUFFCON register.
3: Selected when the device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits
in the BUFFCON register.
4: The IOC is disabled when MCLR is enabled.
5: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
MCP19118/19
DS20005350A-page 6 2014 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Pin Description........................................................................................................................................................................... 12
3.0 Functional Descr iption................................................................................................................................................................ 17
4.0 Electrical Characteristics............................................................................................................................................................ 23
5.0 Digit a l Ele ctrical Cha rac te ristics......... ......................... ................... ......................... ................................................................... 29
6.0 Configuring the MCP19118/19 ...................................................................................................................................................37
7.0 Typical Performance Curves...................................................................................................................................................... 53
8.0 Syste m Ben ch Testin g......... ............. ...... ............ ............. ............. ...... ............. ............ ............................................................... 57
9.0 Device Calibration ...................................................................................................................................................................... 59
10.0 Relative Efficiency Measurement............................................................................................................................................... 67
11.0 Memory Organization................................................................................................................................................................. 69
12.0 Device Configuration.................................................................................................................................................................. 81
13.0 Oscillator Modes......................................................................................................................................................................... 83
14.0 Resets ........................................................................................................................................................................................ 85
15.0 Interrupts .................................................................................................................................................................................... 93
16.0 Power -Down Mode (Sleep) ...................................................................................................................................................... 101
17.0 Watchdog Timer (WDT)............................................................................................................................................................ 103
18.0 Flash Prog ram Memory Contr o l.............................. ............ ............. ............ ............. ............. .................................................. 105
19.0 I/O Ports ................... ............. ...... ............. ............. ...... ............ ....... ............ ...............................................................................111
20.0 Interrupt-on-Change................................................................................................................................................................. 121
21.0 Internal Temperature Indicator Module............... ......... .... .. .... ......... .. .... .. .... ......... .. .... .... .. ......... . ............................................... 123
22.0 Analog-t o-Digital Converter (ADC) Module .............................................................................................................................. 125
23.0 Timer0 Module................. .... .. .. .... .. ....... .... .. .. .... .. ....... .. .... .. .. .... ....... .. .... .. .. .... ....... .. .. .... ............................................................. 135
24.0 Timer1 Module with Gate Control...................................... .. .... ....... .. .. .... .. .. ....... .... .. .... .. .. ....... . ................................................. 137
25.0 Timer2 Module................. .... .. .. .... .. ....... .... .. .. .... .. ....... .. .... .. .. .... ....... .. .... .. .. .... ....... .. .. .... ............................................................. 140
26.0 PWM Module...... .. .... ..... .. .. .... .. .. .. .. ....... .. .. .. .. .... .. ..... .. .... .. .. .. .. ....... .. .. .. .... .. .. .. ....... .. .. .. .. ............................................................. 143
27.0 Master Synchronous Serial Port (M SSP ) Module ..................... .......................................... ..................................................... 147
28.0 In-Circuit Serial Programming™ (ICSP™)............................................................................................................................... 191
29.0 Instruction Set Summary.......................................................................................................................................................... 193
30.0 Developm ent Suppor t............................................................................................................................................................... 203
31.0 Packagin g In fo rmation.............................. ............. ............ ............. ............ ............. ................................................................. 207
Appendix A: Revision History............................................................................................................................................................. 213
Index .................................................................................................................................................................................................. 215
The Microchip Web Site..................................................................................................................................................................... 221
Customer Change Notification Service ..................................................................................... ......................................................... 221
Customer Support........ ................. ........ ................. ...... ................. ................. ...... .............................................................................. 221
Product Identification System............................................................................................................................................................. 223
2014 Microchip Technology Inc. DS20005350A-page 7
MCP19118/19
TO OUR VALUE D CUS TOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our pu blications to better su it your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions o r c omm ents regarding t his publication, p lease c ontact the M arket ing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS3000000 0A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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MCP19118/19
DS20005350A-page 8 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 9
MCP19118/19
1.0 DEVICE OVERVIEW
The MCP1 9118/19 is a highly integrate d, mixe d signa l,
analog pulse-width modulation (PWM) current mode
controller with an integrated microcontroller core for
synch ronous DC/DC st ep-down appli cations. Sinc e the
MCP19118/19 uses traditional analog control circuitry
to regulate the output of the DC/DC converter, the
inte gratio n of the PIC® microcontroller mid-range core
is used to provide complete customization of device
operating parameters, start-up and shutdown profiles,
protection levels and fault handling procedures.
The MCP19118/19 is designed to efficiently operate
from a single 4.5V to 40V supply. It features integrated
synchronous drivers, bootstrap device, internal linear
regulator and 4 kW nonvolatile memory, all in a
space-saving 24-pin 4 mm x 4 mm QFN package
(MCP19118) or 28-pin 5 mm x 5 mm QFN package
(MCP19119).
After initial device configuration using Microchip’s
MPLAB® X Integrated Development Environment (IDE)
software, the PMBus or I2C can be used by a host to
communicate with, or modify, the operation of the
MCP19118/19.
Two internal linear regulators generate two 5V rails.
One 5V rail is used to provide power for the internal
analog circuitry and is contained on-chip. The second
5V rail provid es power to the PIC de vice and is present
on t he VDD pin. It is recommended that a 1 µF capacitor
be placed between VDD and PGND. The VDD pin may
also be directly connecte d to the VDR pin or connected
through a low-pass RC filter. The VDR pin provides
power to the internal synchronous driver.
FIGURE 1-1: TYPICAL APPLICATION CIRCUIT
BOOT
HDRV
LDRV
PHASE
+ISEN
-ISEN
+VSEN
-VSEN
VIN
VDD
VDRV
PGND
GND
MCP19118/9
VIN
VOUT
GPIO
9 (13)
SDA
SCL
I2C
MCP19118/19
DS20005350A-page 10 2014 Microchip Technology Inc.
FIGURE 1-2: MCP19118/19 SYNCHRONOUS BUCK BLOCK DIAGRAM
PHASE
HDRV
LDRV
VIN
VDD
BOOT
VIN
VOUT
VDAC
AVDD
LDO1
LDO2
Bias Gen
BGAP
UVLO
44
VZC
5
Slave
Mode
Master
Mode
VREGREF
UV REF
OV REF
8+5
8
8
VOUT
VOUT
VOUT
OV
UV
BGAP
Lo_on
4
AVDD
VDD
5
OC
Comp
VIN
DLY
4
LVL_SFT
PIC CORE
Debug
MUX
Lo_on
Buck
OV UV VIN_OK OCFLAG A/D Mux
VDR
-ISEN
+VSEN
-VSEN
+ISEN
+ISEN
-ISEN
+VSEN
-VSEN
GND
PGND
I/O(Digital Signals)
I/O
I/O
6
R
5R
VDR
DLY
4
4
3
To ADC
CSDGEN
bit
DC current sense gain
AC current sense gain
11 (15)
2014 Microchip Technology Inc. DS20005350A-page 11
MCP19118/19
FIGURE 1-3: MICROCONTROLLER CORE BLOCK DIAGRAM
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Instruction
Decode &
Control
Timing
Generation
TESTCLKIN
PORTA
8
8
8
3
8 Level St a ck 256
4K x 14
bytes
(13-bit)
Power-up
Timer
Power-on
Reset
Watchdog
Timer
MCLR V
IN
V
SS
Timer0 Timer1
T0CKI
Configuration
8 MHz Internal
Oscillator
Timer2
MSSP
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
Analog Interface
SDA
SCL
PMDATL
EEADDR
Self read/
write flash
memory
Registers
PORTB
GPB0
GPB1
GPB2
GPB6 (
MCP19119
)
GPB4 (
MCP19119
)
PWM
GPB5 (
MCP19119
)
GPA6
GPA7
GPB7 (
MCP19119
)
MCP19118/19
DS20005350A-page 12 2014 Microchip Technology Inc.
2.0 PIN DESCRIPTION
The MCP19118/19 family of devices features pins that
have multiple functions associated with each pin.
Table 2-1 provides a description of the different
functions. See Section 2.1 “Detailed Pin Functional
Description” for more detailed information.
TABLE 2-1: MCP19118/19 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GPA0/AN0/A NALO G_ TEST GPA0 TTL CMOS General purp os e I/O
AN0 AN — A/D Channel 0 input
ANALOG_TEST — — Internal analog signal multiplexer output (1)
GPA1/AN1/CLKPIN G PA1 TTL CMOS General purp ose I/O
AN1 AN — A/D Channel 1 input
CLKPIN — — Switching frequency clock input or output (2 ,3)
GPA2/AN2/T0C KI/ INT GPA2 TTL CMOS General purp ose I/O
AN2 AN — A/D Channel 2 input
T0CKI ST — Timer0 clock input
INT ST — External interrupt
GPA3/AN3 GPA3 TTL CMOS General purp os e I/O
AN3 AN — A/D Channel 3 input
GPA4 GPA4 TTL OD General purp ose I/O
GPA5/MCLR GPA5 TTL — General purpose input only
MCLR ST — Master Clear with internal pull-up
GPA6/ICSPDAT GPA6 ST CMOS General purpos e I/O
ICSPDAT CMOS Serial Programming Data I/O (MCP19118 Only)
GPA7/SCL/ICSPCLK GPA7 ST OD General purpose open-drain I/O
SCL I2C™ OD I2C clock
ICSPCLK ST — Serial Programming Clock (MCP19118 Only)
GPB0/SD A GPB0 T TL OD Gene ral purp ose I/O
SDA I2CODI
2C data inp ut/output
GPB1/AN4/EAPIN GPB1 TTL CMOS General purpose I/O
AN4 AN — A/D Channel 4 input
EAPIN — — Error amplifier signal input/output (3)
GPB2/AN 5 GPB2 T TL CMOS General purpose I/O
AN5 AN — A/D Channel 5 input
GPB4/AN6/ICSPDAT
(MCP19119 Only)GPB4 TTL CMOS General purpose I/O
AN6 AN — A/D Channel 6 input
ICSPDAT ST CMOS Serial Programming Data I/O
Legend: AN = Analog input or output CMOS =C MO S com patible input or output OD = Open Drain
TTL = TTL compatible input ST =Schmitt Trigger input with CMOS levels I2C = Schmitt T rigger input with I 2C
Note 1: Analog Test is selected when the ATST CON<BNCHEN> bit is set.
2: Selected when the device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0>
bits in the BUFFCON register.
3: Selected when the device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits
in the BUFFCON register.
2014 Microchip Technology Inc. DS20005350A-page 13
MCP19118/19
GPB5/AN7/ICSPCLK/
ALT_CLKPIN
(MCP19119 Only)
GPB5 TTL CMOS Gene ral purp os e I/O
AN7 AN — A/D Channel 7 input
ISCPCLK ST — Serial Programming Cloc k
ALT_CLKPIN — — Alternate switching frequency clock input
or output (2,3)
GPB6 (M CP19119 Only) GPB6 TTL CMOS General purp os e I/O
GPB7 (M CP19119 Only) GPB7 TTL CMOS General purp os e I/O
VIN VIN — — Device input supply voltage
VDD VDD — — Internal +5V LDO output pin
VDR VDR — — Gate drive supply input voltage pin
GND GND — — Small signal quiet ground
PGND PGND — — Large signal power ground
LDRV LDRV — — High-current drive signal connected to the gate
of the low-side MOSFE T
HDRV HDRV — — Floating high-current drive signal connected to
the gate of the high-side MOSFET
PHASE PHASE — — Synchronous buck switch node connection
BOOT BOOT — — Floating boo t s trap su ppl y
+VSEN +VSEN — — Positive input of the output voltage sense
differential amplifier
-VSEN -VSEN — — Negative input of the output voltage sense
differential amplifier
+ISEN +ISEN — — Current sense input
-ISEN -ISEN — — Current sense inpu t
EP — — — Exposed The rma l Pad
TABLE 2-1: MCP19118/19 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS =C MO S com patible input or output OD = Open Drain
TTL = TTL compatible input ST =Schmitt Trigger input with CMOS levels I2C = Schmitt T rigger input with I 2C
Note 1: Analog Test is selected when the ATST CON<BNCHEN> bit is set.
2: Selected when the device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0>
bits in the BUFFCON register.
3: Selected when the device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bit s
in the BUFFCON register.
MCP19118/19
DS20005350A-page 14 2014 Microchip Technology Inc.
2.1 Detailed Pin Functional
Description
2.1.1 GPA0 PIN
GPA0 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN0 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 0, b its TR ISA0 a nd ANSA0
must b e set.
When the ATSTCON<BNCHEN> bit is set, this pin is
configured as the ANALOG_TEST function. It is a
buffered output of the internal analog signal
multiplexer. Signals present on this pin are controlled
by the BUFFCON register.
2.1.2 GPA1 PIN
GPA1 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN1 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 1, b its TR ISA1 a nd ANSA1
must b e set.
When the MCP19118/19 is configured as a multiple
output or multi-phase master or slave, this pin is
configured to be the switching frequency
synchronization input or output, CLKPIN. See
Section 3.10.6 “Multi-Phase System” and
Section 3.10.7 “Multiple Output System” for more
information.
2.1.3 GPA2 PIN
GPA2 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN2 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 2, b its TR ISA2 a nd ANSA2
must b e set.
When bit T0CS is set, the T0CKI function is enabled.
See Section 23.0 “Timer0 Module” for more
information.
GPA2 can also be configured as an external interrupt
by setting the INTE bit. See Section 15.2 “GPA2/INT
Interrupt” for more information.
2.1.4 GPA3 PIN
GPA3 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN3 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 3, b its TR ISA3 a nd ANSA3
must b e set.
2.1.5 GPA4 PIN
GPA4 is a true open-drain general purpose pin whose
data direction is controlled in TRISGPA. There is no
internal connection between this pin and the device
VDD, making this pin ideal to be used as an SMBus
Alert pin. This pin does not have a weak pull-up, but
interrupt-on-change is available.
2.1.6 GPA5 PIN
GPA5 is a general purpose TTL input-only pin. An
internal weak pull-up and interrupt-on-change are also
available.
For pr ogr amm in g purposes, this pin is t o b e co nne cte d
to the MCLR pin of the serial programmer. See
Section 28.0 “In-Circuit Serial Programming™
(ICSP™)” for more information.
2.1.7 GPA6 PIN
GPA6 is a general purpose CMOS input/output pin
whose data direction is controlled in TRISGPA. An
interrupt-on-change is also available.
On the MCP19118, the ISCPDAT is the serial
programming data input function. This is used in
conjunction with ICSPCLK to serial program the
device. This pin function is only implemented on the
MCP19118.
2.1.8 GPA7 PIN
GPA7 is a true open-drain general purpose pin whose
data direction is controlled in TRISGPA. There is no
internal connection between this pin and the device
VDD. This pin does not have a weak pull-up, but
interrupt-on-change is available.
When the MCP19118/19 is configured for I2C
communication (see Section 27.2 “I2C Mode
Overview”), GPA7 functions as the I2C clock, SCL.
On the MCP19118, the ISCPCLK is the serial
programming clock function. This is used in conjunction
with ICSPDAT to serial program the device. This pin
function is only implemented on the MCP19118.
2.1.9 GPB0 PIN
GPB0 is a true open-drain general purpose pin whose
data direction is controlled in TRISGPB. There is no
internal connection between this pin and the device
VDD. This pin does not have a weak pull-up, but
interrupt-on-change is available.
When the MCP19118/19 is configured for I2C
communication (see Section 27.2 “I2C Mode
Overview”), GPB0 functions as the I2C clock, SDA.
2014 Microchip Technology Inc. DS20005350A-page 15
MCP19118/19
2.1.10 GPB1 PIN
GPB1 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN4 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 4, b its TR ISB1 a nd ANSB1
must b e set.
When the MCP19118/19 is configured as a multiple
output or multi-phase master or slave, this pin is
configured to be the error amplifier signal input or
output. See Section 3.10.6 “Multi-Phase System”
and Section 3.10.7 “Multiple Output System” for
more information.
2.1.11 GPB2 PIN
GPB2 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN5 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 5, b its TR ISB2 a nd ANSB2
must b e set.
2.1.12 GPB4 PIN
This pin and its ass oc ia t ed func tio ns are o nly av ail abl e
on the MCP1 9119 device.
GPB4 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN6 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 6, b its TR ISB4 a nd ANSB4
must b e set.
On the MCP19119, the ISCPDAT is the serial
programming data input function. This is used in
conjunction with ICSPCLK to serial program the
device. This pin function is only implemented on the
MCP19119.
2.1.13 GBP5 PIN
This pin and its ass oc ia t ed func tio ns are o nly av ail abl e
on the MCP1 9119 device.
GPB5 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN7 is an input to the A/D. To configure this pin to be
read by the A/ D on c hannel 7, b its TR ISB5 a nd ANSB5
must b e set.
On the MCP19119, the ISCPCLK is the serial
programming clock function. This is used in conjunction
with ICSPDAT to serial program the device. This pin
function is only implemented on the MCP19119.
This pin can also be configured as an alternate
switching frequency synchronization input or output,
ALT_CLKPIN, for use in multiple output or multi-phase
systems. See Section 19.1 “Alterna te Pin Func tion”
for more information.
2.1.14 GPB6 PIN
This pin and its associated function s are onl y av ailable
on the MCP19119 device.
GPB6 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
2.1.15 GPB7 PIN
This pin and its associated function s are onl y av ailable
on the MCP19119 device.
GPB7 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
2.1.16 VIN PIN
Device input power connection pin. It is recommended
that capacitance be placed between this pin and the
GND pin of the device.
2.1.17 VDD PIN
The outp ut o f the interna l +5 .0V regula tor i s connected
to this pin. It is recommended that a 1.0 µF bypass
capacitor be connected between this pin and the GND
pin of the device. The bypass capacitor should be
placed physically close to the device.
2.1.18 VDR PIN
The 5V supply for the low-side driver is connected to
this pin. The pin can be connected by an RC filter to the
VDD pin.
2.1.19 GND PIN
GND is the small signal ground connection pin. This pin
should be connec ted to the exposed pad on the bottom
of the package.
2.1.20 PGND PIN
Connect all large signal level ground returns to PGND.
These large-signal level ground traces should have a
small lo op area and minima l length to prevent c ouplin g
of switching noise to sensitive traces.
2.1.21 LDRV PIN
The gate of the low-side or rectifying MOSFET is
connected to LDRV. The PCB trace connecting LDRV
to the gate must be of minimal length and appropriate
width to handle the high peak drive currents and fast
voltage transitions.
MCP19118/19
DS20005350A-page 16 2014 Microchip Technology Inc.
2.1.22 HDRV PIN
The gate of the high-side MOSFET is connected to
HDRV. This is a floating driver referenced to PHASE.
The PCB trace connecting HDRV to the gate must be
of minimal length and appropriate width to handle the
high-peak drive current and fast voltage transitions.
2.1.23 PHASE PIN
The PHASE pin provides the return path for the
high-side gate driver. The source of the high-side
MOSFET, the drain of the low-side MOSFET and the
inductor are connected to this pin.
2.1.24 BOOT PIN
The BOOT pin is the floating bootstrap supply pin for
the high-side gate driver. A capacitor is connected
between this pin and the PHASE pin to provide the
necessary charge to turn on the high-side MOSFET.
2.1.25 +VSEN PIN
The noninverting input of the unity gain amplifier used
for output voltage remote sensing is connected to the
+VSEN pin. This pin can be internally pulled-up to VDD
by setting the PE1<PUEN> bit.
2.1.26 -VSEN PIN
The inverting input of the unity gain amplifier used for
output voltage remote sensing is connected to the
-VSEN pin. This pin can be internally pulled-down to
GND by setting the PE1<PDEN> bit.
2.1.27 +ISEN PIN
The noninverting input of the current sense amplifier is
connec ted to the +ISEN pin.
2.1.28 -ISEN PIN
The inverting input of the current sense amplifier is
connected to the -ISEN pin.
2.1.29 EXPOS ED PAD (EP )
There is no interna l connection to the Exposed Thermal
Pad. The EP should be connected to the GND pin and
to the GND PCB plane to aid in th e removal of the hea t.
2014 Microchip Technology Inc. DS20005350A-page 17
MCP19118/19
3.0 FUNCTIONAL DESCRIPTION
3.1 Linear Regulators
Two internal linear regulators generate two 5V rails.
One 5V rail is used to provide power for the internal
analog circuitry and is contained on-chip. The second
5V rail provides power to the internal PIC core and is
present on the VDD pin. It is recommended that a 1 µF
capacitor be placed between VDD and PGND.
The VDR pin provides power to the internal
synchronous MOSFET driver. VDD can be directly
connec ted t o V DR or connected through a low-pass RC
filter to provide noise filtering. A 1 µF ceramic bypass
capacitor should be placed between VDR and PGND.
When connecting VDD to VDR, the gate drive current
required to drive the ex ternal MOSFETs must be added
to the MCP19118/19 quiescent current, IQ(max). This
total current must be less than the maximum current,
IDD-OUT, available from VDD, that is specified in
Section 4.2 “Electrical Characteristics”.
EQUATION 3-1: TOTAL REGULATOR
CURRENT
EQUATION 3-2: GATE DRIVE CURRENT
Alternatively, an external regulator can be used to
power the synchronous driver. An external 5V source
can be connected to VDR. The amount of current
required from this external source can be found in
Equation 3-2. Care must be taken that the voltage
applied to VDR does no t exceed the maximu m ratings
found in Section 4.1 “Absolute Maximum
Ratings(†)”.
3.2 Inter nal Synchronous Driver
The internal synchronous driver is capable of driving
two N-Channel MOSFETs in a synchronous rectified
buck converter topology. The gate of the floating
MOSFET is connected to the HDRV pi n. The so urce of
this MOSFET is connected to the PHASE pin. The
HDRV pin source and sink current is configurable. By
setting the PE1<DRVSTR> bit, the hig h-side is cap able
of sourcing and sinking a peak current of 1A. By
clearin g this bit, the sour ce and sink peak c urrent is 2A.
The MOSFET connected to the LDRV pin is not
floating. The low-side MOSFET gate is connected to
the LDRV pin and the source of this MOSFET is
connec ted to PGND. The driv e strength of t he LDR V pin
is not configurable. This pin is capable of sourcing a
peak current of 2A. The peak sink current is 4A. This
helps keep the low-side MOSFET off when the
high-si de MOSFET is turn ing on.
3.2.1 MOSFET DRIVER DEAD TIME
The MOSFET driver dead time is defined as the time
between one drive signal going low and the
complimentary drive signal going high. Refer to
Figure 6-2. The MCP19118/19 has the capability to
adjust b oth the hig h-side and lo w-si de driv er dead time
independently. The adjustment of the driver dead time
is controlled by the DEADCON register and is
adjustable in 4 ns increments.
3.2.2 MOSFET DRIVER CONTROL
The MC P19118/19 ha s the a bility to disa ble the entire
synch ronous driver o r just o ne sid e of the sync hronou s
drive signal. The bits that control the MOSFET driver
can be found in Register 8-1.
By setting the ATSTCON<DRVDIS> bit, the entire
sync hronous d river is dis abled. Th e HDRV and LDRV
signals are set low and the PHASE pin is floating.
Clearing this bit allows normal operation.
Individual control of the HDRV or LDRV signal is
accomplished by setting or clearing the
ATSTCON<HIDIS> or ATSTCON<LO DIS> bits. When
either driver is disabled, the output signal is set low.
IDD OUT–IQIDRIVE IEXT
++>
Where:
-I
DD-OUT is the total current available from
VDD
-I
Q is the device quiescent current
-I
DRIVE is the current required to drive the
external MOSFETs
-I
EXT is the amount of current used to power
additional external circuitry
IDRIVE QgHIGH QgLOW
+FSW
=
Where:
-I
DRIVE is the current required to drive the
external MOSFETs
-Q
gHIGH is the total gate charge of the
high-side MOSFET
-Q
gLOW is the total gate charge of the
low-side MOSFET
-F
SW is the switching frequency
Note 1: The PE1<DRVSTR> bit configures the
peak source/sink current of the HDRV
pin.
Note 1: Refer to Figure 1-1 for a graphical
representation of the MOSFET
connections.
Note 1: The DEADCON register controls the
amount o f d ead time ad ded to th e H DRV
or LDR V signal. The dead time circuitry is
enabled by the PE1<LDLYBY> and
PE1<HDLYBY> bits.
MCP19118/19
DS20005350A-page 18 2014 Microchip Technology Inc.
3.3 Output Voltage
The output voltage is configured by the settings
contained in t he OVCCON and O VFC O N re gis t e rs. N o
external resistor divider is needed to set the output
voltage. Refer to Section 6.10 “Output Voltage
Configuration”.
The MCP19118/19 contains a unity gain differential
amplifi er used for remote sensing of the output voltag e.
Connect the +VSEN and -VSEN pins directly at the load
for bette r load regul ation. The + VSEN and -V SEN are the
positive and negative inputs, respectively, of the
diffe rential amplifier.
3.4 Switching Frequency
The sw itchi ng freq uency is c onfig urable over t he rang e
of 100 kHz to 1.6 MHz. The Timer2 module is used to
generate the HDRV/LDRV switching frequency. Refer
to Section 26.0 “PWM Module” for more information.
Example 3-1 shows how to configure the
MCP19118/19 for a switching frequency of 300 kHz.
EXAMPLE 3- 1: CONFIGURING FSW
3.5 Compensation
The MCP19118/19 is an analog peak current mode
controller with integrated adjustable compensation.
The CMPZCON register is used to adjust the
compensation zero frequency and gain. Figure 3-1
shows the internal compensation network with the
output differential amplifie r.
FIGURE 3-1: SI MPLIFIED INTERNAL
COMPENSATION
3.6 Slope Compensation
In current mode control systems, slope compensation
needs to be added to the control path to help prevent
subharmonic oscillation when operating with greater
than 50% duty cycle. In the MCP19118/19, a negative
slope is added to the error amplifier output signal
before it is compared to the current sense signal. The
amount of slope added is controlled by the
SLPCRCON register.
The amount of slope compensation added should be
equal to the inductor current down slope during the
high-side off time.
3.7 Current Sense
The output current is differentially sensed by the
MCP19118/19. The sense element can be either a
resistor placed in series with the output or the series
resistance of the inductor. If the inductor series
resistance is used, a filter is needed to remove the
large AC component of the voltag e that appears across
the inductor and leave only the small AC voltage that
appears across the inductor resistance, as shown in
Figure 3-2. This small AC voltage is representative of
the output current.
FIGURE 3-2: INDUCTOR CURRENT
SENSE FILTER
The value of RS and CS can be found by using
Equation 3-3. When the current sense filter time
constant is set equal to the inductor time constant, the
voltage appearing across CS approximates the current
flowing in the inductor, multiplied by the inductor
resistance.
BANKSEL T2CON
CLRF T2CON ;Turn off Timer2
CLRF TMR2 ;Initialize module
MOVLW 0x19 ;Fsw=300 kHz
MOVWF PR2
MOVLW 0x0A ;Max duty cycle=40%
MOVWF PWMRL
MOVLW 0x00 ;No phase shift
MOVWF PWMPHL
MOVLW 0x04 ;Turn on Timer2
MOVWF T2CON
VREF
+VSEN
-VSEN
Note 1: To enable the slope compensation
circuitry, the ABECON<SLCPBY> bit
must be cleared.
To Load
-ISEN
+ISEN
HDRV
LDRV
PHASE
LR
L
CS
RS
VIN
2014 Microchip Technology Inc. DS20005350A-page 19
MCP19118/19
EQUATION 3-3: CALCULATING FILTER
VALUES
Both AC g ain a nd D C g ain c an be a dde d to the curre nt
sense signal. Refer to Section 6.3 “Current Sense
AC Gain” and Section 6.4 “Current Sense DC Gain”
for more information.
3.7.1 PLACEMENT OF THE CURRENT
SENSE FILTER COMPONENTS
The amplitude of the current sense signal is typically
less than 100 mV peak-to-peak. Therefore, the small
signal current sense traces are very susceptible to
circuit noise. When designing the printed circuit board,
placement of RS and CS is very important. The +ISEN
and -ISEN traces should be routed parallel to each other
with minimum spacing. This Kelvin sense routing
technique helps minimize noise sensitivity. The filter
capacitor, CS, should be placed as close to the
MCP19118/19 as possible. This will help filter any
noise that is injected onto the current sense lines. The
trace connecting CS to the inductor should occur
directly at the inductor and not at any other +VSEN
trace. The filter resistor, RS, should be placed close to
the induc tor. See Figure 3-3 f or comp onent p lacem ent.
Care should also be taken to avoid routing the +ISEN
and -ISEN traces nea r the high cur rent s witc hi ng no des
of the HDRV, LDRV, PHASE or BOOST traces. It is
reco mmended that a ground la yer be pl aced bet ween
these high current traces and the sm all signal current
sense traces.
FIGURE 3-3: CURRENT SENSE FILTER COMPONENT PLACEMENT
L
RL
------RSCS
=
Where:
- L is the inductance value of the output
inductor
-R
L is the series resistance of the output
inductor
-R
S is the current sense filter resistor
-C
S is the current sense filter capacitor
+I
SEN
-I
SEN
INDUCTOR
To
Load
To
PHASE
R
S
C
S
MCP19118/19
DS20005350A-page 20 2014 Microchip Technology Inc.
3.8 Protection Features
3.8.1 INPUT UNDERVOLTAGE LOCKOUT
The input undervoltage lockout (UVLO) threshold is
configurable by the VINLVL register. When the voltage
at the VIN pin of the MCP19118/19 is below the
configurable threshold, the PIR2<VINIF> flag will be
set. This flag is cleared by hardware once the VIN
voltage is greater than the configurable threshold. By
enabling the global interrupts or polling the VINIF bit,
the MCP19118/19 can be disabled when the VIN
voltage is below the threshold.
Some techniques that can be used to disable the
switching of the MCP19118/19 while the VINIF flag is
set include setting the A TSTCON<DVRDIS> bit, setting
the referen ce voltage to 0V, setting the PE1<PUEN> bit
or setting the ATSTCON<HIDIS> and
ATSTCON<LODIS> bits.
3.8.2 OUTPUT OVERCURRENT
The MC P19118/19 sense s th e vo lt a ge drop across th e
high-side MOSFET to determine when an output
overcurrent (OC) exists. This voltage drop is
configurable by the OCCON register and is measured
when the high-side MOSFET is conducting. To avoid
false OC events, leading edge blanking is applied to
the measurements. The amount of blanking is
controlled by the OCLEB<1:0> bits in the OCCON
register. See Section 6.2 “Output Overcurrent” for
more information.
3.8.3 OUTPUT UNDERVOLTAGE
When the output undervoltage DAC is enabled by
setting the ABECON<UVDCEN> bit, the voltage
measured between the +VSEN and -VSEN pins is
monitored and compared to the UV threshold
controlled by the OUVCON register. When the output
voltage is below the threshold, the PIR2<UVIF> flag
will be set. Once set, firmware can determine how the
MCP19118/19 responds to the fault condition and it
must clear the UVIF flag.
By setting the PE1<UVTEE> bit, the HDRV and LDRV
signals will be asserted low when the UVIF flag is set.
The signals will remain low until the flag is cleared.
3.8.4 OUTPUT OVERVOLTAGE
When the output overvoltage DAC is enab led by setting
the ABECON<OVDCEN> bit, the voltage measured
between the +VSEN and -VSEN pins is monitored and
compared to the OV threshold controlled by the
OOVCON register. When the output voltage is above
the threshold, the PIR2<OVIF> flag will be set. Once
set, firmware can determine how the MCP19118/19
responds to the fault condition and it must clear the
OVIF flag.
By setting the PE1<OVTEE> bit, the HDRV and LDRV
signals will be asserted low when the OVIF flag is set.
The signals will remain low until the flag is cleared.
Note 1: The UVLO DAC must be enabled by
setting the VINLVL<UVLOEN> bit.
2: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Globa l Interrupt Enab le (GIE) bit in
the INTCON register.
Note 1: The OC DAC mu st be e nable d by s etting
the OCCON<OCEN> bit.
Note 1: The UV D AC mus t be ena bl ed by setting
the ABECON<UVDCEN> bit.
2: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Globa l Interrupt Enab le (GIE) bit in
the INTCON register.
3: The output of the remote sense
comparator is compared to the UV
threshold. Therefore, the offset in this
comparator should be considered when
calculating the UV threshold.
Note 1: The OV DAC mus t be enable d by setting
the ABECON<UVDCEN> bit.
2: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Globa l Interrupt Enab le (GIE) bit in
the INTCON register.
3: The output of the remote sense
comparator is compared to the OV
threshold. Therefore, the offset in this
comparator should be considered when
calculating the OV threshold.
2014 Microchip Technology Inc. DS20005350A-page 21
MCP19118/19
3.8.5 OVERTEMPERATURE
The MCP19118/19 features a hardware
overtemperature shutdown protection typically set at
+160°C. No firmware fault-handling procedure is
required to shutdown the MCP19118/19 for an
overtemperature condition.
3.9 PIC Microcontroller Core
Integrated into the MCP19118/19 is the PIC
microcontroller mid-range core. This is a fully fun ctional
microcontroller, allowing proprietary features to be
implemented. Setting the CONFIG<CP> bit enables
the code protection. The firmware is then protected
from extern al read s or write s. Var ious stat us and fa ult
bits are available to customize the fault handling
response.
A minimal amount of firmware is required to properly
configure the MCP19118/19. Section 6.0
“Configuring the MCP19118/19” contains detailed
infor mation ab ou t each regist er that needs to be set for
the MCP19118/19 device to operate. To aid in the
development of the required firmware, a Graphical
User Interface (GUI) has been developed. This GUI
can be used to quickly configure the MCP19118/19 for
basic operation. Customized or proprietary features
can then be added to the GUI-generated firmware.
The MCP19118/19 device features firmware debug
support. See Section 30.0 “Development Support”
for more information.
3.10 Miscellaneous Features
3.10.1 DEVICE ADDRESSING
The communication address of the MCP19118/19 is
stored in the SSPADD register. This value can be
loaded when the device firmware is programmed or
configured by external components. By reading a
voltage on a GPIO with the ADC, a device-specific
address can be stored into the SSPADD register.
The MCP1 91 18/19 cont ains a seco nd address regi ster ,
SSPADD2. This is a 7-bit address that can be used as
the SMBus a lert add res s wh en PMBus co mm un ica tio n
is used. See Section 27.0 “Master Synchronous
Serial Port (MSSP) Module” for more information.
3.10.2 DEVICE ENABLE
A GPIO pin can be configured to be a device enable
pin. By configuring the pin as an input, the PORT
register or the interrupt-on-change (IOC) can be used
to enable the device. Example 3-2 shows how to
configure a GPIO as an enable pin by testing the
PORTGPA register.
EXAMPLE 3-2: CONFIGURING GPA3 AS DEVICE ENABLE
Note 1: The GUI can be found on the
MCP19118/19 product page on
www.microchip.com.
2: Microchip's MPLAB X Integrated
Development Environment Software is
required to use the GUI.
BANKSEL TRISGPA
BSF TRISGPA, 3 ;Set GPA3 as input
BANKSEL ANSELA
BCF ANSELA, 3 ;Set GPA3 as digital input
:
: ;Insert additional user code here
:
WAIT_ENABLE:
BANKSEL PORTGPA
BTFSS PORTGPA, 3 ;Test GPA3 to see if pulled high
;A high on GPA3 indicated device to be enabled
GOTO WAIT_ENABLE ;Stay in loop waiting for device enable
BANKSEL ATSTCON
BSF ATSTCON, 0 ;Enable the device by enabling drivers
:
: ;Insert additional code here
:
MCP19118/19
DS20005350A-page 22 2014 Microchip Technology Inc.
3.10.3 OUTPUT POWER GOOD
The output voltage measured between the +VSEN and
-VSEN pins can be monitored by the internal ADC. In
firmware, when this ADC reading matches a
user-def ined power g ood value, a GPIO can be toggled
to indicate the system output voltage is within a
specified range. Delays, hysteresis and time-out
values can all be configured in firmware.
3.10.4 OUTPUT VOLTAGE SOFT START
During start-up, soft start of the output voltage is
accomplished in firmware. By using one of the internal
timers and incrementing the OVCCON or OVFCON
register on a timer overflow, very long soft start times
can be achie ved .
3.10.5 OUTPUT VOLTAGE TRACKING
The MCP19118/19 can be configured to track another
voltage signal at start-up or shutdown. The ADC is
configu red to read a G PIO that has the desired t racking
voltage applied to it. The firmware then handles the
trac king of the int erna l out put vol tage re fere nce t o th is
ADC reading.
3.10.6 MULTI-PHASE SYSTEM
In a multi-phase system, the output of each converter
is conne cte d toge the r. There is one mas ter devi ce that
sets the sys tem switchi ng frequency and provi des each
slave device with an error signal, in order to regulate
the output to the same value.
The MC P1 9118/19 can be c onfigured as a m ul ti-p has e
maste r or slav e by setti ng t he MLTPH< 2:0> bits i n the
BUFFCON re gis te r. When set as a m ult i-ph as e m ast er
device, the internal switching frequency clock is
connec ted to GPA1 and the ou tput of the error am plifier
is connected to GPB1. The GPIOs need to be
configured as outputs.
When set as a multi-phase slave device, the GPA1 pin
is configured as the CLKPIN function. The switching
frequency clock from the master device must be
connected to GPA1. The slave device will synchronize
its internal switching frequency clock to the master
clock. Phase shift can be applied by setting the
PWMPHL register of the slave d evice. The slave G PB1
pin is configured as the error signal input pin (EAPIN).
The maste r error amplifier out put must be conne cted to
GPB1. Ga in can be add ed to the master error ampl ifier
output signal by the SLVGNCON register setting
(Register 6-8). The slave device will use this master
error signa l to regulate th e output volt age. When set as
a sla ve de vice , GPA1 and GPB1 need t o be confi gured
as inputs. Refer to Section 26.1 “Standard
Pulse-Wi d th Modula tion (PW M) Mode” for additi onal
information.
3.10.7 MULTIPLE OUTPUT SYSTEM
In a multiple output system, the switching frequency of
each converter should be synchronized to a master
clock to prevent beat frequencies from developing.
Phase shift is often added to the mas ter clock to help
smooth the system input current. The MCP19118/19
has the abili ty to functi on as a multiple output master or
slave by setting the appropriate MLTPH<2:0> bits in
the BUFFCON register.
When configured as a multiple output master, the
GPA1 pin is set as the CLKPIN output function. The
internal switching frequency clock is applied to this pin
and is to be connected to the GPA1 pin of the slave
units.
When configured as a multiple output slave, the GPA1
pin is set as the CLKPIN input function. The switching
frequency clock of the master device is connected to
this pin. Phase shift can be applied by appropriately
setting the PWMPHL regis ter of the slave d evice. Refer
to Section 26.1 “Standard Pulse-Width Modulation
(PWM) Mode”.
3.10.8 SYSTEM BENCH TESTING
The MCP19118/19 is a highly integrated controller. To
facilitate system prototyping, various internal signals
can be measured by configuring the MCP19118/19 in
Bench Test mode. To accomplish this, the
ATSTCON<BNCHEN> bit is set. This configures GP A0
as the ANALOG _T EST feat ure. Th e sig na ls m eas ure d
on GPA0 are controlled by the ASEL<4:0> bits in the
BUFFCON register. See Section 8.0 “System Bench
Testing” for more information.
Note 1: The ALT_CLKPIN can also be used by
setting the APFCON<CLKSEL> bit. This
function is only available in the
MCP19119.
Note 1: The ALT_CLKPIN can also be used by
setting the APFCON<CLKSEL> bit. This
function is only available in the
MCP19119.
Note 1: The factory-set calibration words are
write-protected even when the
MCP19118/19 is placed in Bench Test
mode.
2014 Microchip Technology Inc. DS20005350A-page 23
MCP19118/19
4.0 ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Ratings(†)
VIN -V
GND...................................................................................................................................................-0.3V to +42V
VIN -V
GND (non-switching transient < 500 ms)...........................................................................................-0.3V to +48V
VBOOT - VPHASE..........................................................................................................................................-0.3V to +6.5V
VPHASE (continuous) ........................................................................................................................GND – 0.3V to +38V
VPHASE (transient < 100 ns)............................................................................................................. GND – 5.0V to +38V
VDD internally generated...................................................................................................................................+5V ±20%
VHDRV, HDRV Pin..........................................................................................................+VPHASE – 0.3V to VBOOT +0.3V
VLDRV, LDRV Pin............................................................................................................. +(VGND – 0.3V) to (VDD +0.3V)
Voltage on MCLR with respect to GND....................................................................................................-0.3V to+13.5V
Maximum Voltage: any other pin..................................................................................... +(VGND – 0.3V) to (VDD +0.3V)
Maximum output current sunk by any single I/O pin...............................................................................................25 mA
Maximum output current sourced by any single I/O pin..........................................................................................25 mA
Maximum current sunk by all GPIO ........................................................................................................................65 mA
Maximum current sourced by all GPIO...................................................................................................................65 mA
ESD protection on all pins (HBM)...........................................................................................................................1.0 kV
ESD protection on all pins (MM)100V
† Not ice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a s tres s rati ng o nl y a nd functional operatio n o f th e device a t th ose or any other co ndi tio ns ab ove those indicated in
the operati onal listings of this specificat ion is not implied. Exposure to maximum rating conditions for extended periods
may affect devi ce reliabi lity.
MCP19118/19
DS20005350A-page 24 2014 Microchip Technology Inc.
4.2 Electrical Characteris tics
Electrical Specifications: Unless otherwise not ed, VIN = 12V, VREF = 1.2V, FSW =300kHz, T
A=+25°C.
Boldface specifications apply over the TA range of -40°C to +125°C.
Parameter Sym. Min. Typ. Max. Units Conditions
Input
Input Voltage VIN 4.5 —40 V
Input Quiescent Current IQ—510 mA Not switching
Shutdown Current ISHDN —1.8—mA Note 4
Adjustable Input
Undervoltage Lockout
Range
UVLO 3—32 V VINLVL is a LOG DAC
Input Undervoltage
Lockout Hysteresis UVLOHYS —13 —% Hysteresis applied to
adjustable UVLO setpoint
Overcurrent
Overcurrent Minimum
Threshold OCMIN —160—mV
Overcurrent Maximum
Threshold OCMAX —620—mV
Overcurrent Mid-Scale
Threshold OCMID 240 400 550 mV
Overcurrent Step Size OCSTEP_SIZE 10 15 25 mV
Adjustable OC Leading
Edge Blanki ng Min im um
Set Point
LEBmin —114—ns
Adjustable OC Leading
Edge Blanki ng Max im um
Set Point
LEBmax —780—ns
Current Se nse
Current Sense Minimum
AC Gain IAC_GAIN —0—dB
Current Sense Maximum
AC Gain IAC_GAIN —22.8—dB
Current Sense AC Gain
Mid-Set Point IAC_GAIN 8.5 11.5 14 dB
Current Sense AC Gain
Step Size IAC_GAIN_STEP —1.5—dB
Current Sense AC Gain
Offset Voltag e IAC_OFFSET -175 9 135 mV
Current Sense Minimum
DC Gain IDC_GAIN —19.5—dB
Current Sense Maximum
DC Gain IDC_GAIN —35.7—dB
Current Sense DC Gain
Mid-Set Point IDC_GAIN 27 28.6 30.3 dB
Current Sense DC Ga in
Step Size IDC_GAIN_STEP —2.3—dB
Note 1: Ensured by design. Not production tested.
2: VDD-OUT is the voltage pres en t at the VDD pin. VDD is the internally generated bias voltage.
3: This is the tot al source curren t for all G PIO pins c ombined. Ind ividual ly, each pi n can so urce a maxim um of
25 mA.
4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h and SLEE P
command issued to PIC core, see Section 16.0 “Power-Down Mode (Sleep)”.
2014 Microchip Technology Inc. DS20005350A-page 25
MCP19118/19
Current Sense DC Ga in
Offset Voltag e IDC_OFFSET 1.4 1.56 1.7 V
Voltage for Zero Current VZC — 1.45 — V VZCCON = 0x80h
Voltage Reference
Adjustable VOUT Range VOUT_RANGE 0.5 —3.6 VV
OUT range with no external
volt a ge div id er
VOUT Coarse Resolution VOUT_COARSE 10.8 15.8 25.8 mV
VOUT Coarse
Mid-Set Point VOUT_COARSE_MID 1.85 2.04 2.25 V
VOUT Fine Resolution VOUT_FINE —0.81mV
Outp ut Ove rvoltage
Adjustable Overvoltage
Range OVRANGE 0—4.5 V
Adjustable Overvoltage
Mid-Set Point OVMID 1.8 22.3 V
Adjustable Overvoltage
Resolution OVR—15 —mV
Output Undervoltage
Adjustable
Undervoltage Range UVRANGE 0—4.5
Adjustable Undervoltage
Mid-Set Point UVMID 1.8 22.3 V
Adjustable Undervoltage
Resolution UVR—15 —mV
Remote Sense Differential Amplifier
Closed-Loop Voltage
Gain AVOL 0.95 11.05 V/V
Comm on Mo de Ra nge VCMR GND – 0.3 —VDD +1.0 VNote 1
Common-Mode
Reject Ratio CMRR —57 — dB
Differen tial Amplifier
Offset VOS —30—mVSee Section 9.4 “Calibration
Word 4 and Calibration
Word 5” and Section 9.5
“Calibration Word 6 and
Calibration Word 7”
Compensation
Minimum Zero Frequency FZERO_MIN —350—Hz
Maximu m Ze ro Freq ue nc y FZERO_MAX — 35000 — Hz
Minimum Error Amplifier
Gain GEA_MIN —0—dB
Maximum Error Amplifier
Gain GEA_MAX — 36.15 — dB
4.2 Electrical Characteris tics (Continued)
Electrical Specifications: Unless otherwise not ed, VIN = 12V, VREF = 1.2V, FSW =300kHz, T
A=+25°C.
Boldface specifications apply over the TA range of -40°C to +125°C.
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Ensured by design. Not production tested.
2: VDD-OUT is the voltage pres en t at the VDD pin. VDD is the internally generated bias voltage.
3: This is the tot al sour ce curren t for all GP IO pin s combined . Individu ally, each pin can source a m aximum of
25 mA.
4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h and SLEE P
command issued to PIC core, see Section 16.0 “Power-Down Mode (Sleep)”.
MCP19118/19
DS20005350A-page 26 2014 Microchip Technology Inc.
Oscillator
Internal Os cillator
Frequency FOSC 7.60 8.00 8.40 MHz
Switching Frequency FSW —F
OSC/N — kHz
Switching Frequency
Range Select N5—80
Maximu m Duty Cycle — (N–1)/N — %/
100
Dead Time Adjustment
Dead Time Step Size DTSTEP —4—ns
HDRV Output Driver
HDRV Source
Resistance RHDRV-SCR —12.6 Measured at 500 mA
Note 1, High Range
—23.5 Measured at 500 mA
Note 1, Low Range
HDRV Sink Resistance RHDRV-SINK —12.6 Measured at 500 mA
Note 1, High Range
—23.5 Measured at 500 mA
Note 1, Low Range
HDRV Source Current IHDRV-SCR —2—ANote 1, High Range
—1—ANote 1, Low Range
HDRV Sink Current IHDRV-SINK —2—ANote 1, High Range
—1—ANote 1, Low Range
HDRV Rise Time tRH —1530 ns Note 1, CLOAD =3.3nF,
High Range
HDRV Fall T ime tFH —1530 ns Note 1, CLOAD =3.3nF,
High Range
LDRV Output Driver
LDRV
Source Resistance RLDRV-SCR —12.5 Measured at 500 mA
Note 1
LDRV Sink Resistance RLDRV-SINK —0.51.0 Measured at 500 mA
Note 1
LDRV Sourc e Current ILDRV-SCR —2—ANote 1
LDRV Sink C urre nt ILDRV-SINK —4—ANote 1
LDRV Rise Time tRL —1530 ns Note 1, CLOAD =3.3nF
LDRV Fall Time tFL —715 ns Note 1, CLOAD =3.3nF
4.2 Electrical Characteris tics (Continued)
Electrical Specifications: Unless otherwise not ed, VIN = 12V, VREF = 1.2V, FSW =300kHz, T
A=+25°C.
Boldface specifications apply over the TA range of -40°C to +125°C.
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Ensured by design. Not production tested.
2: VDD-OUT is the voltage pres en t at the VDD pin. VDD is the internally generated bias voltage.
3: This is the tot al source curren t for all G PIO pins c ombined. Ind ividual ly, each pi n can so urce a maxim um of
25 mA.
4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h and SLEE P
command issued to PIC core, see Section 16.0 “Power-Down Mode (Sleep)”.
2014 Microchip Technology Inc. DS20005350A-page 27
MCP19118/19
Linear Regul ator
Bias Voltage, LDO Output VDD 4.6 5.0 5.4 VV
IN = 6.0V to 40V, Note 2
Internal Circ uitry
Bias Voltage AVDD —5.0 —VV
IN = 6.0V to 40V, Note 2
Maximum VDD Output
Current IDD 30 ——mA
Line Regulation VDD/
(VDD xVIN)—0.050.1 %/V (VDD+1.0V) VIN 40V
Note 2
Load Regulation VDD/VDD -1.75 -0.8 +0.5 %I
DD = 1 mA to 30 mA
Note 2
Output Short-Circuit
Current IDD_SC —65—mAV
IN =(V
DD +1.0V)
Note 2
Dropout Voltage VIN –V
DD —0.51VI
DD =30mA,
VIN =V
DD +1.0V
Note 2
Power Supply
Rejection Ratio PSRRLDO —60—dBf1000 Hz, IDD =25mA,
CIN =0µF, C
DD =1µF
Band Gap Volta ge BG -2.5% 1.23 +2.5% V
GPIO Pins
Maximum GPIO
Sink Current ISINK_GPIO ——90mANote 3, Note 1
Maximum GPIO
Source Current ISOURCE_GPIO ——90mANote 3, Note 1
GPIO Weak
Pull-Up Current IPULL-UP_GPIO 50 250 400 µA VDD =5V
GPIO Output Low
Voltage VOL ——0.6VI
OL =7mA, V
DD=5V,
TA=+90°C
GPIO Output
High Voltage VOH VDD –0.7 — — V I
OH =-2.5mA, V
DD =5V,
TA=+90°C
GPIO Input
Leakage Current GPIO_IIL — ±0.1 ±1 µA Negativ e cu rrent is d efi ned as
current sourced by the pin,
TA=+90°C
GPIO Input Low Voltage VIL GND — 0.8 V I/O Port with TTL buffer
VDD =5V, T
A=+90°C
GND 0.2VDD V I/O Port with Schmitt Trigger
buffer, VDD =5V, T
A=+90°C
GND 0.2VDD VMCLR, TA= +90°C
4.2 Electrical Characteris tics (Continued)
Electrical Specifications: Unless otherwise not ed, VIN = 12V, VREF = 1.2V, FSW =300kHz, T
A=+25°C.
Boldface specifications apply over the TA range of -40°C to +125°C.
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Ensured by design. Not production tested.
2: VDD-OUT is the voltage pres en t at the VDD pin. VDD is the internally generated bias voltage.
3: This is the tot al sour ce curren t for all GP IO pin s combined . Individu ally, each pin can source a m aximum of
25 mA.
4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h and SLEE P
command issued to PIC core, see Section 16.0 “Power-Down Mode (Sleep)”.
MCP19118/19
DS20005350A-page 28 2014 Microchip Technology Inc.
GPIO Input High Voltage VIH 2.0 — VDD V I/O Port with TTL buffer,
VDD =5V, T
A=+90°C
0.8VDD —V
DD V I/O Port with Schmitt Trigger
buffer, VDD =5V, T
A= +90°C
0.8VDD —V
DD VMCLR, TA= +90°C
Thermal Shutdown
Thermal Shutdown TSHD —160—°C
Thermal Shutdown
Hysteresis TSHD_HYS —20—°C
4.3 Thermal Specificat ions
Parameter Sym. Min. Typ. Max. Units Test Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +125 C
Operati ng Temperatur e Range TA-40 — +125 C
Maximum Junction Temperature TJ——+150C
Storage Temperature Range TA-65 — +150 C
Thermal Package Resistances
Thermal Resistance, 24L-QFN 4x4 JA —42—C/W
Thermal Resistance, 28L-QFN 5x5 JA —35.3—C/W
4.2 Electrical Characteris tics (Continued)
Electrical Specifications: Unless otherwise not ed, VIN = 12V, VREF = 1.2V, FSW =300kHz, T
A=+25°C.
Boldface specifications apply over the TA range of -40°C to +125°C.
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Ensured by design. Not production tested.
2: VDD-OUT is the voltage pres en t at the VDD pin. VDD is the internally generated bias voltage.
3: This is the tot al source curren t for all G PIO pins c ombined. Ind ividual ly, each pi n can so urce a maxim um of
25 mA.
4: PE1 = 0x00h, ABECON = 0x00h, ATSTCON = 0x80h, WPUGPA = 0x00h, WPUGPB = 0x00h and SLEE P
command issued to PIC core, see Section 16.0 “Power-Down Mode (Sleep)”.
2014 Microchip Technology Inc. DS20005350A-page 29
MCP19118/19
5.0 DIGITAL ELECTRICAL
CHARACTERISTICS
5.1 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
FIGURE 5-1: LOAD CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency TTime
Lowercase letters (pp) and their meanings:
pp cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppe rcase lett ers and their meanings:
SFFall P Period
HHigh R Rise
I Invalid (high-impedance) V Valid
L Low Z High-impedance
I2C™ only
AA Output acc ess High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CCHD Hold SU Setup
ST DAT Data input hold STO Stop condition
STA Start condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464
CL= 50 pF for all GPIO pins
Load Condition 1 Load Condition 2
MCP19118/19
DS20005350A-page 30 2014 Microchip Technology Inc.
5.2 AC Characteristics: MCP19118/19 (Industrial, Extended)
FIGURE 5-2: EXTERN AL CLOCK TIMING
FIGURE 5-3: CLKOUT AND I/O TIMING
TABLE 5-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Param No. Sym. Characteristic Min. Typ.†Max. Units Conditions
FOSC Oscillator Frequency(1) —8 —MHz
1T
OSC Oscillator Period(1)— 250 — ns
2T
CY Instr ucti on Cycle Time(1) — 1000 — ns
* These parameters are characterized but not tested.
† Dat a in the “Typ.” colum n is at VIN = 12V (VDD = 5V), +25 °C un le ss o therwise s t at ed. These para me ters are
for design guidance only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code.
OSC
Q4 Q1 Q2 Q3 Q4 Q1
1
2
OSC
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
17
20, 21
22
23
19 18
15
old value new value
2014 Microchip Technology Inc. DS20005350A-page 31
MCP19118/19
FIGURE 5-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMI NG
TABLE 5-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ.†Max. Units Conditions
17 TosH2ioV OSC1 (Q1 cycle) to — 50 150*ns
Port output valid — — 300 ns
18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid
(I/O in hold time) 100 — — ns
19 TioV2osH Port input valid to OSC1
(I/O in setup tim e) 0——ns
20 TioR Port output rise time — 10 40 ns
21 TioF Port output fall time — 10 40 ns
22
22A Tinp INT pin high
or low time 25
40 —
——
—ns
ns
23
23A Trbp
Trbp Port A change INT
high or low time Tcy — — ns
* These parameters are characterized but not tested.
† Data in the “Typ.” column is at VIN =12V (V
DD =5V), +25C unless otherwise stated.
VDD
MCLR
Internal
POR
PWRT
Time Out
OSC
Ti me Out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
MCP19118/19
DS20005350A-page 32 2014 Microchip Technology Inc.
FIGURE 5-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 5-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ.†Max. Units Conditions
30 TMCL MCLR Pulse Widt h (Low) 2 — — µs VDD = 5V, -40°C to +85°C
31 TWDT Watchdog Timer Time-Out
Period (No Prescaler) 71833msV
DD = 5V, -40°C to +85°C
32 TOST Oscillation Start-Up Timer
Period — 1024TOSC ——T
OSC = OSC1 period
33* TPWRT Po wer-Up Timer Period
(4 x TWDT)28 64 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset ——2.0µs
* These parameters are characterized but not tested.
† Dat a in the “Typ.” colu mn is a t VIN = 12V ( VDD = 5V), +25°C u nless oth erwis e st ated. T hese p aram eters a re
for design guidance only and are not tested.
TABLE 5-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ.†Max. Units Conditions
40*Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns
With Prescaler 10 — — ns
41*Tt0L T0CKI Low Pulse Width No Pres caler 0.5TCY + 20 — — ns
With Prescaler 10 — — ns
42*Tt0P T0CKI Period Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
* These parameters are characterized but not tested.
† Dat a in the “Typ.” column is at VIN =12V (V
DD = 5V), +25° C unless otherwis e st ated. The se p aramet ers are
for design guidance only and are not tested.
41
42
40
T0CKI
2014 Microchip Technology Inc. DS20005350A-page 33
MCP19118/19
FIGURE 5-6: PWM TIMING
TABLE 5-5: PWM REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ.† Max. Units Conditions
53* TccR PWM (CLKPIN) output rise time — 10 25 ns
54* TccF PWM (CLKPIN) output fall time — 10 25 ns
* These parameters are characterized but not tested.
† Data in the “Typ.” column is at VIN =12V (V
DD = 5V), +25°C unless otherwis e st ate d. Param et ers are for
design guidance only and are not tested.
TABLE 5-6: MCP19118/19 A/D CONVERTER (ADC) CHARACTERISTICS
S tandard Operating Conditions (unless otherwis e stated )
Operati ng tem pera ture -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ.†Max. Units Conditions
AD01 NRResolution — — 10 bit
AD02 EIL Integral Error — — 1LSbAV
DD =5.0V
AD03 EDL Differential Error — — 1 LSb No missing codes to 10 bits
AVDD =5.0V
AD04 EOFF Offset Error — +3.0 +5.0 LSb AVDD =5.0V
AD07 EGN Gain Error — 25LSbAV
DD =5.0V
AD06
AD06A VREF Reference Voltage(3)—AV
DD —V
AD07 VAIN Full -Sca le Range GND — AVDD V
AD08 ZAIN Recommended Impedance
of Analog Voltage Source —— 10k
* These parameters are characterized but not tested.
† Data in the “Typ.” column is at VIN =12V (V
DD = 5V), +25°C unless otherwise stated. These parameters
are for design guidance only and are not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: When ADC is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the ADC module.
Note: Refer to Figure 5-1 for load conditions.
53 54
PWM (CLKPIN)
MCP19118/19
DS20005350A-page 34 2014 Microchip Technology Inc.
FIGURE 5-7: A/D CONVERSION TIMING (NORMAL MODE)
TABLE 5-7: MCP19118/19 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operati ng tem pera ture -40°C TA+125°C
Param
No. Sym. Characteristic Min. Typ.†Max. Units Conditions
AD130* TAD A/D Clock Period 3.0 — 9.0 µ s TOSC-based, VDD = 5.0V
A/D Internal RC Oscillator
Period 1.6 4.0 6. 0 µs At VDD = 5.0V
AD131 TCNV Conversion Time
(not including Acquisition
Time)(1)
—11—T
AD Set GO/DONE bit to new data in
A/D R esu lt r egi ste r
AD132* TACQ Acquisition Time 11.5 — µs
AD133* TAMP Amplifier Settling Time — — 5 µs
AD134 TGO Q4 to A/D Clock Start —
—
TOSC/2
TOSC/
2+T
CY
—
—
—
— If the A/D clo ck source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allow s the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Dat a in the “Typ.” col umn is at VIN = 12V (VDD = 5V), +25°C unles s ot herwi se stat ed. Thes e p a r ameters are
for design guidance only and are not tested.
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
987 3210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
1/2 TCY
6
134
2014 Microchip Technology Inc. DS20005350A-page 35
MCP19118/19
FIGURE 5-8: A/D CONVERSION TIMING (SLEEP MODE)
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
973210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
134
6
8
132
DONE
MCP19118/19
DS20005350A-page 36 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 37
MCP19118/19
6.0 CONFIGURING THE
MCP19118/19
The MCP19118/19 is an analog controller with digital
peripheral. This means that device configuration is
handled through register settings instead of adding
external components. The following s ections detail how
to set the analog control registers.
6.1 Input Undervoltage Lockout
The VINLVL register co nta ins th e digit al v alue t hat set s
the input undervo lt a ge loc ko ut. Wh en t he in put volt ag e
on the VIN pin to the MCP19118/19 is below this
programmed level, the INTCON<VINIF> flag will be
set. This bit is automatically cleared when the
MCP19118/19 VIN voltage rises above this
program med level.
The VINLVL<UVLOEN> bit must be set to enable the
input undervoltage lockout circuitry.
Note: The VINIF interrupt flag bit is set when an
interrupt condition occurs, regardless of
the st ate of its correspo nd ing en able bit or
the Globa l Interrupt Enab le (GIE) b it in the
INTCON register.
REGISTER 6-1: VINLVL: INPUT UNDERVOLTAGE LOCKOUT CONTROL REGISTER
R/W-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UVLOEN — UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UVLOEN: Undervoltage Lockout DAC Control bit
1 = Undervoltage Lockout DAC is enabled
0 = Undervoltage Lockout DAC is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5-0 UVLO<5:0>: Undervoltage Lockout Configuration bits
UVLO<5:0> = 26.5*ln(UVLOSET_POINT/4)
MCP19118/19
DS20005350A-page 38 2014 Microchip Technology Inc.
6.2 Output Overcur rent
The MCP19118/19 features a cycle-by-cycle peak
current limit. By monitoring the OCIF interrupt flag,
custom overcurrent fault handling ca n be impleme nted.
To detect an output overcurrent, the MCP19118/19
senses the volt age drop acr oss the high -side MOSFET
while it is conducting. Leading edge blanking is
incorpo rated to m ask t he ove rcurr ent mea surement for
a given amount of time. This helps prevent false
overcurrent readin gs.
When an output overcurrent i s sensed, t he OCIF flag is
set and the high-side drive signal is immediately
terminated. Without any custom overcurrent handling
implemented, the high-side drive signal will be asserte d
high at the beginning of the next clock cycle. If the
overcurrent condition still exists, the high-drive signal
will again be terminat ed.
The OCIF interrupt flag must be cleared in software.
However, if a subsequent switching cycle without an
overcurrent condition has not occurred, hardware will
immediately set the OCIF interrupt flag.
The OCCON register contains the bits used to
configure both the output overcurrent limit and the
amount of leading edge blanking (see Register 6-2).
The OCCON<OCEN> bit must be set to enable the
input overcurrent circuitry.
Note: The OCIF interrupt flag bit is set when an
interrupt condition occurs, regardless of
the st ate of its correspond ing enable bit or
the Gl obal Interr upt Enable (GIE) bit in the
INTCON register.
2014 Microchip Technology Inc. DS20005350A-page 39
MCP19118/19
REGISTER 6-2: OCCON: OUTPUT OV ERCU RREN T CONTROL REGISTER
R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
OCEN OCLEB1 OCLEB0 OOC4 OOC3 OOC2 OOC1 OOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OCEN: Output Overc urre nt DAC Contro l bit
1 = Output Overcurrent DAC is enabled
0 = Output Overcurrent DAC is disabled
bit 6-5 OCLEB<1:0>: Leadi ng Edge Blank ing
00 = 114 ns blanking
01 = 213 ns blanking
10 = 400 ns blanking
11 = 780 ns blanking
bit 4-0 OOC<4:0>: Output Overcurrent Configuration bits
00000 = 160 mV drop
00001 = 175 mV drop
00010 = 190 mV drop
00011 = 205 mV drop
00100 = 220 mV drop
00101 = 235 mV drop
00110 = 250 mV drop
00111 = 265 mV drop
01000 = 280 mV drop
01001 = 295 mV drop
01010 = 310 mV drop
01011 = 325 mV drop
01100 = 340 mV drop
01101 = 355 mV drop
01110 = 370 mV drop
01111 = 385 mV drop
10000 = 400 mV drop
10001 = 415 mV drop
10010 = 430 mV drop
10011 = 445 mV drop
10100 = 460 mV drop
10101 = 475 mV drop
10110 = 490 mV drop
10111 = 505 mV drop
11000 = 520 mV drop
11001 = 535 mV drop
11010 = 550 mV drop
11011 = 565 mV drop
11100 = 580 mV drop
11101 = 595 mV drop
11110 = 610 mV drop
11111 = 625 mV drop
MCP19118/19
DS20005350A-page 40 2014 Microchip Technology Inc.
6.3 Current Sense AC Gain
The current measured across the inductor is a square
wave that is av era ged by th e c ap acitor ( CS) co nne cte d
between +ISEN and -ISEN. This very small voltage plus
the ripple can be amplified by the current sense AC
gain circuitry. The amount of gain is controlled by the
CSGSCON register.
REGISTER 6-3: CSGSCON: CURRENT SENSE AC GAIN CONTROL REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— Reserved Reserved Reserved CSGS3 CSGS2 CSGS1 CSGS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 Reserved
bit 3-0 CSGS<3:0>: Current Sense AC Gain Setting bits
0000 = 0 dB
0001 = 1.0 dB
0010 = 2.5 dB
0011 = 4.0 dB
0100 = 5.5 dB
0101 = 7.0 dB
0110 = 8.5 dB
0111 = 10.0 dB
1000 = 11.5 dB
1001 = 13.0 dB
1010 = 14.5 dB
1011 = 16.0 dB
1100 = 17.5 dB
1101 = 19.0 dB
1110 = 20.5 dB
1111 = 22.0 dB
2014 Microchip Technology Inc. DS20005350A-page 41
MCP19118/19
6.4 Current Sense DC Gain
DC gain can be adde d to the sens ed inductor current to
allow it to be read b y the ADC. The amount of DC gain
added is controlled by the CSDGCON register.
Adding D C gain t o the curr ent se nse signal used by the
control loop may also be needed in some multi-phase
systems to account for device and component
diffe rences. The CSD GEN bit det ermines if the gained
current sense signal is added back to the AC current
signal (see Register 6-4). If the CSDGEN bit is cleare d,
DC gain can still be added but the gained signal is not
added back to the AC current signal.
REGISTER 6-4: CSDGCON: CURRENT SENSE DC GAIN CONTROL REGISTER
R/W-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
CSDGEN — — — Reserved CSDG2 CSDG1 CSDG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSDGEN: Current Sense DC Gain Enable bit
1 = DC gain current sense signal used in control loop
0 = DC gain current sense signal only read by ADC
bit 6-4 Unimplemented: Re ad as ‘0’
bit 3 Reserved
bit 2-0 CSDG<2:0>: Curre nt Sen se DC Gain Setting bits
000 = 19.5 dB
001 = 21.8 dB
010 = 24.1 dB
011 = 26.3 dB
100 = 28.6 dB
101 = 30.9 dB
110 = 33.2 dB
111 = 35.7 dB
MCP19118/19
DS20005350A-page 42 2014 Microchip Technology Inc.
6.5 Voltage for Zero Current
In mu lti-phase system s, it may be n eces sary to pro vide
some offset to the sensed inductor current. The
VZCC ON r e gist e r ca n b e us ed to p r ov ide a p o si tiv e o r
negative offset in the sensed current. Typically, the
VZCCON will be set to 0x80h, which corresponds to
the sensed inductor current centered around 1.45V.
However, by adjusting the VZCCON register, this
centered voltage can be shifted up or down by
approximate ly 3.28 mV per step.
REGISTER 6-5: VZCCON: VOLTAGE FOR ZERO CURRENT CONTROL REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
VZC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 VZC<7:0>: Voltage for Zero Current Setting bits
00000000 = -420.00 mV Offset
00000001 = -416.72 mV Offset
•
•
•
10000000 = 0 mV Offset
•
•
•
11111110 = +413.12 mV Offset
11111111 = +416.40 mV Offset
2014 Microchip Technology Inc. DS20005350A-page 43
MCP19118/19
6.6 Compensation Sett ing
The MCP19118/19 uses a peak current mode control
architec ture. A con trol referenc e is used to regulate th e
peak cu rrent of the co nverter dire ctly. The inner c urrent
loop essentially turns the inductor into a
voltage-controlled current source. This reduces the
control-to-output transfer function to a simple
single-pole model of a current source feeding a
cap acitor. The desire d resp onse of the overa ll lo op ca n
be tuned by proper placement of the compensation
zero freq uency and gain. Figure 6-1 shows a simpl ified
drawing of the internal compensation. See Register 6-6
for the adjustable zero frequency and gain settings.
FIGURE 6-1: SIMPLIFIED
COMPENSATION
V
REF
+V
SEN
-V
SEN
REGISTER 6-6: CMPZCON: COMPENSATION SETTING CONTROL REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CMPZF3 CMPZF2 CMPZF1 CMPZF0 CMPZG3 CMPZG2 CMPZG1 CMPZG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimpleme nt ed bit, read as ‘0 ’
-n = Val ue at POR ‘1’ = Bit is set ‘0’ = Bit is clear ed x = Bit is unknown
bit 7-4 CMPZF<3:0>: Compens at i on Zero Freque ncy Setting bi ts
0000 = 1500 Hz
0001 = 1850 Hz
0010 = 2300 Hz
0011 = 2840 Hz
0100 = 3460 Hz
0101 = 4300 Hz
0110 = 5300 Hz
0111 = 6630 Hz
1000 = 8380 Hz
1001 = 9950 Hz
1010 = 12200 Hz
1011 = 14400 Hz
1100 = 18700 Hz
1101 = 23000 Hz
1110 = 28400 Hz
1111 = 35300 Hz
bit 3-0 CMPZG<3:0>: Compensation Gain Setting bits
0000 = 36.15 dB
0001 = 33.75 dB
0010 = 30.68 dB
0011 = 28.43 dB
0100 = 26.10 dB
0101 = 23.81 dB
0110 = 21.44 dB
0111 = 19.10 dB
1000 = 16.78 dB
1001 = 14.32 dB
1010 = 12.04 dB
1011 = 9.54 dB
1100 = 7.23 dB
1101 = 4.61 dB
1110 = 2.28 dB
1111 = 0.00 dB
MCP19118/19
DS20005350A-page 44 2014 Microchip Technology Inc.
6.7 Slope Compensation
A negative voltage slope is added to the output of the
error amplifier. This is done to prevent subharmonic
instability when:
1. the operating duty cycle is greater than 50%
2. wide changes in the duty cycle occur.
The amount of negative slope added to the error
amplifier output is controlled by Register 6-7.
The slope compensation is enabled by setting the
ABECON<SLCPBY> bit.
6.7.1 SLPS<3:0> CONFIGURATION
The SLPS<3:0> bits directly control the V/t of the
added ramp. This byte should be set proportional to
the switching frequency according to the following
equation:
EQUATION 6-1:
6.7.2 SLPG<3:0> CONFIGURATION
The SLPG< 3:0> bit s control the amp litude of the a dded
ramp. The values listed above correspond to a 50%
duty cycle waveform and are true only if the
SLPS<3:0> bits are set according to Equation 6-1. If
less amplitude is required, the SLPS<3:0> bits can be
adjusted to a lower switching frequency.
REGISTER 6-7: SLPCRCON: SLOPE COMPENSATION RAMP CONTROL REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SLPG3 SLPG2 SLPG1 SLPG0 SLPS3 SLPS2 SLPS1 SLPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 SLPG<3:0>: Slope Compensation Amplitude Configuration bits
0000 = 0.017 VPK-PK, measured for 50% duty cycle waveform
0001 = 0.022 VPK-PK, measured for 50% duty cycle waveform
0010 = 0.030 VPK-PK, measured for 50% duty cycle waveform
0011 = 0.040 VPK-PK, measured for 50% duty cycle waveform
0100 = 0.053 VPK-PK, measured for 50% duty cycle waveform
0101 = 0.070 VPK-PK, measured for 50% duty cycle waveform
0110 = 0.094 VPK-PK, measured for 50% duty cycle waveform
0111 = 0.125 VPK-PK, measured for 50% duty cycle waveform
1000 = 0.170 VPK-PK, measured for 50% duty cycle waveform
1001 = 0.220 VPK-PK, measured for 50% duty cycle waveform
1010 = 0.300 VPK-PK, measured for 50% duty cycle waveform
1011 = 0.400 VPK-PK, measured for 50% duty cycle waveform
1100 = 0.530 VPK-PK, measured for 50% duty cycle waveform
1101 = 0.700 VPK-PK, measured for 50% duty cycle waveform
1110 = 0.940 VPK-PK, measured for 50% duty cycle waveform
1111 = 1.250 VPK-PK, measured for 50% duty cycle waveform
bit 3-0 SLPS<3:0>: Slope Compensation V/t Configuration bits
Where:
FSW = Device switching frequency
n = Decimal equivalent of SLPS<3:0>
2014 Microchip Technology Inc. DS20005350A-page 45
MCP19118/19
6.8 MASTER Error Signal Ga in
When operating in a multi-phase system, the output of
the MASTER’s error amplifier is used by all SLAVE
device s as their control signal. It is import ant to bal ance
the current in all phases to maintain a uniform
temperature across all phases. Component tolerances
make this balancing difficult. Each SLAVE device has
the abil ity to gain o r attenuate the MASTER error signa l
depending upon the settings in the SLVGNCON
register.
Note: The SLVGNCON register is configured in
the multi-phase SLAVE device.
REGISTER 6-8: SLVGNCON: MASTER ERROR SIGNAL INPUT GAIN CONTROL REGISTER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — —SLVGN<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Re ad as ‘0’
bit 4-0 SLVGN<4:0>: MASTER Error Signal Gain bits
00000 = -3.3 dB
00001 = -3.1 dB
00010 = -2.9 dB
00011 = -2.7 dB
00100 = -2.5 dB
00101 = -2.3 dB
00110 = -2.1 dB
00111 = -1.9 dB
01000 = -1.7 dB
01001 = -1.4 dB
01010 = -1.2 dB
01011 = -1.0 dB
01100 = -0.8 dB
01101 = -0.6 dB
01110 = -0.4 dB
01111 = -0.2 dB
10000 = 0.0 dB
10001 = 0.2 dB
10010 = 0.4 dB
10011 = 0.7 dB
10100 = 0.9 dB
10101 = 1.1 dB
10110 = 1.3 dB
10111 = 1.5 dB
11000 = 1.7 dB
11001 = 1.9 dB
11010 = 2.1 dB
11011 = 2.3 dB
11100 = 2.6 dB
11101 = 2.8 dB
11110 = 3.0 dB
11111 = 3.2 dB
MCP19118/19
DS20005350A-page 46 2014 Microchip Technology Inc.
6.9 MOSFET Driver Programmable
Dead Time
The turn-on delay of the high-side and low-side drive
signals can be configured independently to allow
diff erent MOSFETs and ci rcuit board l ayouts to be used
to construct an optimized system. See Figure 6-2.
Setting the PE1<HDLYBY> and PE1<LDLYBY> bits
enables the high-side and low-side delay, respectively.
The amount of delay added is controlled in the
DEADCON register. See Register 6-9 for more
information.
FIGURE 6-2: MOSFET DRIVER
DEAD TIME
HDLY
LDLY
HDRV
LDRV
REGISTER 6-9: DEADCON: DRIVER DEAD TIME CONTROL REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
HDLY3 HDLY2 HDLY1 HDLY0 LDLY3 LDLY2 LDLY1 LDLY0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 HDLY<3:0>: High-Side Dead Time Configuration bits
0000 = 11 n s delay
0001 = 15 ns delay
0010 = 19 ns delay
0011 = 23 ns delay
0100 = 27 ns delay
0101 = 31 ns delay
0110 = 35 ns delay
0111 = 39 ns delay
1000 = 43 ns delay
1001 = 47 ns delay
1010 = 51 ns delay
1011 = 55 ns delay
1100 = 59 ns delay
1101 = 63 ns delay
1110 = 67 ns delay
1111 = 71 ns delay
bit 3-0 LDLY<3:0>: Low-Side Dead Time Configuration bits
0000 = 4 ns delay
0001 = 8 ns delay
0010 = 12 ns delay
0011 = 16 ns delay
0100 = 20 ns delay
0101 = 24 ns delay
0110 = 28 ns delay
0111 = 32 ns delay
1000 = 36 ns delay
1001 = 40 ns delay
1010 = 44 ns delay
1011 = 48 ns delay
1100 = 52 ns delay
1101 = 56 ns delay
1110 = 60 ns delay
1111 = 64 ns delay
2014 Microchip Technology Inc. DS20005350A-page 47
MCP19118/19
6.10 Output Voltage Configuration
Two registers control the error amplifier reference
voltage. The reference is coarsely set in 15 mV steps
and then finely adjusted in 0.82 mV steps above the
coarse setting (see Registers 6-10 and 6-11). Higher
output voltages can be achieved by using a voltage
divider connected between the output and the +VSEN
pin. Care must be taken to ensure maximum voltage
rating compliance on all pins.
Note: The OVFCON<VOUTEN> bit must be set
to enable the output voltage setting
registers.
REGISTER 6-10: OVCCON: OUTPUT VOLTAGE SET POINT COARSE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OVC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 OVC<7:0>: Output Voltage Set Point Coarse Configuration bits
OVC<7:0> = (VOUT/0.0158) – 1(1)
Note 1: The units for the OVC<7:0> equation are volts.
REGISTER 6-11: OVFCON: OUTPUT VOLTAGE SET POINT FINE CONTROL REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VOUTEN ——OVF<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VOUTEN: Output Voltage DAC Enable bit
1 = Output Voltage DAC is enabled
0 = Output Voltage DAC is disabled
bit 6-5 Unimplemented: Re ad as ‘0’
bit 4-0 OVF<4:0>: Output Voltage Set Point Fine Configuration bits
OVF<4:0> = (VOUT – VOUT_COARSE)/0.0008(1)
Note 1: The units for the OVF<4:0> equation are volts.
MCP19118/19
DS20005350A-page 48 2014 Microchip Technology Inc.
6.11 Output Undervoltage
The output voltage is monitored and, when it is below
the output und ervol tage threshol d, the UVIF fla g is set.
This flag must be cleared in software. See
Section 15.3.1.4 “PIR2 Register” for more
information.
The output undervoltage threshold is controlled by the
OUVCON register.
6.12 Output Overvoltage
The output voltage is monitored and, when it is above
the output overvoltage threshold, the OVIF flag is set.
This flag must be cleared in software. See
Section 15.3.1.4 “PIR2 Register” for more
information.
The output overvoltage threshold is controlled by the
OOVCON register.
REGISTER 6-12: OUVCON: OUTPUT UNDERVOLTAGE DETECT LEVEL CONTROL REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
OUV<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 OUV<7:0>: Output Undervoltage Detect Level Configuration bits
OUV<7:0> = (VOUT_UV_Detect_Level)/0.015(1)
Note 1: The units for the OUV<7:0> equation are volts.
REGISTER 6-13: OOVCON: OUTPUT OVERVOLTAGE DETECT LEVEL CONTROL REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
OOV<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 OOV<7:0>: Output Overvoltage Detect Level Configuration bits
OOV<7:0> = (VOUT_OV_Detect_Level)/0.015(1)
Note 1: The units for the OOV<7:0> equation are volts.
2014 Microchip Technology Inc. DS20005350A-page 49
MCP19118/19
6.13 Analog Peripheral Control
The MCP19118/19 has various analog peripherals.
These peripherals can be configured to allow
customizable operation. Refer to Register 6-14 for
more information.
6.13.1 DIODE EMULATION MODE
The MCP19118/19 can operate in either Diode
Emulation or Synchronous Rectification mode. When
operatin g in Di ode Emul ation mo de, the L DRV s ignal i s
terminated when the voltage across the low-side
MOSFET is approximately 0V. This condition is true
when the inductor current reaches approximately 0A.
Both the HDRV and LDRV signals are low until the
beginning of the next switching cycle. At that time, the
HDRV signal is asserted high, turning on the high-side
MOSFET.
When operating in Synchronous Rectification mode,
the LDRV signal is held high until the beginning of the
next switching cycle. At that time, the HDRV signal is
asserted high, turning on the high-side MOSFET.
The P E1< DECON> bit cont ro ls th e o perat in g mode of
the MC P19118/19.
6.13.2 HIGH-SIDE DRIVE STRENGTH
The peak source and sink current of the high-side
driver can be configured to be either 1A source/sink or
2A source/sink. The PE1<DVRSTR> bit determines
the high-side drive strength.
6.13.3 MOSFET DRIVER DEAD TIME
As described in Section 6.9 “MOSFET Driver
Programmable Dead Time”, the MOSFET driver
dead time can be adjusted. In order to enable dead
time se ttings , the proper b ypass bits must be c leared .
PE1<HDLYBY> and PE1<LDLYBY> control the delay
circuits. Clearing the respective bits allows the dead
time programmed by the DEADCON register to be
added to the appropriate turn-on edge.
6.13.4 OUTPUT VOLTAGE SENSE
PULL-UP/PULL-DOWN
A high-impedance pull-up on the +VSEN pin can be
configured by setting the PE1<PUEN> bit. When set,
the +VSEN pin is internally pulled-up to VDD.
A high-impedance pull-down on the -VSEN can be
configured by setting the PE1<PDEN> bit. When set,
the -VSEN pin is i nternally pulle d-down to ground.
6.13.5 OUTPUT UNDERVOLTAGE
ACCELERATOR
The MCP19118/19 has additional control circuitry to
allow it to respond quickly to an output undervoltage
condition. The enabling of this circuitry is handled by
the PE1<UVTEE> bit. When this bit is set, the
MCP19118/19 will respond to an output undervoltage
condition by setting both the HDRV and LDRV signals
low and turning off both the high-side and low-side
MOSFETs.
6.13.6 OUTPUT OVERVOLTAGE
ACCELERATOR
The MCP19118/19 has additional control circuitry to
allow it to respond quickly to an output overvoltage
condition. The enabling of this circuitry is handled by
the PE1<OVTEE> bit. When this bit is set, the
MCP19118/19 will respond to an output overvoltage
condition by setting both the HDRV and LDRV signals
low and turning off both the high-side and low-side
MOSFETs.
MCP19118/19
DS20005350A-page 50 2014 Microchip Technology Inc.
REGISTER 6-14: PE1: ANALOG PERIPHERAL ENABLE 1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DECON DVRSTR HDLYBY LDLYBY PDEN PUEN UVTEE OVTEE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 DECON: Diode Emulation Mode bit
1 = Diode Emulation mode enabled
0 = Synchronous Rectification mode enabled
bit 6 DVRSTR: High-Side Drive Strength Configuration bit
1 = High-side 1A source/sink drive strength
0 = High-side 2A source/sink drive strength
bit 5 HDLYBY: High-Side Dead Time Bypass bit
1 = High-side dead time bypass is enabled
0 = High-side dead time bypass is disabled
bit 4 LDLYBY: Low-Side Dead Time Bypass bit
1 = Low-side dead time bypass is enabled
0 = Low-side dead time bypass is disabled
bit 3 PDEN: -VSEN Weak Pull-Down Enable bit
1 = -VSEN weak pull-down is enabled
0 = -VSEN weak pull-down is disabled
bit 2 PUEN: +VSEN Weak Pull-Up Enable bit
1 = +VSEN weak pull-up is enabled
0 = +VSEN weak pull-up is disabled
bit 1 UVTEE: Output Undervoltage Accelerator Enable bit
1 = Output undervoltage accelerator is enabled
0 = Output undervoltage accelerator is disabled
bit 0 OVTEE: Output Overvoltage Accele rator Enable bit
1 = Output overvoltage accelerator is enabled
0 = Output overvoltage accelerator is disabled
2014 Microchip Technology Inc. DS20005350A-page 51
MCP19118/19
6.14 Analog Blocks Enable Control
Various analog circuit blocks can be enabled or
disabl ed, as sho w n in Register 6-15. Additional enable
bits are located in the ATSTCON register.
6.14.1 OUTPUT OVERVOLTAGE ENABLE
The output overvoltage is enabled by setting the
ABECON<OVDCEN> bit. Clearing this bit will disable
the outpu t overvolt age circuitry and cause the s etting in
the OOVCON register to be ignored.
6.14.2 OUTPUT UNDERVOLTAGE ENABLE
The output undervoltage is enabled by setting the
ABECON<UVDCEN> bit. Clearing this bit will disable
the output undervoltage circuitry and cause the setting
in the OUVCON register to be ignored.
6.14.3 RELATIVE EFFICIENCY
MEASUREMENT CONTROL
Section 10.0 “Relative Efficiency Measurement”
describes the procedure used to measure the relative
efficiency of the system. Setting the
ABECON<MEASEN> bit initiates the relative
measurement.
6.14.4 SLOPE COMPENSATION CONTROL
The slop e com pensa tion de scribe d in Register 6-7 ca n
be bypassed by setting the ABECON<SLCPBY> bit.
Under normal operation, this bit will always be set.
6.14.5 CURRENT MEASUREMENT
CONTROL
The peak current measurement circuitry is controlled
by the ABECON<CRTMEN> bit. Setting this bit
enables the current measurement circuitry. Under
normal ope rati on, thi s bit will be set .
6.14.6 INTERNAL TEMPERATURE
MEASUREMENT CONTROL
The internal temperature of the silicon can be
measured with the ADC. To enable the internal
temperature measurement circuitry, the
ABECON<TMPSEN> bit must be set.
6.14.7 RELATIVE EFFICIENCY CIRCUITY
CONTROL
Section 10.0 “Relative Efficiency Measurement”
describes the procedure used to measure the relative
efficiency of the system. Setting the
ABECON<RECIREN> bit enables the relative
efficiency meas urement circuitry.
6.14.8 SIGNAL CHAI N CONTROL
Setting the ABECON<PATHEN> bit enables the
volt age con trol p ath. Unde r normal operati on, this bit is
set.
MCP19118/19
DS20005350A-page 52 2014 Microchip Technology Inc.
REGISTER 6-15: ABECON: ANALOG BLOCK ENABLE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OVDCEN UVDCEN MEASEN SLCPBY CRTMEN TMPSEN RECIREN PATHEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OVDCEN: Output overvoltage DAC control bit
1 = Output overvoltage DAC is enabled
0 = Output overvoltage DAC is disabled
bit 6 UVDCEN: Output undervoltage DAC control bit
1 = Output undervoltage DAC is enabled
0 = Output undervoltage DAC is disabled
bit 5 MEASEN: Relative efficiency measurement control bit
1 = Initiate relative efficiency measurement
0 = Relative efficiency measurement not in progress
bit 4 SLCPBY: Slope compensation bypass control bit
1 = Slope compensation is disabled
0 = Slope compensation is enabled
bit 3 CRTMEN: Current measurement circuitry control bit
1 = Current measurement circuitry is enabled
0 = Current measurement circuitry is disabled
bit 2 TMPSEN: Internal temperature sensor control bit
1 = Internal temperature sensor circuitry is enabled
0 = Internal temperature sensor circuitry is disabled
bit 1 RECIREN: Relative efficiency circuitry control bit
1 = Relative efficiency measurement circuitry is enabled
0 = Relative efficiency measurement circuitry is disabled
bit 0 PATHEN: Signal chain circuitry control bit
1 = Signal chain circuitry is enabled
0 = Signal chain circuitry is disabled
2014 Microchip Technology Inc. DS20005350A-page 53
MCP19118/19
7.0 TYPICAL PE RFORMANCE CURVES
Note: Unless otherwise indicated, VIN = 12V, FSW = 300 kHz, TA = +25°C .
FIGURE 7-1: IQ vs. Temperature.
FIGURE 7-2: OVCCON DAC INL vs.
Code and Temperature (-40°C to +125°C).
FIGURE 7-3: OVCCON DAC DNL vs.
Code and Temperature (-40°C to +125°C).
FIGURE 7-4: OVFCON DAC INL vs.
Code and Temperature (-40°C to +125°C).
FIGURE 7-5: OVFCON DAC DNL vs.
Code and Temperature (-40°C to +125°C).
FIGURE 7-6: VDD vs. Input Voltage.
Note: The grap hs and t ab les p rov ided fol lowi ng this note are a s t a tis tic al summar y bas ed on a li mi ted nu mber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
4.8
5.0
5.2
5.4
5.6
c
ent Current (mA)
4.2
4.4
4.6
-40 -25 -10 5 20 35 50 65 80 95 110 125
Quies
c
Temperature (ºC)
-0.6
-0.4
-0.2
0.0
0.2
INL (LSB)
-1.2
-1.0
-0.8
0 64 128 192 256
CODE
0.015
0.020
0.025
0.030
DNL (LSB)
0.005
0.010
0 64 128 192 256
CODE
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
INL (LSB)
-1.0
-0.8
-0.6
-0.4
02468101214161820222426283032
CODE
0.0006
0.0008
0.0010
0.0012
0.0014
0.0016
DNL (LSB)
0.0000
0.0002
0.0004
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
CODE
5.06
5.07
5.08
5.09
VDD (V)
-40ºC
+125ºC
IDD = 1 mA
5.04
5.05
6 8 10 12 14 16 18 20 22 24 26 28 30 32
Input Voltage, VIN (V)
+25ºC
MCP19118/19
DS20005350A-page 54 2014 Microchip Technology Inc.
Note: Unless otherwise indicated, VIN = 12V, FSW = 300 kHz, TA = +25°C.
FIGURE 7-7: VDD vs. Output Current.
FIGURE 7-8: VREGREF vs. Temperature
(VREGREF = 0.6V).
FIGURE 7-9: VREGREF vs. Temperature
(VREGREF = 1.8V).
FIGURE 7-10: VREGREF vs. Temperature
(VREGREF = 3.3V).
FIGURE 7-11: HDRV Dead Time vs.
HDLY Code.
FIGURE 7-12: LDRV Dead Time vs.
LDLY Code.
5.02
5.03
5.04
5.05
5.06
5.07
VDD (V)
- 40ºC
+125ºC
+25ºC
4.99
5.00
5.01
024681012141618202224262830
Current (mA)
059
0.60
0.61
0.62
0.63
VREGREF (V)
OVCCON = 0x28h
0.57
0.58
0
.
59
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (ºC)
1.80
1.81
1.82
1.83
1.84
VREGREF (V)
OVCCON = 0x78h
1.77
1.78
1.79
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (ºC)
3.29
3.30
3.31
3.32
3.33
3.34
3.35
VREGREF (V)
OVCCON = 0xDCh
3.25
3.26
3.27
3.28
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (ºC)
40
50
60
70
80
D
RV Dead Time (ns)
-40ºC
125ºC
10
20
30
0 2 4 6 8 10 12 14 16
H
D
HDLY CODE
+
125ºC
+25ºC
30
40
50
60
70
R
V Dead Time (ns)
+125ºC
+25ºC
0
10
20
0246810121416
LD
R
LDLY CODE
-40ºC
2014 Microchip Technology Inc. DS20005350A-page 55
MCP19118/19
Note: Unless otherwise indicated, VIN = 12V, FSW = 300 kHz, TA = +25°C.
FIGURE 7-13: HDRV RDSon vs.
Temperature.
FIGURE 7-14: HDRV RDSon vs.
Temperature.
FIGURE 7-15: LDRV RDSon vs.
Temperature.
FIGURE 7-16: Oscillator Frequency vs.
Temperature.
FIGURE 7-17: CRNT Voltage vs. Output
Current.
FIGURE 7-18: Rem ote Sense Ampl ifi er
CMRR.
0.8
0.9
1.0
1.1
1.2
1.3
1.4
R
V Resistance ()
DRVSTR = 0
RHDRV-SOURCE
0.4
0.5
0.6
0.7
-40-25-10 5 203550658095110125
HD
R
Temperature (ºC)
RHDRV-SINK
1.5
2.0
2.5
3.0
R
V Resistance ()
DRVSTR = 1
RHDRV-SOURCE
0.5
1.0
-40-25-10 5 203550658095110125
HD
R
Temperature (ºC)
RHDRV-SINK
0.8
1.0
1.2
1.4
1.6
R
V Resistance ()
RLDRV-SOURCE
0.2
0.4
0.6
-40-25-10 5 203550658095110125
LD
R
Temperature (ºC)
RLDRV-SINK
7.99
8.00
8.01
8.02
8.03
8.04
8.05
t
or Frequency (MHz)
7.95
7.96
7.97
7.98
-40-25-105 203550658095110125
Oscilla
t
Temperature (ºC)
1.57
1.58
1.59
1.60
1.61
1.62
1.63
1.64
R
NT Voltage (V)
RIND = 3.0 m
1.53
1.54
1.55
1.56
0 5 10 15 20 25 30
C
R
Output Current (A)
8%
10%
12%
14%
16%
18%
20%
22%
24%
n
tage of Occurences
0%
2%
4%
6%
8%
30 38 47 56 64 73 81 90 100
Perce
n
CMRR (dB)
MCP19118/19
DS20005350A-page 56 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 57
MCP19118/19
8.0 SYSTEM BENCH TESTING
To allow for easier system design and bench testing,
the MCP19118/19 family of devices features a
multiplexer used to output various internal analog
signals. These signals can be measured on the GPA0
pin through a unity gain buffer. The configuration
control of the GPA0 pin is found in the ATSTCON
register.
Control of the signals present at the output of the unity
gain buffer is found in the BUFFCON regist er.
8.1 Analog Bench Test Control
8.1.1 ATSTCON REGISTER
The ATSTCON register contains the bits used to
disable the MOSFET drivers and configure the GPA0
pin as the unity gain buffer out.
Note 1: The DRVDIS bit is reset to ‘1’ so the
high-side and low-side drivers are in a
known state after reset. This bit must be
cleared by software for normal operation.
2: For proper operation, bit 7 must always
be set to ‘1’.
REGISTER 8-1: ATSTCON: ANALOG BENCH TEST CONTROL REGISTER
R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1
Reserved — — Reserved HIDIS LODIS BNCHEN DRVDIS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Reserved: Bit 7 must always be set to ‘1’.
bit 6-5 Unimplemented: Re ad as ‘0’
bit 4 Reserved
bit 3 HIDIS: High-side driver control bit
1 = High-side driver is disabled
0 = High-side driver is enabled
bit 2 LODIS: Low-side driver control bit
1 = Low-side driver is disabled
0 = Low-side driver is enabled
bit 1 BNCHEN: GPA0 bench test configuration control bit
1 = GPA0 is configured for analog bench test output
0 = GPA0 is configured for normal operation
bit 0 DRVDIS: MOSFET driver disable control bit
1 = High-side and low-side drivers are set low, PHASE pin is floating
0 = High-side and low-side drivers are set for normal operation
MCP19118/19
DS20005350A-page 58 2014 Microchip Technology Inc.
8.2 Unity Gain Buffer
The unity gain buffer module is used during a
multi-phase application and while operating in Bench
Test mode.
When the ATSTCON<BNCHEN> bit is set, the de vice
is in Bench Test mode and the ASEL<4:0> bits in the
BUFFCON register determine which internal analog
signal can be measured on the GPA0 pin.
When measuring signals with the unity gain buffer, the
buffer offset must be added to the measured signal.
The factory-measured buffer offset can be read from
memory location 2087h. Refer to Section 11.1.1
“Reading Program Memory as Data” for more
information.
REGISTER 8-2: BUFFCON: UNITY GAIN BUFFER CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MLTPH2 MLTPH1 MLTPH0 ASEL4 ASEL3 ASEL2 ASEL1 ASEL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 MLTPH<2:0>: System conf igu ration bits
000 = Device set as stand-alone unit
001 = Device set as multiple output MASTER
010 = Device set as multiple output SLAVE
011 = Device set as multi-phase MASTER
100 = Device set as multi-phase SLAVE
bit 4-0 ASEL<4:0>: Multiplexer output control bit
00000 = Voltage proportional to current in the inductor
00001 = Error ampl ifier output plus slope compen sation, input to PWM comparator
00010 = Input to slope compensation circuitry
00011 = Band gap reference
00100 = Output voltage reference
00101 = Output voltage after internal differential amplifier
00110 = Unimplemented
00111 = Voltage proportional to the internal temperature
01000 = Internal ground for current sense circuitry, see Section 6.5 “Voltage for Zero Current”
01001 = Output overvoltage comparator reference
01010 = Output undervoltage comparator reference
01011 = Error amplifier output
01100 = For a multi-phase SLAVE, error amplifier signal received from MASTER
01101 = For multi-phase SLAVE, error signal received from MASTER with gain,
see Section 6.8 “MASTER Error Signal Gain”
01110 = VIN divided down by 1/13
01111 = DC inducto r vall ey current
10000 = Unimplemented
•
•
•
11100 = Unimplemented
11101 = Overcurrent reference
11110 = Unimplemented
11111 = Unimplemented
2014 Microchip Technology Inc. DS20005350A-page 59
MCP19118/19
9.0 DEVICE CALIBRATION
Read-only memory locations 2080h through 208Fh
contain factory calibration data. Refer to Section 18.0
“Flash Program Memory Control” for information on
how to read from these memory locations.
9.1 Calibration Word 1
The DOV<3:0> bits at memory location 2080h set the
offset calibration for the output voltage remote sense
differential amplifier. Firmware must read these values
and write them to the DOVCAL register for proper
calibration.
The FCAL<6:0> bits at memory location 2080h set the
internal oscillator calibration. Firmware must read
these values and write them to the OSCCAL register
for proper calibration.
REGISTER 9-1: CALWD1: CALIBRATION WORD 1 REGISTER
U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
——DOV<3:0>
bit 13 bit 8
U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— FCAL<6:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 DOV<3:0>: Output voltage remote sense differential amplifier offset calibration bits
bit 7 Unimplemented: Read as ‘0’
bit 6-0 FCAL<6:0>: Internal oscillator calibration bits
MCP19118/19
DS20005350A-page 60 2014 Microchip Technology Inc.
9.2 Calibration Word 2
The VRO<3: 0> bits at m emory location 2081h c alibrate
the offset of the buffer amplifier of the output voltage
regulation reference set point. This effectively changes
the band gap reference. Firmware must read these
values and write them to the VROCAL register for
proper calibration.
The BGR<3: 0> bits at m emory location 2081h c alibrate
the internal band gap. Firmware must read these
values and write them to the BGRCAL register for
proper calibration.
REGISTER 9-2: CALWD2: CALIBRATION WORD 2 REGISTER
U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
——VRO<3:0>
bit 13 bit 8
U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
— — — —BGR<3:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 VRO<3:0>: Reference voltage offset calibration bits
bit 7-4 Unimplemented: Re ad as ‘0’
bit 3-0 BGR<3:0>: Internal band gap calibration bits
2014 Microchip Technology Inc. DS20005350A-page 61
MCP19118/19
9.3 Calibration Word 3
The TTA<3:0> bits at memory location 2082h calibrate
the overtemperature shutdown threshold point.
Firmware must read these values and write them to the
TTACAL register for proper calibration.
The ZR O<3:0> b its at memo ry locat ion 2082h calibra te
the offset of the error amplifier. Firmware must read
these values and write them to the ZROCAL re gister for
proper calibration.
REGISTER 9-3: CALWD3: CALIBRATION WORD 3 REGISTER
U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
——TTA<3:0>
bit 13 bit 8
U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
— — — —ZRO<3:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 TTA<3:0>: Overtemperature shutdown threshold calibration bits
bit 7-4 Unimplemented: Re ad as ‘0’
bit 3-0 ZRO<3:0>: Error amplifier offset voltage calibration bits
MCP19118/19
DS20005350A-page 62 2014 Microchip Technology Inc.
9.4 Calibration Word 4
and Calibration Word 5
The da ta st ored in the CAL WD4 and CALWD5 registe rs
can be used by firmware to provide a more accurate
internal temperature sensor ADC reading. The
coefficients for a straight line equation can be
generate d by manipulation of the values stored i n these
calibration words. These calibration words contain all
gains and offsets associated with reading the input
voltage with the internal ADC.
9.4.1 CALWD4: INTERNAL
TEMPERATURE READING GAIN
TERM
The CALWD4 register is located at program memory
location 2083h and represents the coefficient, Z, used
in Equation 9-1. This coefficient is used to calculate the
gain of the internal temperature reading by the ADC.
EQUATION 9-1: CALCULATING GAIN
9.4.2 CALWD5: I NTERNA L
TEMPERATURE READING OFFSET
VOLTAGE TERM
The CALWD5 register is located at program memory
location 2084h and represents the coefficient, W, used
in Equation 9-2. This coef ficient is used to calcul ate the
offs et voltage of the internal temperature re ading by the
ADC.
EQUATION 9-2: CALCULATING OFFSET
VOLTAGE
mZ2
N
=
Where:
m = gain
Z = 14-bit integer
N=12
bW2N
=
Where:
b = offset voltage
W = 14-bit two’s complement integer
N=4
REGISTER 9-4: CALWD4: CALIBRATION WORD 4 REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
TANAM<13:8>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
TANAM<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-0 TANAM<13:0>: Coefficient used to find the gain when reading the internal temperature with the ADC
REGISTER 9-5: CALWD5: CALIBRATION WORD 5 REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
TANAI<13:8>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
TANAI<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-0 TANAI<13:0>: Coefficient used to find the offset voltage when reading the internal temperature with the ADC
2014 Microchip Technology Inc. DS20005350A-page 63
MCP19118/19
9.5 Calibration Word 6
and Calibration Word 7
The MCP191 18/19 has the ability to read and report the
system input voltage. Firmware can be written that
uses the data stored in the CALWD6 and CALWD7
registers to improve the accuracy of this voltage
reading. These calibration words contain the gain and
of fset volt age asso ciated with read ing the input vol tag e
with ADC.
9.5.1 CALWD6: INPUT VOLTAGE
READING GAIN TERM
The data stored in the CALWD6 register at program
memory location 2085h is an 8-bit number that
represents the coefficient, Z, used in Equation 9-3. This
coefficient is used to calculate the gain of the input
voltage ADC reading circuitry.
EQUATION 9-3: CALCULATING INPUT
VOLTAGE READING GAIN
9.5.2 CALWD7: INPUT VOLTAGE
READ ING OFFSE T VOLTAGE
The data stored in the CALWD7 register at program
memory location 2086h is an 8-bit two’s complement
integer that represents the offset voltage of the input
voltage reading circuitry.
m1
Z
---2
N
=
Where:
m=gain
Z = 8-bit integer
N=11
REGISTER 9-6: CALWD6: CALIBRATION WORD 6 REGISTER
U-0 U-0 U-0 U-0 U-0 U-0
— — — — — —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
GIVAN<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-8 Unimplemented: Read as ‘0’
bit 7-0 GIVAN<7:0>: Reading input voltage gain term
REGISTER 9-7: CALWD7: CALIBRATION WORD 7 REGISTER
U-0 U-0 U-0 U-0 U-0 U-0
— — — — — —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
VOIVAN<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-8 Unimplemented: Read as ‘0’
bit 7-0 VOIVAN<7:0>: Reading input voltage offset voltage term
MCP19118/19
DS20005350A-page 64 2014 Microchip Technology Inc.
9.6 Calibration Word 8
The BUFF<7:0> bits at memory location 2087h
represent the offset voltage of the unity gain buffer in
millivolts. This is an 8-bit two’s complement number.
The MSB is the sign bit. If the MSB is set to 1, the
resulting number is negative.
REGISTER 9-8: CALWD8: CALIBRATION WORD 8 REGISTER
U-0 U-0 U-0 U-0 U-0 U-0
— — — — — —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
BUFF<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-8 Unimplemented: Read as ‘0’
bit 7-0 BUFF<7:0>: U n ity gain buffer of f se t volt age calib rati on bit s
2014 Microchip Technology Inc. DS20005350A-page 65
MCP19118/19
9.7 Calibration Word 9
and Calibration Word 10
The information stored in the CALWD9 and CALWD10
registers can be use d by f irmwa re to remo ve the offset
and gain of the output differential amplifier. The
coefficients for a straight line equation can be
generated by using the values stored in these
calibration words.
9.7.1 CALWD9: DIFFERENTIAL
AMPLIFIER GA IN TERM
The data stored in the CALWD9 register at program
memory location 2088h represents the coefficient, Z,
used in Equation 9-4. This coefficient is used to
calc ulate the gain of t he differential ampl ifier.
EQUATION 9-4: CALCULATING GAIN
9.7.2 CALWD10: DIFFERENTIAL
AMPLIFIER OFFSET VOLTAGE
TERM
The data stored in the CALWD10 register at program
memory location 2089h represents the coefficient, V,
used in Equation 9-5. This coefficient is used to
calculate the offset voltage of the differential amplifier.
EQUATION 9-5: CALCULATING
OFFSET VOLTAGE
GZ2N
=
Where:
G = differential amplifier gain
Z = 14 -bit integer
N=-12
VOS V 2N
=
Where:
VOS = differential amplifier offset
V = 14-bit integer
N=-12
REGISTER 9-9: CALWD9: CALIBRATION WORD 9 REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DAGN<13:8>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DAGN<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-0 DAGN<13:0>: Differential amplifier gain calibration bits
REGISTER 9-10: CALWD10: CALIBRATION WORD 10 REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DAI<13:8>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DAI<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-0 DAI<13:0>: Differential amplifier offset voltage calibration bits
MCP19118/19
DS20005350A-page 66 2014 Microchip Technology Inc.
9.8 Calibration Word 11
and Calibration Word 12
The information stored in the CAL WD1 1 and CAL WD12
registers can be use d by f irmwa re to remo ve the offset
and gain of ADC measurements.
9.8.1 CALWD11: ADC GAIN TERM
The data stored in the CALWD11 register at program
memory location 208Ah represents the gain of the ADC.
9.8.2 CALWD12: ADC OFFSET VOLTAGE
TERM
The data stored in the CALWD12 register at program
memory location 20 8Bh is a two’ s comple ment numb er
that is used by Equation 9-6 to calculate the offset
voltage of the ADC.
EQUATION 9-6: CALCULATING
ADC OFFSET VOLTAGE
bW2N
=
Where:
b = ADC offset
W = Two’s complement 14-b it int eger
N=6
REGISTER 9-11: CALWD11: CALIBRATION WORD 11 REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
GADC<13:8>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
GADC<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-0 GADC<13:0>: ADC gain term
REGISTER 9-12: CALWD12: CALIBRATION WORD 12 REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
VOADC<13:8>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
VOADC<7:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-0 VOADC<13:0>: Tw o’s complement ADC offset voltage term
2014 Microchip Technology Inc. DS20005350A-page 67
MCP19118/19
10.0 RELATIVE EFFICIENCY
MEASUREMENT
With a constant input voltage, output voltage and load
current, any change in the high-side MOSFET on time
represents a change in the system efficiency. The
MCP19118/19 is capable of measuring the on time of
the high-side MOSFET. Therefore, the relative
efficiency of the system can be measured and
optimized by changing the system parameters, such as
switching frequency , driver dead time or high-side drive
strength.
10.1 Relative Eff ici ency Me asurement
Procedure
To measure the relative efficiency, the RELEFF
register, the ABECON<MEASEN> and
ABECON<RECIREN> bit s and the ADC RELEFF input
are used. The follo wing steps o utline the m easurement
process:
1. Set the ABECON<RECIREN> bit to enable the
measur eme nt circuitry.
2. Clear the ABECON<MEASEN> bit.
3. With the ADC, read the RELEFF channel and
store this reading as the High.
4. With the ADC, read the VZC channel and store
this reading as th e Low.
5. Set the ABECON<MEASEN> bit to initiate a
measurement cy cl e.
6. Monitor the RELEFF <MSDONE> bit. Whe n se t,
it indicates the measurement is complete.
7. When the measurement is complete, use the ADC
to read the RELEFF channel. This value becomes
the Fractional variable in Equation 10-1. This
reading should be accomplished approximately
50 ms after the RELESS<MSDONE> bit is set.
8. Read the value of the RE<6:0> bits in the
RELEFF register and store the reading as
Whole.
9. Clear the ABECON<MEASEN> bit.
10. The relative efficiency is then calculated by the
following equation:
EQUATION 10-1:
Note 1: The RELEFF<MSDONE> bit is set and
cleared automatically.
Whole Fractional Low–
High Low–
--------------------------------------------------+
PR2 1+
--------------------------------------------------------------------------------
Where:
Whole = Value obtained in Step 8 of the
measurement procedure
Fractional = Value obtained in Step 7 of the
measurement procedure
High = Value obtained in Step 3 of the
measurement procedure
Low = Value obtained in Step 4 of the
measurement procedure
Duty Cycle =
REGISTER 10-1: RELEFF: RELATIVE EFFICIENCY MEASUREMENT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MSDONE RE6 RE5 RE4 RE3 RE2 RE1 RE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MSDONE: Relative efficiency measurement done bit
1 = Relative efficiency measurement is complete
0 = Relative efficiency measurement is not complete
bit 6-0 RE<6:0>: Whole clock counts for relative efficiency measurement result
MCP19118/19
DS20005350A-page 68 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 69
MCP19118/19
11.0 MEMORY ORGANIZATION
There are two types of memory in the MCP19118/19:
• Program Memory
• Data Memory
- Special Function Registers (SFRs)
- General Purpose RAM
11.1 Program Memory Organization
The MCP19118/19 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. Only the first 4K x 14 (0000h-0FFFh) is
physically implemented. Addressing a location above
this boundary will cause a wrap-around within the first
4K x 14 space. The Reset vector is at 0000h and the
interrupt vector is at 0004h (see Figure 11-1). The width
of the program memory bus (instruction word) is
14 bits. Since all instructions are a single word, the
MCP19118/19 has space for 4K of instr uctions.
FIGURE 1 1-1: PROGRAM MEMORY MAP
AND STACK FOR
MCP19118/19
Unimplemented
PC<12:0>
13
0000h
0004h
0005h
0FFFh
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-C hip Progra m
Memory
CALL, RETURN
RETFIE, RETLW
1000h
User IDs(1)
Device ID (hardcoded)(1)
Config Word(1)
2000h
2005h
2006h
2007h
200Ah
207Fh
20FFh
2003h
2004h
ICD Instruction(1)
Manufacturing Codes(1)
Note 1: Not code protected.
Shadows 000 -FFFh
2008h
Reserved for
Manufacturing & Test(1)
2080h
Calibration Words(1)
200Bh
208Fh
2090h
Shadows 2000-20FFh
2100h
3FFFh
Reserved
MCP19118/19
DS20005350A-page 70 2014 Microchip Technology Inc.
11.1.1 READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set a
Files Select Register (FSR) to point to the program
memory.
11.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of c onstants. The rec ommended way t o create
such a table is shown in Example 11-1.
EXAMPL E 11-1: RETLW INSTRUCTION
11.2 Data Memory Organization
The data memory (see Table 11-1) is partitioned into
four banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank. Register locations
20h-7Fh in Bank 0, A0h-EFh in Bank 1 and 120h-16 Fh
in Bank 2 are General Purpose Registers,
implemented as static RAM. All other RAM is
unimplemented and returns ‘0’ when read. The
RP<1:0> bits in the STATUS register are the bank
select bits.
To move values f rom one regi ster to anoth er, the valu e
must pass through the W register. This means that, for
all register-to-register moves, two instruction cycles are
required.
The STATUS register contains:
• the arithmetic status of the ALU (Arithmet ic Logic
Unit)
• the Reset status
• the bank select bits for data memory (RAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or c leared accordi ng to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
Therefore, it is recommended that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, see Section 29.0
“Instruction Set Summary”.
constants
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
RP1 RP0
00-> B ank 0 is selected
01-> B ank 1 is selected
10-> B ank 2 is selected
11 -> Bank 3 is selected
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
2014 Microchip Technology Inc. DS20005350A-page 71
MCP19118/19
11.2.1 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operatio n of the de vice (see Table 11-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the microcontroller core are described
in this section. Those related to the operation of the
peripheral features are described in the associated
section for that peripheral feature.
REGISTER 11 -1: STATUS : STATUS REGIS TER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDC
(1)C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for Indirect addressing)
1 = Bank 2 & 3 (100h–1FFh)
0 = Bank 0 & 1 (00h–FFh )
bit 6-5 RP<1:0>: Register Bank Select bits (used for Direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Dig it Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF inst ructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rot ate (RRF, RLF) instru ctions, t his bit is loaded w ith either the high -order or low-o rder
bit of the source register.
MCP19118/19
DS20005350A-page 72 2014 Microchip Technology Inc.
11.3 DATA MEMORY
TABLE 11-1: MCP19118/19 DATA MEMORY MAP
File
Address File
Address File
Address File
Address
Indirect addr.(1)00h Indirect addr. (1)80h Indirect addr.(1)100h Indirect addr. (1)180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTGPA 05h TRISGPA 85h WPUGPA 105h IOCA 185h
PORTGPB 06h TRISGPB 86h WPUGPB 106h IOCB 186h
PIR1 07h PIE1 87h PE1 107h ANSELA 187h
PIR2 08h PIE2 88h BUFFCON 108h ANSELB 188h
PCON 09h APFCON 89h ABECON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
TMR1L 0Ch 8Ch 10Ch PORTICD(2)18Ch
TMR1H 0Dh 8Dh 10Dh TRISICD(2)18Dh
T1CON 0Eh 8Eh 10Eh ICKBUG(2)18Eh
TMR2 0Fh 8Fh 10Fh BIGBUG(2)18Fh
T2CON 10h VINLVL 90h SSPADD 110h PMCON1 190h
PR2 11h OCCON 91h SSPBUF 111h PMCON2 191h
12h 92h SSPCON1 112h PMADRL 192h
PWMPHL 13h CSGSCON 93h SSPCON2 113h PMADRH 193h
PWMPHH 14h 94h SSPCON3 114h PMDATL 194h
PWMRL 15h CSDGCON 95h SSPMSK 115h PMDATH 195h
PWMRH 16h 96h SSPSTAT 116h 196h
17h VZCCON 97h SSPADD2 117h 197h
18h CMPZCON 98h SSPMSK2 118h OSCCAL 198h
OVCCON 19h OUVCON 99h 119h DOVCAL 199h
OVFCON 1Ah OOVCON 9Ah 11Ah TTACAL 19Ah
OSCTUNE 1Bh DEADCON 9Bh 11Bh BGRCAL 19Bh
ADRESL 1Ch SLPCRCON 9Ch 11Ch VROCAL 19Ch
ADRESH 1Dh SLVGNCON 9Dh 11Dh ZROCAL 19Dh
ADCON0 1Eh RELEFF 9Eh 11Eh 19Eh
ADCON1 1Fh 9Fh 11Fh ATSTCON 19Fh
General
Purpose
Register
96 Bytes
20h General
Purpose
Register
80 Bytes
A0h General
Purpose
Register
80 bytes
120h 1A0h
EFh 16F 1EF
7Fh
Accesses
Bank 0 F0h
FFh
Accesses
Bank 0 170h
17Fh
Accesses
Bank 0 1F0h
1FFh
Bank 0 Bank 1 Bank2 Bank3
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2: Only accessible when DBGEN = 0 and ICKBUG<INBUG> = 1.
2014 Microchip Technology Inc. DS20005350A-page 73
MCP19118/19
TABLE 11-2: MCP191 18/19 SPECIAL REGISTERS SUMMARY BANK 0
Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
Value on
all ot her
resets(1)
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
02h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000
03h STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTGPA GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 xxxx xxxx uuuu uuuu
06h PORTGPB GPB7 GPB6 GPB5 GPB4 — GPB2 GPB1 GPB0 xxx- xxxx uuu- uuuu
07h PIR1 — ADIF BCLIF SSPIF ——TMR2IFTMR1IF-000 --00 -000 --00
08h PIR2 UVIF —OCIFOVIF—— VINIF —0-00 --00 0-00 --00
09h PCON —————OTPOR —---- -qq- ---- -uu-
0Ah PCLATH ——— Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF(3)0000 000x 0000 000u
0Ch TMR1L Holding register for the Least Significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
0Dh TMR1H Holding register for the Most Significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
0Eh T1CON —— T1CKPS1 T1CKPS0 —— TMR1CS TMR1ON --00 --00 --uu --uu
0Fh
TMR2 T imer2 Module Register 0000 0000 uuuu uuuu
10h
T2CON ————— TMR2ON T2CKPS1 T2CKPS0 ---- -000 ---- -000
11h PR2 Timer2 Module Period Register 1111 1111 1111 1111
12h —Unimplemented ——
13h PWMPHL SLAVE Phase Shift Register xxxx xxxx uuuu uuuu
14h PWMPHH SLAVE Phase Shift Register xxxx xxxx uuuu uuuu
15h PWMRL PWM Register Low Byte xxxx xxxx uuuu uuuu
16h PWMRH PWM Register High Byte xxxx xxxx uuuu uuuu
17h —Unimplemented — —
18h —Unimplemented — —
19h OVCCON OVC7 OVC6 OVC5 OVC4 OVC3 OVC2 OVC1 OVC0 0000 0000 0000 0000
1Ah OVFCON VOUTEN —— OVF4 OVF3 OVF2 OVF1 OVF0 0--0 0000 0--0 0000
1Bh OSCTUNE ——— TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---0 0000
1Ch ADRESL Least significant 8 bits of the right-shifted result xxxx xxxx uuuu uuuu
1Dh ADRESH Most significant 2 bits of right-shifted result ---- --xx uuuu uuuu
1Eh ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000 -000 0000
1Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets includ e M C LR Reset and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the
mismatch exists.
MCP19118/19
DS20005350A-page 74 2014 Microchip Technology Inc.
TABLE 11-3: MCP19118/19 SPECIAL REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
Values on
all other
resets(1)
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000
83h STATUS IRP(2)RP1(2)RP0 TO PD ZDCC
0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
86h TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h PIE1 — ADIE BCLIE SSPIE —— TMR2IE TMR1IE -000 --00 -000 --00
88h PIE2 UVIE —OCIEOVIE——VINIE—0-00 --00 0-00 --00
89h APFCON — — — — — — — CLKSEL ---- ---0 ---- ---0
8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF(4)0000 000x 0000 000u
8Ch —Unimplemented — —
8Dh —Unimplemented — —
8Eh —Unimplemented — —
8Fh —Unimplemented — —
90h VINLVL UVLOEN — UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0 0-xx xxxx 0-uu uuuu
91h OCCON OCEN OCLEB1 OCLEB0 OOC4 OOC3 OOC2 OOC1 OOC0 0xxx xxxx 0uuu uuuu
92h — —— Reserved Reserved Reserved Reserved Reserved Reserved --xx xxxx --uu uuuu
93h CSGSCON — Reserved Reserved Reserved CSGS3 CSGS2 CSGS1 CSGS0 -xxx xxxx -uuu uuuu
94h — Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved xxxx xxxx uuuu uuuu
95h CSDGCON CSDGEN — — — Reserved CSDG2 CSDG1 CSDG0 0--- xxxx 0--- uuuu
96h — — — — — Reserved Reserved Reserved Reserved ---- xxxx ---- uuuu
97h VZCCON VZC7 VZC6 VZC5 VZC4 VZC3 VZC2 VZC1 VZC0 xxxx xxxx uuuu uuuu
98h CMPZCON CMPZF3 CMPZF2 CMPZF1 CMPZF0 CMPZG3 CMPZG2 CMPZG1 CMPZG0 xxxx xxxx uuuu uuuu
99h OUVCON OUV7 OUV6 OUV5 OUV4 OUV3 OUV2 OUV1 OUV0 xxxx xxxx uuuu uuuu
9Ah OOVCON OOV7 OOV6 OOV5 OOV4 OOV3 OOV2 OOV1 OOV0 xxxx xxxx uuuu uuuu
9Bh DEADCON HDLY3 HDLY2 HDLY1 HDLY0 LDLY3 LDLY2 LDLY1 LDLY0 xxxx xxxx uuuu uuuu
9Ch SLPCRCON SLPG3 SLPG2 SLPG1 SLPG0 SLPS3 SLPS2 SLPS1 SLPS0 xxxx xxxx uuuu uuuu
9Dh SLVGNCON — — — SLVGN4 SLVGN3 SLVGN2 SLVGN1 SLVGN0 ---x xxxx ---u uuuu
9Eh RELEFF MSDONE RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000
9Fh —Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: RA3 pull-up is enabled when pin is con figured as MCLR in Configuration Word.
4: MCLR and WDT Reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the
mismatch exists.
2014 Microchip Technology Inc. DS20005350A-page 75
MCP19118/19
TABLE 11-4: MCP191 18/19 SPECIAL REGISTERS SUMMARY BANK 2
Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
Value on
all other
resets(1)
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
102h PCL Program Counter's (PC) Least Significant byte 0000 000 0 0000 0000
103h STATUS IRP(2)RP1(2)RP0 TO PD ZDCC
0001 1xxx 000q quuu
104h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h WPUGPA — — WPUA5 — WPUA3 WPUA2 WPUA1 WPUA0 --1- 1111 --u- uuuu
106h WPUGPB WPUB7 WPUB6 WPUB5 WPUB4 — WPUB2 WPUB1 —1111 -11- uuuu -uu-
107h PE1 DECON DVRSTR HDLYBY LDLYBY PDEN PUEN UVTEE OVTEE 0000 1100 0000 1100
108h BUFFCON MLTPH2 MLTPH1 MLTPH0 ASEL4 ASEL3 ASEL2 ASEL1 ASEL0 0000 0000 0000 0000
109h ABECON OVDCEN UVDCEN MEASEN SLCPBY CRTMEN TMPSEN RECIREN PATHEN 0000 0000 0000 0000
10Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
10Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF(3)0000 000 x 0000 000u
10Ch —Unimplemented — —
10Dh —Unimplemented — —
10Eh —Unimplemented — —
10Fh
—Unimplemented — —
110h
SSPADD ADD<7:0> 0000 0000 0000 0000
111h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Regis ter xxxx xxxx uuuu uuuu
112h SSPCON1 WCOL SSPOV SSPEN CKP SSPM>3:0> 0000 0000 0000 0000
113h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 000 0 0000 0000
114h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
115h SSPMSK MSK<7:0> 1111 1111 1111 1111
116h SSPSTAT SMP CKE D/A PSR/WUA BF — —
117h SSPADD2 ADD2<7:0> 0000 0000 0000 0000
118h SSPMSK2 MSK2<7:0> 1111 1111 1111 1111
119h —Unimplemented — —
11Ah —Unimplemented — —
11Bh —Unimplemented — —
11Ch —Unimplemented — —
11Dh —Unimplemented — —
11Eh —Unimplemented — —
11Fh —Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets includ e M C LR Reset and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the
mismatch exists.
MCP19118/19
DS20005350A-page 76 2014 Microchip Technology Inc.
TABLE 11-5: MCP19118/19 SPECIAL REGISTERS SUMMARY BANK 3
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
Values on
all other
resets(1)
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
181h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000
183h STATUS IRP(2)RP1(2)RP0 TO PD ZDCC
0001 1xxx 000q quuu
184h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h IOCA IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 0000 0000 0000 0000
186h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — IOCB2 IOCB1 IOCB0 0000 -000 0000 -000
187h ANSELA — — — — ANSA3 ANSA2 ANSA1 ANSA0 ---- 1111 ---- 1111
188h ANSELB —— ANSB5 ANSB4 — ANSB2 ANSB1 —--11 -11- --11 -11-
189h —Unimplemented — —
18Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
18Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF(4)0000 000x 0000 000u
18Ch PORTICD(5)In-Circuit Debug Port Register
18Dh TRISICD(5)In-Circuit Debug TRIS Register
18Eh ICKBUG(5)In-Circuit Debug Register 0--- ---- 0--- ----
18Fh BIGBUG(5)In-Circuit Debug Breakpoint Register ---- ---- ---- ----
190h PMCON1 —CALSEL — — —WRENWR RD-0-- -000 -0-- -000
191h PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----
192h PMADRL PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 0000 0000
193h PMADRH — — — — PMADRH3 PMADRH2 PMADRH1 PMADRH0 ---- 0000 ---- 0000
194h PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 0000 0000
195h PMDATH — — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0 --00 0000 --00 0000
196h —Unimplemented — —
197h —Unimplemented — —
198h OSCCAL — FCALT6 FCALT5 FCALT4 FCALT3 FCALT2 FCALT1 FCALT0 xxxx xxxx uuuu uuuu
199h DOVCAL — — — — DOVT3 DOVT2 DOVT1 DOVT0 xxxx xxxx uuuu uuuu
19Ah TTACAL — — — — TTA3 TTA2 TTA1 TTA0 xxxx xxxx uuuu uuuu
19Bh BGRCAL Reserved Reserved Reserved Reserved BGRT3 BGRT2 BGRT1 BGRT0 xxxx xxxx uuuu uuuu
19Ch VROCAL — — — — VROT3 VROT2 VROT1 VROT0 xxxx xxxx uuuu uuuu
19Dh ZROCAL — — — — ZROT3 ZROT2 ZROT1 ZROT0 xxxx xxxx uuuu uuuu
19Eh —Unimplemented — —
19Fh ATSTCON Reserved —— Reserved HIDIS LODIS BNCHEN DRVDIS 1--0 0001 1--0 0001
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: RA3 pull-up is enabled when pin is con figured as MCLR in Configuration Word.
4: MCLR and WDT Reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will set again if the mis-
match exists.
5: Only accessible when DBGEN = 0 and ICKBUG<INBUG> = 1.
2014 Microchip Technology Inc. DS20005350A-page 77
MCP19118/19
11.3.1 OPTION_REG REGIST ER
The OPTION_REG register is a readable and writable
register, which contains various control bits to
configure:
• Timer0/WDT prescaler
• Extern al GPA2/INT interrupt
•Timer0
• Weak pull-ups on PORTGPA and PORTGPB
Note 1: To achieve a 1:1 prescaler assignment
for Timer0, assign the prescaler to the
WDT by setting PSA bit in the
OPTION_REG register to ‘1’. See
Section 23.1.3
“Software-Programmable Prescaler”.
REGISTER 11-2: OPTION_REG: OPTION REGISTER (Note 1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RAPU: Port GPx Pull-Up Enable bit
1 = Port GPx pull-ups are disabled
0 = Port GPx pull-ups are enabled
bit 6 INTEDG: Interrupt Edge Select bit
0 = Interrupt on rising edge of INT pin
1 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transit ion on T0CKI pin
0 = Internal instruction cycle clo ck
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Ass ig nme nt bit
1 = Prescaler is assigned to WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: Individual WPUx bit must also be enabled.
Bit Value TMR0
Rate WDT Rate
000 1: 2 1: 1
001 1: 4 1: 2
010 1: 8 1: 4
011 1: 16 1: 8
100 1: 32 1: 16
101 1: 64 1: 32
110 1: 128 1: 64
111 1: 256 1: 128
MCP19118/19
DS20005350A-page 78 2014 Microchip Technology Inc.
11.4 PCL and PCLATH
The Program Counter (PC) is 13-bit wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 11-2 shows the two
situations for loading the PC. The upper example in
Figure 11-2 shows how the PC is loaded on a write to PCL
(PCLATH<4:0> PCH). The lower example in
Figure 11-2 shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3> PCH).
FIGURE 11-2: LOADING OF PC IN
DIFFERENT SITUATIONS
11.4.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
content s of th e PCLATH register. This allo ws the enti re
content of the program counter to be changed by
writing the desired upper five bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 13 bits of the program counter will
change to the values conta ined in the PCLATH register
and those being written to the PCL register.
11.4.2 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by addi ng an of fs et
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instru ction s or if the low er eight bit s of the memo ry
address rolls over from 0xFFh to 0X00h in the middle
of the table, then PCLATH must be incremented for
each address rollover that occurs between the table
beginning and the table location within the table.
For more information, refer to Application Note AN556
– “Implementing a Table Read” (DS00556).
11.4.3 COMPUTED FUNCTION CALLS
A computed function CALL allows programs to maintain
tables of functions and provides another way to
execute state machines or look-up tables. When
performing a table read using a computed function
CALL, care should be exercised if the table location
crosses a PCL memory boundary (each 256-byte
block).
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
ins truct ion. PCH<6:3> is load ed wi th PCLATH<6:3> .
11.4.4 STACK
The MCP19118/19 has an 8-level x 13-bit wide
hardware stack (refer to Figure 11-1). The stack space
is not part of either program or data space and the
Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is
executed or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The st ack operates as a circular buf fer . This means th at
af ter the st ack ha s be en PUSHed ei ght time s, th e nin th
push ov erwrite s the va lue tha t was store d fro m the first
push. The tenth p us h ov erwrites the se co nd p us h (an d
so on).
11.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physical reg ister . Address ing
the INDF register will cause indirec t addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register directly
results in no operation being performed (although
Status bits may be affected). An effective 9-bit address
is obtained by concatenating the 8-bit FSR and the IRP
bit in the STATUS register, as shown in Figure 11-3.
A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 11-2.
PC 12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
Opco de <10:0>
8
PC 12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
Destination
Note 1: There are no St atu s b it s to in dic ate Stack
Overflow or Stack Underflow condition s .
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interr upt add res s.
2014 Microchip Technology Inc. DS20005350A-page 79
MCP19118/19
EXAMPLE 11-2: INDIR ECT ADDRESSI NG
FIGURE 11-3 : DIRECT/INDIRECT ADDRESSING
MOVLW 0x40 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,7 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
Data
Memory
Indirect AddressingDirect Addres sing
Bank Select Location Select
RP1 RP0 6 0
From Opcode IRP File Select Register
70
Bank Select Location Select
00 01 10 11 180h
1FFh
00h
7Fh Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail, see Figure 11-2.
MCP19118/19
DS20005350A-page 80 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 81
MCP19118/19
12.0 DEVICE CONFIGURATION
Device Configuration consists of Configuration Word
and Code Prote ction.
12.1 Configuration Word
There are several Configuration Word bits that allow
different timers to be enabled and memory protection
options. These are implemented as Configuration
Word at 2007h.
Note: The DBGEN bit in Configuration Word is
managed automatically by device
development tools, including debuggers
and programmers. For normal device
opera tion , thi s bi t sh oul d be ma intai ned as
a '1'.
REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER
R/P-1 U-1 R/P-1 R/P-1 U-1 U-1
DBGEN —WRT1WRT0 — —
bit 13 bit 8
U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 U-1
—CPMCLRE PWRTE WDTE — — —
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13 DBGEN: ICD Debug bit
1 = ICD debug mode disabled
0 = ICD debug mode enabled
bit 12 Unimplemented: Read as ‘1’
bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bit
11 = Write protection off
10 = 000h to 3FFh write protected, 400h to FFFh may be modified by PMCON1 control
01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON1 control
00 = 000h to FFFh write protected, entire program memory is write protected
bit 9-7 Unimplemented: Re ad as ‘1’
bit 6 CP: Code Protection
1 = Program memory code protection is disabled
0 = P rogram memo ry code protec tion is enabled
bit 5 MCLRE: MCLR Pin Function Select
1 =MCLR
pin i s MCLR function and weak internal pull-up is enabled
0 =MCLR
pin is alternate function, MCLR function is int erna lly disa bl ed
bit 4 PWRTE: Power-Up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0 Unimplemented: Re ad as ‘1’
MCP19118/19
DS20005350A-page 82 2014 Microchip Technology Inc.
12.2 Code Protection
Code pro tec tio n a ll ow s the d ev ice t o b e protected from
unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.
12.2.1 PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in the
Configuration Word. When CP = 0, external reads and
writes of the program memory are inhibited and a read
will return all ‘0’s. The CPU can continue to read
program memory, regardless of the protection bit
settings. Writing the program memory is dependent
upon the write protection setting. See Section 12.3
“Write Protection” for more information.
12.3 Write Protection
Wr ite prot ec tion all ow s the de vi ce t o be prote cte d fro m
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in the Configuration Word define
the size of the program memory block that is protected.
12.4 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only t he Least Si gnifican t seven bit s of the I D locat ions
are reported when using MPLAB Integrated
Development Environment (IDE).
2014 Microchip Technology Inc. DS20005350A-page 83
MCP19118/19
13.0 OSCILLATOR MODES
The MCP19118/19 has one oscillator configuration
which is an 8 MHz intern al oscillator.
13.1 Internal Oscillator (INTOSC)
The Internal Oscillator module provides a system
clock source of 8 MHz. The frequency of the internal
oscillator can be trimmed with a calibration value in the
OSCTUNE register.
13.2 Oscillator Calibration
The 8 MHz internal oscillator is factory-calibrated. The
factory calibration values reside in the read-only
Calib ration Word 1 register . Thes e values must b e read
from the Calibration Word 1 register and stored in the
OSCCAL register. Refer to Section 18.0 “Flash
Program Memory Control” for the procedure on
reading from program memory.
13.3 Frequency Tuning in User Mode
In addition to the factory calibration, the base
frequency can be tuned in the user's application. This
frequency tuning capability allows the user to deviate
from the factory-calibrated frequency. The user can
tune the frequency by writing to the OSCTUNE
register (Register 13-1).
Note 1: The FCAL<6:0> bits from the Calibration
Word 1 register must be written into the
OSCCAL regi ster to ca lib rate the in tern al
oscillator.
REGISTER 13-1: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —TUN<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximu m frequency
01110 =
•
•
•
00001 =
00000 = Center frequency. Oscillator Module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
MCP19118/19
DS20005350A-page 84 2014 Microchip Technology Inc.
13.3.1 OSCILLA TOR DEL AY UPON
POWER-UP, WAKE-UP AND
BASE FREQUENCY CHANGE
In appl ications where th e OSCT UNE register is use d to
shift the frequency of the internal oscillator, the
application should not expect the frequency of the
internal oscillator to stabilize immediately. In this case,
the frequency may shift gradually toward the new
value. The time fo r this f requency sh ift is l ess than eight
cycles of the base frequency.
On power-up, the device is held in reset by the
power-up time, if the power-up timer is enabled.
Following a wake-up from Sleep mode or POR, an
internal delay of ~10 µs is invoked to allow the
memory bias to stabilize before program execution
can begin.
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 83
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.
TABLE 13-2: SUMMARY OF CALIBRATION WORD ASSOCIATED WITH CLOCK SOURCES
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CALWD1 13:8 — — — — DOV3 DOV2 DOV1 DOV0 59
7:0 — FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1 FCAL0
Legend: — = unimplemented loc ations read as ‘0’. Shaded cells are not used by clock sources.
2014 Microchip Technology Inc. DS20005350A-page 85
MCP19118/19
14.0 RESETS
The reset logic is used to place the MCP19118/19 into
a known state. The source of the reset can be
determined by using the device status bits.
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Overtemperature Reset (OT)
•MCLR
Reset
•WDT Reset
To a ll o w V DD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a POR
event.
Some regi sters a re not af fected in any Rese t condit ion;
their status i s un kn own on POR and un ch anged in an y
other Reset. Most other registers are reset to a Reset
state on:
• Power-O n Reset
•MCLR
Reset
•MCLR
Reset during Sleep
• WDT Reset
WDT wake-up does not cause register resets in the
same manner as a WDT Reset, since wake-up is
viewe d as the resump tio n of no rm al op era tion . TO and
PD bits are set or cleared differently in different Reset
situati ons, as indicate d in Table 14-1. Software can use
these bits to determine the nature of the Reset. See
Table 14-2 for a full description of Reset states of all
registers.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is shown i n Figure 14-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 5.0 “Digital
Electrical Characteristics” for pulse width
specifications.
FIGURE 14-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/VPP pin
VDD
WDT
Module
VDD Rise
Detect
On-Chip
WDT
Time-Out
Power-O n Reset
PWRT Chip_Reset
11-Bit Ripple Counter
Reset
Enable PWRT
Sleep
Note 1: Refer to the Configuration Word regi ster (Register 12-1).
RC OSC
TABLE 14-1: TIME OUT IN VARIOUS
SITUATIONS
Power-Up W ake-Up from
Sleep
PWRTE = 0PWRTE = 1
TPWRT ——
MCP19118/19
DS20005350A-page 86 2014 Microchip Technology Inc.
14.1 Power-On Reset (POR)
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-On Reset.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
14.2 MCLR
MCP19118/19 has a noise filter in the MCLR Reset
path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to VDD. The use of an RC network, as shown in
Figure 14-2, is sugge ste d.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When MCLRE = 1, the MCLR pin becomes
an external Reset input. In this mode, the MCLR pin
has a weak pull -up t o VDD.
FIGURE 14-2: RECOMMENDED MCLR
CIRCUIT
TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR TO PD Condition
011Power-On Reset
u0uWDT Reset
u00WDT W ak e-Up
uuuMCLR Reset during normal operation
u10MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
Note: The POR circuit does not produce an
internal Reset when VDD declines. To
re-enable the POR, VDD must reach VSS
for a minimum of 100 µs.
VDD
MCLR
R1
1k (or greater)
C1
0.1 µF
(optional, not critical)
R2
100
(needed w ith
SW1
(optional)
MCP19118/19
capacitor)
2014 Microchip Technology Inc. DS20005350A-page 87
MCP19118/19
14.3 Power-Up Timer (PWRT)
The Power-Up Timer provides a fixed 64 ms (nominal)
time out on power-up only, from POR Reset. The
Power-Up Timer operates from an internal RC
oscill ator. The chip is k ept in Reset as long as PWRT i s
active. The PWRT delay allows the VDD to rise to an
acceptable level. A Configuration bit, PWRTE, can
disabl e (if set) or enable (if cl eared or programmed ) the
Power-Up Timer.
The Power-Up Timer delay will vary from chip to chip
due to:
•V
DD variation
• Temperature variation
• Process variation
14.4 Watchdog T imer (WDT) Reset
The Watchdog Timer generates a Re set if the fi rmwa re
does n ot issu e a CLRWDT instruction within th e time-o ut
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 17.0
“Watchdog Timer (WDT)” for more information.
14.5 Power-Up Timer
The Power-Up T imer optionally delays device execution
after a POR event. T his timer is typically used to allow
VDD to stabilize before allowing the device to start
running.
The Power-Up T im er is controlle d by the PWRTE bit of
Configuration Word.
14.6 S tart-Up Sequence
Upon the release of a POR, the following must occur
before the device begins executing:
• Power-Up Timer runs to completion (if enabled)
• Oscillator start-up timer runs to completion
•MCLR
must be released (if enabled)
The total time out will vary based on the PWRTE bit
status. For example, with PWRTE bit erased (PWRT
disabled), there will be no time out at all.
Figures 14-3,14-4 an d 14-5 depict time-out sequences.
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 14-4). This is useful for testing purposes or
to synchronize more than one MCP19118/19 device
operating in parallel.
14.6.1 POWER CONTROL (PCON)
REGISTER
The Power Co ntrol (PCON) re gister (address 8Eh) ha s
two Status bits to indicate what type of Reset occurred
last.
FIGURE 14-3: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
Note: Voltage spikes below VSS at the MCLR
pin, induc ing current s greater than 80 mA,
may cause latch-up. Thus, a series
resistor of 50-100 should be used when
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to VSS.
TPWRT
TIOSCST
VDD
MCLR
Internal POR
PWRT Time Out
OST Time Out
Internal Reset
MCP19118/19
DS20005350A-page 88 2014 Microchip Technology Inc.
FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
FIGURE 14-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
PWRT Time Out
OST Time Out
Internal Reset
TPWRT
TIOSCST
VDD
MCLR
Internal POR
PWRT Time Out
OST Time Out
Internal Reset
TPWRT
TIOSCST
2014 Microchip Technology Inc. DS20005350A-page 89
MCP19118/19
TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-On
Reset MCLR Reset
WDT R eset
W ak e-Up from Sleep throug h
Interrupt
W ak e-Up from Sleep throug h
WDT Time Out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/
100h/180h xxxx xxxx xxxx xxxx uuuu uuuu
TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/
102h/182h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h/
103h/183h 0001 1xxx 000q quuu(4)uuuq quuu(4)
FSR 04h/84h/
104h/184h xxxx xxxx uuuu uuuu uuuu uuuu
PORTGPA 05h xxxx xxxx uuuu uuuu uuuu uuuu
PORTGPB 06h xxx- xxxx uuu- uuuu uuu- uuuu
PIR1 07h -000 --00 -000 --00 -uuu --uu
PIR2 08h 0-00 --00 0-00 --00 u-uu --uu
PCON 09h ---- -qq- ---- -uu- ---- -uu-
PCLATH 0Ah/8Ah/
10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh/
10Bh/18Bh 0000 000x 0000 000u uuuu uuuu(2)
TMR1L 0Ch xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Dh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 0Eh --00 --00 --uu --uu --uu --uu
TMR2 0Fh 0000 0000 uuuu uuuu uuuu uuuu
T2CON 10h ---- -000 ---- -000 ---- -uuu
PR2 11h 1111 1111 1111 1111 uuuu uuuu
PWMPHL 13h xxxx xxxx uuuu uuuu uuuu uuuu
PWMPHH 14h xxxx xxxx uuuu uuuu uuuu uuuu
PWMRL 15h xxxx xxxx uuuu uuuu uuuu uuuu
PWMRH 16h xxxx xxxx uuuu uuuu uuuu uuuu
OVCCON 19h 0000 0000 0000 0000 uuuu uuuu
OVFCON 1Ah 0--0 0000 0--0 0000 u--u uuuu
OSCTUNE 1Bh ---0 0000 ---0 0000 ---u uuuu
ADRESL(1)1Ch xxxx xxxx uuuu uuuu uuuu uuuu
ADRESH(1)1Dh ---- --xx ---- --uu ---- ---uu
ADCON0(1)1Eh -000 0000 -000 0000 -uuu uuuu
ADCON1(1)1Fh -000 ---- -000 ---- -uuu ----
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISGPA 85h 1111 1111 1111 1111 uuuu uuuu
TRISGPB 86h 1111 1111 1111 1111 uuuu uuuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-On Reset will be activated and registers will be affected differently.
2: One or more bits in the INTCON and/or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-5 for Reset value for specific condition.
MCP19118/19
DS20005350A-page 90 2014 Microchip Technology Inc.
PIE1 87h -000 --00 -000 --00 -uuu --uu
PIE2 88h 0-00 --00 0-00 --00 u-uu --uu
APFCON 89h ---- ---0 ---- ---0 ---- ---u
VINLVL 90h 0-xx xxxx 0-uu uuuu u-uu uuuu
OCCON 91h 0xxx xxxx 0uuu uuuu uuuu uuuu
CSGSCON 93h -xxx xxxx -uuu uuuu -uuu uuuu
CSDGCON 95h 0--- xxxx 0--- uuuu u--- uuuu
VZCCON 97h xxxx xxxx uuuu uuuu uuuu uuuu
CMPZCON 98h xxxx xxxx uuuu uuuu uuuu uuuu
OUVCON 99h xxxx xxxx uuuu uuuu uuuu uuuu
OOVCON 9Ah xxxx xxxx uuuu uuuu uuuu uuuu
DEADCON 9Bh xxxx xxxx uuuu uuuu uuuu uuuu
SLPCRCON 9Ch xxxx xxxx uuuu uuuu uuuu uuuu
SLVGNCON 9Dh ---x xxxx ---u uuuu ---u uuuu
RELEFF 9Eh 0000 0000 0000 0000 uuuu uuuu
WPUGPA 105h --1- 1111 --u- uuuu --u- uuuu
WPUGPB 106h 1111 -11- uuuu -uu- uuuu -uu-
PE1 107h 0000 1100 0000 1100 uuuu uuuu
BUFFCON 108h 000- 0000 000- 0000 uuu- uuuu
ABECON 109h 0000 0000 0000 0000 uuuu uuuu
SSPADD 110h 0000 0000 0000 0000 uuuu uuuu
SSPBUF 111h xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON1 112h 0000 0000 0000 0000 uuuu uuuu
SSPCON2 113h 0000 0000 0000 0000 uuuu uuuu
SSPCON3 114h 0000 0000 0000 0000 uuuu uuuu
SSPMSK 115h 1111 1111 1111 1111 uuuu uuuu
SSPSTAT 116h
SSPADD2 117h 0000 0000 0000 0000 uuuu uuuu
SSPMSK2 118h 1111 1111 1111 1111 uuuu uuuu
IOCA 185h 0000 0000 0000 0000 uuuu uuuu
IOCB 186h 0000 -000 0000 -000 uuuu -uuu
ANSELA 187h ---- 1111 ---- 1111 ---- uuuu
ANSELB 188h --11 -11- --11 -11- --uu -uu-
PMCON1 190h -0-- -000 -0-- -000 -u-- -uuu
PMCON2 191h ---- ---- ---- ---- ---- ----
PMADRL 192h 0000 0000 0000 0000 uuuu uuuu
PMADRH 193h ---- -000 ---- -000 ---- -uuu
PMDATL 194h 0000 0000 0000 0000 uuuu uuuu
TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-On
Reset MCLR Reset
WDT Reset
W ak e-Up from Sleep throug h
Interrupt
W ak e-Up from Sleep throug h
WDT Time Out
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-On Reset will be activated and registers will be affected differently.
2: One or more bits in the INTCON and/or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-5 for Reset value for specific condition.
2014 Microchip Technology Inc. DS20005350A-page 91
MCP19118/19
14.7 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Tables 14-4 and 14-5 show the Reset
conditio ns of thes e regi ster s.
PMDATH 195h --00 0000 --00 0000 --uu uuuu
OSCCAL 198h -xxx xxxx -uuu uuuu -uuu uuuu
DOVCAL 199h ---- xxxx ---- uuuu ---- uuuu
TTACAL 19Ah ---- xxxx ---- uuuu ---- uuuu
BGRCAL 19Bh ---- xxxx ---- uuuu ---- uuuu
VROCAL 19Ch ---- xxxx ---- uuuu ---- uuuu
ZROCAL 19Dh ---- xxxx ---- uuuu ---- uuuu
ATSTCON 19F 1--- 0001 1--- 0001 u--- uuuu
TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-On
Reset MCLR Reset
WDT R eset
W ak e-Up from Sleep throug h
Interrupt
W ak e-Up from Sleep throug h
WDT Time Out
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-On Reset will be activated and registers will be affected differently.
2: One or more bits in the INTCON and/or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-5 for Reset value for specific condition.
TABLE 14-4: RESET STATUS BITS AND
THEIR SIGNIFICANCE
POR TO PD Condition
011Power-On Reset
u0uWDT Reset
u00WDT Wake-Up from Sleep
u10Interrupt Wake-Up from Sleep
uuuMCLR Reset during normal
operation
u10MCLR Reset during Sle ep
00xNot allowed. TO is set on POR
0x0Not allowed. PD is set on POR
TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS (Note 2)
Condition Program
Counter STATUS
Register PCON
Register
Power-On Reset 0000h 0001 1xxx ---- -u0-
MCLR Reset during normal operation 0000h 000u uuuu ---- -uu-
MCLR Reset during Sleep 0000h 0001 0uuu ---- -uu-
WDT Reset 0000h 0000 uuuu ---- -uu-
WDT Wake-Up from Sleep PC + 1 uuu0 0uuu ---- -uu-
Interrupt Wake-Up from Sleep PC + 1(1)uuu1 0uuu ---- -uu-
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable (GIE) bit is set, the return address is pushed
on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
MCP19118/19
DS20005350A-page 92 2014 Microchip Technology Inc.
14.8 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-On Reset (POR)
• Overtemperature (OT)
The PCON register bits are shown in Register 14-1.
REGISTER 14-1: PCON: POWER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0
— — — — —OTPOR —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as '0'
bit 2 OT: Overtemperature Reset Status bit
1 = No Overtemperature Reset occurred
0 = An Overtemperature Reset occurred (must be set in software after an Overtemperature occurs)
bit 1 POR: Power-On Reset Status bit
1 = No Power-On Reset occurred
0 = A Power-On Reset occurred (must be set in software after a Power-On Reset occurs)
bit 0 Unimplemented: Read as '0'
TABLE 14-6: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
PCON —————OTPOR —92
STATUS IRP RP1 RP0 TO PD ZDCC71
Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other ( non Power-Up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2014 Microchip Technology Inc. DS20005350A-page 93
MCP19118/19
15.0 INTERRUPTS
The MCP19118/19 has multiple sources of interrupt:
• External Interrupt (INT pin)
• Interrupt-On-Change (IOC) Interrupts
• Timer0 Overflow Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• ADC Interrupt
• System Overvoltage Error
• System Undervoltage Error
• System Overcurrent Error
• SSP
•BCL
• System Input Undervoltage Error
The Interrup t Control (INTCON) register and Peripheral
Interrupt Request (PIRx) registers record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable (GIE) bit in the INTCON
register enables (if set) all unmasked interrupts or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIEx registers. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occu r automatically:
• The GIE i s c lea red to di sa ble an y fu rthe r interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
The firmwa re within the Interru pt Service Rou tine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR, to avoid repeated
interr upt s. Bec ause the GIE b it is clea red, a ny in terrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific Interrupt’s
operation, refer to its Peripheral chapter.
15.1 Interrupt Latency
For external interrupt events, such as the INT pin or
PORTGPx change interrupt, the interrupt latency will
be three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 15-2). The latency is the same for one or
two-cycle instructi ons.
15.2 GPA 2/INT Interrupt
The external interrupt on the GPA2/INT pin is
edge-tr iggered eit her on the rising edge , if the INTEDG
bit in the OPTION_REG register is set or on the falling
edge, if the INTEDG bit is cleared. When a valid edge
appears on the GPA2/INT pin, the INTF bit in the
INTCON register is set. This interrupt can be disabled
by cleari ng the INTE cont rol bit in the IN TCON registe r .
The INTF bit must be cleared by software in the
Interrupt Service Routine before re-enabling this
interrupt. The GPA2/INT interrupt can wake-up the
processor from Sleep, if the INTE bit was set prior to
going into Sleep. See Section 16.0 “Power-Down
Mode (Sleep)” for details on Sleep and Section 16.1
“Wake-Up from Sleep” for timing of wake-up from
Sleep through GPA2/INT interrupt.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts which were
ignored are still pending to be serviced
when the GIE bit is set again.
Note: The ANSELx registers must be initialized
to config ure an analog channel as a digit al
input. Pins configured as analog inputs
will read ‘0’ and cannot generate an
interrupt.
MCP19118/19
DS20005350A-page 94 2014 Microchip Technology Inc.
FIGURE 15-1: INTE RRUPT LOGIC
FIGURE 15-2: INT PIN INTERRUPT TIMING
TMR1IF
TMR1IE
SSPIF
SSPIE
T0IF
T0IE
INTF
INTE
GIE
PEIE
Wake-Up (If in Sleep mode)
Interrupt to CPU
PEIF
ADIF
ADIE
UVIF
UVIE
OVIF
OVIE
OCIF
OCIE
VINIF
VINIE
BCLIF
BCLIE
TMR2IF
TMR2IE
IOCF
IOCE
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
CLKIN
CLKOUT
INT pin
INTF flag
(INTCON reg.)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) I nst ( 0005h)
Dummy Cyc le
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the sam e whethe r I ns t ( PC ) is a si ngle cycl e or a two-cycle ins t ru ct io n.
3: CLKOU T i s available on ly in INTOSC and R C Oscillato r modes.
4: For minimum width of INT pulse, refer to the AC specifications in Section 5.0 “Digital Electrical
Characteristics”.
5: INTF is en abled to be set any time dur in g th e Q 4 –Q1 cycles .
(
1)
(
2)
(
3)
(
4)
(
5)
(
1)
2014 Microchip Technology Inc. DS20005350A-page 95
MCP19118/19
15.3 Interrupt Control Registers
15.3.1 INTCON REGISTER
The INTCON register is a readable and writable
register that contains the various enable and flag bits
for the TMR0 register overflow, interrupt-on-change
and external INT pin interrupts.
Note: Interru pt flag bit s are set w hen an interr upt
condition occurs, re gardless of the state of
its corresponding enable bit or the Global
Interrupt Enable (GIE) bit in the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 15-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE IOCE T0IF INTF IOCF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCE: Interrupt-on-Change Enable bit(1)
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2)
1 = TMR0 register overflowed (must be cleared in software)
0 = TM R0 register did no t overfl ow
bit 1 INTF: External Interrupt Flag bit
1 = The external interrupt occurred (must be cleared in software)
0 = The external interrupt did not occur
bit 0 IOCF: In terr upt-on-Cha nge Interrupt Fl ag bit
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins changed state
Note 1: The IOCx registers must also be enabled.
2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
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15.3.1.1 PIE1 Regi st er
The PIE1 register (Register 15-2) contains the
Peripheral Interrupt Enable bits.
Note 1: The PEIE bit in the INTCON registe r must
be set to enable any peripheral interrupt.
REGISTER 15-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
— ADIE BCLIE SSPIE —— TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as '0'
bit 6 ADIE: ADC Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 BCLIE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrup t
bit 4 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 3-2 Unimplemented: Read as '0'
bit 1 TMR2IE: Timer2 Interrupt Enable
1 = Enables the Timer2 interrupt
0 = Disables the Timer2 interrupt
bit 0 TMR1IE: Timer1 Interrupt Enable
1 = Enables the Timer1 interrupt
0 = Disables the Timer1 interrupt
2014 Microchip Technology Inc. DS20005350A-page 97
MCP19118/19
15.3.1.2 PI E2 Register
The PIE2 register (Register 15-3) contains the
Peripheral Interrupt Enable bits.
Note 1: The PEIE bit in the INTCON registe r must
be set to enable any peripheral interrupt.
REGISTER 15-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
UVIE —OCIEOVIE—— VINIE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UVIE: Output Undervoltage Interrupt enable bit
1 = Enables the UV interrupt
0 = Disables the UV interrupt
bit 6 Unimplemented: Read as '0'
bit 5 OCIE: Output Overcurrent Interrupt enable bit
1 = Enables the OC interrupt
0 = Disables the OC interrupt
bit 4 OVIE: Output Overvoltage Interrupt enable bit
1 = Enables the OV interrupt
0 = Disables the OV interrupt
bit 3-2 Unimplemented: Read as '0'
bit 1 VINIE: VIN UVLO Interrupt Enable
1 = Enables the VIN UVLO interrupt
0 = Disables the VIN UVLO interrupt
bit 0 Unimplemented: Read as '0'
MCP19118/19
DS20005350A-page 98 2014 Microchip Technology Inc.
15.3.1.3 PIR1 Register
The PIR1 register (Register 15-4) contains the
Peripheral Interrupt Flag bits.
Note 1: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Globa l Inte rrupt Enabl e (GIE) bit in
the INTCON register. User software
should ensure the appropriate interrupt
flag bits are clear prior to enabling an
interrupt.
REGISTER 15-4: PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
— ADIF BCLIF SSPIF — — TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as '0'
bit 6 ADIF: ADC Interrupt Flag bit
1 = ADC conversion complete
0 = ADC conversion has not completed or has not been started
bit 5 BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3-2 Unimplemented: Read as '0'
bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match did not occur
bit 0 TMR1IF: Timer1 Interrupt Flag
1 = Timer1 rolled over (must be cleared in software)
0 = Timer1 did not roll over
2014 Microchip Technology Inc. DS20005350A-page 99
MCP19118/19
15.3.1.4 PIR2 Register
The PIR2 register (Register 15-5) contains the
Peripheral Interrupt Flag bits.
Note 1: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Globa l Inte rrupt Enabl e (GIE) bit in
the INTCON register. User software
should ensure the appropriate interrupt
flag bits are clear prior to enabling an
interrupt.
REGISTER 15-5: PIR2: PERIPHERAL INTERRUPT FLAG REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
UVIF —OCIFOVIF——VINIF—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UVIF: Output undervoltage error interrupt flag bit
1 = Output undervoltage error has occurred
0 = Output undervoltage error has not occurred
bit 6 Unimplemented: Read as '0'
bit 5 OCIF: Output overcurrent error interrupt flag bit
1 = Output overcurrent error has occurred
0 = Output overcurrent error has not occurred
bit 4 OVIF: Output ov ervoltage error interrupt flag bit
1 = Output overvoltage error has occurred
0 = Output overvoltage error has not occurred
bit 3-2 Unimplemented: Read as '0'
bit 1 VINIF: VIN Status bit
1 = VIN is below acceptabl e leve l
0 = VIN is at accept abl e lev el
bit 0 Unimplemented: Read as '0'
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 95
OPTION_REG RAPU INTEDG T0CE T0SE PSA PS2 PS1 PS0 77
PIE1 — ADIE BCLIE SSPIE —— TMR2IE TMR1IE 96
PIE2 UVIE —OCIEOVIE—— VINIE —97
PIR1 — ADIF BCLIF SSPIF —— TMR2IF TMR1IF 98
PIR2 UVIF —OCIFOVIF—— VINIF —99
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
MCP19118/19
DS20005350A-page 100 2014 Microchip Technology Inc.
15.4 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary holding registers W_TEMP and
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Figure 11-2). These 16 locations are
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in Example 15-1 can be used to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit) register
• Restore the W register
EXAMPLE 15-1: SAVING STATUS AND W REGISTERS IN RAM
Note: The MCP19118/19 device does not
require saving the PCLATH. However, if
computed GOTOs are used in both the ISR
and the main code, the PCLATH must be
saved and restored in the ISR.
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
2014 Microchip Technology Inc. DS20005350A-page 101
MCP19118/19
16.0 POWER-DOWN MODE (SLEEP)
The Power-Down mode is entered by executing a
SLEEP instruction.
Upon entering Sleep mode, the following conditions
exist:
1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.
2. The PD bit in the STATUS register is cleared.
3. The TO bit in the STATUS register is set.
4. CPU clock is not disabled.
5. The Timer1 oscillator is unaffected and
peripherals that operate from it may continue
operation in Sleep.
6. The ADC is unaffected.
7. The I/O ports maintain the status they had
before SLEEP was executed (driving high, low or
high-impedance).
8. Resets other than WDT are not affected by
Sleep mode.
9. Analog circuitry is unaffected by execution of
SLEEP instruction.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry s ourci ng current from I/O pins
• Current dra w fr om pi ns w i th int erna l w eak p ull -ups
• Modules using Timer1 oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or GND externally to avoid switching
currents caused by floating inputs.
The SLEEP instruction does not affect the analog
circuitry. The enable state of the analog circuitry does
not chang e with the execu tion of the SLEEP instruction.
Examples of internal circuitry that might be sourcing
current include modules, such as the DAC. See
Section 22.0 “Analog-to-Digital Converter (ADC)
Module” for more information on this module.
16.1 Wake-Up from Sleep
The devi ce can wa ke-up from Sleep th rough one of th e
following events:
1. External Reset input on MCLR pin, if enabled
2. POR Re set
3. Watchdog Timer, if enabled
4. Any external interrupt
5. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first t wo ev ent s wil l cause a devic e Reset . The last
three events are considered a continuation of program
execution. To determine whether a device Reset or
Wake-Up event occurred, refer to Section 14.7
“Determining the Cause of a Reset”.
The follo wing periphe ral interrupt s can wake the device
from Sleep:
1. Timer1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. A/D conver sion
3. Interrupt-on-change
4. External Interrupt from the INT pin
When the SLEEP instruction is being e xecuted, the next
instruction (PC + 1) is prefetched. For the device to
wake-up thro ugh an interrupt event, the corres pon ding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
ins tructi on afte r the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instr uction, the de vice will then call the Interru pt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should hav e an NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
MCP19118/19
DS20005350A-page 102 2014 Microchip Technology Inc.
16.1.1 WAKE-UP USIN G INTERR UPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llowin g wil l occur:
• If the interrupt occurs before the execution of a
SLEEP instruction:
-SLEEP instruction will execute as an NOP
- WDT and WDT prescaler will not be cleared
-The TO
bit in the STATUS register w il l no t be
set
-The PD
bit in the STATUS register wi ll not b e
cleared
• If the interrupt occurs during or after the
execution of a SLEEP instruction:
-SLEEP instruction will be completely
executed
- The devic e will immediat ely wake-u p from
Sleep
- WDT and WDT prescaler will be cleared
-The TO
bit in the STATUS register will be set
-The PD
bit in the STATUS register will be
cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as an NOP.
FIGURE 16-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 95
IOCA IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 122
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — IOCB2 IOCB1 IOCB0 122
PIE1 — ADIE BCLIE SSPIE —— TMR2IE TMR1IE 96
PIE2 UVIE —OCIEOVIE——VINIE—97
PIR1 — ADIF BCLIF SSPIF — —TMR2IF TMR1IF 98
PIR2 UVIF —OCIFOVIF—— VINIF —99
STATUS IRP RP1 RP0 TO PD ZDCC 71
Legend: — = unimplemented, read as ‘0’. Shaded c ells are no t used in Power-Dow n mode.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(1)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy Cycle
PC + 2 0004h 0005h
Dummy Cycle
TOST
PC + 2
Note 1: GIE = 1 assumed. In this case, a fter wake-up , the processor calls the ISR at 0004h. I f GIE = 0, execut ion
will con tin ue in-l ine.
2014 Microchip Technology Inc. DS20005350A-page 103
MCP19118/19
17.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a free-running timer. The WDT
is ena bled b y set ting th e WDTE bi t in the Confi guratio n
Word (default setting).
During normal operation, a WDT time out generates a
device Reset. If the device is in Sleep mode, a WDT
time out causes the device to wake-up and continue
with normal operation.
The WDT ca n be perm an ently disabl ed by c le aring the
WDTE bit in the Configuration Word register. See
Section 12.1 “Configuration Word” for more
information.
17.1 Watchdog T imer (WDT) Operation
During normal operation, a WDT time out generates a
device Reset. If the device is in Sleep mode, a WDT
time out causes the device to wake-up and continue
with normal operation; this is known as a WDT
wake-up. The WDT can be permanently disabled by
clearing the WDTE configuration bit.
The postscaler assignment is fully under software
control and c an be ch anged during progra m exe cutio n.
17.2 WDT Period
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see Table 5-4). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be as si gne d to th e WD T un der soft ware c ont rol b y
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the presc al er, if assigne d to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time out.
17.3 WDT Programming
Considerations
Under worst-case conditions (i.e., VDD =Minimum,
Temperature = Maximum, Maximum WDT prescaler), it
may take several seconds before a WDT time out
occurs.
FIGURE 17-1: WATCHDOG TIMER WITH SHARED PRESCALER BLOCK DIAGRAM
T0CKI
T0SE
Pin
TMR0
Watchdog
Timer WDT
Time Out
PS<2:0>
Data Bus
Set Flag Bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.
2: The WDTE bit is in the Configuration Word register.
0
1
0
1
0
1
8
8
8-Bit
Prescaler
0
1
FOSC/4
PSA
PSA
PSA
Sync
2 TCY
WDTE
MCP19118/19
DS20005350A-page 104 2014 Microchip Technology Inc.
TABLE 17-1: WDT STATUS
Conditions WDT
WDTE = 0ClearedCLRWDT Command
Exit Sleep
TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Register on
Page
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 77
Legend: Shaded cells are not us ed by the Watchdog T i me r.
TABLE 17-3: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH WATCHDOG TIMER
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG 13:8 — — DBGEN —WRT1 WRT0 — — 81
7:0 —CP MCLRE PWRTE WDTE ———
Legend: — = unimplemented location, read as ‘1’. Shad ed cells are not used by Watchd og Timer.
2014 Microchip Technology Inc. DS20005350A-page 105
MCP19118/19
18.0 FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation (full VIN range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers (SFR) (see Registers 18-1
to 18-5). There are six SFRs used to read and write
this memory:
•PMCON1
•PMCON2
•PMDATL
•PMDATH
• PMADRL
• PMADRH
When interfacing the program memory block, the
PMDATL and PMDATH registers form a two-byte
word, which holds the 14-bit data for read/write, while
the PMADRL and PMADRH registers form a two-byte
word, which holds the 13-bit address of the FLASH
location being accessed. These devices have 4K
words of program Flash with an address range from
0000h to 0FFFh.
The program memory allows single-word read and a
four-wo rd wr i te. A fou r-word w rite aut om atic al ly era se s
the row of the location and writes the new data (erase
before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash program me mory.
Depending on the settings of the Flash Program
Memory Enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory. However, reads of the program memory are
allowed.
When the Flash Program Memory Code Protection
(CP) bit is enabled, the program memory is
code-protected and the device programmer (ICSP)
cannot access data or program memory.
18.1 PMADRH and PMADRL Registers
The PMADRH and PMADRL registers can address up
to a maximum of 4K words of program memory.
When selecting a program address value, the Most
Significant Byte (MSB) of the address is written to the
PMADRH register and the Least Significant Byte
(LSB) is written to the PMADRL register.
18.2 PMCON1 and PMCON2 Registers
PMCON1 is the control register for the data program
memory acces ses.
Control bits RD and WR initiate read and write,
resp ectivel y. These bits canno t be cleare d, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The CALSEL bit allows the user to read locations in
test memory in case there are calibration bits stored in
the calibration word locations that need to be
transferred to SFR trim registers. The CALSEL bit is
only for reads and, if a write operation is attempted
with CALSEL = 1, no write will occur.
PMCON2 is not a physic al reg is ter. Readin g PMCO N 2
will read all '0's. The PMCON2 register is used
exclusively in the flash memory write sequence.
MCP19118/19
DS20005350A-page 106 2014 Microchip Technology Inc.
18.3 Flash Program Memory
Control Registers
REGISTER 18-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMDATL<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PMDATL<7:0>: 8 Least Significant Data Bits Read from Program Memory
REGISTER 18-2: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMADRL<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PMADRL<7:0>: 8 Least Signific an t Addre ss Bits for Program Me mory Rea d/Write Ope ratio n
REGISTER 18-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——PMDATH<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Re ad as ‘0’
bit 5-0 PMDATH<5:0>: 6 Most Si gnifican t Data Bits Read from Program Memory
2014 Microchip Technology Inc. DS20005350A-page 107
MCP19118/19
REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — PMADRH<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Re ad as ‘0’
bit 3-0 PMADRH<3:0>: S pecifies t he 4 Most Significant Address bits or High bits for Program Memory Reads.
REGISTER 18-5: PMCON1: PROGRAM MEMORY CONTROL REGISTER 1
U-1 R/W-0 U-0 U-0 U-0 R/W-0 R/S-0 R/S-0
— CALSEL — — —WRENWR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
S = Bit can only be set
bit 7 Unimplemented: Read as '1'
bit 6 CALSEL: Program Memory calibration space select bit
1 = Select test memory area for reads only (for loading calibration trim registers)
0 = Select user area for reads
bit 5-3 Unimplemented: Re ad as '0'
bit 2 WREN: Program Memory Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the Flash Program Memory
bit 1 WR: Write Control bit
1 = Initiates a write cy cle to pro gram memory. (The bit is cleared by hardware when wr ite is complete .
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the Flash memory is complete
bit 0 RD: Read Cont rol bit
1 = Initiates a program memory read. (The read takes one cycle. The RD is cleared in hardware; the
RD bit can only be set (not cleared) in software).
0 = Does not initiate a Flash memory read
MCP19118/19
DS20005350A-page 108 2014 Microchip Technology Inc.
18.3.1 READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must
write two bytes of the address to the PMADRL and
PMADRH registers and then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle after setting the control bit to read the
data. This causes the second instruction immediately
following the “BSF PMCON1,RD” instruction to be
ignored. The data is av ailabl e, in th e very n ext cy cle, i n
the PMDATL and PMDATH registers; it can be read as
two bytes in the following instructions. PMDATL and
PMDATH registers will hold this value until another
read or until it is written to by the user (during a write
operation).
EXAMPLE 18-1: FLASH PROGRAM READ
FIGURE 18-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION – NORMAL MODE
BANKSELPM_ADR; Change STATUS bits RP1:0 to select bank with PMADR
MOVLWMS_PROG_PM_ADDR;
MOVWFPMADRH; MS Byte of Program Address to read
MOVLWLS_PROG_PM_ADDR;
MOVWFPMADRL; LS Byte of Program Address to read
BANKSELPMCON1; Bank to containing PMCON1
BSF PMCON1, RD; EE Read
NOP ; First instruction after BSF PMCON1,RD executes normally
NOP ; Any instructions here are ignored as program
; memory is read in second cycle after BSF PMCON1,RD
;
BANKSELPMDATL; Bank to containing PMADRL
MOVFPMDATL, W; W = LS Byte of Program PMDATL
MOVFPMDATH, W; W = MS Byte of Program PMDATL
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF PMCON1,RD
Executed here INSTR (PC + 1)
Executed here NOP
Executed here
PC PC + 1 PMADRH,PMADRL PC+3 PC + 5
Flash ADDR
RD bit
INSTR (PC) PMDATH,PMDATL INSTR (PC + 3)
PC + 3 PC + 4
INSTR (PC + 4)
INSTR (PC + 1)
INSTR (PC - 1)
Executed here INSTR (PC + 3)
Executed here INSTR (PC + 4)
Executed here
Flash DATA
PMDATH
PMDATL
Register
EERHLT
2014 Microchip Technology Inc. DS20005350A-page 109
MCP19118/19
18.3.2 WRITING TO THE FLASH
PROGRAM MEMORY
A word of the Flash program memory may only be
written to if the word is in an unprotected segment of
memory, as defined in Section 12.1 “Configuration
Word” (bits WRT<1:0>).
Flash program memory must be written in four-word
blocks. See Figures 18-2 and 18-3 for more details. A
block consists of four words with sequential addresses,
with a lower boundary defined by an address, where
PMADRL<1:0> = 00. All block writes to program
memory are done as 16-word erase by four-word write
operations. The write operation is edge-aligned and
cannot occur across bou ndaries.
To write program data, the WREN bit must be set and
the data must first be loaded into the buffer registers
(see Figure 18-2). This is accomplished by first writing
the destination address to PMADRL and PMADRH and
then writing the data to PMDATL and PMDATH. After
the address and data have been set, the following
sequence of events must be executed:
1. Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
2. Set the WR control bit in the PMCON1 register.
All four buffer register locations should be written to
with correct data. If less than four words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the
program memory location(s) not being written and
loads it i nto the PMDATL and PMDATH registers . Then
the sequence of events to transfer data to the buffer
registers must be executed.
To transfer data from the buffer registers to the program
memory, the PMADRL and PMADRH registers must
point to the last location in the four-word block
(PMADRL<1:0> = 11). Then the foll owing se quenc e of
events must be exe cu ted :
1. Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
2. Set the WR control bit in the PMCON1 register
to begin the write operation.
The user must follow the same specific sequence to
initiate the write for each word in the program block,
writing each program word in sequence (000, 001,
010, 011). When the write is performed on the last
word (PMADRL<1 :0> = 11), a blo ck of si xteen words is
automatically erased and the content of the four-word
buffer registers are written into the program memory.
After th e “BSF PMCON1,WR” instruction, the processor
requires tw o c ycles to se t up the era se /write opera tio n.
The user must place tw o NOP i ns truc tio ns after the WR
bit is set. Sinc e dat a is being written to buf fe r registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operat io ns for the typi ca l 4 ms, only during the cycle in
which the erase takes place (i.e., the last word of the
sixteen-word block erase). This is not Sleep mode, as
the clocks and peripherals will continue to run. After
the four-word write cycle, the processor will resume
operation with the third instruction after the PMCON1
write instruction. The above sequence must be
repeated for the higher 12 words.
Refer to Figure 18-2 for a block diagram of the buffer
registers and the control signals for test mode.
18.3.3 PROTECTION AGAINST SPURIOUS
WRITE
There are conditions when the device should not write
to the program memory. To protect against spurious
writes, various mechanisms have been built in. On
power-up, WREN is cleared. Also, the Power-Up
Timer (72 ms duration) prevents program memory
writes.
The write initiate sequence and the WREN bit help
prevent an accidental write during a power glitch or
software malfunction.
18.3.4 OPERATION DURING CODE PROTECT
When the device is code-protected, the CPU is able to
read and write unscrambled data to the program
memory. The test mode access is disabled.
18.3.5 OPERATION DURING WRITE PROTECT
When the program memory is write-protected, the
CPU can read and execute from the program memory.
The portions of program memory that are
write-protected cannot be modified by the CPU using
the PMCON registers. The write protection has no
effect in ICSP mode.
Note: The write-protect bits are used to protect the
users’ program from modification by the
user’s code. They have no effect when
programming is performed by ICSP. The
code-protect bits, when programmed for
code protection, will prevent the program
memory from being written via the ICSP
interface.
Note: An era se i s onl y in itia ted for the write of four
words, just after a row boundary; or
PMCON1<WR> set with PMADRL<3:0> =
xxxx0011.
MCP19118/19
DS20005350A-page 110 2014 Microchip Technology Inc.
FIGURE 18-2: BLOCK WRITES TO 4K FLASH PROGRAM MEMORY
FIGURE 18-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION
14 14 14 14
Program Memory
Buff er Regi ste r
PMADRL<1:0> = 00
Buffer Regist er
PMADRL<1:0> = 01
Buffer Register
PMADRL<1:0> = 10
Buffer Register
PMADRL<1:0> = 11
PMDATL
PMDATH
75 07 0
6 8
First word of block
to be written
If at n e w r o w
sixteen words of
Flash are erased,
then four buffers
are transferred to
Flash automatically
after this word is
written
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF PMCON1,WR
Executed here INSTR (PC + 1)
Executed here
PC + 1
Flash
INSTR PMDATH,PMDATL INSTR (PC+3)
INSTR
NOP
Executed here
Flash
Flash
PMWHLT
WR bit
Processor halted
EE Write Time
PMADRH,PMADRL PC + 3 PC + 4
INSTR (PC + 3)
Executed here
ADDR
DATA
Memory
Location
ignored
read
PC + 2
INSTR (PC+2)
(INSTR (PC + 2)
NOP
Executed here
(PC) (PC + 1)
2014 Microchip Technology Inc. DS20005350A-page 111
MCP19118/19
19.0 I/O PORTS
In general, when a peripheral is enabled, that pin may
not be used as a general purpose I/O pin.
Each port has two registers for its operation. These
registers are:
• TRISGPx registers (data direction register)
• POR TGPx registers (rea d the levels o n the pins of
the device)
Some ports may have one or more of the following
additional registers. These registers are:
• ANSELx (analog select)
• WPUx (weak pull-up)
Ports with analog functions also have an ANSELx
register, which can disable the digital input and save
power. A simpl ifi ed mo del of a gen eri c I /O port, witho ut
the interfaces to other peripherals, is shown in
Figure 19-1.
FIGURE 19-1: GENERIC I/O PORTGPX
OPERATION
EXAMPLE 19-1: INITIALIZI NG PO RTA
QD
CK
Write LAT x
Data Register
I/O pin
Read PORTx
Write PORTx
TRISx
Read LATx
Data Bus
To peripherals
ANSELx
VDD
VSS
; This code example illustrates
; initializing the PORTGPA register. The
; other ports are initialized in the same
; manner.
BANKSEL PORTGPA;
CLRF PORTGPA;Init PORTA
BANKSEL ANSELA;
CLRF ANSELA;digital I/O
BANKSEL TRISGPA;
MOVLW B'00011111';Set GPA<4:0> as
;inputs
MOVWF TRISGPA;and set GPA<7:6> as
;outputs
MCP19118/19
DS20005350A-page 112 2014 Microchip Technology Inc.
19.1 Alternate Pin Funct ion
The Alternat e Pin Fun ct ion Control (APFC ON) reg is ter
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 19-1. For the MCP19119 device,
the following function can be moved between different
pins:
• Frequency Synchronization Clock Input/Output
This bit has no effect on the values of any TRIS
register. PORT and TRIS ove rrides wil l be rou ted to the
correct pin. The unselected pin will be unaffected.
19.2 PORTGPA and TRISGPA Registers
PORT GP A is an 8-bit wide, bidirec tional port consis ting
of five CMOS I/O, two open-drain I/O and one
open-drain input-only pin. The corresponding data
direction re gister is TRISGP A (Register 19-3). Setting a
TRISGPA bit (= 1) will make the corresponding
PORTGPA pin an input (i.e., disable the output driver).
Clearing a TRISGPA bit (= 0) will make the
corresponding PORTGPA pin an output (i.e., enables
output driver). The exception is GPA5, which is input
only and its TRISGPA bit will always read as ‘1’.
Example 19-1 shows how to initialize an I/O port.
Reading the PORTGPA register (Register 19-2) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
read-modify-write operations.
The TRISGPA register (Register 19-3) controls the
PORTGP A pin output drivers, even when they are being
used as analog inputs. The user must ensure the bits in
the TRISGPA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’. If the pin is configured for a digital
output (e ither port or alternate functi on), the TRISGPA
bit must be cleared in order for the pin to drive the signal
and a read will ref l ect the state of the pin.
19.2.1 INTERRUPT-ON-CHANGE
Each PORTGPA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCA<7:0>
enable or disable the interrupt function for each pin.
The interrupt-on-change feature is disabled on a
Power-On Reset. Refer to Section 20.0 “Interrupt-
on-Change” for more information.
19.2.2 WEAK PULL-UPS
PORTGPA <3:0> and PORTGP A5 have an internal weak
pull-up. PORTGPA<7:6> are special ports for the SSP
module and do not have weak pull-ups. Individual control
bits can enable or disable the internal weak pull-ups (see
Register 19-4). The weak pull- up is automatically turned
off when the port pin is configured as an output, an
alternative function or on a Power-On Reset setting the
RAPU bit in the OPTION_REG register. The weak pull-up
on GPA5 is enabled when configured as MCLR pin by
setting bit 5 in the Configuration Word register and
disabled when GPA5 is an I/O. There is no software
control of the MCLR pull-up.
REGISTER 19-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CLKSEL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 CLKSEL: Pin Selection bit
1 = Multi-phase or multiple output clock function is on GPB5
0 = Multi-phase or multiple output clock function is on GPA1
2014 Microchip Technology Inc. DS20005350A-page 113
MCP19118/19
19.2.3 ANS ELA REG IS T ER
The ANSELA register (Register 19-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allows
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on the
digital output functions. A pin with TRISGPA clear and
ANSELA s et will still opera te as a di gita l outp ut, bu t the
Input mode wi ll be anal og. Th is can cause unex pected
behavior when executing read-modify-write
instruc tio ns on the affec ted port .
19.2.4 PORTGPA FUNCTIONS AND
OUTPUT PRIORITIES
Each PORTGPA pin is multiplexed with other functions.
The pins, their combined functions and their output
priorities are shown in Table 19-1. For additional
information, refer to the appropriate section in this data
sheet.
PORTGPA pins GPA7 and GPA4 are true open-drain
pins w ith n o c onne cti on b ack to VDD.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input func tio ns , su ch as AD C , a re no t shown in
the priority lists. These inputs are active when the I/O
pin is set for Analog mode using the ANSELA register.
Digital output functions may control the pin when it is in
Analog mode with the priority shown in Table 19-1.
Note: The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSELA bits
must be initialized to ‘0’ by user software.
TABLE 19-1: PORTGPA OUTPUT
PRIORITY
Pin Name Func tion Priority (1)
GPA0 GPA0
AN0
ANALOG_TEST
GPA1 GPA1
AN1
CLKPIN
GPA2 GPA2
AN2
T0CKI
INT
GPA3 GPA3
AN3
GPA4 GPA4 (open-drain input/output)
GPA5 GPA5 (open-drain data input only)
GPA6 GPA6
ICSPDAT (MCP19118 Only)
GPA7 GPA7 (open- dra in output)
SCL
ICSPCLK (MCP19118 Only)
Note 1: Priority listed from highest to lowest.
REGISTER 19-2: PORTGPA: PORTGPA REGISTER
R/W-x R/W-x R-x R-x R/W-x R/W-x R/W-x R/W-x
GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPA7: General Purpose Open-Drain I/O pin.
bit 6 GPA6: General Purpose I/O pin.
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 5 GPA5/MCLR: General Purpose Open-Drain I/O pin.
bit 4 GPA4: General Purpose Open-Drain I/O pin.
bit 3-0 GPA<3:0>: General Purpose I/O pin.
1 = Port pin is > VIH
0 = Port pin is < VIL
MCP19118/19
DS20005350A-page 114 2014 Microchip Technology Inc.
REGISTER 19-3: TRISGPA: PORTGPA TRI-STATE REGISTER
R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 TRISA<7:6>: PORTGPA Tri-State Control bit
1 = PORTGPA pin configured as an input (tri-stated)
0 = PORTGPA pin configured as an output
bit 5 TRISA5: GPA5 Port Tri-State Control bit
This bit is always ‘1’ as GPA5 is an input only
bit 4-0 TRISA<4:0>: PORTGPA Tri-State Control bit
1 = PORTGPA pin configured as an input (tri-stated)
0 = PORTGPA pin configured as an output
REGISTER 19-4: WPUGPA: WEAK PULL-UP PORTGPA REGISTER
U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1
—— WPUA5 — WPUA3 WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 WPUA5: Weak Pull-Up Register bit
1 = Pull-up enabled.
0 = Pull-up disabled.
bit 4 Unimplemented: Read as ‘0’
bit 3-0 WPUA<3:0>: Weak Pull-Up Register bit
1 = Pull-up enabled.
0 = Pull-up disabled.
Note 1: The weak pull-up device is enabled only when the global RAPU bit is enabled, the pin is in input mode
(TRISGPA = 1), the individual WPUA bit is enabled (WPUA = 1) and the pin is not configured as an
analog inp ut.
2: GPA5 weak pull-up is also enabled when the pin is configured as MCLR in the Configuration Word
register.
2014 Microchip Technology Inc. DS20005350A-page 115
MCP19118/19
REGISTER 19-5: ANSELA: ANALOG SELECT PORTGPA REGISTER
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — —ANSA<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 ANSA<3:0>: Analog Select PORTGPA Register bit
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA — — — — ANSA3 ANSA2 ANSA1 ANSA0 115
APFCON — — — — — — — CLKSEL 112
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 77
PORTGPA GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 113
TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114
WPUGPA ——WPUA5— WPUA3 WPUA2 WPUA1 WPUA0 114
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTGPA.
MCP19118/19
DS20005350A-page 116 2014 Microchip Technology Inc.
19.3 PORTGPB and TRISGPB
Registers
PORTGPB is an 8-bit wide, bidirectional port consisting
of seven general purpose I/O ports. The corresponding
data direction register is TRISGPB (Register 19-7).
Setting a TRISG PB bit (= 1) will make the corresponding
PORTGPB pin an input (i.e., disable the output driver).
Clearing a TRISGPB bit (= 0) will make the
correspon din g PORTGPB pin a n o utpu t (i.e ., e nab le the
outp ut dr ive r). Example 19-1 shows how to initialize an
I/O port.
Some pins for PORTGPB are multiplexed with an
alternate function for the peripheral or a clock func tion. In
general, when a peripheral or clock function is enabled,
that pin m ay not b e us ed as a ge neral purpose I/O pi n.
Reading the PORTGPB register (Register 19-6) reads
the st atus of the pins, whereas writing to i t will write to the
PORT latch. All write operations are read-modify-write
operations.
The TRISGPB register (Register 19-7) controls the
PORTGPB pin output driver s, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISGPB register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’. If the pin is configu red for a digital
output (either port or alternate function), the TRISGPB bit
must be cleared in order for the pin to drive the signal and
a read will reflect the state of the pin.
19.3.1 INTERRUPT-ON-CHANGE
Each PORTGPB pin is individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:4> and
IOCB <2:0 > enab le or d isab le the i nter rupt func tion f or
each pin. The interrupt-on-change feature is disabled
on a Power-On Reset. Refer to Section 20.0
“Interrupt-on-Change” for more information.
19.3.2 WEAK PULL-UPS
Each of the PORTGPB pins has an individually
configurable internal weak pull-up. Control bits
WPUB<7:4> and WPUB<2:1> enable or disable each
pull-up (see Register 19-8). Each weak pull-up is
auto matica lly turn ed off when the port pin is conf igure d
as an output. All pull-ups are disabled on a Power-On
Reset by the RAPU bi t in the OP TION_REG regi ster.
19.3.3 ANS ELB REG IS T ER
The ANSELB register (Register 19-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allows
analog functions on the pin to operate correctly.
The state of the ANSELB bit s has no effect on the d igital
output functions. A pin with TRISGPB clear and
ANSELB set will still operate as a digital output, but the
Input mode will be analog. This can cause unexpected
behavior when executing read-modify-write instructions
on the af fected port.
19.3.4 PORTGPB FUNCTIONS AND
OUTPUT PRIORITIES
Each PORTGPB pin is multiplexed with other functions.
The pins, their combined functions and their output
priorities are shown in Table 19-3. For additional
information, refer to the appropriate section in this data
sheet.
PORTGPB pin GPB0 is a true open-drain pin with no
connecti on b ack to VDD.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC, and some digital
input fun ctions are not in clude d in the list bel ow. These
inputs are active when the I/O pin is set for Analog
mode using the ANSELB registers. Digital output
functions may control the pin when it is in Analog mode,
with the priority shown in Table 19-3.
Note: The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSELB bits
must be initialized to ‘0’ by the user’s
software.
TABLE 19-3: PORTGPB OUTPUT
PRIORITY
Pin Name Function Priority(1)
GPB0 GPB0 (open-drain input/output)
SDA
GPB1 GPB1
AN4
EAPIN
GPB2 GPB2
AN5
GPB4 GPB4
AN6
ICSPDAT/ICDDAT (MCP19119 Only)
GPB5 GPB5
AN7
ICSPCLK/ICDCLK (MCP19119
Only)
ALT_CLKPIN (MCP19119 Only)
GPB6 GPB6
GPB7 GPB7
Note 1: Priority listed from highest to lowest.
2014 Microchip Technology Inc. DS20005350A-page 117
MCP19118/19
REGISTER 19-6: PORTGPB: PORTGPB REGIST ER
R/W-x R/W-x R/W-x R/W-x U-x R/W-x R/W-x R/W-x
GPB7(1)GPB6(1)GPB5(1)GPB4(1)— GPB2 GPB1 GPB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 GPB<7:4>: General Purpose I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 3 Unimplemented: Read as ‘0’
bit 2-0 GPB<2:0>: General Purpose I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Not implemented on MCP19118.
REGISTER 19-7: TRISGPB: PORTGPB TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-1 R/W-1 R/W-1 R/W-1
TRISB7(1)TRISB6(1)TRISB5(1)TRISB4(1)— TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 TRISB<7:4>: PORTGPB Tri-State Control bit
1 = PORTGPB pin con figured as an input (tri-stat ed)
0 = PORTGPB pin con figured as an outp ut
bit 3 Unimplemented: Read as ‘1’
bit 2-0 TRISB<2:0>: PORTGPB Tri-State Control bit
1 = PORTGPB pin con figured as an input (tri-stat ed)
0 = PORTGPB pin con figured as an outp ut
Note 1: Not implemented on MCP19118.
MCP19118/19
DS20005350A-page 118 2014 Microchip Technology Inc.
REGISTER 19-8: WPUGPB: WEAK PULL-UP PORTGPB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 U-0
WPUB7(2)WPUB6(2)WPUB5(2)WPUB4(2)— WPUB2 WPUB1 —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 WPUB<7:4>: Weak Pull-Up R egister bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-1 WPUB<2:1>: Weak Pull-Up R egister bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 0 Unimplemented: Read as ‘0’
Note 1: The weak pull-up device is enabled only when the global RAPU bit is enabled, the pin is in Input mode
(TRISGPA = 1), the individual WPUB bit is enabled (WPUB = 1) and the pin is not configured as an
analog inp ut.
2: Not implemented on MCP19118.
REGISTER 19-9: ANSELB: ANALOG SELECT PORTGPB REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 U-0
——ANSB5
(2)ANSB4(2)— ANSB2 ANSB1 —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 ANSB<5:4>: Analog Select PORTGPB Register bit
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
bit 3 Unimplemented: Read as ‘0’
bit 2-1 ANSB<2:1>: Analog Select PORTGPB Register bit
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
bit 0 Unimplemented: Read as ‘0’
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: Not implemented on MCP19118.
2014 Microchip Technology Inc. DS20005350A-page 119
MCP19118/19
TABLE 19-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELB —— ANSB5 ANSB4 — ANSB2 ANSB1 —118
APFCON — — — — — — — CLKSEL 112
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 77
PORTGPB GPB7 GPB6 GPB5 GPB4 — GPB2 GPB1 GPB0 117
TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — TRISB2 TRISB1 TRISB0 117
WPUGPB WPUB7 WPUB6 WPUB5 WPUB4 — WPUB2 WPUB1 —118
Legend: — = unimplemented locations read as ‘0’. Shaded c ells are not us ed by PORTGP B.
MCP19118/19
DS20005350A-page 120 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 121
MCP19118/19
20.0 INTERRUPT-ON-CHANGE
Each PORTGPA and PORTGPB pin is individually
configu rable as an interrupt-on-change pin. Control bits
IOCA and IOCB enabl e or disable the inte rrupt function
for each pin. Refer to Registers 20-1 and 20-2. The
interrupt-on-change is disabled on a Pow er-On Reset.
The interrupt-on-change on GPA5 is disabled when
configured as MCLR pin in the Configuration Word
register.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTGPA or PORTGPB. The mismatched outputs of
the last read of all the PORTGPA and PORTGPB pins
are OR’ed together to set the Interrupt-on-Change
Interrupt Flag bit (IOCF) in the INTCON register.
20.1 Enabling the Module
To allow individual port pins to generate an interrupt, the
IOCIE bit in the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
20.2 Individual Pin Configuration
To enable a pin to detect an interrupt-on-change, the
associated IOCAx or IOCBx bit in the IOCA or IOCB
register is set.
20.3 Clearing Interrupt Flags
The user, in the Interrupt Service Routine, clears the
interrupt by:
a) Any read of PORTGPA or PORTGPB AND
Clear flag bit IOCF. This will end the mismatch
condition;
OR
b) Any write of PORTGPA or PORTGPB AND
Clear flag bit IOCF will end the mismatch
condition.
A mismatch condition will continue to set flag bit IOCF.
Reading PORTGPA or PORTGPB will end the
mismatch condition and allow flag bit IOCF to be
cleared. The latch holding the last read value is not
affected by a MCLR Reset. After this Reset, the IOCF
flag will continue to be set if a mismatch is present.
20.4 Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCE bit is s et.
Note: If a change on the I/O pin should occur
when any PORTGPA or PORTGPB
operation is being executed, then the
IOCF interrupt flag may not get set.
MCP19118/19
DS20005350A-page 122 2014 Microchip Technology Inc.
20.5 Interrupt -on-Change Registers
REGISTER 20-1: IOCA: INTERRUPT-ON-CHANGE PORTGPA REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 IOCA<7:6>: Interrupt-on-Change PORTGPA Register bits.
1 = Interrupt-on-cha nge enabl ed on the pin .
0 = Interrupt-on-change disabled on the pin.
bit 5 IOCA<5>: Interrupt-on-Change PORTGPA Register bits(1).
1 = Interrupt-on-cha nge enabl ed on the pin .
0 = Interrupt-on-change disabled on the pin.
bit 4-0 IOCA<4:0>: Interrupt-on-Change PORTGPA Register bits.
1 = Interrupt-on-cha nge enabl ed on the pin .
0 = Interrupt-on-change disabled on the pin.
Note 1: The Interrupt-on-change on GPA5 is disabled if GPA5 is configured as MCLR.
REGISTER 20-2: IOCB: INTERRUPT-ON-CHANGE PORTGPB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
IOCB7(1)IOCB6(1)IOCB5(1)IOCB4(1)— IOCB2 IOCB1 IOCB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTGPB Register bits.
1 = Interrupt-on-cha nge enabl ed on the pin .
0 = Interrupt-on-change disabled on the pin.
bit 3 Unimplemented: Read as ‘0’
bit 2-0 IOCB<2:0>: Interrupt-on-Change PORTGPB Register bits.
1 = Interrupt-on-cha nge enabl ed on the pin .
0 = Interrupt-on-change disabled on the pin.
Note 1: Not implemented on MCP19119.
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA ————ANSA3ANSA2ANSA1ANSA0115
ANSELB —— ANSB5 ANSB4 — ANSB2 ANSB1 —118
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 96
IOCA IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 122
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — IOCB2 IOCB1 IOCB0 122
TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114
TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — TRISB2 TRISB1 TRISB0 117
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change.
2014 Microchip Technology Inc. DS20005350A-page 123
MCP19118/19
21.0 INTERNAL TEMPERATURE
INDICATOR MODULE
The MCP19118/19 is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit's operating temperature
rangeis -40°C to + 125°C. The outp ut is a v oltag e that i s
proportional to the device temperature. The output of
the temperature indicator is internally connected to the
device ADC.
21.1 Circuit Operation
The TMPSEN bit in the ABECON register
(Register 6-15) is set to enable the internal
temperature measurement circuit. The MCP19118/19
overtemperature shutdown feature is NOT controlled
by this bit.
FIGURE 21-1: TEMPERATURE CIRCUIT
DIAGRAM
21.2 Temperature Output
The output of the circuit is measured using the internal
analog-to-digital converter. Channel 10 is reserved for
the temperature circuit output. Refer to Section 22.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The temperature of t he silicon die can be calcula ted by
the ADC measurement by using Equation 21-1.
EQUATION 21-1: SILICON DIE
TEMPERATURE
TMPSEN
ADC
MUX
VDD
ADC
CHS Bits
(ADCON0 Register)
n
VOUT
TEMP_DIE ADC READING 1.75–
13.3mV/
C
-----------------------------------------------------------=
MCP19118/19
DS20005350A-page 124 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 125
MCP19118/19
22.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the right justified conversion
resu lt into th e ADC re sult regi sters (ADRESH:A DRESL
register pair). Figure 22-1 shows the block diagram of
the ADC.
The intern al band gap s upplies the v oltage refe rence to
the ADC.
The AD C can genera te an i nterrupt upon com pletio n of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 22-1: ADC B LOCK DIAGRAM
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2: See the ADCO N0 registe r (Register 22-1) for de tailed analog ch annel sel ection pe r device.
3: Not implemented on MCP19118.
00000
00001
00010
00011
00100
00101
00111
00110
01000
01001
01010
01011
RELEFF
ADC
VOUT
VREF
ADON
GO/DONE
CHS4:CHS0
ADRESH ADRESL
10
VSS
TEMP_ANA
GPA0
VIN_ANA
CRT
GPB4(3)
VZC
VREF
OVREF
UVREF
VBGR
ANA_IN
DEMAND
GPB2
DCI 01100
GPA1
GPA3
GPA2
GPB1
GPB5(3)
10000
10001
10010
10011
10100
10101
10110
10111
MCP19118/19
DS20005350A-page 126 2014 Microchip Technology Inc.
22.1 ADC Configuration
When configuring and using the ADC, the following
functio ns must be considere d:
• Port configuration
• Channel selection
• ADC convers ion cl ock source
• Interrupt control
• Result formatting
22.1.1 PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 19.0 “I/O Ports” for more information.
22.1.2 CHANNEL SELECTION
There are up to 19 channel selections available on the
MCP19118 and 21 channe l selections av ailable on the
MCP19119:
• AN<6:0> pins
• VIN_ANA: 1/13 of the input voltage (VIN)
•VREGREF: V
OUT reference voltage
• OV_REF: reference for OV comparator
• UV_REF: reference for UV comparator
• VBGR: band gap reference
• VOUT: output voltage
• CRT: voltage proportional to the AC inductor
current
• VZC: an internal ground, Voltage for Zero Current
• DEMAND: input to slope compensation circuitry
• RELEFF: relative efficient measurement channel
• TMP_ANA: voltage proportional to silicon die
temperature
• ANA_IN: for a multi-phase slave, error amplifier
signal received from master
• DCI: DC inductor valley current
The CHS<4:0> bits in the ADCON0 register determi ne
which channel is connected to the sample and hold
circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 22.2
“ADC Operation” for more information.
22.1.3 ADC CONVERSION CLOCK
The source of the conversion clock is
software-selectable via the ADCON1<ADCS> bits.
There are five possible clock options:
•F
OSC/8
•F
OSC/16
•F
OSC/32
•F
OSC/64
•F
RC (clock derived from internal oscillator with a
divisor of 16)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 1 1 T AD periods,
as shown in Figure 22-2.
For a correct conversion, the appropriate TAD
specif ica tio n m us t be m et . R efe r to th e A/D conv ers io n
requirements in Section 5.0 “Digital Electrical
Characteristics” for more information. Table 22-1
gives examples of appropriate ADC clock selections.
Note: Analo g v ol tages on any pi n t hat is d efin ed
as a digital input may cause the input
buffer to conduct excess current. Note: Unless usin g the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
T ABLE 22-1: ADC CLOCK PERIOD (T AD) VS.
DEVICE OPERATING
FREQUENCIES
ADC Clock Period (TAD)Device
Frequency
(FOSC)
ADC
Clock Source ADCS<2:0> 8 MHz
FOSC/8 001 1.0 µs(2)
FOSC/16 101 2.0 µs
FOSC/32 010 4.0 µs
FOSC/64 110 8.0 µs(3)
FRC x11 2.0-6.0 µs(1,4)
Legend: Sh aded cells are outsid e of recomm ended
range.
Note 1: The FRC source has a typical TAD time of
4µs for V
DD >3.0V.
2: These values violate the minimum
required TAD time.
3: For faster conve rsion times, the selection
of another clock source is recommended.
4: The FRC clock source is onl y
recommended if the conversion will be
performed during Sleep.
2014 Microchip Technology Inc. DS20005350A-page 127
MCP19118/19
FIGURE 22-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
22.1.4 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
convers ion. The ADC Interrupt Flag is the PIR1<ADIF >
bit. The ADC Interrupt Enable is the PIE1<ADIE> bit.
The ADIF bit must be cleared in software.
This interrupt can be generated while the device is
operatin g or while in Slee p. If the device is in Slee p, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the INTCON<GIE> and INTCON<PEIE>
bits must be disabled. If the INTCON<GIE> and
INTCON<PEI E> bits are ena bled, exec ution will switc h
to the Interrupt Service Routine.
22.1.5 RESULT FORMATTING
The 10-bit A/D conversion result is supplied in right
justified format only.
Figure 22-3 shows the output format.
FIGURE 22-3: 10-BIT A/D RESULT FORMAT
TAD1TAD2TAD3 TAD4TAD5 TAD6TAD7TAD8 TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9TAD10TCY - TAD
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9 b6 b5 b4 b3 b2 b1
b8 b7
On the followi ng cy cle :
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
(ADFM = 1)MSB LSB
bit 7 bit 0 bit 7 bit 0
Read as ‘0’ 10-bit A/D Result
MCP19118/19
DS20005350A-page 128 2014 Microchip Technology Inc.
22.2 ADC Operation
22.2.1 STARTING A CONVERSION
To enable the ADC module, the ADCON0<ADON> bit
must be set to a ‘1’. Setting the ADCON0<GO/DONE>
bit to a ‘1’ will start the Analog-to-Digital conversion.
22.2.2 COMPLETION OF A CONVERSION
When the conversion is co mplete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH: ADRESL regis ters with new
conversion result
22.2.3 TERMINATING A CONVERSION
If a co nver sion must b e term ina ted be fore comp leti on,
the GO/DONE bit can be cleared in software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion.
Addition ally, a two T AD delay is required before anoth er
acquisition can be initiated. Following the delay, an
input acquisition is automatically started on the
selected channel.
22.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC wa its on e additio nal instru ction bef ore sta rting th e
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
22.2.5 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Config ure pin as analo g (Refe r to the ANSEL
register)
2. Configure the ADC module:
• Select ADC conversion clock
• Select ADC input channel
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polli ng the GO /DO N E bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrup t flag (requi red if interrupt
is enabled).
EXAMPLE 22-1: A/D CON VERSION
Note: The GO/DONE bit shou ld not be se t in the
same instruction that turns on the ADC.
Refer to Section 22.2.5 “A/D
Conversion Procedure”.
Note: A devi ce Rese t forces all reg is ters to th eir
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
Note 1: The glo bal interru pt can b e disabl ed if the
user is att empting to w ake-u p from Sleep
and resume in-line code execution.
2: Refer to Section 22.4 “A/D Acquisition
Requirements”.
;This code block configures the ADC
;for polling, Frc clock and AN0 input.
;
;Conversion start & polling for completion ;
are included.
;
BANKSEL ADCON1 ;
MOVLW B’01110000’ ;Frc clock
MOVWF ADCON1 ;
BANKSEL TRISGPA ;
BSF TRISGPA,0 ;Set GPA0 to input
BANKSEL ANSELA ;
BSF ANSELA,0 ;Set GPA0 to analog
BANKSEL ADCON0 ;
MOVLW B’01000001’ ;Select channel AN0
MOVWF ADCON0 ;Turn ADC On
CALL SampleTime ;Acquisiton delay
BSF ADCON0,1 ;Start conversion
BTFSC ADCON0,1 ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRESH ;
MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
2014 Microchip Technology Inc. DS20005350A-page 129
MCP19118/19
22.3 ADC Register Definitions
The following registers are used to control the
operation of the ADC:
REGISTER 22-1: ADCON0: A/D CONTROL REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-2 CHS<4:0>: Analog Channel Selec t bit s
00000 = VIN_ANA (analog voltage proportional to 1/13 of VIN)
00001 = VREGREF (reference voltage for VREG output)
00010 = OV_REF (reference for overvoltage comparator)
00011 = UV_REF (reference for undervoltage comparator)
00100 = VBGR (band gap reference)
00101 = INT_VREG (internal version of the VREG load voltage)
00110 = CRT (voltage proportional to the current in the inductor)
00111 = VZC (an internal ground, Voltage for Zero Current)
01000 = DEMAND (input to current loop, output of demand mux)
01001 = RELEFF (analog voltage proportional to duty cycle)
01010 = TMP_ANA (analog voltage proportional to temperature)
01011 = ANA_IN (demanded current from the remote master)
01100 = DCI (dc inductor valley current)
01101 = Unimplemented
01110 = Unimplemented
01111 = Unimplemented
10000 = GPA0 (i.e. ADDR1)
10001 = GPA1 (i.e. ADDR0)
10010 = GPA2 (i.e. Temperature Sensor Input)
10011 = GPA3 (i.e. Tracking Voltage)
10100 = GPB1
10101 = GPB2
10110 = GPB4(1)
10111 = GPB5(1)
11000 = Unimplemented
11001 = Unimplemented
11011 = Unimplemented
11100 = Unimplemented
11101 = Unimplemented
11110 = Unimplemented
11111 = Unimplemented
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled an d consumes no operating current
Note 1: Not implemented on MCP19118.
MCP19118/19
DS20005350A-page 130 2014 Microchip Technology Inc.
REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— ADCS<2:0> — — — —
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 ADCS<2:0>: A/D Conversion Cloc k Select bit s
000 = Reserved
001 =F
OSC/8
010 =F
OSC/32
x11 =F
RC (clock derived from internal oscillator with a divisor of 16)
100 = Reserved
101 =F
OSC/16
110 =F
OSC/64
bit 3-0 Unimplemented: Re ad as ‘0’
REGISTER 22-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH)
U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x
— — — — — — ADRES9 ADRES8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 ADRES<9:8>: Most Significant A/D Results
REGISTER 22-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL)
R-x R-x R-x R-x R-x R-x R-x R-x
ADRES<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: Least Significant A/D results
2014 Microchip Technology Inc. DS20005350A-page 131
MCP19118/19
22.4 A/D Acquisition Requirements
For the AD C to meet its speci fie d ac curacy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 22-4. The source
impeda nce (RS) and the inte rnal sam pling swi tch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD); refer
to Figure 22-4.
The maximum recommended impedance for
analo g sources i s 10 k. As the sou rce imped ance i s
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 22-1 may be used. This equation
assumes th at 1/2 LSb error i s used (1,02 4 steps for th e
ADC). The 1/2 LSb error is the m aximum erro r al lowe d
for the ADC to meet its specified resolution.
EQUATION 22-1: ACQUISITION TIME EXAMPLE
Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion.
2: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
TACQ Amplif ier Settling Time Hold Capacitor Char ging Time Temperature Coefficient++=
TAMP TCTCOFF
++=
2 µs TCTemperature - 25°C0.05 µs/°C++=
TCCHOLD RIC RSS RS
++ ln(1/2047)–=
10 pF 1 k
7 k
10 k
++– ln(0.0004885)=
1.37=µs
VAPPLIED 1e
TC
–
RC
----------
–
VAPPLIED 11
2n1+
1–
------------------------------–
=
VAPPLIED 11
2n1+
1–
------------------------------–
VCHOLD
=
VAPPLIED 1e
TC
–
RC
----------
–
VCHOLD
=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Temperature +50°C and external impedance of 10 k
5.0 V VDD
=
Assumptions:
Note: Where n = number of bits of the ADC.
TACQ 2 µs 1.37µs 50°C- 25°C0.05µs/°C++=
4.67 µs=
MCP19118/19
DS20005350A-page 132 2014 Microchip Technology Inc.
FIGURE 22-4: ANALOG INPUT MODEL
FIGURE 22-5: ADC TRANSFER FUNCTION
CPIN
VA
RS
Analog
5pF
VDD
VT 0.6V
VT 0.6V ILEAKAGE(1)
Sampling
Switch
SS RSS
CHOLD = 10 pF
VSS/VREF-
6V
Sampling Switc h
5V
4V
3V
2V
567891011
(k)
VDD
RSS
Input
pin
Legend:
Note 1: Refer to Section 5.0 “Digital Electrical Characteristics”.
CHOLD = Sample/ Hol d Capacitanc e
CPIN = Input Capacitance
ILEAKAGE = Leakage current at the pin due to various junctions
RIC = Interconnect Resistance
RSS = Resistance of Sampling Switch
SS = Sampling Switch
VT= Threshold Voltage
RIC 1k
3FFh
3FEh
ADC Output Code
3FDh
3FCh
03h
02h
01h
00h
Full-Scale
3FBh
0.5 LSB
VREF-Zero-Scale
Transition VREF+
Transition
1.5 LSB
Full-Scale Range
Analog Input Voltage
2014 Microchip Technology Inc. DS20005350A-page 133
MCP19118/19
TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 129
ADCON1 — ADCS2 ADCS1 ADCS0 — — — — 130
ADRESH —————— ADRES9 ADRES8 130
ADRESL ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 130
ANSELA — — — — ANSA3 ANSA2 ANSA1 ANSA0 115
ANSELB —— ANSB5 ANSB4 — ANSB2 ANSB1 —118
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 95
PIE1 —ADIEBCLIE SSPIE — — TMR2IE TMR1IE 96
PIR1 —ADIFBCLIF SSPIF — — TMR2IF TMR1IF 98
TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114
TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — TRISB2 TRISB1 TRISB0 117
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
MCP19118/19
DS20005350A-page 134 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 135
MCP19118/19
23.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Inter rupt on ov erflow
Figure 23-1 is a block diagram of the Timer0 module.
FIGURE 23-1: BLOCK DIAGRAM OF TIMER0
23.1 Timer0 Operation
The T ime r0 module can be used as either an 8-b it timer
or an 8-bit counter.
23.1.1 8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
select ed by c learin g the T0 CS bit in the OPTION _REG
register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
23.1.2 8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin. The
incrementing edge is determined by the
OPTION_REG<T0SE> bit.
8-Bit Counter mode usin g the T0CK I pin is selected by
setting the OPTION_REG<T0CS> bit to ‘1’.
23.1.3 SOFTWARE-PROGRAMMABLE
PRESCALER
A single software-programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the OPTION_REG<PSA>
bit. To assig n the prescaler to T imer0 , the PSA bit must
be cleared to ‘0’.
There are eight prescaler options for the Timer0
module ranging from 1: 2 to 1:2 56. The presca le value s
are selectable via the PS<2:0> bits in the
OPTION_REG register . In order to have a 1:1 prescaler
value for the Timer0 module, the prescaler must be
disabled by setting the OPTION_REG<PSA> bit.
The prescaler is not readable or writable. When
assigned to the T im er0 module, all i nstructions writing to
the TMR0 register will clear the prescaler.
T0CKI
TMR0SE
TMR0
PS<2:0>
Data Bus
Set Flag bit TMR0IF
on Overflow
TMR0CS
0
1
0
18
8
8-bit
Prescaler
FOSC/4
PSA
Sync
2 T
CY
Overflow to Timer1
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two-instruction cycle delay when
TMR0 is written.
MCP19118/19
DS20005350A-page 136 2014 Microchip Technology Inc.
23.1.4 SWITCHING PRESCA LE R
BETWEEN TIMER0 AND WDT
MODULES
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values . When chan gin g th e presca le r ass ig nme nt fro m
Timer0 to the WDT module, the instruction sequence
shown in Example 23-1 must be executed.
EXAMPLE 23-1: CHANGING PRE SCALER
(TIMER0 WDT)
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequ en c e m us t be ex ec u ted (see Example 23-2).
EXAMPLE 23-2: CHANGING PRESCALER
(WDT TIMER0)
23.1.5 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The
INTCON<T0IF> interrupt flag bit is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit can only
be cleared in software. The Timer0 interrupt enable is
the INTCON<T0IE> bit.
23.1.6 USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Coun ter mo de, t he synchronizatio n
of the T0CKI input and the Timer0 register is
accomplished by samp ling the prescaler ou tput on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements, as
shown in Section 5.0 “Digital Electrical
Characteristics”.
23.1.7 OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
BANKSEL TMR0 ;
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W ;bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ;to 1:32
CLRWDT ;Clear WDT and
;prescaler
BANKSEL OPTION_REG ;
MOVLW b’11110000’ ;Mask TMR0 select and
ANDWF OPTION_REG,W ;prescaler bits
IORLW b’00000011’ ;Set prescale to 1:16
MOVWF OPTION_REG ;
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 96
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 77
TMR0 Timer0 Module Register 135*
TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114
Legend: — = Unimplemented locations, read as ‘0’. Shad ed cells ar e not used by th e Timer0 module.
* Page provid es regi st er inform ation.
2014 Microchip Technology Inc. DS20005350A-page 137
MCP19118/19
24.0 T IMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer with the following
features:
• 16-bit timer register pair (TMR1H:TMR1L)
• Readable and Writable (both registers)
• Selectable internal clock source
• 2-bit prescaler
• Inter rupt on ov erflow
Figure 24-1 is a block diagram of the Timer1 module.
FIGURE 24-1: TIMER1 BLOCK DIAGRAM
24.1 Timer1 Operation
The T imer1 module is a 16-bit incrementi ng timer which
is accessed through the TMR1H:TMR1L register pair.
Writes to TMR1H or TMR1L directly update the
counter. The timer is incremented on every instruction
cycle.
Timer1 is enabled by configuring the
T1CON<TMR1ON> bit. Table 24-1 displays the Timer1
enable selectio ns .
24.2 Clock Source Selection
The T1CON<TMR1CS> bit is used to select the clock
source for Timer1. Table 24-1 displays the clock source
selections.
24.2.1 INTERNAL CLOCK SOURCE
The TMR1H:TMR1L register pair will increment on
multiples of FOSC or FOSC/4 as determined by the
Timer1 prescaler.
As an example, when the FOSC internal clock source is
selected, the T imer1 regist er value will increment by four
count s every instruction c lock cycle .
TMR1H TMR1L
TMR1CS T1CKPS<1:0>
Prescaler
1, 2, 4, 8
1
02
Set flag bit
TMR1IF on
Overflow TMR1(1)
TMR1ON
Note 1: TMR1 register increments on rising edge.
FOSC
FOSC/4
TABLE 24-1: CLOCK SOURCE
SELECTIONS
TMR1CS Clock Source
18 MHz system clock (FOSC)
02 MHz instruction clock (FOSC/4)
MCP19118/19
DS20005350A-page 138 2014 Microchip Technology Inc.
24.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CON<T1CKPS> bits
control the prescale counter . The prescale counter is not
directly readable or writable; however, the prescaler
counter is cleared upon a w rite to TMR1 H or TMR1L.
24.4 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt f lag bi t i n the PIR 1 regi ste r i s
set. To enable the interrupt on rollover, you must set
these bits:
• T1C ON<T MR1ON> bit
• PIE1<TMR1IE> bit
• INTCON<PEIE> bit
• INTCON<GIE> bit
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
24.5 Timer1 in Sleep
Unlike other standard mid-range Timer1 modules, the
MCP19118/19 Timer1 module only clocks from an
internal system clock and thus does not run during
Sleep mode, nor can it be used to wake the device from
this mode.
24.6 Timer1 Control Register
The T ime r1 Control (T1 CON) register is used to co ntrol
Timer1 and select the various features of the Timer1
module.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
REGISTER 24-1: T1CON: TIMER1 CONTROL REGISTER
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
—— T1CKPS1 T1CKPS0 —— TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TMR1CS: Tim er1 Cloc k Sourc e Contro l bit
1 = 8 M Hz system clo ck (FOSC)
0 = 2 MHz instruction clock (FOSC)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = S tops Timer1, Clears Timer1 gate flip-flop
2014 Microchip Technology Inc. DS20005350A-page 139
MCP19118/19
TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 95
PIE1 —ADIE BCLIE SSPIE — — TMR2IE TMR1IE 95
PIR1 —ADIF BCLIF SSPIF — — TMR2IF TMR1IF 98
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 137*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 137*
T1CON —— T1CKPS1 T1CKPS0 —— TMR1CS TMR1ON 138
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.
MCP19118/19
DS20005350A-page 140 2014 Microchip Technology Inc.
25.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
• 8-bit timer register (TMR2)
• 8-bit period register (PR2)
• Interrupt on TMR2 match with PR2
• Software-programmable prescaler (1:1, 1:4, 1:16)
See Figure 25-1 for a block diagram of Timer2.
25.1 Timer2 Operation
The clock input to the Timer2 module is the system
clock (FOSC). The cl ock is fed into the T imer2 pre scaler ,
which has prescaler options of 1:1, 1:4 or 1:16. The
output of the prescaler is then used to increment the
TMR2 register.
The val ues of T MR2 and PR2 are co nstan tly com pared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, TMR2 is reset to 00h on the next
incr em ent cy cl e.
The match output of the Timer2/PR2 comparator is
used to set the PIR1<TMR2IF>.
The TMR2 and PR2 registers are both fully readable
and w rita ble. O n any Rese t, the TMR2 regis ter is set to
00h and the PR2 register is set to FFh.
Time r2 is tur ned on by sett ing the T 2C ON<TM R2ON>
bit to a ‘1’. T imer2 is turn ed off by clearing the TMR2ON
bit to a ‘0’.
The Timer2 prescaler is controlled by the
T2CON<T2CKPS> bits. The prescaler counter is
cleared when:
• A write to TMR2 occurs
• A write to T2CON occurs
• Any device Reset occurs (Power-On Reset,
MCLR Reset, Watchdog Timer Reset or
Brown-Out Reset)
FIGURE 25-1: TIMER2 BLOCK DIAGRAM
Note: TMR2 is not cleared when T2CON is
written.
Comparator
TMR2 Sets Flag
TMR2
Output
Reset
Prescaler
PR2
2
FOSC 1:1, 1:4, 1:8, 1:16
EQ
bit TMR2IF
T2CKPS<1:0>
2014 Microchip Technology Inc. DS20005350A-page 141
MCP19118/19
25.2 Timer2 Control Register
REGISTER 25-1: T2CON: TIMER2 CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 TMR2ON: Ti mer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
10 =Prescaler is 8
11 =Prescaler is 16
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 95
PIE1 —ADIE BCLIE SSPIE ——TMR2IETMR1IE 96
PIR1 —ADIF BCLIF SSPIF ——TMR2IFTMR1IF 98
PR2 Timer2 Module Period Register 140*
T2CON ————— TMR2ON T2CKPS1 T2CKPS0 141
TMR2 Holding Register for the 8-bit TMR2 Time Base 140*
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.
MCP19118/19
DS20005350A-page 142 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 143
MCP19118/19
26.0 PWM MODULE
The CCP module implemented on the MCP19118/19
is a modified version of the CCP module found in
standard mid-range microcontrollers. In the
MCP19118/19, the PWM module is used to generate
the system clock or system oscillator. This system
clock will control the MCP19118/19 switching
frequency, as well as set the maximum allowable duty
cycle. The PW M modu le does not co ntinuo usly a djust
the duty cycle to control the output voltage. This is
accomplished by the analog control loop and
associat ed cir cuitry.
26.1 Standard Pulse-Width Modulation
(PWM) Mode
The PWM module output signal is used to set the
operating switching frequency and maximum
allowable duty cycle of the MCP19118/19. The actual
duty cycle on the HDRV and LDRV is controlled by the
analog PWM control loop. However, this duty cycle
cannot be greater than the value in the PWMRL
register.
There are two modes of operation that concern the
system clock PWM signal. These modes are
stand-alone (nonfrequency synchronization) and
frequenc y sy nc hronization.
26.1.1 STAND-ALONE (NONFREQUENCY
SYNCHRONIZATION) MODE
When the MCP19118/19 is running stand-alone, the
PWM signal functions as the system clock. It is
operating at the programmed switching frequency with
a programmed maximum duty cycle (DCLOCK). The
programmed maximum duty cycle is not adjusted on a
cycle-by-cycle basis to control the MCP19118/19
system output. The required duty cycle (DBUCK) to
control the output is adjusted by the MCP19118/19
analog control loop and associated circuitry. DCLOCK
does, however, set the maximum allowable DBUCK.
EQUATION 26-1:
26.1.2 SWITCHING FREQUENCY
SYNCHRONIZATION MODE
The MCP19118/19 can be programmed to be a
switching frequency MASTER or SLAVE device. The
MASTER device functions as described in
Section 26.1.1 “Stand-Alone (NonFrequency
Synchronization) Mode” with the exception of the
system clock also being applied to GPA1.
A SLAVE device will receive the MASTER system
clock on GPA1. This MASTER system clock will be
OR’ed with the output of the TIMER2 module. This
OR’ed signal will latch PWMRL into PWMRH and
PWMPHL into PWMPHH.
Figure 26-1 shows a simplified block diagram of the
CCP module in PWM mode.
The PWMPHL register allows for a phase shift to be
added to the SLAVE system clock.
It is des ired to have th e MCP19 118/19 SLAVE device’ s
system clock start point shifted by a programmed
amount from the MASTER system clock. This SLAVE
phase shift is specified by writing to the PWMPHL
register. The SLAVE phase shift can be calculated by
using the following equation.
EQUATION 26-2:
DBUCK 1D
CLOCK
–
SLAVE PHASE SHIFT=PWMPHL•TOSC•(T2 PRESCALE VALUE)
MCP19118/19
DS20005350A-page 144 2014 Microchip Technology Inc.
FIGURE 26-1: SIMPLIFIED PWM BLOCK DIAGRAM
A PWM output (Figure 26-2) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 26-2: PW M OUTP UT
26.1.3 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation:
EQUATION 26-3:
When TMR2 is equal to PR2, the following two events
occur on the next increment cycle:
•TMR2 is cleared
• The PWM du ty c ycle is l atc hed from PWM RL in to
PWMRH
CLKPIN_IN
R
SQ
QOSC SYSTEM
CLOCK
LATCH DATA
LATCH DATA
RESET TIMER
8 8
88
Comparator Comparator
Comparator
TMR2
(Note 1)
88
8
8
PR2
PWMPHL PWMRL
PWMRH
(SLAVE)
PWMPHH
(SLAVE)
Note 1: TIMER 2 should be clocked by FOSC (8 MHz).
Period
Duty Cycle
TMR2 = PR2 + 1
TMR2 = PWMRH
TMR2 = PR2 + 1
PWM PERIOD=[(PR2)+1] x TOSC x(T2 PRESCAL E VALUE)
2014 Microchip Technology Inc. DS20005350A-page 145
MCP19118/19
26.1.4 PWM DUTY CYCLE (DCLOCK)
The PWM duty cycle (DCLOCK) is specified by writing
to the PWMRL register. Up to 8-bit resolution is
available. The following equation is used to calculate
the PWM duty cycle (DCLOCK):
EQUATION 26-4:
The PWMRL bits can be written to at any time, but the
duty cycle value is not latched into PWMRH until after
a match between PR2 and TMR2 occurs.
26.2 Operation during Sleep
When the device is placed in Sleep, the allocated
timer w ill not increm ent and the st a te of the modul e wil l
not change. If the CLKPIN pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
PWM DUTY CYCLE=PWMRL x TOSC x(T2 PRESCALE VALUE)
TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH PWM MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
APFCON — — — — — — — CLKSEL 112
T2CON — — — — — TMR2ON T2CKPS1 T2CKPS0 141
PR2 Timer2 Module Period Register 140*
PWMRL PWM Register Low Byte 143*
PWMPHL SLAVE Phase Shift Byte 143*
BUFFCON MLTPH2 MLTPH1 MLTPH0 ASEL4 ASEL3 ASEL2 ASEL1 ASEL0 58
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode.
* Page provides register information.
MCP19118/19
DS20005350A-page 146 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 147
MCP19118/19
27.0 MASTER SY NCHRONOUS
SERIAL PORT (MS SP)
MODULE
27.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
periphera l or m icroc ontroll er dev ices. Th ese p eriphera l
devices may be Serial EEPROMs, shift registers,
displa y drivers, A/D converte rs, etc. The MSSP modul e
only operates in Inter-Integrated Circuit (I2C) mode.
The I2C interface supports the following modes and
features:
•Master mode
• Slave mode
• Byte NACKi ng (Slav e mo de)
• Limited Multi-Master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Dual Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 27-1 is a block diagram of the I2C interface
module in Master mode. Figure 27-2 is a diagram of the
I2C interface module in Slave mode.
FIGURE 27-1: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Read Write
SSPSR
Start bit, Stop bit,
Start bit detect ,
SSPBUF
Internal
data bus
Set/Reset: S, P, SSPST AT, WCOL, SSPxOV
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate (SSPCO N2)
Stop bit detect,
Write collision detect,
Cl ock arbitration ,
Stat e counte r f or,
end of XMI T/ RC V,
SCL
SCL in
Bus Collision
SDA in
Receive Enable (RCEN)
Clock Cntl
Clock arbitrate /BC O L detect
(Hold off clock source)
[SSPM 3:0]
Baud rate
Reset SEN, PEN (SSPCON 2)
generator
(SSPADD)
Address Match detect
Set SS PIF, BCLIF
MCP19118/19
DS20005350A-page 148 2014 Microchip Technology Inc.
FIGURE 27-2: MSSP BLOCK DIAGRAM (I2C SLAVE M ODE)
27.2 I2C MODE OVERVIEW
The Inter-Integrated Circuit Bus (I2C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment, where the master
devices initiate the communication. A slave device is
controlled through addressing.
The MSSP module has eight registers for I2C
operation. They are the:
• MSSP Status Register (SSPSTAT)
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Control Register3 (SSPCON3)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
• MSSP Address Register2 (SSPADD2)
• MSSP Address Mask Register1 (SSPMSK)
• MSSP Address Mask Register2 (SSPMSK2)
The SSPCON1 regi ster is u sed to define the I2C mode.
Four selection bits (SSPCON1<3:0>) allow one of the
following I2C modes to be selected:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Master mode, clock = OSC/4 (SSPADD +1)
•I
2C firmware controlled Master mode (Slave idle)
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the data received byte
was data or address, if the next byte is completion of
the 10-bi t address and if this will be a read or wr ite dat a
transfer.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operation, the
SSPBUF and SSPSR create a double buffer receiver.
This allows reception of the next byte to begin before
reading the last byte of received data. When the
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred, the SSPOV
bit (SSPCON1<6>) i s set and the byte i n the SSPSR i s
lost.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
SCL
SDA
Shift
Clock
MSb LSb
SSPMSK Reg
2014 Microchip Technology Inc. DS20005350A-page 149
MCP19118/19
The I2C bus specifies two signal connections:
• Ser ial Clock (SCL)
• Serial Data (SDA)
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply vo ltage. Pu lli ng the l ine to gro und is con si dere d
a logical zero; letting the line float is considered a
logical one.
Before selecting any I2C mode, the SC L and SD A pin s
must be programmed to inputs by setting the
appropriate TRIS bits. Selecting I2C mode, by setting
the SSPEN bit, enables the SCL and SDA pins to be
used as clock and data lines in I2C mode.
Figure 27-3 shows a typical connection between two
devices configured as master and slave.
FIGURE 27-3: I2C MASTER/SLAVE
CONNECTION
The I2C bus can operate with one or more master
devices and one or more slave devices.
There are four pote nti al mo des o f o pera tion for a g ive n
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is rec eiving data from a slave )
•Slave Transmit mode
(slave is transmitting data to a master)
• Slave Rece ive mode
(slave is receiving data from the master)
To begin communication, a master device starts out in
Master T ransmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a
single Read/Write bit, which determines whether the
master intends to transmit to or receive data from the
slave dev ic e.
If the requested slave exists on the bus, it will respond
with an Acknowledge bi t, othe rw ise kno w n as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the
complement, either in Receive mode or Transmit
mode, respectivel y.
A Sta rt bit is indic at ed by a high-to -low tran si tio n of the
SDA line while the SCL line is held high. Address and
data bytes are se nt out, Most S ignifi cant b it (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave and is sent
out as a l ogica l zero when it i ntends to wri te dat a to th e
slave.
The Acknowledge (ACK) bit is an active-low signal,
which holds the SDA line low to indicate to the
transmitter that the slave device has received the
transmitted data and is ready to receive more.
The transition of a data bit is always performed while
the SCL line is held low . Transitions tha t occur while th e
SCL line is held high are used to indicate Start an d Stop
bits.
If the master intends to write to the slave, then it
repeatedly sends out a byte of data, with the slave
responding after each byte with an ACK bit. In this
example, the maste r device is in Master T ransmit mode
and the slave i s in Sl ave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave and
responds after each byte with an ACK bit. In this
exampl e, the master de vice is in Ma ster Rece ive mod e
and the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the t ransmiss ion by sendin g a S top bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDA line,
while the SCL line is held high.
In some cases, the master may want to maintain
control o f the bu s and rein itiate ano ther transm ission. If
so, the master device may send another Start bit in
place of the S top bit or last ACK bit when it is in Receive
mode.
The I2C bus specifies three me ssage protocols:
• Single message where a master writes data to a
slave
• Single message where a master reads data from
a slave
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves
When one devic e i s trans m itti ng a log ic al one or lettin g
the line float and a second device is transmitting a
logical zero or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on th e SCL lin e, is call ed clock st retching .
Clock stretching gives slave devices a mechanism to
control the flow of da ta. Wh en this de tectio n is used on
the SD A li ne , i t i s ca lle d arbi tration. Arbitra tion ensure s
that there is only one master device communicating at
any si ngl e time .
Master
SCL
SDA
SCL
SDA
Slave
VDD
VDD
MCP19118/19
DS20005350A-page 150 2014 Microchip Technology Inc.
27.2.1 CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfe r of mo re data through the
process of Clock Stretching. An addressed slave
dev ice may ho ld t he SC L cloc k lin e low aft er re ceiv ing
or sending a bit, indicating that it is not yet ready to
continue. The master that is communicating with the
slave will attempt to raise the SCL line in order to
transfer the next bit, but will detect that the clock line
has not yet been released. Because the SCL
connection is open-drain, the slave has the ability to
hold that line low until it is ready to continue
communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
27.2.2 ARBITRATION
Each mas ter dev ic e mu st m on ito r the b us f or Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message unti l the bus retu rns to an
Idle st a te.
However, two master devices may try to initiate a
transmission on or about the same time. When this
occurs, the process of arbitration begins. Each
transmitter checks the level of the SDA data line and
compares it to the level that it expects to find. The first
transmitter to observe that the two levels don't match
loses arbitration and must stop transmitting on the SDA
line.
For example, if one transmitter holds the SDA line to a
logica l one (lets it fl oat) and a se co nd tran sm itte r holds
it to a logical zero (pulls it low), the result is that the
SDA line wil l be low. The first tra nsmitter then observe s
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any
complications, because so far, the transmission
appears exactly as expected with no other transmitter
disturbing the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
dif ferent sla ve devices a t the addr ess stag e, the mast er
sending the lower slave address always wins
arbitration. When two master devices send messages
to the same slave address and addresses can
sometimes refer to multiple slaves, the arbitration
process must continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
27.3 I2C MODE OPERATION
All MSSP I2C communication is byte-oriented and
shifted out MSb first. Six SFR registers and two
interrupt flags interface the module with the PIC
microcontroller and user software. Two pins, SDA and
SCL, are exercised by the module to communicate
with other external I2C devi ces.
27.3.1 BYTE FORM AT
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa,
followed by an Acknowledge bit sent back. After the
8th falling edge of the SCL line, the device outputting
data on the SDA changes that pin to an input and
reads in an acknowledge value on the next clock
pulse.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
27.3.2 DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
27.3.3 SDA AND SCL PINS
On the MCP19118/19, the SCL and SDA pins are
always open-drain. These pins should be set by the
user to inputs by setting the appropriate TRIS bits.
Note: Data is tied to output zero when an I2C
mode is enabled.
2014 Microchip Technology Inc. DS20005350A-page 151
MCP19118/19
27.3.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SSP-
CON3<SDAHT> bit. Hold time is the time SDA is held
valid after the falling edge of SCL. Setting the SDAHT
bit selects a longer 300 ns minimum hold time and may
help on buses with large capacitance.
27.3.5 START CONDITION
The I2C specification defines a Start condition as a
transition of SDA from a high to a low state, while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 27-4 shows the wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This doe s not co nform to the I2C Specification th at
states no bus collision can occur on a Start.
27.3.6 STOP CONDITION
A Stop co nditio n is a tra nsition of the SDA line from a
low state to a high state while the SCL line is high.
27.3.7 RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address . The mas te r may want to ad dress th e same or
another slave.
In 10-bit Addressing Slave mode, a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed,
matching both high and low address bytes, the master
can issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a fu ll m atc h wi th R/W clear in 10-b it mode, a prior
match flag is set and maintained. Until a Stop
condition, a high address with R/W clear or a high
address match fails.
TABLE 27-1: I2C BUS TERMS
TERM Description
Transmitter The device which shifts data out onto the bus.
Receiver The device which shifts data in from the bus.
Master The device that initiates a transfer, generates clock signals and terminates a transfer.
Slave The device addressed by the master.
Multi-Master A bus with more than one device that can initiate data transfers.
Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration
ensures that the message is not corrupted.
Synchronization Procedure to synchronize the clocks of two or more devices on the bus.
Idle No master is controlling the bus and both SDA and SCL lines are high.
Active Any time one or more master devices are controlling the bus.
Addressed Slave Slave device that has received a matching address and is actively being clocked by a master.
Matching Address Address byte that is clocked into a slave that matches the value stored in SSPADDx.
Write Request Slave receives a matching address with R/W bit clear and is ready to clock in data.
Read Request Master send s an ad dress byte w ith th e R/W bit set, in dicati ng tha t it wi shes to clo ck dat a o ut of
the slave. This data is the next and all following bytes until a Restart or Stop.
Clock Stretching When a device on the bus holds SCL low to stall communication.
Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high
state.
Note: At least one SCL low time must appear
before a Stop is valid. Therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
MCP19118/19
DS20005350A-page 152 2014 Microchip Technology Inc.
27.3.8 START/STOP CONDITION
INTERRUPT MASKING
The SSPCON3<SCIE> and SSPCON3<PCIE> bits
can enable the generation of an interrupt in slave
modes that do not typically support this function.
These bits will have no effect on slave modes where
inter rupt on Start and Stop detec t are a lready enab led.
FIGURE 27-4: I2C START AND STOP CONDITIONS
FIGURE 27-5: I2C RESTART CONDITION
27.3.9 ACKNOWLEDGE SEQUENCE
The 9th SCL pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low si gnal, pul l ing the
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The result of an ACK is placed in the
SSPCON2<ACKSTAT> bit.
Slave software, when the AHEN and DHEN bits are
set, allows the user to set the ACK value sent back to
the transmitter. The SSPCON2<ACKDT> bit is
set/cleared to determine the response.
Slave hardware will generate an ACK response if the
SSPCON3<AHEN> and SSPCON3<DHEN> bits are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the SSPSTAT<BF> bit or the
SSPCON1<SSPOV> bit are set when a byte is
received, an ACK will not be sent.
When the module is addressed, after the 8th falling
edge of SCL on the bus, the SSPCON3<ACKTIM> bit
is set. The ACKTIM bit indic ates the acknowl edge tim e
of the active bus. The ACKTIM Status bit is only active
when the AHEN bit or DHEN bit is enabled.
SDA
SCL P
Stop
Condition
S
Start
Condition
Change of
Data Allowed
Change of
Data Allowed
Restart
Condition
Sr
Change of
Data Allowed
Change of
Data Allowed
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27.4 I2C SLAVE MODE OPERATION
The MSSP Slave mode operates in one of the four
modes selected in the SSPCON1<SSPM> bits. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing mode operates the same as
7-bit, with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operate the
same as the other modes. The exception is the SSPIF
bit getti ng set u pon de tectio n of a Start, Re st art or Stop
condition.
27.4.1 SLAVE MODE ADDRESSES,
SSPADD
The SSPADD register contains the Slave mode
address. The first byte received after a Start or Restart
condition is compared against the value stored in this
register. If the byte matches, the value is loaded into
the SSPBUF register and an interrupt is generated. If
the val ue does not m atch, t he mod ule go es idl e and n o
indication is given to the software that anything
happened.
The SSPMSK register affects the address matching
process. See Section 27.4.10 “SSPMSKx Register”
for more information.
27.4.2 SECOND SLAVE MODE ADDRESS,
SSPADD2
The SSPADD2 register co nt ains a seco nd Slave mode
address. To enable the use of this second Slave mode
address, bit 0 must be set. The first byte received after
a Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPBUF register and an
interrupt is generated. If the value does not match, the
module goes Idle and no indication is given to the
software that anything happened.
The SSPMSK2 register affects the address matching
process. See Section 27.4.10 “SSPMSKx Register”
for more information.
27.4.2.1 I2C Slave 7-Bit Addressing Mode
In 7-bit Addre ss in g m od e, t he LSb of t he received da t a
byte is i gnored w hen d eterminin g if there i s an add ress
match.
27.4.2.2 I2C Slave 10-Bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
comp are d t o th e b ina ry v al ue of ‘ 1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 in the SSPADDx register.
After the acknowledge of the high byte, the UA bit is
set and SCL is held low until the user updates
SSPADDx with the low address. The low address byte
is cl oc ke d in an d al l ei g ht bi ts ar e c ompar e d t o the lo w
address value in SSPADDx. Even if there is no
address match, SSPIF and UA are set and SCL is hel d
low until SSPADDx is updated to receive a high byte
again. When SSPADDx is updated, the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing
communication. A transmission can be initiated by
issuing a Restart once the slave is addressed and
clocking in the high address with the R/W bit set. The
slave hardware will then acknowledge the read
request and prepare to clock out data. This is only
valid for a slave after it has received a complete high
and low address byte match.
27.4.3 SLAVE RECEP TION
When the R/W bi t of a ma tc hin g re ce iv ed add res s by te
is clear, the SSPSTAT<R/W> bit is cleared. The
received address is loaded into the SSPBUF register
and acknowledged.
When an overflow condition exists for a received
address , then a Not Acknowl edge is given. An overfl ow
condition is defined as either SSPSTAT<BF> bit or bit
SSPCON1<SSPOV> bit is set. The
SSPCON3<BOEN> bit modifies this operation. For
more information, see Register 27-5.
An MSSP interrupt is generated for each transferred
data b yte. Flag bit, SSPIF, must be clear ed by software.
When the SSPCON2<SEN> bit is set, SCL will be held
low (clock stretch) following each received byte. The
clock must be released by setting the
SSPCON1<CKP> bit, except sometimes in 10-bit
mode.
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DS20005350A-page 154 2014 Microchip Technology Inc.
27.4.3.1 7-Bit Addressing Reception
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
7-bit Addressing mode, all decisions made by
hardware or software and their effect on reception.
Figures 27-6 and 27-7 are used as a visual reference
for this description.
This is a step-by-step process of what typically must
be done to accomplish I2C communication.
1. Start bit detected.
2. SSPSTAT<S> bit is set; SSPIF is set i f Interrupt-
on-Start detect is enabled.
3. Matching a ddress with R/W bit clear i s received.
4. The sla ve pulls SDA low, sending an ACK to the
master, and sets SSPIF bit.
5. Software clears the SSPIF bit.
6. Software re ads received address from SSPBUF,
clearing the BF flag.
7. If SEN = 1, slave software sets CKP bit to
release the SCL line.
8. The master clocks out a data byte.
9. Slave drives SDA low, sending an ACK to the
master, and sets SSPIF bit.
10. Software clears SSPIF.
1 1. Software reads the received by te from SSPBUF,
clearing BF.
12. Steps 8–12 are repeated for all received bytes
from the master .
13. Master sends Stop condition, setting
SSPSTAT<P> bit, and the bus goes Idle.
27.4.3.2 7-Bit Reception with AHEN and
DHEN
Slave device reception with AHEN and DHEN set
operat es the sa me as w i tho ut th es e op tions, with extra
interrupts and clock stretching added after the 8th
falling edge of SCL. These additional interrupts allow
the slave software to decide whether it wants to ACK
the receive address or data byte, rather than the
hardware. This functionality adds support for PMBus
that was not present on previous versions of this
module.
This list describes the steps that need to be taken by
slave software to use these options for I2C
communication. Figure 27-8 displays a module using
both address and data holding. Figure 27-9 includes
the operation with the SSPCON2<SEN> bit set.
1. SSPSTAT<S> bit is set; SSPIF is set if interrupt
on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
falling edge of SCL.
3. Slave clears the SSPIF.
4. Slave can look at the SSPCON3<ACKTIM> bit
to determine if th e SSPIF was after or before the
ACK.
5. Slave reads the address value from SSPBUF,
clearing the BF flag.
6. Slave sets ACK value cloc ke d out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPIF.
1 1. SSPIF set and CKP cleared af ter 8th falling edge
of SCL for a received data byte.
12. Slave looks at SSPCON3<ACKTIM> bit to
determine the source of the interrupt.
13. Slave reads the received data from SSPBUF
clearing BF.
14. S tep s 7–1 4 are the s ame f or eac h rece ived dat a
byte.
15. Communication is ended by either the slave
sending an ACK =1 or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is d is abl ed, the sl av e wil l only know
by polli ng the SSTSTAT<P> b it.
Note: SSPIF is still set after the 9th falling edge of
SCL even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to master is SSPIF not set.
2014 Microchip Technology Inc. DS20005350A-page 155
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FIGURE 27-6: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Receiving Addr ess
ACK
Receiving Data
ACK
Receiving Data ACK =1
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
SSPIF
BF
SSPOV
12345678 12345678 12345678
999
ACK is not sent.
SSPOV set because
SSPBUF is still full.
Cleared by software
First byte
of data is
available
in SSPBUF
SSPBUF is read
SSPIF set on 9th
falling edge of
SCL
Cleared by software
P
Bus master sends
Stop condition
S
From slave to master
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DS20005350A-page 156 2014 Microchip Technology Inc.
FIGURE 27-7: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
SEN SEN
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL 123456789 123456789 123456789 P
SSPIF set on 9th
SCL is not held
CKP is written to 1 in software,
CKP is written to ‘1’ in software,
ACK
low because
falling edge of SCL
releasing SCL
ACK is not sent.
Bus master sends
CKP
SSPOV
BF
SSPIF
SSPOV set because
SSPBUF is still full.
Cleared by software
First byte
of data is
available
in SSPBUF
ACK=1
Cleared by software
SSPBUF is read
Clock is held low until CKP is set to ‘1’
releasing SCL
Stop condition
S
ACK ACK
Receive Ad dr ess Receive D ata Receive Data
R/W=0
2014 Microchip Technology Inc. DS20005350A-page 157
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FIGURE 27-8: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Receiving Address Receiving Data Received Data
P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
BF
CKP
S
P
12345678 912345678 912345678
Master sends
Stop cond iti on
S
Data is read from SSPBUF
Cleared by software
SSPIF is set on
9th falling edge of
SCL, after ACK
CKP set by software,
SCL is released
Slave software
9
ACKTIM cleared by
hardwa re in 9th
rising edge of SCL
sets ACKDT to
NACK
When DHEN=1:
CKP i s cleared by
hardware on 8th falling
edge of SCL
Slave software
clears ACKDT to
ACK the received
byte
ACKTIM set by hardware
on 8th falling edge of SCL
When AHEN=1:
CKP is cleared by hardware
and SC L is stretched
Address is
read from
SSBUF
ACKTIM set by hardware
on 8th falling edge of SCL
ACK
Master r eleases SDAx
to slave for ACK sequence
No interrupt
after NACK
from slave
ACK=1
ACK
ACKDT
ACKTIM
SSPIF If AHEN = 1:
SSPIF is set
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FIGURE 27-9: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
Receiving Address Receive Data Receive Data
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
SSPIF
BF
ACKDT
CKP
S
P
ACK
S12345678 912345678 9 12345678 9
ACK
ACK
Clea r ed by software
ACKTIM is cleared by hardw are
SSPBUF can be
Set by so ftware,
read any time before
next by te is lo ad ed
rele ase SCL
on 9th rising edge of SCL
Received
address is loaded into
SSPBUF
Slave softw ar e cle ar s
ACK DT t o ACK
R/W = 0Master releases
SDA to slave for ACK sequence
the r eceived byt e
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
ACKTIM is set by hardware
on 8th falling edge of SCL
When DHEN = 1;
on the 8th fallin g ed ge
of SCL of a received
data byte, CKP is cleared
Rece iv ed data is
avai lable on SSPB UF
Slave s ends
NACK
CKP is not cl eared
if NACK
P
Master sends
Stop condition
No interrupt after
if NACK
from slave
ACKTIM
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27.4 .4 SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an ad dress matc h occurs , the SSPSTAT<R/W> bit
is set. The received address is loaded into the SSPBUF
register and an ACK pulse is sent by the slave on the
9th bit.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 27.4.7
“Clock S tretching” for more details). By stretching the
clock , the mast er will b e unable to asse rt anoth er cloc k
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSPBUF
register which also lo ads the SSPSR re gister. Then the
SCL pin should be released by setting the
SSPCON1<CKP> bit. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the 9th SCL input pulse. This ACK
value is copied to the SSPCON2<ACKSTAT> bit. If
ACKSTAT is set (NACK), then the data transfer is
complete. In this case, when the NACK is latched by the
slave, the slave goes Idle and waits for another
occurrence of the Start bit. If the SDA line was low
(ACK), the next transmit data must be loaded into the
SSPBUF register. Again, the SCL pin must be released
by setting the CKP bit.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the 9th clock pulse.
27.4.4.1 Slave Mode Bus Collision
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SSPCON3<SBCDE> bit is set, the
PIR<BCLIF> bi t is set. O nce a bus col lision is d etected,
the slave goes Idle and waits to be addressed again.
User software can use the BCLIF bit to handle a slave
bus co lli si on.
27.4.4.2 7-Bit Transmission
A master device ca n transmit a read request to a slave
and then clock data out of the slave. The list below
outlines what software for a slave will need to do to
accomplish a standard transmission. Figure 27-10 can
be used as a reference to this list.
1. Master sends a Start condition on SDA and
SCL.
2. SSPST AT<S> bit is set; SSPIF is set if Interrupt-
on-Start detect is enabled.
3. Matching address with R/W bit set is received by
the slave setting SSPIF bit.
4. Slave hardware generates an ACK and sets
SSPIF.
5. SSPIF bit is cleared by user.
6. Software reads the received address from
SSPBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
8. The slave software loads the transmit data into
SSPBUF.
9. CKP bit is set releasing SCL, allowing the
master to clock the data out of the slave.
10. SSPIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a NACK, the clock is not
held, but SSPIF is still set.
15. The master send s a Res tart co nditio n or a Sto p.
16. The slave is no longer addresse d.
Note 1:If the master ACKs, the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
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FIGURE 27-10 : I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Receiving Address Automatic Transmitting Data Automatic Transmitting Data
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA
SCL
SSPIF
BF
CKP
ACKSTAT
R/W
D/A
S
P
Received address
When R/W is set
R/W is copied fro m the
Indicates an address
is read from SSPBUF
SCL is always
held low after 9th SCL
fall ing edge
matching address byte
has been received
Master’s NACK
is copied to
ACKSTAT
CKP is not
held for
NACK
BF is automatically
cleared after 8th falling
edge of SCL
Data to transmit is
loaded into SSPBUF
Set by software
Cleared by softw a re
ACK
ACK
ACK
R/W = 1
SP
Master sends
Stop condition
2014 Microchip Technology Inc. DS20005350A-page 161
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27.4.4.3 7-Bit Transmission with Address
Hold Enabled
Setting the SSPCON3<AHEN> bit enables additional
clock stretching and interrupt generation after the 8th
falling edge of a received matching address. Once a
matchi ng addres s has bee n cloc ked in, CKP is cl eared
and the SSPIF interrupt is set.
Figure 27-11 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condi tio n; th e SSPSTAT<S>
bit is set; S SPIF is set if Interrupt-on-Start d etect
is enabled.
3. Master sends matching address with R/W bit
set. Afte r the 8th falling edge of th e SCL line , the
CKP bit is cleared and SSPIF interrupt is
generated.
4. Slave software clears SSPIF.
5. Slave software reads SSPCON3<ACKTIM> bit
and SSPSTAT<R/W> and SSPSTAT<D/A> bits
to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software de ci des from th is i nfo rmation i f it
wishes to ACK or NACK and sets
SSPCON2<ACKDT> bit accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clock s in the ACK value from the slave.
10. Slave hardware automatically clears the CKP b it
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an A CK value on th e 9th SCL pulse.
15. Slave hardware copies the ACK value into the
SSPCON2<ACKSTAT> bit.
16. Steps 10–15 are repeated for each byte
transmitted to th e master f rom the sl ave.
17. If the master sends a NACK, the slave releases
the bus, all ow in g the mast er to se nd a Stop and
end the communication.
Note: SSPBUF cannot be loaded until after the
ACK.
Note: Master must send a NACK on the last byte
to ensure that the slave releases the SCL
line to receive a Stop.
MCP19118/19
DS20005350A-page 162 2014 Microchip Technology Inc.
FIGURE 27-11: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
Receiving Address Automatic Transmitting Data Automatic Transmitting Data
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA
SCL
SSPIF
BF
ACKDT
ACKSTAT
CKP
R/W
D/A
Received add ress
is read from SSPBUF
BF is automatically
clear ed afte r 8th falling
edge of SCL
Data to transmit is
loaded into SSPBUF
Cleared by software
Slave clears
ACKDT to ACK
address
Master’s ACK
response is copied
to SSPSTAT
CKP not cleared
aft er NACK
Set by software,
releases SCL
ACKTIM is cleared
on 9th rising edge of SCL
ACKTIM is set on 8th falling
edge of SCL
Wh en AHEN = 1;
CKP is cleared by har dwar e
after receiving matching
address.
When R/W = 1;
CKP is always
cleared after ACK
SP
Master sends
Stop condition
ACK
R/W = 1
Master releases SDAx
to slave for ACK sequence
ACK ACK
ACKTIM
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27.4.5 SLAVE M ODE 10-BI T ADDR ES S
RECEPTION
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
10-bit Addressing mode.
Figure 27-12 is used as a visual reference for this
description.
This is a step-by-step process of what must be done
by slave software to accomplish I2C commun ication.
1. Bus starts Idle.
2. Master sends Start condition; SSPSTAT<S> bit
is set; SSPIF is set if Interrupt-on-Start detect is
enabled.
3. Master sends matc hing high address with R/W
bit clear; SSPSTAT<UA> bit is set.
4. Slave sends ACK and SSPIF is set.
5. Software clears the SSPIF bit.
6. Software re ads received address from SSPBUF,
clearing the BF flag.
7. Slave loads low address into SSPADDx,
releasing SCL.
8. Master sends matching low-address byte to the
slave; UA bit is set.
9. Slave sends ACK and SSPIF is set.
10. S lave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slave’s ACK on the 9th SC L pulse;
SSPIF is set.
14. If SSPCON2<S EN> bit is set, CKP is cleared b y
hardware and the clock is stretched.
15. S lave clears SSPIF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set, the slave sets CKP to release the
SCL.
18. Steps 13–17 repeat for each received byte.
19. Master sends St op to end the tran sm is si on.
27.4.6 10-BIT ADDRESSING
WITH ADDRESS OR DATA HOLD
Receptio n using 10-bit addressing with AHEN or DHEN
set is the same as wit h 7-bit modes. The on ly difference
is the need to update the SSPADDx register using the
UA bit. Al l func tional ity, spec ifical ly when the C KP bit i s
cleared and the SCL line is held low, are the same.
Figure 27-13 can be used as a reference of a slave in
10-bit addressing with AHEN set.
Figure 27-14 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
Note: Updat es to th e SSPADDx r egi ste r are not
all owed until after the ACK sequence.
Note: If the low address does not match, SSPIF
and UA are still set so that the slave
software can set SSPADDx back to the
high address. BF is not set because there
is no match. CKP is unaffected.
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DS20005350A-page 164 2014 Microchip Technology Inc.
FIGURE 27-12 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
SSPIF
Receive First Address Byte
ACK
Receive Second Address Byte
ACK
Receive Data
ACK
Receive Data
ACK
11110A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
UA
CKP
12345678912345678
9 123456789123456789P
Master sends
Stop condition
Cleared by software
Receive address is
Software updates SSPADD
Data is read
SCL is held low
Set by software,
while CKP = 0
from SSPBUF
releasing SCL
When SEN = 1;
CKP is cleared after
9th falling edge of r eceived byte
read from SSPBUF
and releases SCL
When UA = 1;
If address matches
Set by hardware
on 9th falling edge
SSPADD it i s loaded into
SSPBUF
SCL is held low
S
BF
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FIGURE 27-13 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
Receive First Address Byte
UA
Receive Second Address Byte
UA
Receive Data
ACK
Receive Data
1 1 1 1 0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
SDA
SCL
SSPIF
BF
ACKDT
UA
CKP
ACKTIM
12345678 9
S
ACK
ACK
12345678 91234567891
2
SSPBUF
is read from
Received data
SSPBUF can be
read anytime before
the next recei ved byte
Cleared by software
falling edge of SCL
not allowed until 9th
Update to SSPADD is
Set CKP with software
releases SCL
SCL
clears UA and releases
Update of SSPADD,
Set by hardware
on 9th falling edge
Slave software clears
ACKDT to ACK
the received byte
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
ACKTIM is set by hardware
on 8th falling edge of SCL
Cleared by software
R/W = 0
MCP19118/19
DS20005350A-page 166 2014 Microchip Technology Inc.
FIGURE 27-14 : I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
Receiving Address
ACK
Receiving Second Address Byte
Sr
Receive First Address Byte
ACK
Transmitting Data Byte
1 1 1 1 0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0
A9 A8 D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
SSPIF
BF
UA
CKP
R/W
D/A
123456789 123456789 123456789 123456789
ACK = 1
P
Master sends
Stop condition
Master sends
NACK
Master sends
Restart event
ACK
R/W = 0
S
Cleared by software
After SSPADD is
updated, UA is cleared
and SCL is released
High address is loaded
Received address is Data to transmit is
Set by software
Indicates an address
When R/W = 1;
R/W is copied from the
Set by hardware
UA indicates SSPADD
SSPBUF loaded
with received address
must be update d
has been received
loaded into SSPBUF
releases SCL
Master’s NACK
is copied
matching addr ess b yte
CKP is cleared on
9th falling edge of SCLx
read from SSPBUF
back into SSPADD
ACKSTAT
Set by hardware
2014 Microchip Technology Inc. DS20005350A-page 167
MCP19118/19
27.4.7 CLOCK STRETCHING
Clock stretching o ccurs when a device on the bu s holds
the SCL line low, effectively pausing communication.
The slave may stretch the clock to allow more time to
handle data or prepare a response for the master
device. A master device is not concerned with
stretching, as anytime it is active on the bus and not
transferri ng data it is stretchi ng. Any stretchin g done by
a slave is invisible to the master software and handled
by the hardware that generates SCL.
The SSPCON1<CKP> bit is used to control stretching
in software. Any time the CKP bit is cleared, the module
will wait for the SCL line to go low and then hold it.
Setting CKP will release SCL and allow more
communication.
27.4.7.1 Normal Clock Stretching
Following an ACK, if the SSPSTAT<R/W> bit is set,
causing a read request, the slave hardware will clear
CKP. This allows the slave time to update SSPBUF
with data to transfer to the master. If the
SSPCON2<SEN> bit is set, the slave hardware will
always stretch the clock after the ACK sequence.
Once the slave is ready, CKP is set by software and
communica tion resumes.
27.4.7. 2 10-Bit Add r ess i ng Mode
In 10-bit Addressing mode, when the UA bit is set, the
clock is alwa ys str etched . This is the onl y time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPADDx.
27.4.7.3 Byte NACKing
When SSPCON3<AHEN> bit is set, CKP is cleared by
the hardware after the 8th falling edge of SCL for a
received matching address byte. When
SSPCON3<DHEN> bit is set, CKP is cleared after the
8th falling edge of SCL for received data.
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
27.4.8 CLOCK SYNCHRONIZATION
AND THE CKP BIT
Any time the CKP bit is cleare d, the module will wait f or
the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SC L output is alre ady sampled lo w . The refore,
the CKP bi t will not ass ert the SCL lin e until an e xternal
I2C master device has already asserted the SCL line.
The S CL ou t p ut w i l l re ma i n l ow un til t h e C K P bi t is se t
and all other devices on the I2C bus have released
SCL. This ensures that a write to the CKP bit will not
violate the minimum high time requirement for SCL
(see Figure 27-15).
FIGURE 27-15: CLOCK SYNCHRONIZATION TIMING
Note 1: The BF bit has no effect on whether the
clock will be stretched or not. This is
different than previous versions of the
module that wo uld not s tretch the clock or
clear CKP, if SSPBUF was read before
the 9th falling edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPBUF was l oaded before t he 9th falling
edge of SCL. It is now alwa ys cleared for
read reques t s.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
SDA
SCL
DX ‚ – 1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON1
CKP
Master dev ic e
releases clock
Master dev ic e
asserts clock
MCP19118/19
DS20005350A-page 168 2014 Microchip Technology Inc.
27.4.9 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master device. The exception is the general call
address, which can address all devices. When this
address is used, all devices wi ll, in th eory, respond with
an acknowledge.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
SSPCON2<GCEN> bit is set, the slave module will
automatically ACK the reception of this address,
regardless of the value stored in SSPADDx. After the
slav e clocks in an address of all z eros with the R/W bit
clear, an interrupt is generated and slave software can
read SSPBUF and respond. Figure 27-16 shows a
gene ral ca ll reception seq ue nce .
In 10-bit Address mod e, the UA bit will not be set on th e
reception of the general call address. The slave will
prepare to receive the second byte as data, just as it
would in the 7-bit mode.
If the SSPCON3<AHEN> bit reg ister is set, j ust as with
any other address reception, the slave hardware will
stretch the clock after the 8th fa lling edge of SCL. The
slave must then set its ACKDT value and release the
clock with communication progressing as it would
normally.
FIGURE 27-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
27.4.10 SSPM SK X REGI S TER
An SSP Mask (SSPMSKx) register (Registers 27-6
and 27-8) is available in I2C Slave mode as a mask for
the value held in the SSPSRx register during an
address comparison operation. A zero (‘0’) bit in the
SSPMSKx register has the effect of making the
corresponding bit of the received address a “don’t
care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>
• 10-bit Add ress mode: ad dress compa re of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
R/W = 0
ACK
General Call Addr ess
Address is compared to General Call Address
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
GCEN (SSPCON2<7>)
’1’
2014 Microchip Technology Inc. DS20005350A-page 169
MCP19118/19
27.5 I2C Master Mode
Master mode is enabled by setting and clearing the
appropria te SSPCON1 < SSPM> bi t s and by se ttin g th e
SSPEN bit. In Master mode, the SDA and SCK pins
must be configured as inputs. The MSSP peripheral
hardware will override the output driver TRIS controls
when necessary, to drive the pins low.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set or the bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition detected
• Stop con dition detec ted
• Data transfer byte transmitted/received
• Acknowledg e transmitted/received
• Repea ted Start generate d
27.5.1 I2C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the begi nning of the ne xt seria l transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit w ill be l ogi c ‘ 0’. Ser ial da ta is
transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
and the end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will b e
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and the end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 27.6 “Baud
Rate Generator” for more details.
27.5.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin i s actua ll y sa mpled hig h. Wh en the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<7:0> and begins
counting. This ensures that the SCL high time will
always be at le ast one BRG rollover cou nt in the event
that the clock is held low by an external device
(Figure 27-17).
Note 1: The MSSP module, when configured in
I2C Mas ter m ode, d oes n ot al low que uing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediate ly write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPBUF did not occur.
2: When in Master mode, Start/Stop
detection is masked and an interrupt is
generated when the SEN/PEN bit is
cleared and the generation is complete.
MCP19118/19
DS20005350A-page 170 2014 Microchip Technology Inc.
FIGURE 27-17: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
27.5.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Trans mit seq uence is i n progre ss, th e
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is s et, it i nd icates th at a n a ction on SSPBUF
was attempted while the module was not Idle.
27.5.4 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable (SEN) bit in the SSPCON2 register. If the SDA
and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the SSPSTAT<S> bit to be
set. Following this, the Baud Rate Generator is
reloaded with the contents of SSPADD<7:0> and
resumes its count. When the Baud Rate Generator
times out (TBRG), the SSPCON2<SEN> bit will be
automatically cleared by hardware; the Baud Rate
Generat or i s su sp end ed , leaving t he SDA lin e h el d l ow
and the Start condition is complete.
FIGURE 27-18: FIRST STAR T BIT TIMING
SDA
SCL
SCL deasserted but slave holds
DX ‚ – 1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
Note: Beca use queuing of ev ents is not allo wed,
writing to the lower five bits in the
SSPCON2 register is disabled until the
Start condition is complete.
Note 1: If at the beginning of the Start condition
the SDA and SCL pins are already
sampled low, or if during the Start
condition the SCL line is sampled low
before the SDA line is driven low, a bus
collision occurs, the Bus Collision
Interrupt Flag, BCLIF, is set, the Start
condition is aborted and the I2C module is
reset into its Idle state.
2: The Philips I2C S pecification states that a
bus collision cannot occur on a Start.
SDA
SCL S
TBRG
1st bit 2nd bit
TBRG
SDA = 1, At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here Set S bit (SSPSTAT <3>)
and sets SSPIF bit
2014 Microchip Technology Inc. DS20005350A-page 171
MCP19118/19
27.5.5 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the
SSPCON2<RSEN> bit is programmed high and the
master state machine is no longer active. When the
RSEN bit i s set, the SCL p in is as se rted low. When th e
SCL pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDA pin is released
(brought high) for one Baud Rate Generator count
(TBRG). When the Baud Rate Generator times out, if
SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by the assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the SSPCON2<RSEN>
bit will be automatically cleared and the Baud Rate
Generator will not be reloaded, leaving the SDA pin
held low . As soon as a Start condition i s detected on the
SDA and SCL pins, the SSPSTAT<S> bit will be set.
The SSPIF bit will not be set until the Baud Rate
Generator has timed out.
FIGURE 27-19: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progre ss , it will not t ak e effect.
2: A bus collision during the Repeated Start
conditi on occ urs if:
•SDA is sampled low when SCL goes
from low-to-high.
•SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
SDA
SCL
Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,SDA = 1,
SCL (no chang e) SCL = 1
occurs here
TBRG TBRG TBRG
and sets SSPIF
Sr
MCP19118/19
DS20005350A-page 172 2014 Microchip Technology Inc.
27.5.6 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit addr ess is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full (BF) flag bit and will allow the Baud
Rate Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollove r count (TBRG). D at a should b e vali d before SCL
is released high . When the SCL pin is rel eased high, i t
is held that way for TBRG. The data on the SDA pin must
remain stabl e for that dur ation and s ome hold ti me after
the next falling edge of SCL. After the 8th bit is shifted
out (the falling edge of the 8th clock), the BF flag is
cleared and the master releases the SDA. This allows
the slave device being addressed to respond with an
ACK bit during the 9th bit time if an address match
occurre d or if da ta was received prope rly. The st atus of
ACK is written into the ACKSTAT b it on the rising edg e
of t he 9th clock. If the maste r receives an Acknowledge,
the Acknowledge Status (ACKSTAT) bit is cleared. If
not, the b it is set. Af ter the 9th clock, the SSPI F bit is set
and the master clock (Baud Rate Generator) is
suspended until the next data byte is loaded into the
SSPBUF, leaving SCL low and SDA unchanged
(Figure 27-20).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falli ng e dge of the 8th cl oc k, th e m aster will rel eas e
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the 9th clock, the
master will sample the SDA pin to see if the address
was rec ognized by a sla ve. The st atus of the ACK bit is
loaded into the SSPCON2<ACKSTAT> bit. Following
the falling edge of the 9th clock transmission of the
address, the SSPIF is set, the BF flag is cleared and
the Baud Rate Generator is turned off until another
write to the SSPBUF t akes pla ce, holdin g SCL low and
allowing SDA to float.
27.5.6.1 BF Status Flag
In Transmit mode, the SSPSTAT<BF> bit is set when
the CPU writes to SSPBUF and is cleared when all
eight bits are shifted out.
27.5.6.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
27.5.6.3 ACKSTAT Status Flag
In Transmit mode, the SSPCON2<ACKSTAT> bit is
cleared when the slave has sent an Acknowledge
(ACK =0) and is set when the slave does Not
Acknowledge (ACK =1). A slave sends an
Acknowledge when it has recognized its address
(including a general call) or when the slave has
properly received its data.
27.5.6.4 Typical Transmit Sequence
1. The user generates a Start condition by setting
the SSPCON2<SEN> bit.
2. SSPIF is set by hardware on completion of the
Start.
3. SSPIF is cleared by software.
4. The MSSP module will wait the required start
time before any other ope rati on takes place .
5. The user loads the SSPBUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPBUF is written to.
7. The MSSP module shif t s in the ACK bit f rom th e
slave device and writes its value into the
SSPCON2<ACKSTAT> bit.
8. The MSSP mo dule g enerate s an interrup t at th e
end of the 9th clock cycle by setting the SSPIF
bit.
9. The user loads the SSPBUF with eight bits of
data.
10. Data is shi fte d out the SD A pin un til all e ight bit s
are transmitted.
11. The MSSP module shif ts in th e ACK bit fr om the
slave device and writes its value into the
SSPCON2<ACKSTAT> bit.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the SSPCON2<PEN> or
SSPCON2<RSEN> bits. Interrupt is generated
once the Stop/Restart condition is complete.
2014 Microchip Technology Inc. DS20005350A-page 173
MCP19118/19
FIGURE 27-20 : I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0> )
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
R/W = 0
Transm it A ddr es s t o Sl ave
123456789 123456789 P
Cleared by software service routine
SSPBUF is written by software
from SSP interrupt
Af t er Start condition, SEN cl eared by hardwar e
S
SSPBUF wr i tten with 7- bit add re ss and R/W
start tra nsmit
SCL he ld lo w
while CPU
respond s to SSPIF
SEN = 0
of 10-bit A ddr ess
Write SSPCON2<0> S EN = 1
St art co ndition begins From slav e, clear AC KSTAT bit SSPCON2 <6>
ACKSTAT in
SSPCON2 = 1
Cleared by software
SSPBUF written
PEN
R/W
Cl eared by software
MCP19118/19
DS20005350A-page 174 2014 Microchip Technology Inc.
27.5.7 I2C MASTER MODE RECE PTI ON
Master mode recepti on is enab led by progra mmin g the
Receive Enable (RCEN) bit in the SSPCON2 register.
The Baud Rate Generator begins counting and on each
rollover the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the 8th clock, the
receive enable flag is automatically cleared, the
contents of the SSPSR are loaded into the SSPBUF,
the BF flag bit is set, the SSPIF flag bit is set and the
Baud Rate Generator is suspended from counting,
holding SCL low. The MSSP is now in Idle state
awaiti ng the n ext comm and. When the buf fer is read b y
the CPU, the BF flag bit is automatically cleared. The
user can then send an Acknowledge bit at the end of
reception by setting the Acknowledge Sequence
Enable (ACKEN) bit in the SSPCON2 register.
27.5.7.1 BF Status Flag
In receiv e op era tion , the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
27.5.7.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
27.5.7.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
27.5.7.4 Typical Receive Sequence
1. The user generates a Start condition by setting
the SSPCON2<SEN> bit.
2. SSPIF is set by hardware on completion of the
Start.
3. SSPIF is cleared by software.
4. The user writes SSPBUF with the slave address
to transmit and the R/W bit set.
5. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPBUF is written to.
6. The MSSP module shif t s in the ACK bit f rom th e
slave device and writes its value into the
SSPCON2<ACKSTAT> bit.
7. The MSSP mo dule g enerate s an interrup t at th e
end of the 9th clock cycle by setting the SSPIF
bit.
8. User sets the SSPCON2<RCEN> bit and the
master clocks in a byte from the slav e.
9. After the 8th falling edge of SCL, SSPIF and BF
are set.
10. Master clears SSPIF and reads the received
byte from SSPBUF, clears BF.
11. Master sets ACK value sent to slave in
SSPCON2<ACKDT> bit and initiates the ACK
by setting the ACKEN bit.
12. Master’s ACK is clocked out to the slave and
SSPIF is set.
13. The user clears SSPIF.
14. S teps 8–13 are rep eat ed for each recei ved by te
from the slave .
15. Master sends a NACK or Stop to end
communication.
Note: The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
2014 Microchip Technology Inc. DS20005350A-page 175
MCP19118/19
FIGURE 27-21 : I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus ma st e r
terminates
transfer
ACK
Receiving Data from slave
Receiving Data from slave
D0
D1
D2
D3D4
D5
D6D7
ACK
R/W
Transmit Address to slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here, ACK from slave
Mas ter configured as a receiver
by programming SSPCON2<3> (RCEN = 1)PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared by softw are
start XMIT
SEN = 0
SSPOV
SDA = 0, SCLx = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared by software
Cleared by software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from master
Set SSPIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknow-
led ge se que nc e
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1, start
next r eceiv e
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPxIF
ACKEN
begin Start condition
Cleared by software
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
RCEN
Mas ter conf igured as a receiver
by programming SSPCON2<3> (RCEN = 1)RCEN cleared
automatically ACK from master
SDA = ACKDT = 0 RCEN cleared
automatically
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27.5.8 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable (ACKEN) bit in the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is
automatically cleared, the Baud Rate Generator is
turned off and the MSSP module then goes into Idle
mode (Figure 27-22).
27.5.8.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur ).
27.5.9 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
(PEN) in the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the 9th clock. When the PEN bit is set,
the master will as ser t the SD A li ne low. When the SD A
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and, one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the
SSPSTAT<P> bit is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 27-23).
27.5.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 27-22: ACKNOWLEDGE SEQUENCE WAVEFORM
SDA
SCL
SSPIF set at
Acknowledge sequence starts here,
write to SSPCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SSPIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
Note: TBRG = one Baud Rate Ge nerator period.
2014 Microchip Technology Inc. DS20005350A-page 177
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FIGURE 27-23: STOP CONDITION RECEIVE OR TRANSMIT MODE
27.5.10 SLEEP OPERATION
While i n Sleep mo de, the I2C slave m odule c an receive
addresses or data and, when an address match or
complete byte transfer occurs, wakes the processor
from Sleep (if the MSSP interrupt is enabled).
27.5.11 EFFECTS OF A RESET
A Reset disable s the MSSP module and termina tes the
current transfer.
27.5.12 MULTI-MAS TER MO DE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
deter mination of when the bus i s free. The S top (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit in the SSPSTAT register is set
or the bus is Idle, wi th both the S and P bit s clear . When
the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
27.5.13 MU LT I -M AS T ER CO M MU NI C AT I ON ,
BUS COLLI SION AND BU S
ARBITRATION
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA, by letting SDA float high
and another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA pin is
‘0’, then a bus collision has t aken place. The master will
set the Bus Collision Interrupt Flag (BCLIF) and reset
the I2C port to its Idle state (Figure 27-24).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are d easserted and the
SSPBUF can b e written to. When the us er servic es th e
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I2C bus is free, the user can resume
communication by asserting a Start condition .
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be t aken when the P bit is set in the SSPSTAT
register or the bus is Idle and the S and P bits are
cleared.
SCL
SDA
SDA asserted low before rising edge of c lock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Note: TBRG = one Baud Rate Generator period.
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FIGURE 27-24: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
27.5.13.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are s ampled low a t the beginni ng of
the Start condition (Figure 27-25).
b) SCL is sampl ed l ow be fore SDA is asse rted low
(Figure 27-26).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low or the SCL pin is already
low, then all of the following occur:
• the Start condition is abort ed
• the BCLIF f lag is set
• the MSSP module is reset to its Idle state
(Figure 27-25)
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Ra te Generator i s loaded and coun ts down. If the
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 27-27). If, however , a ‘1’ is sampled on th e SDA
pin, the SDA pin is asserte d low at the en d of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high,
data does not match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
Note: The reason that bus collision is not a
factor during a Start condition is that no
two bus masters can assert a Start
condition at the exact same time.
Therefore, one master will always assert
SDA before the other. This co nditio n does
not caus e a b us co llision b ec ause the two
masters must be allowed to arbitrate the
first address following the Start condition.
If the address is the same, arbitration
must be allowed to continue into the data
portion, Repeated Start or Stop
conditions.
2014 Microchip Technology Inc. DS20005350A-page 179
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FIGURE 27-25: BUS COLLISION DURING START CONDITION (SDA ONLY)
FIGURE 27-26: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA
SCL
SEN SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.SSPIF and BCLIF are
cleared by software
SSPIF and BCLIF are
cleared by software
Set BCLIF,
Start condition. Set BCLIF.
SDA
SCL
SEN bus c ollision occurs. Se t BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleare d
by software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time out,
’0’’0’
’0’’0’
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FIGURE 27-27: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN
Set S
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
by softwareset SSPIF
SDAx = 0, SCL = 1,
SCLx pulled low after BRG
time out
Set SSPIF
’0’
SDA pulled low by other master.
Reset BRG and assert SDAx.
Set SEN, enable Start
se quence if SDA = 1, SCL = 1
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27.5.13.2 Bus Collision during a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user releases SDA and the pin is allowed to
float hig h, t he BRG is lo aded w ith SSPADD and counts
down to zero. The SCL pin is then deasserted and,
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 27-28).
If SDA is sampled high, the BRG is relo aded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exa ctly the s ame time .
If SCL goes from high-to-low before the BRG times out
and SDA has not already been as serted, a bus collision
occurs. In this case, another master is attempting to
tran smit a data ‘1’ during the Repeated Start condition
(see Figure 27-29.)
If, at the end of the BRG time out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 27-28: BUS COLLISION DURING A REPEATED S TART CONDITION (CASE 1)
FIGURE 27-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared by software
’0’
’0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
by so ftware
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
’0’
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DS20005350A-page 182 2014 Microchip Technology Inc.
27.5.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pi n is deassert ed, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the Baud Rate Generator is loaded with SSPADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 27-30). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 27-31).
FIGURE 27-30: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 27-31: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after T BRG,
set BCLIF
’0’
’0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA
SCL goes low before SDA goes high,
set BCLIF
’0’
’0’
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TABLE 27-1: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
V alues on
Page:
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 95
PIE1 —ADIE BCLIE SSPIE — — TMR2IE TMR1IE 96
PIR1 —ADIF BCLIF SSPIF — — TMR2IF TMR1IF 98
TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114
TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 —TRISB2 TRISB1 TRISB0 117
SSPADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 189
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 148*
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 186
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 187
SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 188
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 189
SSPSTAT SMP CKE D/A PSR/WUA BF 185
SSPMSK2 MSK27 MSK26 MSK25 MSK24 MSK23 MSK22 MSK21 MSK20 190
SSPADD2 ADD27 ADD26 ADD25 ADD24 ADD23 ADD22 ADD21 ADD20 190
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode.
* Page provides register information.
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DS20005350A-page 184 2014 Microchip Technology Inc.
27.6 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator
availa ble for c lo ck gen erat ion in I2C Master mode. The
Baud Rate Generator (BRG) reload value is placed in
the SSPADD register . When a write occurs to SSPBUF,
the Baud Rate Generator will automatically begin
counting down.
Once the given operation is comp lete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 27-32 triggers the
value from SSP ADD to be loaded into the BRG counter .
This occurs twice for each oscillation of the module
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 27-2 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 27-1:
FIGURE 27-32: BAUD RATE GENERATOR BLOCK DIAGRAM
FCLOCK
FOSC
SSPADD 1+4
----------------------------------------------=
SSPM<3:0>
BRG Down Counter
SSPCLK FOSC/2
SSPADD<7:0>
SSPM<3:0>
SCL Reload
Control Reload
Note: Values of 0x00, 0x 01 and 0x 02 a r e n ot v ali d
for SSPADD when used as a Baud Rate
Generator for I2C . This is an implement ation
limitation.
TABLE 27-2: MSSP CLOCK RATE W/BRG
FOSC FCY BRG Value FCLOCK
(2 Rollovers of BRG)
8 MHz 2 MHz 04h 400 kHz(1)
8 MHz 2 MHz 0Bh 166 k Hz
8 MHz 2 MHz 13h 100 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2014 Microchip Technology Inc. DS20005350A-page 185
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REGISTER 27-2: SSPSTAT: SSP STATUS REGISTER
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Data Input Sample bit
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: Clock Edge Selec t bit
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Re se t)
0 = Stop bit was not detected last
bit 3 S: Start bit
(This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/W ri te bit information
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or NACK bit.
In I2 C Slave mode:
1 =Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bi t with SEN, RSEN, PEN, RCEN or ACKEN wil l indica te if the MSSP is in Idle m ode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit:
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
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REGISTER 27-3: SSPCON1: SSP CONTROL REGISTER 1
R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HS = Bit is set by hardware C = User cleared
bit 7 WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit (1)
1 = A byte is rece iv ed whi le the SSPBUF reg is ter is s til l hol din g the previous b yte. SSPOV is a “d on’ t
care” in Transmit mode (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
1 = Enables the serial port and config ures the SD A and SCL pins as the so urce of the s erial port p ins (2)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Selec t bit
In I2 C Slave mode:
SC L release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = Reserved
0100 = Reserved
0101 = Reserved
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC/(4 x (SSPADD+1))(3)
1001 = Reserved
1010 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, the SDA and SCL pins must be configured as inputs.
3: SSPADD values of 0, 1 or 2 are not supported for I2C Mode.
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REGISTER 27-4: SSPCON2: SSP CONTROL REGISTER 2
R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
H = Bit is set by hardware S = User set -n/n = Value at POR/Value at all other resets
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowl edge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Ackno wledge sequence on SDA and SCL pins and tran smit ACKDT dat a bit. Automatically
cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Re ceive Idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
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REGISTER 27-5: SSPCON3: SSP CONTROL REGISTER 3
R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n/n = Value at POR/Value at
all other resets ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ACKTIM: Acknowledge Time Status bit(2)
1 = Indicates the I2C bus is in an Acknowledge sequence, set on the 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on the 9th rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(1)
bit 5 SCIE: Start Condition Interrupt Enable bit
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(1)
bit 4 BOEN: Buffer Overwrite Enable bit
In I2C Master mode:
This bit is ignore d.
In I2C Slave mode:
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0 = SSPBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputt ing a high state, the BCLIF
bit in the PIR2 register is set, and bus goes Idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit in the
SSPCON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I 2C Slave mode only)
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
in the SSPCON1 register and SCL is held low.
0 = Data holding is disabled
Note 1: This bit has no effect in slave modes where Start and Stop condition detection is explicitly listed as
enabled.
2: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
2014 Microchip Technology Inc. DS20005350A-page 189
MCP19118/19
REGIST ER 27-6: SSPMSK : S S P MA SK REGIS T ER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 27-7: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Master mode:
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) x 4)/FOSC
10-Bit Slave mode — Most Significant Address byte:
bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit
patt ern sen t by mast er is fixed by I2C sp ecificat ion and mu st be equa l to ‘11110’. Howeve r , those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”
10-Bit Slave mode — Least Significant Address byte:
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bi t Slave mode:
bit 7-1 ADD<7:1>: 7-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”
MCP19118/19
DS20005350A-page 190 2014 Microchip Technology Inc.
REGISTER 27-8: SSPMSK2: SSP MASK REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK27 MSK26 MSK25 MSK24 MSK23 MSK22 MSK21 MSK20
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 MSK2<7:1>: Mask bi ts
1 = The received address bit n is compared to SSPADD2<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK2<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPADD2<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 27-9: SSPADD2: MSSP ADDRESS 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADD27 ADD26 ADD25 ADD24 ADD23 ADD22 ADD21 ADD20
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Master mode:
bit 7-0 ADD2<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most Significant Address byte:
bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit
patt ern sen t by mast er is fixed by I2C sp ecificat ion and mu st be equa l to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD2<2:1>: Two Most Si gnifican t bits of 10-bit address
bit 0 ADD2<0>: SSPADD2 Enable bit.
1 = Enable address matc hi ng with SSPADD2
0 = Disable address matching with SSPADD2
10-Bit Slave mode — Least Significant Address byte:
bit 7-0 ADD2<7:0>: Ei ght Least Significant bits o f 10-bit address
7-Bi t Slave mode:
bit 7-1 ADD2<7:1>: 7-bit address
bit 0 ADD2<0>: SSPADD2 Enable bit.
1 = Enable address matc hi ng with SSPADD2
0 = Disable address matching with SSPADD2
2014 Microchip Technology Inc. DS20005350A-page 191
MCP19118/19
28.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be p ro gramme d w ith t he most recen t f irmw are
or a custom firmware. Five pins are needed for ICSP
programming:
• ICSPCLK
• ICSPDAT
•MCLR
•V
DD
•V
SS
In Program/Verify mode, the Program Memory, User IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a
bidirectional I /O used for t ransferring the serial data and
the ICSPC LK pin is the clock input. T he device is plac ed
into a Program/Verify mode by holding the ICSPDAT and
ICSPCLK pins low , while raising the MCLR pin from VIL to
VIHH.
28.1 Common Programming Interfa ces
Connection to a target device is typically done through
an ICSP header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin,
6-connector) configuration. See Figure 28-1.
FIGURE 28-1: ICD RJ-11 STYLE
CONNECTOR INTERFACE
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 28-2.
FIGURE 28-2: PI CKit™ PROGRAMMER-STYLE CONNEC TOR INTERFAC E
1
2
3
4
5
6
Target
Bottom Side
PC Board
MCLR VSS
ICSPCLK
VDD
ICSPDAT
NC
Pin Description
1 = 1 = MCLR
2=2 = V
DDTarget
3=3 = V
SS (ground)
4 = 4 = ICSPD AT
5 = 5 = ICSPCLK
6 = 6 = No Connect
1
2
3
4
5
6
* The 6-pin header (0.100" spacing) accepts 0.025" square pins.
Pin Description*
1 = 1 = MCLR
2=2 = V
DDTarget
3=3 = V
SS (ground)
4=4 = ICSPDAT
5=5 = ICSPCLK
6 = 6 = No Connect
Pin 1 Indicator
MCP19118/19
DS20005350A-page 192 2014 Microchip Technology Inc.
For addit ional interfac e recommend ations, refer to yo ur
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The t ype of isolatio n is highly dependent on the specifi c
applic ation and may i nclude d evices, such as resistors ,
diodes or even jumpers. See Figure 28-3 for more
information.
FIGURE 28-3: TYPICAL CONNECTION FOR ICSP PROGRAMMING
28.2 In-Circui t Debugger
In-circuit debugging requires access to the ICDCLK,
ICDDATA and MCLR pins. These pins are only
available on the MCP19119 device.
VDD
VPP
VSS
External Device to be
Data
Clock
VDD
MCLR
VSS
ICSPDAT
ICSPCLK
**
*
To Normal Connections *Isolation devices (as required)
Programming
Signals Programmed
VDD
2014 Microchip Technology Inc. DS20005350A-page 193
MCP19118/19
29.0 INSTRUCTION SET SUMMARY
The MCP19118/19 instruction set is highly orthogonal
and is comprised of three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
Each instruction is a 14-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands, which further specify the operation
of the instruction. The formats for each of the
categories are presented in Figure 29-1, while the
various opcode fields are summarized in Table 29-1.
Table 29-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the resul t of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W regis ter . If ‘d’ is one, the res ult is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or liter al value.
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency of 4 MHz, this gives a no rmal
instruction execution time of 1 µs. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
change d as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as an NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
29.1 Read-Modif y-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified,
and the result is stored according to either the
instruction or the destination designator ‘d’. A read
operation is performed on a register even if the
instruction writes to that register.
For example, a CLRF PORTA instruction will read
PORTGPA, clear all the data bits, then write the result
back to PORTGPA. This example would have the
unintended consequence of clearing the condition that
set the IOCF flag.
FIGURE 29-1: GENERAL FORMAT FOR
INSTRUCTIONS
TABLE 29-1: OPCODE FIELD
DESCRIPTIONS
Field Description
f Register f ile addr ess (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time Out bit
C Carry bit
DC Digit carry bit
Z Zero bit
PD Power-Down bit
Byte-Oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-Oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
MCP19118/19
DS20005350A-page 194 2014 Microchip Technology Inc.
TABLE 29-2: MCP19118/19 INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Inc rement f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interru pt
Return with literal in W
Return from Subrou tine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
Note 1: When an I/O register is modified as a function o f itse lf (e.g ., MOVF PORTA, 1), the value used will be that
value pr ese nt on the pins th emse lves. For e xampl e, if the dat a latch is ‘1’ fo r a pin c onfigu red as in put and
is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared if assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles.
The second cycle is executed as an NOP.
2014 Microchip Technology Inc. DS20005350A-page 195
MCP19118/19
29.2 Instruction Descriptions
ADDLW Add literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the
W register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Add the con tents of the W re gister
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W registe r . I f
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
‘k’. The r esult is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is sto r ed bac k in regi ste r ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Affe cte d: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Affe cte d: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affe cte d: None
Descr iption: If bit ‘b’ in regis ter ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in reg ister ‘f’ is ‘0’, t he ne xt
instruction is discarded, and an
NOP is execut ed instea d, making
this a two-cycle instruction.
MCP19118/19
DS20005350A-page 196 2014 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription If bit ‘b ’ in registe r ‘f’ is ‘0’, the next
instructi on is exec uted .
If bit ‘b’ is ‘1’, then the next
instruction is discarded and an
NOP is executed instead, making
this a two-cycle instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loa ded from PCLATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Desc ript ion : The content s of regi ste r ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affe cte d: T O, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF C omplement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affe cte d: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affe cte d: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2014 Microchip Technology Inc. DS20005350A-page 197
MCP19118/19
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decrem ented. If ‘d’ is ‘0’, th e result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
resu lt is ‘0’, then an NOP is
executed instead, making it a
two-cycle instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremen ted. If ‘ d’ is ‘0’, the res ult
is placed in the W registe r. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Affe cte d: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a n NOP is executed
instead, making it a two-cycle
instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Affe cte d: Z
Descr iption: The con tents of t he W register a re
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W registe r.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destination)
Status Affe cte d: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
MCP19118/19
DS20005350A-page 198 2014 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Desc ript ion : The contents of register ‘f’ is
moved to a dest ination dependent
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1,
the destination is file register ‘f’
itself. d = 1 is useful to test a file
register since Status flag Z is
affected.
Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W = value in
FSR register
Z= 1
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Desc ription: The eig ht-bit literal ‘k ’ is loaded into
W register. The “don’t cares” will
assemble as ‘0’s.
Words: 1
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
Status Affe cte d: None
Description: Move data from W register to
register ‘f’.
Words: 1
Cycles: 1
Example: MOVW
FOPTION
Before Instruction
OPTION = 0xFF
W = 0x4F
After Instruction
OPTION = 0x4F
W = 0x4F
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affe cte d: None
Description: No operation.
Words: 1
Cycles: 1
Example: NOP
2014 Microchip Technology Inc. DS20005350A-page 199
MCP19118/19
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
Description: Return from Interrupt. Stack is
POPed an d Top-of-S tack (T OS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE (INT-
CON<7>). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affe cte d: None
Description: The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words: 1
Cycles: 2
Example:
TABLE
DONE
CALL TABLE;W contains
;table offset
;value
GOTO DONE
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ;End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affe cte d: None
Description: Return from subroutine. The stack
is POPed an d t he top of th e s t a ck
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
MCP19118/19
DS20005350A-page 200 2014 Microchip Technology Inc.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110
0110
C=0
After Instruction
REG1 = 1110
0110
W = 1100
1100
C=1
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The contents of register ‘f’ are
rotat ed one bit to the r ight throug h
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is place d
back in register ‘f’.
Register fC
Register fC
SLEEP Enter Sleep mode
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affe cte d: TO, PD
Descripti on: The power-down S tatus bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer an d its
prescaler are cleare d.
The processor is put into Sleep
mode with th e oscillat or stopped.
SUBLW Subtract W from literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Descr iption : The W register is subtracte d (two’ s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
Result Condition
C = 0W k
C = 1W k
DC = 0W<3:0> k<3:0>
DC = 1W<3:0> k<3:0>
2014 Microchip Technology Inc. DS20005350A-page 201
MCP19118/19
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status Affected: C, DC, Z
Description: Subtract (two’s complement
method) W reg ister from regist er ‘f’.
If ‘d’ is ‘0’, the resu lt is sto red i n the
W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f ’.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW Exclusive OR literal with W
Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-b it
literal ‘k’. The result is placed in
the W register.
C = 0W f
C = 1W f
DC = 0W<3:0> f<3:0>
DC = 1W<3:0> f<3:0>
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Affe cte d: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
MCP19118/19
DS20005350A-page 202 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 203
MCP19118/19
30.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a ful l range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Progra mm ers
- MPLAB PM3 Device Programmer
• Low-C ost D emonstr ation/Development Boards,
Evaluation Kits and Starter Kits
• Third- party Develo pment Tools
30.1 MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With com plete projec t managem ent, visual cal l graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multipl e project s with simu ltane ous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hin ts as you type
• Automati c c od e f orm atti ng bas ed on us er-d efi ned
rules
• Live parsing
User-Friendly, Customiz abl e Interfa ce :
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Work spac es:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
MCP19118/19
DS20005350A-page 204 2014 Microchip Technology Inc.
30.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Co mpilers inc lude an asse mbler , li nker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an
executable file. MPLAB XC Compiler uses the
assembler to produce its object file. Notable features of
the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB X IDE compatibility
30.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly co de
• Conditional assembly for multipurpose
sour ce fil es
• Directives that allow complete control over the
assembly process
30.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a rout in e from a l ibra ry is cal led fro m a source file, o nl y
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, re placement, delet ion and extra c tion
30.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archive d o r linked w ith ot her relocat ab le ob jec t
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB X IDE compatibility
2014 Microchip Technology Inc. DS20005350A-page 205
MCP19118/19
30.6 MPLAB X SIM Software Simul ator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent tool .
30.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradeable through future firm-
ware downloads in MPLAB X IDE. MPLAB REAL ICE In-
circuit emulator offers significant advantages over com-
petitive emulators including full-speed emulation, run-
time variable watches, trace analysis, complex break-
points, logic probes, a ruggedized probe interface and
long (up to three meters) interconn ection ca bles.
30.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 int erface and is connected to t he target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
30.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 In-Circuit Debugger allows
debugging and programming of PIC and dsPIC Flash
microcontrollers at a most affordable price point using
the powerful graphical user interface of the MPLAB
IDE. The MPLAB PICkit 3 In-Circuit Debugger is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector
(comp at ible w i th MPL AB ICD 3 a nd MPL AB R EAL ICE
In-Circuit Emulator). The connector uses two device I/
O pins and the Reset line to implement in-circuit
debugging and In-Circuit Serial Programming™
(ICSP™).
30.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and er ror messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code pro tec tio n in thi s m ode . Th e MP LAB PM 3 D ev ice
Programm er conne cts to the host PC via an RS-23 2 or
USB cable. The MPLAB PM3 Devic e Progra mmer ha s
high-speed communications and optimized algorithms
for quick programming of large memory devices, and
incorporates an MMC card for file storage and data
applications.
MCP19118/19
DS20005350A-page 206 2014 Microchip Technology Inc.
30.11 Demonstration/Development
Boards, Evaluati on Kits
and Starter Kit s
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
use d in teac hing environments, for prototypin g custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a l ine of evaluation k its and demonstr a-
tion software for analog fil ter desi gn, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluati on kits.
30.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace S ystems
• Protoc ol A nal yz ers from com p a n ie s, su ch as
Saleae and To tal Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
2014 Microchip Technology Inc. DS20005350A-page 207
MCP19118/19
31.0 PACKAGING INFORMATION
31.1 Package Marking Information
28-Lead QFN (5x5x0.9 mm) (MCP19119 only) Example
PIN 1 PIN 1
19119
E/MQ ^^
1439256
3
e
24-Lead QFN (4x4x0.9 mm) (MCP19118 only) Example
19118
E/MJ ^^
1439
256
3
e
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
RoHS Comp liant JEDEC® designator for Matte Tin (Sn)
*This package is RoHS Compliant. The RoHS Compliant
JEDEC designator ( ) can be found on the outer packaging
for this package.
Note: In the event the fu ll Mic rochip part nu mber ca nnot be marked on one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Example
MCP19118/19
DS20005350A-page 208 2014 Microchip Technology Inc.
24-Lead Plastic Quad Flat, No Lead Package (MJ) – 4x4x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc. DS20005350A-page 209
MCP19118/19
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP19118/19
DS20005350A-page 210 2014 Microchip Technology Inc.
B
A
0.10 C
0.10 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
NOTE 1
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-140C Sheet 1 of 2
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN or VQFN]
2X
28X
D
E
1
2
N
e
28X L
28X K
E2
D2
28X b
A3
A
C
SEATING
PLANE
A1
2014 Microchip Technology Inc. DS20005350A-page 211
MCP19118/19
Microchip Technology Drawing C04-140C Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
28-Lead Plastic Quad Flat, No Lead Package (MQY) – 5x5x0.9 mm Body [QFN or VQFN]
Dimension Limits
Units
D
Overall Width
Overall Length
Exposed Pad Length
Exposed Pad Width
Contact Thickness
D2
E2
E
3.35
MILLIMETERS
0.20 REF
MIN
A3
MAX
5.00 BSC
3.25
Contact Length
Contact Width
L
b
0.45
0.30
Notes:
1.
KContact-to-Exposed Pad 0.20
NOM
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
2.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Standoff A1 0.02
Overall Height A 0.90
Pitch e0.50 BSC
Number of Pins N28
0.35
0.18
3.15
3.15
0.00
0.80
0.25
0.40
-
3.25
5.00 BSC
3.35
0.05
1.00
-
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M.
Package is saw singulated.
MCP19118/19
DS20005350A-page 212 2014 Microchip Technology Inc.
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern
With 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-2140A
2014 Microchip Technology Inc. DS20005350A-page 213
MCP19118/19
APPENDIX A: RE VISION HISTORY
Revision A (October 2014)
• Original Release of this Document.
MCP19118/19
DS20005350A-page 214 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 215
MCP19118/19
INDEX
A
A/D Specifications......................................................3, 5, 33
A/D Conversion........ ....... ................... ............ ...................127
Requirements..............................................................34
Timing...................................................................34, 35
Absolute Maximum Ratings ................................................23
AC Characteristics ..............................................................30
ACKSTAT .........................................................................172
ACKSTAT Status Flag......................................................172
ADC ..................................................................................125
Acquisition Requirements .................... .... .... ........... ..131
Associ a te d Re g i sters..................... ............ ............. ..133
Block Diag ram........... ............ ............. ............. ..........125
Calculating Acquisition Time.....................................131
Channel Selection...................................... ....... .... ....126
Configuration.............................................................126
Configuring Interrupt.................................................128
Conversi o n Clo ck................................... ...................126
Conversion Procedure ....................... .... .... ......... .. ....128
Internal Sampling Switch(RSS) IMPEDANCE ...............131
Interrupts...................................................................127
Operation..................................................................128
Operation during Sleep.............................................128
Port Configuration.....................................................126
Register Definiti o n s.................................... ...............129
Source Impedance............ .... ........... .... ...... ........... ....131
Special Event Trigger................................................128
ADCON0 Register .............................................................129
ADCON1 Register .............................................................130
ADRESH Register (ADFM = 0).........................................130
ADRESL Register (ADFM = 0)..........................................130
Alternate Pin Function.......................................................112
Analog Blocks Enable Control ............................. ......... .... ..51
Analog Peripheral Control...................................................49
Analog-to-Digital Converter. See AD C
ANSELA Re g i ster .. ....... ............ ...... ............. ...... ............. ..115
ANSELB Re g i ster .. ....... ............ ...... ............. ...... ............. ..118
APFCON Register.............................................................112
Assembler
MPASM Assembler...................................................204
B
Bench Testing
Analog Be n ch Te st Control........ ............ ............. ........57
System........................................................................57
BF .............................................................................172, 174
BF Status Flag ..........................................................172, 174
Block Diagrams
ADC ..........................................................................125
ADC Transfer Function.............................................132
Analog Input Model...................................................132
Generic I/O Port........................................................111
Inter rupt Logic......... ............ ....... ............ ............. ........94
MCLR Circuit................. ............. .................. ............. ..86
MCP19118/19 Synchronous Buck Block Diagram......10
MSSP (I2C Master Mode).........................................147
MSSP (I2C Slave Mode).............. .. .... .. .. .. .... ..... .. .... ..148
On-Chip Rese t Circuit.................................................85
Simpl i fied PWM............. ...... ............. ...... ............. ......144
Timer0.......................................................................135
Timer1.......................................................................137
Timer2.......................................................................140
Watchdog Timer............................. .... .. .... .. ......... .. ....103
C
C Compilers
MPLAB C18.............................................................. 204
Calibration Word
Associated Registers.................................................. 84
Capture/Com p a re /PWM ...... .. .. ..... ...... ...... ..... ...... .. ... 14 3 , 14 5
Clock Switching.................................................................. 84
Code Examples
A/D Conver sion ......................... ................... ............ 128
Assign i n g Prescal e r to Timer0....... ...... ............. ...... .. 136
Assigning Prescaler to WDT..................................... 136
Init i a li zi n g PORT A ... .. ......... ...... ...... ...... ..... ...... ...... ... 11 1
Saving Status and W Registers in RAM................... 100
Compensation .................................................................... 18
Compensation Setting ........................................................ 43
Com p u te d Func ti o n C a l l s ...... ..... ...... ...... ...... ..... .......... ...... . 78
Computed GOTO................................................................ 78
Current
Measurement Control................................................. 51
Current Sense ........................................................ 18, 40, 41
Customer Change Notification Service............................. 221
Custome r Notification Se rvice ..... ......................... ............ 221
Customer Support.................................... ............. ...... ...... 221
D
Data Memor y.................. ............. ................... ............ ........ 70
Data Memory Map.............................................................. 72
DC and AC Characteristics................................................. 53
Graphs and Tables..................................................... 53
DC Ch a r a cteri stics. ...... ...... ...... ..... ...... ...... ..... ...... ...... ...... ... 30
Development Support....................................................... 203
Device
Configurati o n ... .. ...... ...... ......... ...... ...... ..... ...... ....... 37 , 8 1
Code Protection. ................................................. 82
Configurati o n Word .. ..... ...... .......... ..... ...... .......... . 81
ID Locations ....................................................... 82
Write Protection.................................................. 82
Devi ce C a l i b r a t io n........ ...... ...... ..... ...... .......... ..... ...... ...... ..... 5 9
Cali b r a ti o n W o r d 1........... ..... ...... ...... ..... ...... .......... ..... 5 9
Calibration Word 10.................................................... 65
Calibration Word 11.................................................... 66
Calibration Word 12.................................................... 66
Cali b r a ti o n W o r d 2........... ..... ...... ...... ..... ...... .......... ..... 6 0
Cali b r a ti o n W o r d 3........... ..... ...... ...... ..... ...... .......... ..... 6 1
Cali b r a ti o n W o r d 4........... ..... ...... ...... ..... ...... .......... ..... 6 2
Cali b r a ti o n W o r d 5........... ..... ...... ...... ..... ...... .......... ..... 6 2
Cali b r a ti o n W o r d 6........... ..... ...... ...... ..... ...... .......... ..... 6 3
Cali b r a ti o n W o r d 7........... ..... ...... ...... ..... ...... .......... ..... 6 3
Cali b r a ti o n W o r d 8........... ..... ...... ...... ..... ...... .......... ..... 6 4
Cali b r a ti o n W o r d 9........... ..... ...... ...... ..... ...... .......... ..... 6 5
Device Overview ................................................................... 9
Digital Electrical Characteristics ......................................... 29
Diode Emulation Mode .......................... .. .. ....... .. .. .... .. .. .. .. .. 49
E
ECCP/CCP. See Enhanced Capture/Compare/PWM
Electrical Characteristics .............................................. 23, 24
Errata.................................................................................... 7
External Clock..................................................................... 30
F
Features
Miscellaneous............................................................. 21
Protection ................................................................... 20
MCP19118/19
DS20005350A-page 216 2014 Microchip Technology Inc.
Synchronous Buck........................................................1
Firmware Instructions........................................................193
Flash Pr o g ram Memory Control................. ............ ...........105
Operation During Code Protect.................................109
Operation during write Protect..................................109
Protecting..................................................................109
Reading.....................................................................108
Writing to...................................................................109
Flash Pr o g r a m Mem o ry Co nt rol Registers........................106
H
High-Side Drive Strength ..... ...............................................49
I
I/O Ports..........................................................................111
I2C Mode (MSSP)
Acknowledge Sequence Timing. ...............................176
Associ a te d Re g i sters......................... ............ ...........183
Bus Collision
During a Repeated Start Condition...................181
During a St a rt Condition..................... ............. ..178
During a Stop Condition....................................182
Effects of a Reset ......................................................177
I2C Clock Rate w/BRG..............................................184
Master Mode.............................................................169
Clock Arbitration................................................169
Operation..........................................................169
Reception..........................................................174
Start Condition Timing ..............................170, 171
Transmission.....................................................172
Multi-Master Comm unication, Bus Collision and Arbitra-
tion....................................................................177
Multi-Master Mode ....................................................177
Operation ..................................................................150
Read/Write Bit Information (R/W Bit ) ........ ...... .. ..... ...153
Slave Mode
10-Bit Addres s Recep tion.......... ............ ...........163
Operation..........................................................153
Sleep Operation........................................................177
Stop Condition Timing..................... ................... .......176
I2C Mode (MSSPx)
Acknowledge Sequence ...........................................152
Overview...................................................................148
Slave Mode
Bus Collision......... ............................................159
Clock Synchronization ......................................167
General Call Address Support.. ........................168
SSPMSKx Register...................... ................... ..168
Transmission.....................................................159
In-Circuit Serial Programming (ICSP)...............................191
Common Programming Interfaces............................191
In-Circuit Debugger...................................................192
Indirect Addressing .............................................................78
Input....................................................................................24
Type............................................................................12
Undervoltage Lockout...........................................20, 37
Instruction Format.............................................................193
Instruction Set...................................................................193
ADDLW.....................................................................195
ADDWF.....................................................................195
ANDLW.....................................................................195
ANDWF.....................................................................195
BCF...........................................................................195
BSF...........................................................................195
BTFSC ......................................................................195
BTFSS...................................................................... 196
CALL......................................................................... 196
CLRF ........................................................................ 196
CLRW....................................................................... 196
CLRWDT .................................................................. 196
COMF....................................................................... 196
DECF........................................................................ 196
DECFSZ ................................................................... 197
GOTO ....................................................................... 197
INCF ......................................................................... 197
INCFSZ..................................................................... 197
IORLW...................................................................... 197
IORWF...................................................................... 197
MOVF ....................................................................... 198
MOVLW.................................................................... 198
MOVWF.................................................................... 198
NOP.......................................................................... 198
RETFIE..................................................................... 199
RETLW..................................................................... 199
RETURN................................................................... 199
RLF........................................................................... 200
RRF .......................................................................... 200
SLEEP...................................................................... 200
SUBLW..................................................................... 200
SUBWF..................................................................... 201
SWAPF..................................................................... 201
XORLW .................................................................... 201
XORWF .................................................................... 201
Summary Ta b l e...................... ............. ............. ...... .. 194
Internal Sampling Switch (RSS) IMPEDANCE...................... 131
Internal Synchronous Driver ............................................... 17
Internal Temperature Indicator Module . ............................ 123
Circuit Ope ration....................................................... 123
Temp e r a t u r e O u tp u t ...... .. ...... ..... ...... ...... ......... ...... ... 123
Internal Temperature Measurement Control....................... 51
Internet Addre ss ......................... ....... ...... ...... ...... ....... ...... 221
Interrupt-on-Change ......................................................... 121
Associated Registers................................................ 122
Clearing In te rrupt Flags...... ....... ............................... 121
Enabling the Module................................................. 121
Operation in Sleep.................................................... 121
Pin Co n fi g u ratio n. .. ...... ...... ...... ..... ...... .. ...... ..... ...... ... 121
Registers .................................................................. 122
Interrupts
ADC.......................................................................... 128
Associated Registers.................................................. 99
Context Saving......................................................... 100
Control Registers........................................................ 95
RA2/INT...................................................................... 93
TMR1........................................................................ 138
L
Linear Regulators ............................................................... 17
M
MASTER Error Signal Gain................................................ 45
Master Synchronous Serial Port. See MSSP
MCLR.................................................................................. 86
Internal........................................................................ 86
Memory Organization ......................................................... 69
Data............................................................................ 70
Program...................................................................... 69
Microc h i p In te rnet Web Sit e.... ...... ............. ...... ............. .... 221
MOSFET............ ...... ....... ...... ...... .... 15, 16, 17, 46, 49, 57, 67
Driver Dead Time.................. ......... .... .. .... .... ....... .... .... 17
MOSF ET Driv e r
2014 Microchip Technology Inc. DS20005350A-page 217
MCP19118/19
Dead Time ..................................................................49
Programmable Dead Time..........................................46
MPLAB ASM30 Assembler, Linker, Librarian ...................204
MPLAB Integrated Development Environment Software..203
MPLAB PM3 Device Programmer ....................................205
MPLAB REA L IC E In -Circuit Emulator System.................205
MPLINK Object Linker/MP L IB Objec t Librarian................204
MSSP................................................................................147
Arbitration..................................................................150
Baud Rate Generator................................................184
Clock Stretching........................................................150
I2C Bus Terms ..........................................................151
I2C Master Mode.......................................................169
I2C Mode...................................................................148
I2C Mode Operation..................................................150
I2C Slave Mode Operation........................................153
Module Overview......................................................147
Multi -P h a se System............................... ............ ............. ....22
O
OPCODE Fiel d Descr ip tions.......................... ...................193
Oscillator.............................................................................83
Associ a te d Re g i sters..................... ............ ............. ....84
Calibration...................................................................83
Delay upon Power-Up.................................................84
Frequency Tuning.................................... .. ......... .. .. ....83
Internal Oscillator........................................................83
Oscillator Module ................................................................84
Output .................................................................................49
Multiple System ...........................................................22
Overcurrent.....................................................20, 38, 39
Overvoltage.....................................................20, 25, 48
Overvoltage Enable . ...................................................51
Power Good. ...... ............. ............. ................... ............22
Type............................................................................12
Under Voltage.......................................................20, 48
Under Voltage Accelerator..........................................49
Under Voltage Enable.................................................51
Undervoltage...............................................................25
Voltage........................................................................18
Soft-Start.............................................................22
Tracking..............................................................22
Voltage Configuration ... .. .... .. ......... .. .. .... .. .... ....... .. .... ..47
Voltage Sense Pull-Up/Pull-Down ..............................49
Overcurrent.........................................................................39
Overvoltage Acceler ator ........................................ .............49
P
Packaging.........................................................................207
Marking.....................................................................207
Specifications............................................................208
PCL.....................................................................................78
Modifying.....................................................................78
PCLATH..............................................................................78
PCON Register.............................................................87, 92
Pin Diagram
24-Pin QFN...................................................................2
28-Pin QFN...................................................................4
Pinout Description
Summary...................................................................3, 5
Pinout Description Table................. ....... .... .. .... .. ....... .... .. ....12
PIR1 Regi ster........... ................... ............. ............ ............. ..98
PIR2 Regi ster........... ................... ............. ............ ............. ..99
PMADRH Register............................................................105
PMADRL Register. ....................................................105, 106
PMCON1 Register..................................... .. .... .. .......105, 107
PMCON2 Register........ ............. ......................... .............. 105
PMDATH Register............................................................ 106
PMDA T L R e g i s ter.... ...... ...... ..... ...... ...... .. ...... ..... ...... ...... ... 10 6
PMDRH Register.............................................................. 107
PORTB
Additional Pin Functions
Weak Pull-Up.................................................... 117
Pin Descriptions and Diagrams ................................ 119
PORTGPA................................................................ 112, 121
ANSELA Register..................................................... 113
Associated Registers................................................ 115
Functions and Output Priorities.............................. .. 113
Interrupt-on-Change ................................................. 112
Wea k Pu l l - U p s..... .. ...... ..... ...... ...... .. ...... ..... ...... ...... ... 11 2
PORTGPA Regi ster...... ............. ...... ............ ............. ........ 112
PORTGPB................................................................ 116, 121
ANSELB Register..................................................... 116
Associated Registers................................................ 119
Functions and Output Priorities.............................. .. 116
Interrupt-on-Change ................................................. 116
P1B/P1C/P1D.Capture/Compare/PWM ................... 116
Wea k Pu l l - U p s..... .. ...... ..... ...... ...... .. ...... ..... ...... ...... ... 11 6
PORTGPB Regi ster...... ............. ...... ............ ............. 116, 117
Power-Down Mode (Sleep)............................................... 101
Associated Registers................................................ 102
Power-On Reset (POR)...................................................... 86
Power-Up Timer (PWRT).................................................... 87
Prescaler, Timer1
Select (T1 C KPS1: T1C KPS 0 Bi ts ) .... ..... .. ...... .. ...... .. ... 46
Product Identification System........................................... 223
Program Memory................................................................ 69
Map and Stack (MCP19118/19) ................................. 69
Prog r a m Me mory Protection..... ...... .. ...... .. ..... .. ...... ...... ...... . 82
Prog r a mming , D e v i ce In stru c ti o ns............ ..... .. ...... ...... .. ... 19 3
Pulse-Width Modulation...................................................... 33
Associated Registers................................................ 145
Duty Cycle........ ................... ............................... ...... 14 5
Module...................................................................... 143
Operating during Sleep............................................. 145
Period....................................................................... 144
Stand-Alone Mode.............................................. .... .. 143
Standard Mode......................................................... 143
Switching Frequency Synchronizati on Mode............ 143
R
Read-Modify-Write Operations......................................... 193
Register
OVFCON (Output Voltage Set Point Fine Control)..... 47
Registers
ABECON (Ana log Block Enable Control) ................... 52
ADCON0 (ADC Control 0)........................................ 129
ADCON1 (ADC Control 1)........................................ 130
ADRESH (ADC Result High) wi th ADFM = 0 ........... 130
ADRESL (ADC Result Low) with ADFM = 0............. 130
ANSELA (Analog Select GPA) ................................. 115
ANSELB (Analog Select GPB) ................................. 118
APFCON (Alternate Pin Function Control) ............... 112
ATSTCON (Analog Benc h Test Control).................... 57
BUFFCON (Unit y Gain Buffer Control)................... .... 58
CALWD1 (Calibration Word 1) ................................... 59
CALWD10 (Calibration Word 10) ............................... 65
CALWD11 (Calibration Word 11) ............................... 66
CALWD12 (Calibration Word 12) ............................... 66
CALWD2 (Calibration Word 2) ................................... 60
CALWD3 (Calibration Word 3) ................................... 61
CALWD4 (Calibration Word 4) ................................... 62
MCP19118/19
DS20005350A-page 218 2014 Microchip Technology Inc.
CALWD5 (Calibration Word 5)....................................62
CALWD6 (Calibration Word 6)....................................63
CALWD7 (Calibration Word 7)....................................63
CALWD8 (Calibration Word 8)....................................64
CALWD9 (Calibration Word 9)....................................65
CMPZCON (Compensation Setting Control) ..............43
CONFIG (Configuration Wo rd)...... ................... ...........81
CSDGCON (Voltage For Zero Current Control)..........41
CSGSCON (Current Sense AC Gain Control)............40
DEADCON (Driver Dead Time Control)......................46
INTCON (Interrupt Control).........................................95
IOCA (Interrupt-on-Change PORTGPA)............ .......122
IOCB (Interrupt-on-Change PORTGPB)............ .......122
LPCRCON (Slope Compensation Ramp Control).......44
OCCON (Output Overcurrent Control)........................39
OOVCON (Output Overvoltage Detect Level Control) 48
OPTION_R EG (Option) ............................... ............. ..77
OSCTUNE (Oscillator Tuni n g)................. ...................83
OUVCON (Output Undervoltage Detect Level Control)..
48
OVCCON (Output Voltage Set Point Coarse Control) 47
PCON (Power Control) .........................................87, 92
PE1 (Analog Peripheral Enable 1 Control) .................50
PIE1 (Peripheral Interrupt Enable 1)...........................96
PIE2 (Peripheral Interrupt Enable 2)...........................97
PIR1 (Peripheral Interrupt Flag)..................................98
PIR2 (Peripheral Interrupt Flag)..................................99
PMADRL (Program Memory Address)......................106
PMCON1 (Program Memory Control).......................107
PMDATH (Program Memory Data)...........................106
PMDATL (Program Memory Data)............................106
PMDRH (Program Memory Address)........................107
PORTGPA ................................................................113
PORTGPB ................................................................117
RELEFF (Relative Efficiency Measurement) ..............67
Reset Values....................... ............ ............. ............. ..89
SLVGNCON (MASTER Error Signal Input Gain Control)
45
Special Registers Summary......................73, 74, 75, 76
SSPADD (MSS P Addr ess and Baud Rate, I2C Mode) ...
189, 190
SSPCON1 (MSSPx Control 1)..................................186
SSPCON1 (SSP Control) ..........................................186
SSPCON2 (SSP Control 2) .......................................187
SSPCON3 (SSP Control 3) .......................................188
SSPMSK (SSP Mas k)......... ............ ............. .............18 9
SSPMSK2 (SS P Mas k)....... ............ ............. .............190
SSPSTAT (SSP Status)............................................185
STATUS......................................................................71
T1CON (Timer1 Con tr o l)....... ............... .....................138
TRISA (Tri-State PORTA).........................................114
TRISGPB (PORTGPB Tri-State) ..............................117
TXCON .....................................................................141
VINLVL (Input Under Voltage Lockout Control)..........37
VZCCON (Voltage for Zero Current Control)..............42
WPUGPA (Weak Pull-Up PORTGPA)......................114
WPUGPB (Weak Pull-Up PORTGPB)......................118
Relative Efficiency Circuity Control.....................................51
Relative Efficiency Measurement........................................67
Procedure ...................................................................67
Rela ti v e Ef fi ciency Mea sure me n t Con tr ol ... ...... ...... ...... ..... .51
Reset...................................................................................85
Determi n i n g Causes ..... ...... ............ ............. ............. ..91
Resets.................................................................................85
Associ a te d Re g i sters......................... ............ .............92
Revision History................................................................213
S
Signal Chain Control........................................................... 51
Sleep
Wake-U p from....... ...... ............ ....... ............ ....... ........101
Wake-U p Usin g In te rrupts........................................ 102
Slope Compensation .................................................... 18, 44
Slope Compensation Control.............................................. 51
Software Simulator (MPLAB SIM) .................................... 205
Special Event Trigger .......................................................128
Special Function Registers................................................. 71
Special Registers Summary
Bank 0 ....... ............. ...... ............. ............ ............. ...... .. 73
Bank 1 ....... ............. ...... ............. ............ ............. ...... .. 74
Bank 2 ....... ............. ...... ............. ............ ............. ...... .. 75
Bank 3 ....... ............. ...... ............. ............ ............. ...... .. 76
SSPADD Registe r..................................................... 189, 190
SSPCON1 Register.......................................................... 186
SSPCON2 Register.......................................................... 187
SSPCON3 Register.......................................................... 188
SSPMSK Register .................. ............. ............ ................. 189
SSPMSK2 Regi ster .................. ............. ............ ............. .. 190
SSPOV ............................................................................. 174
SSPOV Status Flag.......................................................... 174
SSPSTAT Regi ster....... ............ ............. ............ ............. ..185
R/W Bit ... .. ...... ..... .. ...... ...... ...... ..... ...... .. ...... ..... ...... ... 153
Stack................................................................................... 78
Start-Up Sequence ............................................................. 87
STATUS Regi ster........... ............ ............. ............ ............. .. 71
Switching Frequency ..........................................................18
System Ben c h T e s t in g... .. ...... ...... ..... ...... ...... ...... .. ........ 22, 57
T
T1CON Registe r......................... ................................ ...... 138
T1CKPS1:T1CKPS0 Bits............................................ 46
Temperature Indicator Module.......................................... 123
The rm a l Sp e cifi ca tions ...... ...... ...... ..... ...... .......... ..... ...... ..... 28
Timer Requirements
RESET, Watchdog Timer, Oscillator Start-Up Timer and
Power-Up............................................................ 32
Timer0....................................................................... 135, 141
8-Bit Counter Mode................................................... 135
8-Bi t Timer Mode.............. ............. ...... ...... ............. .. 135
Associated Registers................................................ 136
External Clock...........................................................136
Operation.................................................................. 135
Operation During Sleep............................................ 136
T0CKI ....................................................................... 136
Timer0 Module.................................................................. 135
Timer1............................................................................... 137
Associated Registers................................................ 139
Associ a te d registe rs ............................ ...... ............. .. 139
Clock Source Selection............................................. 137
Control Reg i ster.................................................. ...... 138
Interrupt .................................................................... 138
Operation.................................................................. 137
Operation During Sleep............................................ 138
Prescaler .................................................................. 138
Sleep ........................................................................ 138
TMR1H Register....................................................... 137
TMR1L Register........................................................ 137
Timer1 Module.................................................................. 137
Timer2
Associated Registers................................................ 141
Control Reg i ster.................................................. ...... 141
Operation.................................................................. 140
Timer2 Module.................................................................. 140
2014 Microchip Technology Inc. DS20005350A-page 219
MCP19118/19
Timer2/4/6
Associ a te d Re g i sters..................... ............ ............. ..141
Timers
Timer1
T1CON..............................................................138
Timer2/4/6
TXCON.............................................................141
Timing Diagrams
Acknowledge Sequence ...........................................176
Baud Rate Generator with Clock Arbitration.. ...........170
BRG Reset due to SDA Arbitration during Start Condition
180
Bus Collision during a Repeated Start Condition (Case 1)
181
Bus Collision during a Repeated Start Condition (Case 2)
181
Bus Collision during a Start Condition (SCL = 0)......179
Bus Collision during a Stop Condition (Case 1)........182
Bus Collision during a Stop Condition (Case 2)........182
Bus Collision during Start Condition (SDA only).......179
Bus Collision for Transmit and Acknowledge............178
Capture/Compare/PWM..............................................33
Clock Synchronization ..............................................167
First Start Bit Timing .................. ...... ............ .............170
I2C Master Mode (7 or 10-Bit Transmission) ............173
I2C Master Mode (7-Bit Reception)...........................175
I2C Stop Condition Receive or Transmit Mode.........177
INT Pin Interrupt..........................................................94
Power-Up Timer............................. ................... ..........31
Repeat Start Condition..................... .. .... .. .. .. ....... .. ....171
Reset...........................................................................31
Start- Up Timer ........................ ............. ................... ....31
Time-Out Sequence
Case 1 ................................................................87
Case 2 ................................................................88
Case 3 ................................................................88
Timer0.........................................................................32
Timer1.........................................................................32
Wake-Up from Interrupt ............................................102
Watchdog Timer............................... .... .... .. ......... .... .. ..31
Timing Parameter Symbology........................ ...... ............. ..29
Timing Requirements
CLKOUT and I/O. . .......................................................31
External Clock.............................................................30
TRISA Register.................................................................114
TRISGPA ..........................................................................112
TRISGPA Register............................................................112
TRISGPB Register....................................................116, 117
TXCON (Timer2/4/6) Register ..........................................141
Typical Ap p l ication Circ u it..... ................................................9
Typica l Pe rformance Cu rv e s.............................. ............. ....53
U
Undervoltage Lockout
Input............................................................................37
Unity Gain Buffer............... ................... ............ ...................58
V
Voltage For Zero Current.......... .... .. ........... .... .. .... ......... .... ..42
W
Watchdog Timer (WDT).............. .... ......... .... .... .... .......87, 103
Associ a te d Re g i sters..................... ............ ............. ..104
Configuration Word w/ Watchdog Timer...................104
Operation..................................................................103
Period........................................................................103
Programming Considerations................................... 103
WCOL....................................................... 170, 172, 174, 176
WCOL Status Flag.................................... 170, 172, 174, 176
WPUGPA R e g i ste r ...... .......... ..... ...... ...... ...... ..... ...... ...... ... 11 4
WPUGPB R e g i ste r ...... .......... ..... ...... ...... ...... ..... ...... ...... ... 11 8
WWW Address ....... ...... ...... ............. ...... ...... ............. ...... .. 221
WWW, On-Line Support....................................................... 7
MCP19118/19
DS20005350A-page 220 2014 Microchip Technology Inc.
2014 Microchip Technology Inc. DS20005350A-page 221
MCP19118/19
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at
www.microchip.com. This web site is used as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
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Questions (FAQ), technical support requests,
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CUSTOMER CHANGE NOTIFICATION
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To register, access the Microchip web site at
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CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
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Customers should contact their distributor,
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Technical s upport is a vailable through the web si te
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MCP19118/19
DS20005350A-page 222 2014 Microchip Technology Inc.
NOTES:
2014 Microchip Technology Inc. DS20005350A-page 223
MCP19118/19
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP19118: Digitally Enhanced Power Analog Controller with
Integrated Synchronous Driver
MCP19119: Digitally Enhanced Power Analog Controller with
Integrated Synchronous Driver
Ta pe and Reel
Option: Blank = S tandard packaging (tube)
T = Tape and Reel
Temperature
Range: E= -40C to+ 125C( Extended)
Package: MJ = 24-lead Plastic Quad Flat, No Lead Package -
4x4x0.9 mm body (QFN)
MQ = 28-lead Plastic Quad Flat, No Lead Package -
5x5x0.9 mm body (QFN)
Examples:
a) MCP19 118-E/MJ: Exte nd ed temperatu re,
24LD QFN 4x4 package
b) MCP19118T-E/MJ: Tape and Reel,
Extended temperature,
24LD QFN 4x4 package
a) MCP19 119-E/MQ : Exte nd ed tem per atu re,
28LD QFN 5x5 package
b) MCP19119T-E/MQ: Tape and Reel,
Extended temperature,
28LD QFN 5x5 package
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
[X](1)
Tape and Reel
Option
-
MCP19118/19
DS20005350A-page 224 2014 Microchip Technology Inc.
NOTICE TO CUSTOMERS
This product is subject to a license from Power-One®, Inc. related to digital power technology
(DPT) patents owned by Power-One, Inc. This license does not extend to stand-alone power
supply products.
2014 Microchip Technology Inc. DS20005350A-page 225
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
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devices in life support and/or safety applications is entirely at
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conveyed, implicitly or otherwise, under any Microchip
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KleerNet logo, MiWi, MPASM, MPF, MPLAB Cert ified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology I ncorporat ed in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology I nc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidia r y of Mic rochip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporat ed, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63276-693-9
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that i ts family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005350A-page 226 2014 Microchip Technology Inc.
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Worldwide Sales and Service
03/25/14
