LTC6268-10/LTC6269-10
1
626810f
For more information www.linear.com/LTC6268-10
TYPICAL APPLICATION
FEATURES DESCRIPTION
4GHz Ultra-Low Bias
Current FET Input Op Amp
The LTC
®
6268-10/LTC6269-10 is a single/dual 4GHz FET-
input operational amplifier with extremely low input bias
current and low input capacitance. It also features low
input-referred current noise and voltage noise making it an
ideal choice for high speed transimpedance amplifiers, and
high-impedance sensor amplifiers. It is a decompensated
op amp that is gain-of-10 stable.
It operates on 3.1V to 5.25V supply and consumes 16.5mA
per amplifier. A shutdown feature can be used to lower
power consumption when the amplifier is not in use.
The LTC6268-10 single op amp is available in 8-lead SOIC
and 6-lead SOT-23 packages. The SOIC package includes
two unconnected pins which can be used to create an input
pin guard ring to protect against board leakage currents.
The LTC6269-10 dual op amp is available in 8-lead MSOP
with exposed pad and 3mm × 3mm 10-lead DFN packages.
They are fully specified over the –40°C to 85°C and the
–40°C to 125°C temperature ranges.
20kΩ TIA Frequency Response
20kΩ Gain 210MHz Transimpedance Amplifier
APPLICATIONS
n Gain Bandwidth Product: 4GHz
n Low Input Bias Current:
n ±3fA Typ. Room Temperature
n 4pA Max at 125°C
n Current Noise (100kHz): 7fA/√Hz
n Voltage Noise (1MHz): 4.0nV/√Hz
n Extremely Low CIN 0.45pF
n Rail-to-Rail Output
n AV ≥10
n Slew Rate: +1500V/µs, –1000V/µs
n Supply Range: 3.1V to 5.25V
n Quiescent Current: 16.5mA
n Operating Temp Range: –40°C to 125°C
n Single in 8-Lead SO-8, 6-Lead TSOT-23 Packages
n Dual in 8-Lead MS8, 3mm × 3mm 10-Lead
DFN 10 Packages
n Transimpedance Amplifiers
n ADC Drivers
n Photomultiplier Tube Post-Amplifier
n Low IBIAS Circuits
L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
+
–
LTC6268-10
626810 TA01
2.5V
PARASITIC
FEEDBACK C
2.5V
PD
–2.5V
VOUT = –IPD • 20k
BW = 210MHz
PD = OSI OPTOELECTRONICS, FCI-125G-006
20kΩ
IPD
FREQUENCY (Hz)
10k
100k
1M
10M
100M
1G
60
63
66
69
72
75
78
81
84
87
90
626810 TA01b
LTC6268-10/LTC6269-10
2
626810f
For more information www.linear.com/LTC6268-10
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V+ to V– ...........................................5.5V
Input Voltage ...............................V– – 0.2V to V+ + 0.2V
Input Current (+IN, –IN) (Note 2) ........................... ±1mA
Input Current (SHDN) ............................................ ±1mA
Output Current (IOUT) (Note 8, 9) ......................... 135mA
Output Short-Circuit Duration (Note 3) ... Thermally Limited
Operating Temperature Range
LTC6268-10I/LTC6269-10I ................... –40°C to 85°C
LTC6268-10H/LTC6269-10H .............. –40°C to 125°C
(Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
SHDN
V+
OUT
V–
NC
–IN
+IN
NC
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 120°C/W (NOTE 5)
1
2
3
6
5
4
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
V+
SHDN
–IN
OUT
V–
+IN
TJMAX = 150°C, θJA = 192°C/W (NOTE 5)
1
2
3
4
OUTA
–INA
+INA
V–
8
7
6
5
V+
OUTB
–INB
+INB
TOP VIEW
MS8E PACKAGE
8-LEAD PLASTIC MSOP
9
V–
TJMAX = 150°C, θJA = 40°C/W (NOTE 5)
EXPOSED PAD (PIN 9) IS V–, IT IS RECOMMENDED TO SOLDER TO PCB
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1V+
OUTB
–INB
+INB
SDB
OUTA
–INA
+INA
V–
SDA
11
V–
TJMAX = 150°C, θJA = 43°C/W (NOTE 5)
EXPOSED PAD (PIN 11) IS V–, IT IS RECOMMENDED TO SOLDER TO PCB
Specified Temperature Range (Note 4)
LTC6268-10I/LTC6269-10I ................... –40°C to 85°C
LTC6268-10H/LTC6269-10H .............. –40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature S8, S6 and
MS8E (Soldering, 10 sec) .................................300°C
LTC6268-10/LTC6269-10
3
626810f
For more information www.linear.com/LTC6268-10
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6268IS6-10#TRMPBF LTC6268IS6-10#TRPBF LTGQT 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6268HS6-10#TRMPBF LTC6268HS6-10#TRPBF LTGQT 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6268IS8-10#PBF LTC6268IS8-10#TRPBF 626810 8-Lead Plastic SOIC –40°C to 85°C
LTC6268HS8-10#PBF LTC6268HS8-10#TRPBF 626810 8-Lead Plastic SOIC –40°C to 125°C
LTC6269IMS8E-10#PBF LTC6269IMS8E-10#TRPBF LTGRM 8-Lead Plastic MSOP –40°C to 85°C
LTC6269HMS8E-10#PBF LTC6269HMS8E-10#TRPBF LTGRM 8-Lead Plastic MSOP –40°C to 125°C
LTC6269IDD-10#PBF LTC6269IDD-10#TRPBF LGRK 10-Lead Plastic DD –40°C to 85°C
LTC6269HDD-10#PBF LTC6269HDD-10#TRPBF LGRK 10-Lead Plastic DD –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage VCM = 2.75V
l
–0.7
–3
0.2 0.7
3
mV
mV
VCM = 4.0V
l
–1.0
–4.5
0.2 1.0
4.5
mV
mV
TC VOS Input Offset Voltage Drift VCM = 2.75V 4 μV/°C
IBInput Bias Current
(Notes 6, 8)
VCM = 2.75V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
VCM = 4.0V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
IOS Input Offset Current (Notes 6, 8) VCM = 2.75V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
l
l
–40
–450
–2
±6 40
450
2
fA
fA
pA
enInput Voltage Noise Density, VCM = 2.75V f = 1MHz 4.0 nV/√Hz
Input Voltage Noise Density, VCM = 4.0V f = 1MHz 4.0 nV/√Hz
Input Referred Noise Voltage f = 0.1Hz to 10Hz 12.6 μVP-P
inInput Current Noise Density, VCM = 2.75V f = 100kHz 7 fA/√Hz
Input Current Noise Density, VCM = 4.0V f = 100kHz 7 fA/√Hz
RIN Input Resistance Differential >1000 GΩ
Common Mode >1000 GΩ
CIN Input Capacitance Differential (DC to 200MHz) 0.1 pF
Common Mode (DC to 100MHz) 0.45 pF
CMRR Common Mode Rejection Ratio VCM = 0.5V to 3.2V (PNP Side)
l
72
68
85 dB
dB
VCM = –0.1V to 4.5V
l
64
52
82 dB
dB
IVR Input Voltage Range Guaranteed by CMRR l–0.1 4.5 V
The l denotes specifications that apply over the full operating
temp erature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, VCM = mid-supply), RL = 1kΩ, VSHDN
is unconnected.
5.0V ELECTRICAL CHARACTERISTICS
LTC6268-10/LTC6269-10
4
626810f
For more information www.linear.com/LTC6268-10
The l denotes specifications that apply over the full operating
temp erature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, VCM = mid-supply), RL = 1kΩ, VSHDN
is unconnected.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection Ratio VCM = 1.0V, VSUPPLY Ranges from 3.1V to 5.25V
l
78
75
95 dB
dB
Supply Voltage Range l3.1 5.25
AVOpen Loop Voltage Gain VOUT = 0.5V to 4.5V RLOAD = 10k
l
125
40
250 V/mV
V/mV
RLOAD = 100
l
10
2
21 V/mV
V/mV
VOL Output Swing Low (Input Overdrive 30mV)
Measured from V–ISINK = 10mA
l
80 140
200
mV
mV
ISINK = 25mA
l
130 200
260
mV
mV
VOH Output Swing High (Input Overdrive 30mV)
Measured from V+ISOURCE = 10mA
l
70 140
200
mV
mV
ISOURCE = 25mA
l
160 270
370
mV
mV
ISC Output Short Circuit Current (Note 9)
l
60
40
90 mA
mA
ISSupply Current Per Amplifier
l
15
9
16.5 18
25
mA
mA
Supply Current in Shutdown
(Per Amplifier)
l
0.39 0.85
1.5
mA
mA
ISHDN Shutdown Pin Current VSHDN = 0.75V
VSHDN =1.50V
l
l
–12
–12
2
2
12
12
µA
µA
VIL SHDN Input Low Voltage Disable l0.75 V
VIH SHDN Input High Voltage Enable. If SHDN is Unconnected, Amp is Enabled l1.5 V
tON Turn On Time, Delay from SHDN Toggle to
Output Reaching 90% of Target
SHDN Toggle from 0V to 2V 360 ns
tOFF Turn Off Time, Delay from SHDN Toggle to
Output High Z
SHDN Toggle from 2V to 0V 183 ns
GBW Gain-Bandwidth Product (Note 8) f = 10MHz l3500 4000 MHz
SR+ Slew Rate+ AV = 11 (RF = 1000, RG = 100)
VOUT = 0.5V to 4.5V, Measured 20% to 80%,
RLOAD = 500Ω
l
1100
600
1500
V/µs
V/µs
SR– Slew Rate– AV = 11 (RF = 1000, RG = 100)
VOUT = 4.5V to 0.5V, Measured 80% to 20%,
l
900
500
1000
V/µs
V/µs
FPBW Full Power Bandwidth (Note 7) 4VP-P 73 MHz
HD Harmonic Distortion(HD2/HD3) AV = 10, 10MHz. 2VP-P, VCM = 2.25V, RL = 1k,
RF = 450Ω, RG = 50Ω
–91/–96 dB
ILEAK Output Leakage Current in Shutdown VSHDN = 0V, VOUT = 0V
VSHDN = 0V, VOUT = 5V
400
400
nA
nA
5.0V ELECTRICAL CHARACTERISTICS
LTC6268-10/LTC6269-10
5
626810f
For more information www.linear.com/LTC6268-10
3.3V ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temp erature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, VCM = mid-supply), RL = 1kΩ,
VSHDN is unconnected.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage VCM = 1.0V
l
–0.7
–3
0.2 0.7
3
mV
mV
VCM = 2.3V
l
–1.0
–4.5
0.2 1.0
4.5
mV
mV
TC VOS Input Offset Voltage Drift VCM = 1.0V 4 µV/C
IBInput Bias Current (Notes 6, 8) VCM = 1.0V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
VCM = 2.3V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
l
l
–20
–900
–4
±3 20
900
4
fA
fA
pA
IOS Input Offset Current (Notes 6, 8) VCM = 1.0V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
l
l
–40
–450
–2
±6 40
450
2
fA
fA
pA
enInput Voltage Noise Density, VCM =1.0V f = 1MHz 4.0 nV/√Hz
Input Voltage Noise Density, VCM = 2.3V f = 1MHz 4.0 nV/√Hz
Input Referred Noise Voltage f = 0.1Hz to 10Hz 13.5 μVP-P
inInput Current Noise Density, VCM = 1.0V f = 100kHz 7 fA/√Hz
Input Current Noise Density, VCM = 2.3V f = 100kHz 7 fA/√Hz
RIN Input Resistance Differential
Common Mode
>1000
>1000
GΩ
GΩ
CIN Input Capacitance Differential (DC to 200MHz)
Common Mode (DC to 100MHz)
0.1
0.45
pF
pF
CMRR Common Mode Rejection Ratio VCM = 0.5V to 1.2V (PNP Side)
l
63
60
90 dB
dB
VCM = –0.1V to 2.8V (Full Range)
l
60
50
77 dB
dB
IVR Input Voltage Range Guaranteed by CMRR l–0.1 2.8 V
AVOpen Loop Voltage Gain VOUT = 0.5V to 2.8V RLOAD = 10k
l
80
40
200 V/mV
V/mV
RLOAD = 100
l
10
2
18 V/mV
V/mV
VOL Output Swing Low
(Input Overdrive 30mV).
Measured from V–
ISINK = 10mA
l
80 140
200
mV
mV
ISINK = 25mA
l
140 200
260
mV
mV
VOH Output Swing High
(Input Overdrive 30mV).
Measured from V+
ISOURCE = 10mA
l
80 140
200
mV
mV
ISOURCE = 25mA
l
170 270
370
mV
mV
ISC Output Short Circuit Current (Note 9)
l
50
35
80 mA
mA
ISSupply Current per Amplifier
l
14.5
9
16 17.5
25
mA
mA
LTC6268-10/LTC6269-10
6
626810f
For more information www.linear.com/LTC6268-10
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Current in Shutdown
(Per Amplifier)
l
0.23 0.6
1.2
mA
mA
ISHDN Shutdown Pin Current VSHDN = 0.75V
VSHDN = 1.5V
l
l
–12
–12
2
2
12
12
µA
µA
VIL SHDN Input Low Voltage Disable l0.75 V
VIH SHDN Input High Voltage Enable. If SHDN is Unconnected, Amp Is Enabled l1.5 V
tON Turn On Time, Delay from SHDN Toggle
to Output Reaching 90% of Target
SHDN Toggle from 0V to 2V 750 ns
tOFF Turn Off Time, Delay from SHDN Toggle
to Output High Z
SHDN Toggle from 2V to 0V 201 ns
GBW Gain-Bandwidth Product (Note 8) f = 10MHz l3500 4000 MHz
SR+ Slew Rate+ AV = 11 (RF = 1000, RG = 100),
VOUT = 1V to 2.3V, Measured 20% to 80%,
RLOAD = 500Ω
l
800
600
1500
V/µs
V/µs
SR– Slew Rate– AV = 11 (RF = 1000, RG = 100),
VOUT = 1V to 2.3V, Measured 80% to 20%,
RLOAD = 500Ω
l
600
400
1000
V/µs
V/µs
FPBW Full Power Bandwidth (Note 7) 2.3VP-P 105 MHz
HD Harmonic Distortion(HD2/HD3) A = 10, 10MHz. 2VP-P, VCM = 1.65V, RL = 1k,
RF = 450Ω, RG = 50Ω
–67/–78 dB
3.3V ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, VCM = mid-supply) RL = 1kΩ, VSHDN
is unconnected.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by two series connected ESD protection
diodes to each power supply. The input current should be limited to less
than 1mA. The input voltage should not exceed 200mV beyond the power
supply.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LTC6268-10I/LTC6269-10I is guaranteed to meet specified
performance from –40°C to 85°C. The LTC6268-10H/LTC6269-10H is
guaranteed to meet specified performance from –40°C to 125°C.
Note 5: Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are for short traces
connected to the leads.
Note 6: The input bias current is the average of the currents into the
positive and negative input pins. Typical measurement is for S8 package.
Note 7: Full Power Bandwidth is determined from distortion performance
in a gain-of-10 configuration with HD2/HD3 < –40dB (1%) as the criteria
for a valid output.
Note 8: This parameter is specified by design and/or characterization and
is not tested in production.
Note 9: The LTC6268-10/LTC6269-10 is capable of producing peak
output currents in excess of 135mA. Current density limitations within
the IC require the continuous current supplied by the output (sourcing or
sinking) over the operating lifetime of the part be limited to under 135mA
(Absolute Maximum).
LTC6268-10/LTC6269-10
7
626810f
For more information www.linear.com/LTC6268-10
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Voltage
vs Common Mode Voltage
Input Offset Voltage
vs Supply Voltage
Input Offset Voltage
vs Output Current
Input Offset Voltage Distribution Input Offset Voltage Distribution
TA = 25°C, unless otherwise noted.
VCM (V)
–2.5
–1
VOS (mV)
0.8
0.4
0.6
0
0.2
–0.8
–0.6
–0.4
–0.2
1
–1.25 1.25 2.50
626810 G05
VS = ±2.5V
VS (V)
3
–1
VOS (mV)
0.6
0.8
0
–0.8
–0.6
–0.4
–0.2
0.2
0.4
1
3.5 5 5.54 4.5
626810 G06
VS = 3.1V to 5.25V
VCM = 1V
OUTPUT CURRENT (mA)
–100
–0.20
VOS (mV)
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
–80 –60 40 60 80 10040 0–20 20
626810 G07
VCM = 1.5V
VS = ±2.5V
VCM = 0.25V
0
250
200
150
100
50
300
626810 G01
VS = ±2.5V
VCM = 0.25V
–0.4 –0.3 0.2 0.3 0.4 0.5 0.6–0.2 –01 00.1
VOS (mV)
NUMBER OF UNITS
0
200
150
100
50
250
626810 G02
VS = ±2.5V
VCM = 1.5V
–0.4 –0.3 0.2 0.3 0.4 0.5 0.6–0.2 –01 00.1
VOS (mV)
NUMBER OF UNITS
V
S
= ±2.5V
V
CM
= 0.25V
TEMPERATURE (°C)
–50
–30
–10
10
30
50
70
90
110
130
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OS (mV)
vs Temperature
Input Offset Voltage
626810 G03
V
S
= ±2.25V
V
CM
= 0.25V
H–GRADE
I–GRADE
DISTRIBUTION (µV/°C)
–15
–10
–5
0
5
10
15
0
5
10
15
20
25
NUMBER OF UNITS
Drift Distribution
Input Offset
626810 G04
FREQUENCY (MHz)
0.01
0.1
1
10
100
1000
0
20
40
60
80
100
PSRR vs Frequency
626810 G08
+PSRR
–PSRR
V
S
= ±2.5V, V
CM
= 0.25V
FREQUENCY (MHz)
0.01
0.1
1
10
100
1000
0
20
40
60
80
100
CMRR vs Frequency
626810 G09
Vs = ±2.5V, V
CM
= 0.25V
LTC6268-10/LTC6269-10
8
626810f
For more information www.linear.com/LTC6268-10
TYPICAL PERFORMANCE CHARACTERISTICS
Output Saturation Voltage
vs Load Current (Output Low)
Output Saturation Voltage
vs Load Current (Output High)
Output Short Circuit Current
vs Supply Voltage
Input Bias Current vs Common
Mode Voltage
Input Bias Current vs Supply
Voltage Input Bias Current vs Temperature
TA = 25°C, unless otherwise noted.
–IN
+IN
COMMON MODE VOLTAGE (V)
0.0
–300
INPUT BIAS CURRENT (fA)
INPUT BIAS CURRENT (fA)
300
200
VS = 5V
100
0
–100
–200
–10.0
10.0
8.0
6.0
4.0
2.0
0.0
–2.0
–4.0
–6.0
–8.0
1.0 4.0 5.02.0 3.0
626810 G10
SUPPLY VOLTAGE (V)
3.0
–10
INPUT BIAS CURRENT (fA)
–2
–1
–4
–3
–5
–7
–6
–9
–8
0
3.5 5.0 5.54.0 4.5
626810 G11
VS = 3.2V TO 5.25V
VCM = 1.0V
+IN
–IN
TEMPERATURE (°C)
25
–200
CURRENT (fA)
1400
1000
1200
800
400
600
0
200
1600
45 105 12565 85
626810 G12
–IN
+IN
VS = ±2.5V
VCM = 0.25V
LOAD CURRENT (mA)
0.0
0
OUTPUT SATURATION VOLTAGE (mV)
160
120
40
80
200
10.05.0 20.0 25.015.0
626810 G13
VS = ±2.5V
VCM = 0.25V
TA = –55°C
TA = 25°C
TA = 125°C
LOAD CURRENT (mA)
0.0
–280
OUTPUT SATURATION VOLTAGE (mV)
–40
–120
–200
–240
–80
–160
0
5.0 20.0 25.010.0 15.0
626810 G14
VS = ±2.5V
VCM = 0.25V
TA = –55°C
TA = 25°C
TA = 125°C
VS (V)
3.0
–200
ISC (mA)
150
0
–100
–150
50
100
–50
200
3.5 5.0 5.54.0 4.5
626810 G15
SINKING
SOURCING
TA = –55°C
TA = 25°C
TA = 125°C
FREQUENCY(MHz)
0.01
0.1
1
0
2
4
6
8
10
VOLTAGE NOISE DENSITY (nV/√Hz)
Density
Input Referred Voltage Noise
626810 G16
V
S
= ±2.5V
V
CM
= 0.25V
FREQUENCY (MHz)
0
100
200
300
400
500
0
2
4
6
8
10
VOLTAGE NOISE DENSITY (nV/√Hz)
Voltage Noise
Wide Band Input Referred
626810 G17
V
S
= ±2.5V
V
CM
= 0.25V
V
S
= ±2.5V
A
V
= 11
V
CM
= –0.25V
TIME (s)
0
1
2
3
4
5
6
7
8
9
10
–20
–16
–12
–8
–4
0
4
8
12
16
20
Referred Voltage Noise
0.1Hz to 10Hz Input
626810 G18
LTC6268-10/LTC6269-10
9
626810f
For more information www.linear.com/LTC6268-10
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY(MHz)
0
50
100
150
200
0
3
6
9
12
15
CURRENT NOISE DENSITY (ρA/√Hz)
Current Noise
Input Referred
626810 G20
V
S
= ±2.5V
V
CM
= 0.25V
GAIN
PHASE
FREQUENCY(MHz)
0.01
0.1
1
10
100
0
20.0
40.0
60.0
80.0
–135
–90
–45
0
45
Gain/Phase vs Frequency
626810 G21
FREQUENCY(MHz)
0.001
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
OUTPUT IMPEDANCE (Ω)
vs Frequency
Output Impedance
626810 G22
AV = 10V
AV = 100V
TIME (ns)
0
40
80
120
160
200
–200
–100
0
100
200
VOUT (mV)
Small Signal Step Response
626810 G25
V
S
= ±2.5V
V
CM
= 0.25V
AV = 10V/V, 20mV STEP
RL = 1kΩ, CL = 2.7pF
TIME (ns)
0
40
80
120
160
200
–200
–100
0
100
200
VOUT (mV)
Small Signal Step Response
626810 G26
V
S
= ±2.5V
V
CM
= 1.25V
AV = 10V/V, 20mV STEP
RL = 1kΩ, CL = 2.7pF
TIME (ns)
–0
40
80
120
160
200
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
VOUT (V)
Large Signal Step Response
626810 G27
V
S
= ±2.5V
V
CM
= 0.25V
AV = 10V/V, 200mV STEP
RL = 1kΩ
TIME (ns)
0
40
80
120
160
200
–200
–100
0
100
200
VOUT (mV)
Small Signal Step Response
626810 G24
V
S
= ±2.5V
V
CM
= 0.25V
AV = 10V/V, 20mV STEP
RL = 1kΩ
V
S
= ±2.5V
V
OUT
= 2VP–P
R
L
= 1kΩ
R
F
= 450Ω
R
G
= 50Ω
A
V
= 10V
V
CM
= –0.25V
HD2
HD3
FREQUENCY (MHz)
0.1
1
10
–140
–120
–100
–80
–60
–40
–20
Distortion vs Frequency
Harmonic
626810 G23
V
S
= ±2.5V
A
V
= 11
V
CM
= 1.5V
TIME (s)
0
1
2
3
4
5
6
7
8
9
10
–20
–16
–12
–8
–4
0
4
8
12
16
20
VOLTAGE NOISE (µV)
Referred Voltage Noise
0.1Hz to 10Hz Input
626810 G19
LTC6268-10/LTC6269-10
10
626810f
For more information www.linear.com/LTC6268-10
PIN FUNCTIONS
–IN: Inverting Input of the Amplifier. The voltage range of
this pin is from V– to V+ –0.5V.
+IN: Non-Inverting Input. The voltage range of this pin is
from V– to V+ –0.5V.
V+: Positive Power Supply. Total supply (V+ – V–) voltage
is from 3.1V to 5.25V. Split supplies are possible as long
as the total voltage between V+ and V– is between 3.1V
and 5.25V. A bypass capacitor of 0.1µF should be used
between V+ to ground as close to the pin as possible.
V–: Negative Power Supply. Normally tied to ground, it
can also be tied to a voltage other than ground as long
as the voltage difference between V+ and V– is between
3.1V and 5.25V. If it is not connected to ground, bypass
it to ground with a capacitor of 0.1µF as close to the pin
as possible.
SHDN, SDA, SDB: Active Low op amp shutdown, threshold
is 0.75V above the negative supply, V–. If left unconnected,
the amplifier is enabled.
OUT: Amplifier Output.
NC: Not connected. May be used to create a guard ring
around the input to guard against board leakage currents.
See Applications Information section for more details.
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Shutdown
Voltage
Supply Current vs Shutdown
Voltage
TA = 25°C, unless otherwise noted.
SHUT DOWN VOLTAGE (V)
0.0
0
SUPPLY CURRENT (mA)
25
15
20
10
5
1.5 2.00.5 1.0
626810 G31
VS = 5V
VCM = 2.75V
AV = 1
TA = –55°C
TA = 25°C
TA = 125°C
SHUT DOWN VOLTAGE (V)
0.0
0
SUPPLY CURRENT (mA)
25
15
20
10
5
1.5 2.00.5 1.0
626810 G32
VS = 3.1V
VCM = 1V
AV = 1
TA = –55°C
TA = 25°C
TA = 125°C
TIME (ns)
–0
40
80
120
160
200
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
VOUT (V)
Large Signal Step Response
626810 G28
V
S
= ±2.5V
V
CM
= 0.25V
AV = 10V/V, 200mV STEP
RL = 1kΩ, CL = 2.7pF
Supply Current vs Supply Voltage
SUPPLY VOLTAGE (V)
3.0
0
SUPPLY CURRENT (mA)
30
15
18
21
24
27
12
9
6
3
3.5 5.0 5.54.0 4.5
626810 G30
TA = –55°C
TA = 25°C
TA = 125°C
VCM = 1V
AV = 1
TIME (ns)
–0
40
80
120
160
200
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
VOUT (V)
Large Signal Step Response
626810 G29
V
S
= ±2.5V
V
CM
= 1.25V
AV = 10V/V, 200mV STEP
RL = 1kΩ, CL = 2.7pF
LTC6268-10/LTC6269-10
11
626810f
For more information www.linear.com/LTC6268-10
V–
V+
D7
D6 Q7
Q5 Q6
Q3 Q4
BUFFER
I0
C0
Q1
D4
Q2 D5
OUT
Q9
Q8
–IN
+IN
SHDN
D2
D0
D1
D3
INPUT REPLICA
INPUT REPLICA
CMOS INPUT
BUFFER
REFERENCE
GENERATION
COMPLEMENTARY
INPUT STAGE
CASCODE STAGE
626810 BD
(ONE POLARITY SHOWN IN INPUT PINS)
SIMPLIFIED SCHEMATIC
LTC6268-10 Simplified Schematic Diagram
LTC6268-10/LTC6269-10
12
626810f
For more information www.linear.com/LTC6268-10
OPERATION
The LTC6268-10/LTC6269-10 input signal range is speci-
fied from the negative supply to 0.5V below the positive
power supply, while the output can swing from rail-to-rail.
The schematic above depicts a simplified schematic of
the amplifier.
The input pins drive a CMOS buffer stage. The CMOS buffer
stage creates replicas of the input voltages to boot strap
the protection diodes. In turn, the buffer stage drives a
complementary input stage consisting of two differential
amplifiers, active over different ranges of input common
mode voltage. The main differential amplifier is active with
input common mode voltages from the negative power
supply to approximately 1.55V below the positive supply,
with the second amplifier active over the remaining range
to 0.5V below the positive supply rail. The buffer and
output bias stage uses a special compensation technique
ensuring stability of the op amp. The common emitter
topology of output transistors Q1/Q2 enables the output
to swing from rail-to-rail.
APPLICATIONS INFORMATION
Figure 1. Simplified TIA Schematic
voltage noise (eN) consists of flicker noise (or 1/f noise),
which dominates at lower frequencies, and thermal noise
which dominates at higher frequencies. For LTC6268-10,
the 1/f corner, or transition between 1/f and thermal noise,
is at 40kHz. The iN and RF contributions to input referred
noise current at the minus input are relatively straight
forward, while the eN contribution is amplified by the noise
gain. Because there is no gain resistor, the noise gain is
calculated using feedback resistor(RF) in conjunction
with impedance of CIN as (1 + 2π RF • CIN • Freq), which
increases with frequency. All of the contributions will be
limited by the closed loop bandwidth. The equivalent input
current noise is shown in Figure 2 and Figure 3, where eN
represents contribution from input referred voltage noise
(eN), iN represents contribution from input referred current
noise (iN), and RF represents contribution from feedback
resistor (RF). TIA gain (RF) and capacitance at input (CIN)
are also shown on each figure. Comparing Figure 2 and
Figure 3, iN dominates at higher frequencies. At lower
frequencies, the RF contribution dominates. Since aver-
age wide band eN is 4.0nV/√Hz (see typical performance
characteristics), RF contribution will become a lesser factor
at lower frequencies if RF is less than 860Ω as indicated
by the following equation:
eN/R
F
4kT /RF
1
–
+
CF
RF
CIN
GND
IN
OUT
626810 F01
Noise
To minimize the LTC6268-10’s noise over a broad range
of applications, careful consideration has been placed on
input referred voltage noise (eN), input referred current
noise (iN) and input capacitance CIN.
For a transimpedance amplifier (TIA) application such as
shown in Figure 1, all three of these op amp parameters,
plus the value of feedback resistance RF, contribute to noise
behavior in different ways, and external components and
traces will add to CIN. It is important to understand the
impact of each parameter independently. Input referred
LTC6268-10/LTC6269-10
13
626810f
For more information www.linear.com/LTC6268-10
Optimizing the Bandwidth for TIA Application
The capacitance at the inverting input node can cause
amplifier stability problems if left unchecked. When the
feedback around the op amp is resistive (RF), a pole will
be created with RF||CIN. This pole can create excessive
phase shift and possibly oscillation. Referring to Figure1,
the response at the output is:
R
F
1+2s+S2
2
Where RF is the DC gain of the TIA, ω is the natural fre-
quency of the closed loop, which can be expressed as:
=2GBW
R
F
(C
IN
+C
F
)
Hence the maximum achievable bandwidth of TIA is:
GBW
2 RF(CIN )
fTIA (Hz) =
APPLICATIONS INFORMATION
Figure 2 Figure 3
ζ is the damping factor of the loop, which can be ex-
pressed as:
=1
2
1
2GBW •RF(CIN +CF)
+RFCF+CIN +CF
1+AO
•2GBW
RFCIN +CF
( )
Where CIN is the total capacitance at the inverting input
node of the op amp, GBW is the gain bandwidth of the
op amp, and AO is the DC open loop gain of the op amp.
The small capacitor CF in parallel with RF can introduce
enough damping to stabilize the loop. By assuming CIN
>> CF, the following condition needs to be met for CF,
CF>CIN
•GBW •RF
Since LTC6268-10 is a decompensated op amp with gain-
of-10 stable, it requires that CIN/CF ≥ 10. Table 1 shows
the minimum and maximum CF for RF of 20k and 402k
and CIN of 1pF and 5pF.
Table 1. Min/Max CF
RFCIN = 1pF CIN = 5pF
20kΩ 60fF/100fF 140fF/500fF
402kΩ 13fF/100fF 31fF/500fF
FREQUENCY (MHz)
0.01
0.1
1
10
100
1000
0.001
0.01
0.1
1
10
100
CURRENT NOISE DENSITY pA/√Hz)
626810 F02
TOTAL
eN
iN
RN
RF = 20kΩ,
CIN = 1pF,
CF = 60fF
FREQUENCY (MHz)
0.01
0.1
1
10
100
1000
0.001
0.01
0.1
1
10
100
CURRENT NOISE DENSITY pA/√Hz)
6268-10 F03
TOTAL
eN
iN
RN
RF = 499kΩ,
CIN = 1pF,
CF = 13fF
LTC6268-10/LTC6269-10
14
626810f
For more information www.linear.com/LTC6268-10
APPLICATIONS INFORMATION
Achieving Higher Bandwidth with Higher Gain TIAs
Good layout practices are essential to achieving best
results from a TIA circuit. The following two examples
show drastically different results from an LTC6268-10 in
a 402k TIA. (See Figure 4.) The first example is with an
0805 resistor in a basic circuit layout. In a simple layout,
without expending a lot of effort to reduce feedback ca-
pacitance, the rise time achieved is about 87ns (Figure5),
implying a bandwidth of 4MHz (BW = 0.35/tr). In this case,
the bandwidth of the TIA is limited not by the GBW of
the LTC6268-10, but rather by the fact that the feedback
capacitance is reducing the actual feedback impedance
(the TIA gain itself) of the TIA. Basically, it’s a resistor
bandwidth limitation. The impedance of the 402kΩ is being
reduced by its own parasitic capacitance at high frequency.
From the 4MHz bandwidth and the 402k low frequency
gain, we can estimate the total feedback capacitance as
C = 1/(2π • 4MHz • 402kΩ) = 0.1pF. That’s fairly low, but
it can be reduced further.
With some extra layout techniques to reduce feedback
capacitance, the bandwidth can be increased. Note that
we are increasing the effective “bandwidth” of the 402k
resistance. A very powerful method to reduce feedback
capacitance is to shield the E field paths that give rise to
the capacitance. In this particular case, the method is to
place a ground trace between the resistor pads. Such a
ground trace shields the output field from getting to the
summing node end of the resistor and effectively shunts
the field to ground instead. The trace increases the output
load capacitance very slightly. See Figure 6 for a pictorial
representation.
Figure 7 shows the dramatic increase in bandwidth simply
by careful attention to low capacitance methods around
the feedback resistance. Bandwidth and rise time went
from 4MHz (87ns) to 34MHz (10.3ns), a factor of 8. The
ground trace used for LTC6268-10 was much wider than
that used in the case of the LTC6268 (see LTC6268 data
sheet), extending under the entire resistor dielectric. As-
suming all the bandwidth limit is due to feedback capaci-
tance (which isn't fair), we can calculate an upper limit of
Cf = 1/(2π • 402kΩ • 34MHz) = 11.6fF.
Figure 4. LTC6268-10 and Low Capacitance Photodiode
in a 402kΩ TIA
Figure 5. Time Domain Response of 402kΩ TIA without
Extra Effort to Reduce Feedback Capacitance. Rise Time
Is 87ns and BW Is 4MHz
PARASITIC
FEEDBACK C
402k
–2.5
626810 F04
K
A
PD
CASE
–2.5
PD: OSI FCI-125G-006
+2.5
IPD
VOUT
+
–
LTC6268-10
626810 F05
LASER DRIVE
(2mA/DIV)
OUTPUT
(500MV/DIV)
20ns/DIV
LTC6268-10/LTC6269-10
15
626810f
For more information www.linear.com/LTC6268-10
Maintaining Ultralow Input Bias Current
Leakage currents into high impedance signal nodes can
easily degrade measurement accuracy of fA signals. High
temperature applications are especially susceptible to these
issues. For humid environments, surface coating may be
necessary to provide a moisture barrier.
There are several factors to consider in a low input bias
current circuit. At the femtoamp level, leakage sources can
come from unexpected sources including adjacent signals
on the PCB, both on the same layer and from internal
layers, any form of contamination on the board from the
assembly process or the environment, other components
on the signal path and even the plastic of the device pack-
age. Care taken in the design of the system can mitigate
these sources and achieve excellent performance.
APPLICATIONS INFORMATION
Figure 6. A Normal Layout at Left and a Field-Shunting Layout at Right. Simply Adding a Ground Trace Under the Feedback Resistor
Does Much to Shunt Field Away from the Feedback Side and Dumps It to Ground. Note That the Dielectric Constant of Fr4 and
Ceramic Is Typically4, so Most of the Capacitance Is in the Solids and Not Through the Air. Feedback C is Reduced from 100fF at Left
to 11.6fF at Right
CERAMIC R SUBSTRATE RESISTIVE
ELEMENT
E FIELD ⇒ C
ENDCAP
K
A
G
–2.5
FR4
IPD
VOUT
+
–
LTC6268-10
E E
CERAMIC R SUBSTRATE RESISTIVE
ELEMENT
EXTRA GND
TRACE UNDER
RESISTOR
TAKE E FIELD TO GND,
MUCH LOWER C
ENDCAP
626810 F06
K
A
G
–2.5
FR4
IPD
VOUT
+
–
LTC6268-10
The choice of device package should be considered because
although each has the same die internally, the pin spacing
and adjacent signals influence the input bias current. The
LTC6268-10/LTC6269-10 is available in SOIC, MSOP,
DFN and SOT-23 packages. Of these, the SOIC has been
designed as the best choice for low input bias current. It
has the largest lead spacing which increases the imped-
ance of the package plastic and the pinout is such that the
two input pins are isolated on the far side of the package
from the other signals. The gull-wing leads on this pack-
age also allow for better cleaning of the PCB and reduced
contamination-induced leakage. The other packages have
advantages in size and pin count but do so by reducing
the input isolation. Leadless packages such as the DFN
offer the minimum size but have the smallest pin spacing
and may trap contaminants under the package.
The material used in the construction of the PCB can
sometimes influence the leakage characteristics of the
design. Exotic materials such as Teflon can be used to
improve leakage performance in specific cases but they
are generally not necessary if some basic rules are applied
in the design of conventional FR4 PCBs. It is important to
keep the high impedance signal path as short as possible
on the board. A node with high impedance is susceptible
to picking up any stray signals in the system so keeping it
as short as possible reduces this effect. In some cases, it
may be necessary to have a metallic shield over this por-
tion of the circuit. However, metallic shielding increases
capacitance. Another technique for avoiding leakage paths
is to cut slots in the PCB. High impedance circuits are also
Figure 7. LTC6268-10 in a 402kΩ TIA with Extra
Layout Effort to Reduce Feedback Capacitance Achieves
10.3ns Total System Rise Time, or 34MHz Total System
Bandwidth
626810 F07
LASER DRIVE
(2mA/DIV)
OUTPUT
(500MV/DIV)
20ns/DIV
LTC6268-10/LTC6269-10
16
626810f
For more information www.linear.com/LTC6268-10
APPLICATIONS INFORMATION
susceptible to electrostatic as well as electromagnetic ef-
fects. The static charge carried by a person walking by the
circuit can induce an interference on the order of 100’s of
femtoamps. A metallic shield can reduce this effect as well.
The layout of a high impedance input node is very important.
Other signals should be routed well away from this signal
path and there should be no internal power planes under
it. The best defense from coupling signals is distance and
this includes vertically as well as on the surface. In cases
where the space is limited, slotting the board around the
high impedance input nodes can provide additional isola-
tion and reduce the effect of contamination. In electrically
noisy environments the use of driven guard rings around
these nodes can be effective (see Figure 8). Adding any
additional components such as filters to the high imped-
ance input node can increase leakage. The leakage current
of a ceramic capacitor is orders of magnitude larger than
the bias current of this device. Any filtering will need to
be done after this first stage in the signal chain.
Driving Capacitive Load
The layout of the output node is also very important since
LTC6268-10/LTC6269-10 is very sensitive to capacitive
loading due to the very high gain-bandwidth-product. Ap-
preciable ringing will be observed when capacitive loading
is more than 5pF.
Low Input Offset Voltage
The LTC6268-10 has a maximum offset voltage of ±2.5mV
(PNP region) over temperature. The low offset voltage is
essential for precision applications. There are 2 differ-
ent input stages that are used depending on the input
common mode voltage. To increase the versatility of the
LTC6268-10, the offset voltages are trimmed for both
regions of operation.
Rail-to-Rail Output
The LTC6268-10 has a rail-to-rail output stage that has
excellent output drive capability. It is capable of deliver-
ing over ±40mA of output drive current over temperature.
Furthermore, the output can reach within 200mV of either
rail while driving ±10mA. Attention must be paid to keep
the junction temperature of the IC below 150°C.
Input Protection
To prevent breakdown of internal devices in the input stage,
the two op amp inputs should NOT be separated by more
than 2.0V. To help protect the input stage, internal circuitry
will engage automatically if the inputs are separated by
>2.0V and input currents will begin to flow. In all cases,
care should be taken so that these currents remain less
than 1mA. Additionally, if only one input is driven, inter-
nal circuitry will prevent any breakdown condition under
Figure 8. Example Layout of Inverting Amplifier
(or Transimpedance) with Leakage Guard Ring
(a)
(b)
HIGH-Z
SENSOR
(RIN)
LOW IMPEDANCE
NODE ABSORBS
LEAKAGE CURRENT
GUARD RING
LEAKAGE
CURRENT
NC
+IN
NC
–IN V+
V–
SD
OUT
‡
‡ NO LEAKAGE CURRENT. V–IN = VGRD
§ AVOID DISSIPATING SIGNIFICANT AMOUNTS OF POWER IN THIS RESISTOR.
IT WILL GENERATE THERMAL GRADIENTS WITH RESPECT TO THE INPUT PINS
AND LEAD TO THERMOCOUPLE-INDUCED ERROR.
VBIAS
V–IN
RF§
626810 F8
LTC6268-10
S8
NO SOLDER
MASK OVER
GUARD RING
+
–
GUARD RING
LTC6268-10
LEAKAGE
CURRENT
LEAKAGE CURRENT IS ABSORBED BY GROUND INSTEAD OF
CAUSING A MEASUREMENT ERROR.
VOUT
V+
V–
HIGH-Z SENSOR
RF
VBIAS
+
–
VIN RIN
LTC6268-10/LTC6269-10
17
626810f
For more information www.linear.com/LTC6268-10
APPLICATIONS INFORMATION
transient conditions. The worst-case differential input
voltage usually occurs when the +input is driven and the
output is accidentally shorted to ground while in a unity
gain configuration.
ESD
ESD Protection devices can be seen in the simplified sche-
matic. The +IN and –IN pins use a sophisticated method
of ESD protection that incorporates a total of 4 reverse-
biased diodes connected as 2 series diodes to each rail.
To maintain extremely low input bias currents, the center
node of each of these series diode chains is driven by a
buffered copy of the input voltage. This maintains the two
diodes connected directly to the input pins at low reverse
bias, minimizing leakage current of these ESD diodes to
the input pins.
The remaining pins have traditional ESD protection, using
reverse-biased ESD diodes connected to each power supply
rail. Care should be taken to make sure that the voltages
on these pins do not exceed the supply voltages by more
than 100mV or these diodes will begin to conduct large
amounts of current.
Shutdown
The LTC6268-10S6, LTC6268-10S8, and LTC6268-10DD
have SHDN pins that can shut down the amplifier to less
than 1.2mA supply current per amplifier. The SHDN pin
voltage needs to be within 0.75V of V– for the amplifier
to shut down. During shutdown, the output will be in a
high output resistance state, so the LTC6268-10 is suit-
able for multiplexer applications. The internal circuitry is
kept in a low current active state for fast recovery. When
left floating, the SHDN pin is internally pulled up to the
positive supply and the amplifier is enabled.
LTC6268-10/LTC6269-10
18
626810f
For more information www.linear.com/LTC6268-10
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
LTC6268-10/LTC6269-10
19
626810f
For more information www.linear.com/LTC6268-10
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
LTC6268-10/LTC6269-10
20
626810f
For more information www.linear.com/LTC6268-10
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MS8E) 0213 REV K
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
1.68
(.066)
1.88
(.074)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ±0.102
(.066 ±.004)
1.88 ±0.102
(.074 ±.004) 0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
0.1016 ±0.0508
(.004 ±.002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev K)
LTC6268-10/LTC6269-10
21
626810f
For more information www.linear.com/LTC6268-10
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTC6268-10/LTC6269-10
22
626810f
For more information www.linear.com/LTC6268-10
LINEAR TECHNOLOGY CORPORATION 2015
LT 0415 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6268-10
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
Op Amps
LTC6268/LTC6269 500MHz Ultra-Low Bias Current FET Input Op Amp Unity Gain Stable, Ultra Low Input Bias Current (3fA), 500MHz GBW
LTC6244 Dual 50MHz, Low Noise, Rail-to-Rail, CMOS Op Amp Unity Gain Stable, 1pA Input Bias Current, 100μV Max Offset.
LTC6240/LTC6241/
LTC6242
18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amp 18MHz GBW, 0.2pA Input Current, 125μV Max Offset.
LTC6252/LTC6253/
LTC6254
720MHz, 3.5mA Power Efficient Rail-to-Rail I/O Op Amp 720MHz GBW, Unity Gain Stable, Low Noise
LTC6246/LTC6247/
LTC6248
180MHz, 1mA Power Efficient Rail-to-Rail I/O Op Amps 180MHz GBW, Unity Gain Stable, Low Noise
LT1818 400MHz, 2500V/µs, 9mA Single Operational Amplifier Unity Gain Stable, 6nV/√Hz Unity Gain Stable
LT6236 215MHz, Rail-to-Rail Output, 1.1nV/√Hz, 3.5mA Op Amp Family 350μV Max Offset Voltage, 3V to 12.6V Supply
LT6411 650MHz Differential ADC Driver/Dual Selectable Amplifier SR 3300V/µs, 6ns 0.1% Settling.
SAR ADC
LTC2376-18/
LTC2377-18/
LTC2378-18/
LTC2379-18
18-Bit, 250ksps to 1.6Msps, Low Power SAR ADC, 102dB SNR 18mW at 1.6Msps, 3.4μW at 250sps, –126dB THD.
100kΩ TIA Frequency Response
100kΩ Gain 90MHz Transimpedance Amplifier
+
–
LTC6268-10
626810 TA02
2.5V
PARASITIC
FEEDBACK C
2.5V
PD
–2.5V
VOUT = –IPD • 100k
BW = 90MHz
PD = OSI OPTOELECTRONICS, FCI-125G-006
OUTPUT NOISE = 20mVP-P MEASURED ON A 100MHz BW
100kΩ
IPD
FREQUENCY(Hz)
1M
10M
100M
626810 TA3
79
109
106
103
100
97
94
91
88
85
82