XS1-U8A-64-FB96-C5 - XMOS - Datasheet.Live

XS1-U8A-64-FB96 Datasheet

2013/07/19 Document Number: X6319,

XS1-U8A-64-FB96 Datasheet 1

Table of Contents

1 xCORE Multicore Microcontrollers .............................. 2

2 XS1-U8A-64-FB96 Features .................................. 4

3 Pin Conﬁguration ....................................... 5

4 Signal Description ....................................... 6

5 Example Application Diagram ................................ 8

6 Product Overview ....................................... 9

7 xCORE Tile Resources ..................................... 10

8 Oscillator ............................................ 11

9 Boot Procedure ......................................... 12

10 Memory ............................................. 16

11 USB PHY ............................................. 16

12 Analog-to-Digital Converter ................................. 17

13 Supervisor Logic ........................................ 17

14 Energy management ..................................... 18

15 JTAG ............................................... 20

16 Board Integration ....................................... 21

17 Example XS1-U8A-64-FB96 Board Designs ......................... 25

18 DC and Switching Characteristics .............................. 29

19 Package Information ..................................... 34

20 Ordering Information ..................................... 35

Appendices .............................................. 36

A Conﬁguring the device .................................... 36

B Processor Status Conﬁguration ............................... 39

C xCORE Tile Conﬁguration .................................. 48

D Digital Node Conﬁguration .................................. 56

E Analogue Node Conﬁguration ................................ 63

F USB PHY Conﬁguration .................................... 67

G ADC Conﬁguration ...................................... 74

H Deep sleep memory Conﬁguration ............................. 77

I Oscillator Conﬁguration ................................... 77

J Real time clock Conﬁguration ................................ 79

K Power control block Conﬁguration ............................. 80

L Device Errata .......................................... 92

M JTAG, xSCOPE and Debugging ................................ 92

N Schematics Design Check List ................................ 94

O PCB Layout Design Check List ................................ 96

P Associated Design Documentation ............................. 97

Q Related Documentation .................................... 97

R Revision History ........................................ 98

X6319,

XS1-U8A-64-FB96 Datasheet 2

TO OUR VALUED CUSTOMERS

It is our intention to provide you with accurate and comprehensive documentation for the hardware and

software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/.

XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with

no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes

no representation that the information, or any particular implementation thereof, is or will be free from any

claims of infringement and again, shall have no liability in relation to any such claims.

XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries,

and may not be used without written permission. Company and product names mentioned in this document

are the trademarks or registered trademarks of their respective owners.

X6319,

XS1-U8A-64-FB96 Datasheet 3

1 xCORE Multicore Microcontrollers

The XS1-U Series is a comprehensive range of 32-bit multicore microcontrollers

that brings the low latency and timing determinism of the xCORE architecture to

mainstream embedded applications. Unlike conventional microcontrollers, xCORE

multicore microcontrollers execute multiple real-time tasks simultaneously. De-

vices consist of one or more xCORE tiles, each containing between four and eight

independent xCORE logical processors. Each logical core can execute computa-

tional code, advanced DSP code, control software (including logic decisions and

executing a state machine) or software that handles I/O.

Because xCORE multicore microcontrollers are completely deterministic, you can

write software to implement functions that traditionally require dedicated hardware.

You can simulate your program like hardware, and perform static timing analysis

using the xTIMEcomposer development tools.

The devices include scheduling hardware that performs functions similar to those

of an RTOS; and hardware that connects the cores directly to I/O ports, ensuring not

only fast processing but extremely low latency. The use of interrupts is eliminated,

ensuring deterministic operation.

I/O pins

DC-DC PMIC

Multichannel ADC

USB 2.0 PHY

SRAM

64KB

Security

OTP ROM

JTAG

debug

I/O pins

Hardware

response

ports

xCORE logical core

xTIME: schedulers

timers, clocks

PLL

SRAM

64KB

Security

OTP ROM

JTAG

debug

I/O pins

Hardware

response

ports

xCORE logical core

xTIME: schedulers

timers, clocks

xCONNECT

channels, links

xCONNECT: channels, links

xCONNECT

channels, links

PLL

Figure 1:

XS1-U Series:

6-16 core

devices

XS1-U devices are available in a range of resource densities, package, performance

and temperature grades depending on your needs. XS1-U devices have up to

eight logical cores on a single xCORE tile, providing 500-700 MIPS, 28 GPIO, and

64Kbytes of SRAM.

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XS1-U8A-64-FB96 Datasheet 4

1.1 xSOFTip

xCORE devices are backed with tested and proven IP blocks from the xSOFTip

library, which allow you to quickly add interface and processor functionality such

as Ethernet, PWM, graphics driver, and audio EQ to your xCORE device.

xSOFTip blocks are written in high level languages and use xCORE resources

to implement given function. This means xSOFTip is software and brings the

associated beneﬁts of easy maintenance and fast compilation time, while being

accessible to anyone with embedded C skills.

The graphical xSOFTip Explorer tool lets you browse available xSOFTip blocks

from our library, understand the resource usage, conﬁgure the blocks to your

speciﬁcation, and estimates the right device for your design. It is included in xTIME-

composer Studio or available as a standalone tool from xmos.com/downloads.

1.2 xTIMEcomposer Studio

Designing with XS1-U devices is simple thanks to the xTIMEcomposer Studio

development environment, which includes a highly eﬃcient compiler, debugger

and device programming tools. Because xCORE devices operate deterministically,

they can be simulated like hardware within the development tools: uniquely in

the embedded world, xTIMEcomposer Studio therefore includes a static timing

analyzer, cycle-accurate simulator, and high-speed in-circuit instrumentation.

xTIMEcomposer can also be used to load the executable ﬁle onto the device and

debug it over JTAG, programmed it into ﬂash memory on the board, or write it to

OTP memory on the device. The tools can also encrypt the ﬂash image and write

the decrpytion key securely to OTP memory.

xTIMEcomposer can be driven from either a graphical development environ-

ment that will be familiar to any C programmer, or the command line. They

are supported on Windows, Linux and MacOS X and available at no cost from

xmos.com/downloads.

Information on using the tools is provided in a separate user guide, X3766.

X6319,

XS1-U8A-64-FB96 Datasheet 5

2 XS1-U8A-64-FB96 Features

·Eight-Core Multicore Microcontroller with Advanced Multi-Core RISC Architecture

•Up to 500 MIPS shared between up to 8 real-time logical cores

•Each logical core has:

— Guaranteed throughput of between 1

/4and 1

/8of tile MIPS

— 16x32bit dedicated registers

•159 high-density 16/32-bit instructions

— All have single clock-cycle execution (except for divide)

—

32x32

→

64-bit MAC instructions for DSP, arithmetic and user-deﬁnable cryptographic

functions

·USB PHY, fully compliant with USB 2.0 speciﬁcation

·12b 1MSPS 4-channel SAR Analog-to-Digital Converter

·1 x LDO

·2 x DC-DC converters and Power Management Unit

·Watchdog Timer

·Onchip clocks/oscillators

•Crystal oscillator

•20MHz/31kHz silicon oscillators

·Programmable I/O

•38 general-purpose I/O pins, conﬁgurable as input or output

— Up to 9 x 1bit port, 2 x 4bit port, 1 x 8bit port

— 3 xCONNECT links

•Port sampling rates of up to 60 MHz with respect to an external clock

•32 channel ends for communication with other cores, on or oﬀ-chip

·Memory

•64KB internal single-cycle SRAM for code and data storage

•8KB internal OTP for application boot code

•128 bytes Deep Sleep Memory

·Hardware resources

•6 clock blocks

•10 timers

•4 locks

·JTAG Module for On-Chip Debug

·Security Features

•Programming lock disables debug and prevents read-back of memory contents

•AES bootloader ensures secrecy of IP held on external ﬂash memory

·Ambient Temperature Range

•0 °C to 70 °C

·Speed Grade

•5: 500 MIPS

·Power Consumption with USB running (typical)

•300 mW (typical)

•Sleep Mode: 500 µW

·96-pin FBGA package 0.8 mm pitch

X6319,

XS1-U8A-64-FB96 Datasheet 6

3 Pin Conﬁguration

AVDD ADC0

TDO ADC1

TCK RST_N

TMS TDI

XI/

CLK

DEBUG_

XO OSC_

EXT_N

X0D43/

WAKE NC

VSUP NC

SW1 SW1

VDDCORE VDDCORE

PGND

VSUP VSUP

PGND

VDD1V8

MODE[1]

SW2

MODE[0]

VDDIO

X0D22

X0D21

X0D20

X0D19

X0D18

X0D17

X0D16

X0D15 X0D13

X0D70X0D14

X0D69X0D68

X0D67X0D66

X0D65X0D64

X0D63X0D62

X0D61X0D58

X0D57X0D56

X0D55X0D54

X0D52 X0D53

X0D50 X0D51

X0D49X0D12

X0D11

X0D10

X0D01

X0D00

X0D24

X0D35

USB_

VBUS

MODE[3]

USB_

MODE[2]

USB_

ADC3

ADC2

GND GND GND GND

X6319,

XS1-U8A-64-FB96 Datasheet 7

4 Signal Description

Module Signal Function Type Active Properties

PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger Input, OT=Output Tristate, S=Switchable

RS=Required for SPI boot (§9)

Power

GND Digital ground GND —

PGND Power ground GND —

SW1 DCDC1 switched output voltage PWR —

SW2 DCDC2 switched output voltage PWR —

VDD1V8 1v8 voltage supply PWR —

VDDCORE Core voltage supply PWR —

VDDIO Digital I/O power PWR —

VSUP Power supply (3V3/5V0) PWR —

Analog

ADC0 Analog input Input —

ADC1 Analog input Input —

ADC2 Analog input Input —

ADC3 Analog input Input —

AVDD Supply and reference voltage PWR —

USB

USB_DN USB Serial Data Inverted I/O —

USB_DP USB Serial Data I/O —

USB_ID USB Device ID (OTG) - Reserved Output —

USB_VBUS USB Power Detect Pin Input —

Clocks

MODE[3:0] Boot mode select Input — PU, ST

OSC_EXT_N Use Silicon Oscillator Input Low ST

XI/CLK Crystal Oscillator/Clock Input Input —

XO Crystal Oscillator Output Output —

JTAG

DEBUG_N Multi-chip debug I/O Low PU

TCK Test clock Input — PU, ST

TDI Test data input Input — PU, ST

TDO Test data output Output — PD, OT

TMS Test mode select Input — PU, ST

Misc RST_N Global reset input Input Low PU, ST

I/O

X0D00 P1A0I/O — PDS, RS

X0D01 P1B0I/O — PDS, RS

X0D10 P1C0I/O — PDS, RS

X0D11 P1D0I/O — PDS, RS

X0D12 P1E0I/O — PDS

X0D13 XLB4

out P1F0I/O — PDS

X0D14 XLB3

out P4C0P8B0P16A8P32A28 I/O — PDS

X0D15 XLB2

out P4C1P8B1P16A9P32A29 I/O — PDS

X0D16 XLB1

out P4D0P8B2P16A10 I/O — PDS

X0D17 XLB0

out P4D1P8B3P16A11 I/O — PDS

X0D18 XLB0

in P4D2P8B4P16A12 I/O — PDS

(continued)

X6319,

XS1-U8A-64-FB96 Datasheet 8

Module Name Function Type Active Properties

I/O

X0D19 XLB1

in P4D3P8B5P16A13 I/O — PDS

X0D20 XLB2

in P4C2P8B6P16A14 P32A30 I/O — PDS

X0D21 XLB3

in P4C3P8B7P16A15 P32A31 I/O — PDS

X0D22 XLB4

in P1G0I/O — PDS

X0D24 P1I0I/O — PDS

X0D35 P1L0I/O — PDS

X0D43/WAKE P8D7P16B15 I/O — PUS

X0D49 XLC4

out P32A0I/O — PDS

X0D50 XLC3

out P32A1I/O — PDS

X0D51 XLC2

out P32A2I/O — PDS

X0D52 XLC1

out P32A3I/O — PDS

X0D53 XLC0

out P32A4I/O — PDS

X0D54 XLC0

in P32A5I/O — PDS

X0D55 XLC1

in P32A6I/O — PDS

X0D56 XLC2

in P32A7I/O — PDS

X0D57 XLC3

in P32A8I/O — PDS

X0D58 XLC4

in P32A9I/O — PDS

X0D61 XLD4

out P32A10 I/O — PDS

X0D62 XLD3

out P32A11 I/O — PDS

X0D63 XLD2

out P32A12 I/O — PDS

X0D64 XLD1

out P32A13 I/O — PDS

X0D65 XLD0

out P32A14 I/O — PDS

X0D66 XLD0

in P32A15 I/O — PDS

X0D67 XLD1

in P32A16 I/O — PDS

X0D68 XLD2

in P32A17 I/O — PDS

X0D69 XLD3

in P32A18 I/O — PDS

X0D70 XLD4

in P32A19 I/O — PDS

X6319,

XS1-U8A-64-FB96 Datasheet 9

5 Example Application Diagram

3V3/5V0

GND

C1 C2 C3

E5 VSS

VSS

VSUP

AVDD

U1A

XS1_U8A-64-FB96

VSUP

VSS

VDDCORE

VDDIO

SW1

VDD1V8

SW2

PGND

4U7 100N

C10

100N

GND

GND GND

GND

3V33V3

100N

GND GND

22U22U

C5C4

4U7

Figure 2:

Simpliﬁed

Reference

Schematic

X6319,

XS1-U8A-64-FB96 Datasheet 10

6 Product Overview

The XS1-U8A-64-FB96 comprises a digital and an analog node, as shown in Figure 3.

The digital node comprises an xCORE Tile, a Switch, and a PLL (Phase-locked-loop).

The analog node comprises the USB PHY, a multi-channel ADC (Analog to Digital

Converter), deep sleep memory, an oscillator, a real-time counter, and power

supply control.

I/O pins

DC-DC PMIC

Multichannel ADC

Oscillator

Real-time clock

Supervisor

Watchdog, brown out

PowerOnRST

USB 2.0 PHY

SRAM

64KB

Security

OTP ROM

JTAG

debug

I/O pins

Hardware

response

ports

xCORE logical core 0

xCORE logical core 1

xCORE logical core 2

xCORE logical core 3

xCORE logical core 4

xCORE logical core 5

xCORE logical core 6

xCORE logical core 7

xTIME: schedulers

timers, clocks

PLL

xCONNECT: channels, links

Channels

xCONNECT Links

Figure 3:

Block

Diagram

All communication between the digital and analog node takes place over a link that

is connected to the Switch of the digital node. As such, the analog node can be

controlled from any node on the system. The analog functions can be conﬁgured

using a set of node conﬁguration registers, and a set of registers for each of the

peripherals.

The device can be programmed using high-level languages such as C/C++ and the

XMOS-originated

language, which provides extensions to C that simplify the

control over concurrency, I/O and timing, or low-level assembler.

6.1 XCore Tile

The xCORE Tile is a ﬂexible multicore microcontroller component with tightly

integrated I/O and on-chip memory. The tile contains multiple logical cores that

run simultaneously, each of which is guaranteed a slice of processing power and

can execute computational code, control software and I/O interfaces. The logical

cores use channels to exchange data within a tile or across tiles. Multiple devices

can be deployed and connected using an integrated switching network, enabling

more resources to be added to a design. The I/O pins are driven using intelligent

ports that can serialize data, interpret strobe signals and wait for scheduled times

or events, making the device ideal for real-time control applications.

6.2 USB PHY

The USB PHY is fully compliant with the USB 2.0 speciﬁcation. It supports high

speed (480-Mbps) and full speed (12Mbps) operation.

X6319,

XS1-U8A-64-FB96 Datasheet 11

The XMOS XUD software component performs all the low-level I/O operations re-

quired to meet the USB 2.0 speciﬁcation, removing all low-level timing requirements

from the application.

6.3 ADC and Power Management

Each XS1-U8A-64-FB96 device includes a set of analog components, including a

12b, 4-channel ADC, power management unit, watchdog timer, real-time counter

and deep sleep memory. The device reduces the number of additional external

components required and allows designs to be implemented using simple 2-layer

boards.

7 xCORE Tile Resources

7.1 Logical cores, Synchronizers and Locks

The tile has up to 8 active logical cores, which issue instructions down a shared

four-stage pipeline. Instructions from the active cores are issued round-robin. If

up to 4 logical cores are active, each core is allocated a quarter of the processing

cycles. If more than four logical cores are active, each core is allocated at least

cycles (for ncores). Figure 4shows the guaranteed core performance depending

on the number of cores used.

Speed Grade, MIPS, and fre-

quency

Minimum MIPS per core (for ncores)

1 2 3 4 5 6 7 8

5: 500 MIPS, 500 MHz 125 125 125 125 100 83 71 63

Figure 4:

Logical core

performance

There is no way that the performance of a logical core can be reduced below these

predicted levels. Because cores may be delayed on I/O, however, their unused

processing cycles can be taken by other cores. This means that for more than

four logical cores, the performance of each core is often higher than the predicted

minimum.

Synchronizers are provided for fast synchronization in a group of logical cores. In

a single instruction a logical core can block until all other logical cores in a group

have reached the synchronizer. Locks are provided for fast mutual exclusion. A

logical core can acquire or release a lock in a single instruction.

7.2 Channel Ends, Links and Switch

Logical cores communicate using point-to-point connections formed between

two channel ends. Between tiles, channel communications are implemented over

xConnect Links and routed through switches. The links operate in either 2 wires per

direction or 5 wires per direction mode, depending on the amount of bandwidth

required. Circuit switched, streaming and packet switched data can both be

supported eﬃciently. Streams provide the fastest possible data rates between tiles

(up to 313 MBit/s), but each stream requires a single link to be reserved between

X6319,

XS1-U8A-64-FB96 Datasheet 12

switches on two tiles. All packet communications can be multiplexed onto a single

link.

Information on the supported routing topologies that can be used to connect

multiple devices together can be found in the XS1-L Link Performance and Design

Guide, X2999.

7.3 Ports and Clock Blocks

Ports provide an interface between the logical cores and I/O pins. The XS1-U8A-

64-FB96 includes a combination of 1bit, 4bit and 8bit ports. In addition the wider

ports are partially or fully bonded out making the connected pins available for I/O

or xCONNECT links. All pins of a port provide either output or input. Signals in

diﬀerent directions cannot be mapped onto the same port.

The operation of each port can be synchronized to a clock block. A clock block

can be connected to an external clock input, or it can be run from the divided

reference clock. A clock block can also output its signal to a pin. On reset, each

port is connected to clock block 0, which runs from the processor reference clock.

The ports and links are multiplexed, allowing the pins to be conﬁgured for use by

ports of diﬀerent widths or links. If an xConnect Link is enabled, the pins of the

underlying ports are disabled. If a port is enabled, it overrules ports with higher

widths that share the same pins. The pins on the wider port that are not shared

remain available for use when the narrower port is enabled. Ports always operate

at their speciﬁed width, even if they share pins with another port.

7.4 Processor Timers

Processor timers are 32-bit counters that are relative to the processor reference

clock. A processor timer is deﬁned to tick every 10 ns. This value is derived from

the reference clock, which is conﬁgured to tick at 100 MHz by default.

8 Oscillator

The oscillator block provides:

An oscillator circuit. Together with an external resonator (crystal or ceramic),

the oscillator circuit can provide a clock-source for both the real-time counter

and the xCORE Tile. The external resonator can be chosen by the designer to

have the appropriate frequency and accuracy. If desired, an external oscillator

can be used on the XI/CLK input pin.

A 20 MHz silicon oscillator. This enables the device to boot and execute code

without requiring an external crystal. The silicon oscillator is not as accurate as

an external crystal.

A 31,250 Hz oscillator. This enables the real-time counter to operate whilst the

device is in low-power mode. This oscillator is not as accurate as an external

crystal.

X6319,

XS1-U8A-64-FB96 Datasheet 13

The oscillator can be controlled through package pins, a set of peripheral registers,

and a digital node control register.

A package pin OSC_EXT_N is used to select the oscillator to use on boot. It must

be grounded to select an external resonator or connected to VDDIO to select the

on-chip 20 MHz oscillator. If an external resonator is used, then it must be in the

range 5-100 MHz. If the USB PHY is used, then an external crystal (12 or 24 MHz)

or an external oscillator (12, 24, 48, or 96 MHz) is required in order to provide a

stable USB clock. Two more package pins, MODE0 and MODE1 are used to inform

the node of the frequency.

The analog node runs at the frequency provided by the oscillator. Hence, increasing

the clock frequency will speed up operation of the analog node, and will speed up

communicating data with the digital node. The digital node has a PLL.

The PLL creates a high-speed clock that is used for the switch, tile, and reference

clock. The PLL multiplication value is selected through the two MODE pins, and

can be changed by software to speed up the tile or use less power. The MODE pins

are set as shown in Figure 5:

Oscillator MODE Tile PLL Ratio PLL settings

Frequency 1 0 Frequency OD F R

5-13 MHz 0 0 130-399.75 MHz 30.75 1 122 0

13-20 MHz 1 1 260-400.00 MHz 20 2 119 0

20-48 MHz 1 0 167-400.00 MHz 8.33 2 49 0

48-100 MHz 0 1 196-400.00 MHz 4 2 23 0

Figure 5:

PLL multiplier

values and

MODE pins

Figure 5also lists the values of

and

, which are the registers that deﬁne

the ratio of the tile frequency to the oscillator frequency:

Fcor e =Fosc ×F+1

2×

R+1×

OD +1

and

must be chosen so that 0

≤R≤

63,0

≤F≤

4095,0

≤OD ≤

7, and

260

MHz ≤Fosc ×F+1

2×1

R+1≤

GHz

. The

, and

values can be modiﬁed

by writing to the digital node PLL conﬁguration register.

The MODE pins must be held at a static value until the third rising edge of the

system clock following the deassertion of the system reset.

For 500 MHz parts, once booted, the PLL must be reprogrammed to provide this

tile frequency. The XMOS tools perform this operation by default.

Further details on conﬁguring the clock can be found in the XS1-L Clock Frequency

Control document, X1433.

9 Boot Procedure

The device is kept in reset by driving RST_N low. When in reset, all GPIO pins

are high impedance. When the device is taken out of reset by releasing RST_N

X6319,

XS1-U8A-64-FB96 Datasheet 14

the processor starts its internal reset process. After approximately 750,000 input

clocks, all GPIO pins have their internal pull-resistor enabled, and the processor

boots at a clock speed that depends on MODE0 and MODE1.

The processor boot procedure is illustrated in Figure 6. In normal usage, MODE[3:2]

controls the boot source according to the table in Figure 7. If bit 5 of the security

Start

Execute program

Primary boot

Bit [5] set

Boot according to

boot source pins

Copy OTP contents

to base of SRAM

Boot ROM

Yes

Security Register

OTP

Figure 6:

Boot

procedure

MODE[3] MODE[2] Boot Source

0 0 None: Device waits to be booted via JTAG

0 1 Reserved

1 0 xConnect Link B

1 1 SPI

Figure 7:

Boot source

pins

The boot image has the following format:

·A 32-bit program size sin words.

·Program consisting of s×4bytes.

A 32-bit CRC, or the value 0x0D15AB1E to indicate that no CRC check should be

performed.

The program size and CRC are stored least signiﬁcant byte ﬁrst. The program

is loaded into the lowest memory address of RAM, and the program is started

from that address. The CRC is calculated over the byte stream represented by the

program size and the program itself. The polynomial used is 0xEDB88320 (IEEE

802.3); the CRC register is initialized with 0xFFFFFFFF and the residue is inverted

to produce the CRC.

X6319,

XS1-U8A-64-FB96 Datasheet 15

9.1 Boot from SPI

If set to boot from SPI, the processor enables the four pins speciﬁed in Figure 8,

and drives the SPI clock at 2.5 MHz (assuming a 400 MHz core clock). A READ

command is issued with a 24-bit address 0x000000. The clock polarity and phase

are 0 / 0.

Pin Signal Description

X0D00 MISO Master In Slave Out (Data)

X0D01 SS Slave Select

X0D10 SCLK Clock

X0D11 MOSI Master Out Slave In (Data)

Figure 8:

SPI pins

The xCORE Tile expects each byte to be transferred with the least-signiﬁcant bit

ﬁrst. Programmers who write bytes into an SPI interface using the most signiﬁcant

bit ﬁrst may have to reverse the bits in each byte of the image stored in the SPI

device.

If a large boot image is to be read in, it is faster to ﬁrst load a small boot-loader

that reads the large image using a faster SPI clock, for example 50 MHz or as fast

as the ﬂash device supports.

The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed.

If required, an SPI boot program can be burned into OTP that uses diﬀerent pins.

9.2 Boot from xConnect Link

If set to boot from an xConnect Link, the processor enables Link B around 200

ns after the boot process starts. Enabling the Link switches oﬀ the pull-down on

resistors X0D16..X0D19, drives X0D16 and X0D17 low (the initial state for the

Link), and monitors pins X0D18 and X0D19 for boot-traﬃc. X0D18 and X0D19

must be low at this stage. If the internal pull-down is too weak to drain any residual

charge, external pull-downs of 10K may be required on those pins.

The boot-rom on the core will then:

1. Allocate channel-end 0.

Input a word on channel-end 0. It will use this word as a channel to acknowledge

the boot. Provide the null-channel-end 0x0000FF02 if no acknowledgment is

required.

3. Input the boot image speciﬁed above, including the CRC.

4. Input an END control token.

5. Output an END control token to the channel-end received in step 2.

6. Free channel-end 0.

7. Jump to the loaded code.

X6319,

XS1-U8A-64-FB96 Datasheet 16

9.3 Boot from OTP

If an xCORE tile is set to use secure boot (see Figure 6), the boot image is read

from address 0 of the OTP memory in the tile’s security module.

This feature can be used to implement a secure bootloader which loads an en-

crypted image from external ﬂash, decrypts and CRC checks it with the processor,

and discontinues the boot process if the decryption or CRC check fails. XMOS

provides a default secure bootloader that can be written to the OTP along with

secret decryption keys.

Each tile has its own individual OTP memory, and hence some tiles can be booted

from OTP while others are booted from SPI or the channel interface. This enables

systems to be partially programmed, dedicating one or more tiles to perform a

particular function, leaving the other tiles user-programmable.

9.4 Security register

The security register enables security features on the xCORE tile. The features

shown in Figure 9provide a strong level of protection and are suﬃcient for

providing strong IP security.

Feature Bit Description

Disable JTAG 0

The JTAG interface is disabled, making it impossible

for the tile state or memory content to be accessed

via the JTAG interface.

Disable Link access 1

Other tiles are forbidden access to the processor state

via the system switch. Disabling both JTAG and Link

access transforms an xCORE Tile into a “secure island”

with other tiles free for non-secure user application

code.

Secure Boot 5

The processor is forced to boot from address 0 of the

OTP, allowing the processor boot ROM to be bypassed

(see §9).

Redundant rows 7 Enables redundant rows in OTP.

Sector Lock 0 8 Disable programming of OTP sector 0.

Sector Lock 1 9 Disable programming of OTP sector 1.

Sector Lock 2 10 Disable programming of OTP sector 2.

Sector Lock 3 11 Disable programming of OTP sector 3.

OTP Master Lock 12

Disable OTP programming completely: disables up-

dates to all sectors and security register.

Disable JTAG-OTP 13

Disable all (read & write) access from the JTAG inter-

face to this OTP.

Disable Global Debug 14 Disables access to the DEBUG_N pin.

21..15

General purpose software accessable security register

available to end-users.

31..22

General purpose user programmable JTAG UserID

code extension.

Figure 9:

Security

features

X6319,

XS1-U8A-64-FB96 Datasheet 17

10 Memory

10.1 OTP

The xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with

a security register that conﬁgures system wide security features. The OTP holds

data in four sectors each containing 512 rows of 32 bits which can be used to

implement secure bootloaders and store encryption keys. Data for the security

from the OTP to SRAM and executed ﬁrst on the processor.

The OTP memory is programmed using three special I/O ports: the OTP address

port is a 16-bit port with resource ID 0x100200, the OTP data is written via a 32-bit

port with resource ID 0x200100, and the OTP control is on a 16-bit port with ID

0x100300. Programming is performed through libotp and xburn.

10.2 SRAM

The xCORE Tile integrates a single 64 KB SRAM bank for both instructions and

data. All internal memory is 32 bits wide, and instructions are either 16-bit or

32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and

are executed within one tile clock cycle. There is no dedicated external memory

interface, although data memory can be expanded through appropriate use of the

ports.

10.3 Deep Sleep Memory

The XS1-U8A-64-FB96 device includes 128 bytes of deep sleep memory for state

storage during sleep mode. Data stored in the memory is lost if the device is

powered down.

11 USB PHY

The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go func-

tionality. The PHY is conﬁgured through a set of peripheral registers (Appendix F),

and data is communicated through ports on the digital node. A library, libxud_s.a,

is provided to implement USB device functionality.

For device mode, USB_ID does not need to be connected; USB_DN and USB_DP must

be wired up to the USB-connector as a matched diﬀerential pair. The USB_VBUS pin

must be connected to the USB-connector. If the system is not bus-powered, a 2.2

uF capacitor to ground should be included on the VBUS pin of the USB-connector.

11.1 Logical Core Requirements

The XMOS XUD software component runs in a single logical core with endpoint and

application cores communicating with it via a combination of channel communica-

tion and shared memory variables.

X6319,

XS1-U8A-64-FB96 Datasheet 18

Each IN (host requests data from device) or OUT (data transferred from host to

device) endpoint requires one logical core.

To guarantee correct operation the USB logical core must run at at least 80 MIPS,

and the logical cores that communicate with the USB core must also run at 80

MIPS. This means that no more than six logical cores execute at any one time on a

500MHz device.

12 Analog-to-Digital Converter

The device has a 12-bit 1MSample/second Successive Approximation Register (SAR)

Analogue to Digital Converter (ADC). It has 4 input pins which are multiplexed

into the ADC. The sampling of the ADC is controlled using GPIO pin X0D24 that

is triggered either by writing to port 1I, or by driving the pin externally. On each

rising edge of the sample pin the ADC samples, holds and converts the data value

from one of the analog input pins. Each of the 4 inputs can be enabled individually.

Each of the enabled analog inputs is sampled in turn, on successive rising edges of

the sample pin. The data is transmitted to the channel-end that the user conﬁgures

during initialization of the ADC. Data is transmitted over the channel in individual

packets, or in packets that contain multiple consecutive samples. The ADC uses an

external reference voltage, nominally 3V3, which represents the full range of the

ADC. The ADC conﬁguration registers are documented in Appendix G.

The minimum latency for reading a value from the ADC into the xCORE register is

shown in Figure 10:

Sample Tile clock frequency Start of packet Subsequent samples

32-bit 500 MHz 840 ns 710 ns

32-bit 400 MHz 870 ns 740 ns

16-bit 500 MHz 770 ns 640 ns

16-bit 400 MHz 800 ns 670 ns

Figure 10:

Minimum

latency to

read sample

from ADC to

xCORE

13 Supervisor Logic

An independent supervisor circuit provides power-on-reset, brown-out, and watch-

dog capabilities. This facilitates the design of systems that fail gracefully, whilst

keeping BOM costs down.

The reset supervisor holds the chip in reset until all power supplies are good. This

provides a power-on-reset (POR). An external reset is optional and the pin RST_N

can be left not-connected.

If at any time any of the power supplies drop because of too little supply or too

high a demand, the power supervisor will bring the chip into reset until the power

supplies have been restored. This will reboot the system as if a cold-start has

happened.

X6319,

XS1-U8A-64-FB96 Datasheet 19

The 16-bit watchdog timer provides 1ms accuracy and runs independently of the

real-time counter. It can be programmed with a time-out of between 1 ms and 65

seconds (Appendix E). If the watchdog is not set before it times out, the XS1-U8A-

64-FB96 is reset. On boot, the program can read a register to test whether the

reset was due to the watchdog. The watchdog timer is only enabled and clocked

whilst the processor is in the AWAKE power state.

14 Energy management

XS1-U8A-64-FB96 devices can be powered by:

An external 5v core and 3.3v I/O supply, increasing eﬃciency for USB bus

powered applications.

·A single 3.3v supply.

14.1 DC-DC

XS1-U8A-64-FB96 devices include two DC-DC buck converters which can be con-

ﬁgured to take input voltages between 3.3-5V power supply and output circuit

voltages (nominally 1.8V and 1.0V) required by the analog peripherals and digital

node.

14.2 Power mode controller

The device transitions through multiple states during the power-up and powerdown

process.

The device is quiescent in the ASLEEP state, and is running in the AWAKE state. The

other states allow a controlled transition between AWAKE and ASLEEP.

A transition from AWAKE state to ASLEEP state is instigated by a sleep request:

either a write to the general control register or from the USB block requesting entry

to standby mode. Sleep requests must only be made in the AWAKE state.

A transition from the ASLEEP state into the AWAKE state is instigated by a wakeup

request triggered by a request from the USB block to exit standby mode an input,

or a timer. The device only responds to a wakeup stimulus in the ASLEEP state. If

wakeup stimulus occurs whilst transitioning from AWAKE to ASLEEP, the appropriate

response occurs when the ASLEEP state is reached.

Conﬁguration is through a set of registers documented in Appendix K.

14.3 Deep Sleep Modes and Real-Time Counter

The normal mode in which the XS1-U8A-64-FB96 operates is the AWAKE mode. In

this mode, all cores, memory, and peripherals operate as normal. To save power,

the XS1-U8A-64-FB96 can be put into a deep sleep mode, called ASLEEP, where

the digital node is powered down, and most peripherals are powered down. The

XS1-U8A-64-FB96 will stay in the ASLEEP mode until one of three conditions:

X6319,

XS1-U8A-64-FB96 Datasheet 20

RESET

AWAKE

ASLEEP

Power Up

Transition states

Waking 1/Waking 2

Transition states

Sleeping1/Sleeping2

Sleep Request

Enter USB Standby

Wakeup Request

Input Activity

Timer Event

Exit USB Standby System Reset

Figure 11:

XS1-U8A-64-

FB96 Power

Up States and

Transitions

1. An external pin is asserted or deasserted (set by the program);

2. The 64-bit real-time counter reaches a value set by the program; or

3. The USB host (if USB is enabled) performs a wakeup.

When the chip is awake, the real-time counter counts the number of clock ticks

on the oscillator. As such, the real-time counter will run at a ﬁxed ratio, but

synchronously with the 100 MHz timers on the xCORE Tile. When asleep, the

real-time counter can be automatically switched to the 31,250 Hz silicon oscillator

to save power (see Appendix I). To ensure that the real-time counter increases

linearly over time, a programmable value is added to the counter on every 31,250

Hz clock-tick. This means that the clock will run at a granularity of 31,250 Hz

but still maintain real-time in terms of the frequency of the main oscillator. If an

accurate clock is required, even whilst asleep, then an external crystal or oscillator

shall be provided that is used in both AWAKE and ASLEEP state.

The designer has to make a trade-oﬀ between accuracy of clocks when asleep

and awake, costs, and deep-sleep power consumption. Four example designs are

shown in Figure 12.

X6319,

XS1-U8A-64-FB96 Datasheet 21

Clocks used Power BOM Accuracy

Awake Asleep Asleep costs Awake Asleep

20 Mhz SiOsc 31,250 SiOsc lowest lowest lowest lowest

24 MHz Crystal 31,250 SiOsc lowest medium highest lowest

5 MHz ext osc 5 MHz ext osc medium highest highest highest

24 MHz Crystal 24 MHz crystal highest medium highest highest

Figure 12:

Example

trade-oﬀs in

oscillator

selection

During deep-sleep, the program can store some state in 128 bytes of Deep Sleep

Memory.

14.4 Requirements during sleep mode

Whilst in sleep mode, the device must still be powered as normal over 3V3 or 5V0

on VSUP, and 3V3 on VDDIO; however it will draw less power on both VSUP and

VDDIO.

For best results (lowest power):

·The XTAL bias and XTAL oscillators should be switched oﬀ.

·The sleep register should be conﬁgured to

·Disable all power supplies except DCDC2.

·Set all power supplies to PFM mode

·Mask the clock

·Assert reset

All GPIO and JTAG pins should be quiescent, and none should be driven against

a pull-up or pull-down.

·3V3 should be supplied as the input voltage to VSUP.

This will result in a power consumption of less than 100 uA on both VSUP and

VDDIO.

If any power supply loses power-good status during the asleep-to-awake or awake-

to-asleep transitions, a system reset is issued.

15 JTAG

The JTAG module can be used for loading programs, boundary scan testing, in-

circuit source-level debugging and programming the OTP memory.

The JTAG chain structure is illustrated in Figure 13. Directly after reset, three

TAP controllers are present in the JTAG chain: the debug TAP, the boundary scan

TAP and the processor TAP. The debug TAP provides access into the peripherals

including the ADC and USB. The boundary scan TAP is a standard 1149.1 compliant

X6319,

XS1-U8A-64-FB96 Datasheet 22

TDI

DEBUG_N

TDO

TCK

TMS

BS TAP PROCESSOR

TAP

TDITDI TDOTDO

DEBUG

TAP

TDI TDO

Figure 13:

JTAG chain

structure

TAP that can be used for boundary scan of the I/O pins. The processor TAP provides

access into the xCORE Tile, switch and OTP for loading code and debugging.

The JTAG module can be reset by holding TMS high for ﬁve clock cycles.

The DEBUG_N pin is used to synchronize the debugging of multiple processors.

This pin can operate in both output and input mode. In output mode and when

conﬁgured to do so, DEBUG_N is driven low by the device when the processor hits

a debug break point. Prior to this point the pin will be tri-stated. In input mode and

when conﬁgured to do so, driving this pin low will put the processor into debug

mode. Software can set the behavior of the processor based on this pin. This pin

should have an external pull up of 4K7-47K

Ω

or left not connected in single core

applications.

The JTAG device identiﬁcation register can be read by using the IDCODE instruction.

Its contents are speciﬁed in Figure 14.

Bit31 Device Identiﬁcation Register Bit0

Version Part Number Manufacturer Identity 1

00000000000000000011011000110011

0 0 0 0 3 6 3 3

Figure 14:

IDCODE

return value

The JTAG usercode register can be read by using the USERCODE instruction. Its

contents are speciﬁed in Figure 15. The OTP User ID ﬁeld is read from bits [22:31]

of the security register , see §10.1 (all zero on unprogrammed devices).

Bit31 Usercode Register Bit0

OTP User ID Unused Silicon Revision

00000000000000101100000000000000

0 0 0 2 C 0 0 0

Figure 15:

USERCODE

return value

16 Board Integration

XS1-U8A-64-FB96 devices are optimized for layout on low cost, 2 layer PCBs

using standard design rules. Careful layout is required to maximize the device

X6319,

XS1-U8A-64-FB96 Datasheet 23

performance. XMOS therefore recommends that the guidelines in this section are

followed when laying out boards using the device.

The XS1-U8A-64-FB96 includes two DC-DC buck converters that take input voltages

between 3.3-5V and output the 1.8V and 1.0V circuits required by the digital core

and analogue peripherals. The DC-DC converters should have a 4.7uF X5R or X7R

ceramic capacitor and a 100nF X5R or X7R ceramic capacitor on the VSUP input

pins M1 and M2. These capacitors must be placed as close as possible to the

those pins (within a maximum of 5mm), with the routing optimized to minimize

the inductance and resistance of the traces.

The SW output pin must have an LC ﬁlter on the output with a 4.7uH inductor and

22uF X5R capacitor. The capacitor must have maximum ESR value of 0.015R, and

the inductor should have a maximum DCR value of 0.07R, to meet the eﬃciency

speciﬁcations of the DC-DC converter, although this requirement may be relaxed if

a drop in eﬃciency is acceptable. A list of suggested inductors is in Figure 16.

Part number Current Max DCR Package

Yuden CBC2518T4R7M 680 mA 260 mΩ2518 (1007)

TDK NLCV32T-4R7M-PFR 620 mA 200 mΩ3225 (1210)

Murata LQM2HPN4R7MGC 800 mA 225 mΩ2520 (1008)

Sumida 0420CDMCBDS-4R7MC 3400 mA 80 mΩ4.7 x 4.3 mm

Wurth 744043004 1550 mA 70 mΩ4.8 x 4.8 mm

Murata LQH55DN4R7M03L 2700 mA 57 mΩ5750 (2220)

Figure 16:

Example 4.7

µH inductors

The traces from the SW output pins to the inductor and from the output capacitor

back to the VDD pins must be routed to minimize the coupling between them.

The power supplies must be brought up monotonically and input voltages must

not exceed speciﬁcation at any time.

The VDDIO supply to the XS1-U8A-64-FB96 requires a 100nF X5R or X7R ceramic

decoupling capacitor placed as close as possible to the supply pins.

If the ADC Is used, it requires a 100nF X5R or X7R ceramic decoupling capacitor

placed as close as possible to the AVDD pin. Care should be taken to minimize

noise on these inputs, and if necessary an extra 10uF decoupling capacitor and

ferrite bead can be used to remove noise from this supply.

The crystal oscillator requires careful routing of the XI / XO nodes as these are

high impedance and very noise sensitive. Hence, the traces should be as wide and

short as possible, and routed over a continuous ground plane. They should not

be routed near noisy supply lines or clocks. The device has a load capacitance of

18pF for the crystal. Care must be taken, so that the inductance and resistance of

the ground returns from the capacitors to the ground of the device is minimized.

X6319,

XS1-U8A-64-FB96 Datasheet 24

16.1 Land patterns and solder stencils

The land pattern recommendations in this document are based on a RoHS compliant

process and derived, where possible, from the nominal Generic Requirements for

Surface Mount Design and Land Pattern Standards

IPC-7351B

speciﬁcations. This

standard aims to achieve desired targets of heel, toe and side ﬁllets for solder-

joints.

Solder paste and ground via recommendations are based on our engineering and

development kit board production. They have been found to work and optimized

as appropriate to achieve a high yield. These factors should be taken into account

during design and manufacturing of the PCB.

The following land patterns and solder paste contains recommendations. Final land

pattern and solder paste decisions are the responsibility of the customer. These

should be tuned during manufacture to suit the manufacturing process.

The package is a 96 pin Ball Grid Array package on a 0.8mm pitch with 0.4mm

balls.

An example land pattern is shown in Figure 17.

ø0.35

0.80

8.80

Figure 17:

Example land

pattern

Pad widths and spacings are such that solder mask can still be applied between the

pads using standard design rules. This is highly recommended to reduce solder

shorts.

X6319,

XS1-U8A-64-FB96 Datasheet 25

16.2 Ground and Thermal Vias

Vias next to each ground ball into the ground plane of the PCB are recommended

for a low inductance ground connection and good thermal performance. Vias with

with a 0.6mm diameter annular ring and a 0.3mm drill would be suitable.

16.3 Moisture Sensitivity

XMOS devices are, like all semiconductor devices, susceptible to moisture absorp-

tion. When removed from the sealed packaging, the devices slowly absorb moisture

from the surrounding environment. If the level of moisture present in the device

is too high during reﬂow, damage can occur due to the increased internal vapour

pressure of moisture. Example damage can include bond wire damage, die lifting,

internal or external package cracks and/or delamination.

All XMOS devices are Moisture Sensitivity Level (MSL) 3 - devices have a shelf life

of 168 hours between removal from the packaging and reﬂow, provided they

are stored below 30C and 60% RH. If devices have exceeded these values or an

included moisture indicator card shows excessive levels of moisture, then the parts

should be baked as appropriate before use. This is based on information from Joint

IPC/JEDEC Standard For Moisture/Reﬂow Sensitivity Classiﬁcation For Nonhermetic

Solid State Surface-Mount Devices J-STD-020 Revision D.

X6319,

XS1-U8A-64-FB96 Datasheet 26

17 Example XS1-U8A-64-FB96 Board Designs

This section shows example schematics and layout for a 2-layer PCB.

Figures 18 shows example schematics and layout. It uses a 24 MHz crystal

for the clock, and an SPI ﬂash for booting. The XS1-U8A-64-FB96 is powered

directly from 5V. An optional ESD protection device is included to increase ESD

protection from 2 to 15 kV.

Figures 19 shows example schematics and layout for a design that uses an

oscillator rather than a crystal. If required a 3V3 oscillator can be used (for

example when sharing an oscillator with other parts of the design), but a resistor

bridge must be included to reduce the XI/CLK input from 3V3 to 1V8.

Figure 20 shows example schematics and layout for a design that does not use

USB and that runs oﬀ the internal 20 MHz oscillator. The XS1-U8A-64-FB96 is

powered directly from 3V3.

Flash, AVDD, RST, and JTAG connectivity are all optional. Flash can be removed if

the processor boots from OTP. The AVDD decoupler and wiring can be removed if

the ADC is not used. RST_N and all JTAG wiring can be removed if debugging is

not required (see Appendix M)

X6319,

XS1-U8A-64-FB96 Datasheet 27

Project Name

Size Sheet Name Rev

Sheet ofDate 08/02/2013

1V0

1 1

SU1 Reference Design - USB + Xtal

SU1_USB_XTAL.PrjPCB

XS1_U8A_FB96

VDDIO M6

VDDIO M7

VDDIO L6

VSS

SW1 J1

VSUP

VDDCORE K1

PGND L1

SW2 M5

VDD1V8M4

PGND M3

SW1 J2

VSUP

VDDCORE K2

PGND L2

VSUP

U1A

XS1_U8A_FB96

XI/CLK

DEBUG_N

MODE0

MODE1

MODE2

MODE3

RST_N

TCK

TDI

D2TDO

TMS

X0D0A9

X0D10 A10

X0D11 B10

X0D12 A11

X0D13 M12

X0D14 L11

X0D15 M11

X0D16 L10

X0D17 M10

X0D18 L9

X0D1B9

X0D19 M9

X0D20 L8

X0D21 M8

X0D35 A8

X0D49 A12

X0D50 B11

X0D51 B12

X0D52 C11

X0D53 C12

X0D54 D11

X0D55 D12

X0D56 E11

X0D57 E12

X0D58 F11

X0D61 F12

X0D62 G11

X0D63 G12

X0D64 H11

X0D65 H12

X0D66 J11

X0D67 J12

X0D68 K11

X0D69 K12

X0D70 L12

USB_DP

USB_DN

USB_VBUS

USB_ID

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

AVDD

X0D24 B8

X0D43/WAKEG1

OSC_EXT_N

X0D22 L7

U1B

GND GND

100N

4U7

GND GND GN D

3V3

4U7

22U

GND GND

24M

ABLS

33P

GND GND

RST_N

DEBUG_N

TCK

TMS

TDI

TDO

GND

MSEL

3V3A

USB_DP

USB_DN

M25P40

4MBIT

HOLD_N

7WP_N

VCC 8

GND 4

SO 2

SCK

CS_N

3V3

GND

10K

3V3

X0D0

X0D11

X0D10

X0D1

X0D0

X0D1

X0D10

100N

GND

HEADER_RA

11 12

GND

MSEL

TDI

TMS

TCK

DEBUG_N

TDO

RST_N

100N

C9 100N

C10

GND

USB_B

DP3

VBUS1

DM2

S1 5

GND 4

S2 6

C13

100N

C11

100N

C12

330R

XXA

FB1

GND GND

GND

USB_DN

USB_DP

TPD2E001

VCC

NC2

IO13

GND

IO2

GND

X0D11

X0D12

X0D13

X0D14

X0D15

X0D16

X0D17

X0D18

X0D19

X0D20

X0D21

X0D22

X0D24

X0D35

X0D43

X0D49

X0D50

X0D51

X0D52

X0D53

X0D54

X0D55

X0D56

X0D57

X0D58

X0D61

X0D62

X0D63

X0D64

X0D65

X0D66

X0D67

X0D68

X0D69

X0D70

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

X0D12

X0D13

X0D14

X0D15

X0D16 X0D17

X0D18 X0D19

X0D20 X0D21

X0D22

X0D24 X0D35

X0D43

X0D49

X0D50 X0D51

X0D52 X0D53

X0D54 X0D55

X0D56 X0D57

X0D58 X0D61

X0D62 X0D63

X0D64 X0D65

X0D66 X0D67

X0D68 X0D69

X0D70

NCP699SN33

GND

VIN

1VOUT5

NC4

GND

100N

C14

2U2

C15

GND GND

3V3

HEADER_17X2

3433

3231

3029

2827

2625

2423

2221

2019

1817

1615

1413

1211

109

1 2

GND

NCP699SN33

GND

VIN

1VOUT5

NC4

GND

100N

C17

2U2

C16

GND GND

3V3A

SU1 Power

Notes:

External crystal= 24 MHz

Mode [1:0] = 1 0 (internal pullup)

Analogue supply and LDO U4 may be ommited if ADC is

not required

Design assumes external 5V supply from USB

5V to 3V3 LDO IO Power

5V to 3V3 LDO Analogue Power

(only required if ADC is used)

USB and Input Protection

Program Flash

SU1 IO and Analogue

(only required if ADC is used)

XSYS Link

For prototype designs it is recommended that

one fo the three available xlink connections

is bought out to the XSYS to enable XSCOPE

debugging

Figure 18:

Example

XTAL

schematic,

with top and

bottom

layout of a

2-layer PCB

X6319,

XS1-U8A-64-FB96 Datasheet 28

Project Name

Size Sheet Name Rev

Sheet ofDate 08/02/2013

1V1

1 1

SU1 Reference Design USB + Osc

SU1_USB_OSC.PrjPCB

XS1_U8A_FB96

VDDIO M6

VDDIO M7

VDDIO L6

VSS

SW1 J1

VSUP

VDDCORE K1

PGND L1

SW2 M5

VDD1V8M4

PGND M3

SW1 J2

VSUP

VDDCORE K2

PGND L2

VSUP

U1A

XS1_U8A_FB96

XI/CLK

DEBUG_N

MODE0

MODE1

MODE2

MODE3

RST_N

TCK

TDI

D2TDO

TMS

X0D0A9

X0D10 A10

X0D11 B10

X0D12 A11

X0D13 M12

X0D14 L11

X0D15 M11

X0D16 L10

X0D17 M10

X0D18 L9

X0D1B9

X0D19 M9

X0D20 L8

X0D21 M8

X0D35 A8

X0D49 A12

X0D50 B11

X0D51 B12

X0D52 C11

X0D53 C12

X0D54 D11

X0D55 D12

X0D56 E11

X0D57 E12

X0D58 F11

X0D61 F12

X0D62 G11

X0D63 G12

X0D64 H11

X0D65 H12

X0D66 J11

X0D67 J12

X0D68 K11

X0D69 K12

X0D70 L12

USB_DP

USB_DN

USB_VBUS

USB_ID

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

AVDD

X0D24 B8

X0D43/WAKEG1

OSC_EXT_N

X0D22 L7

U1B

GND GND

100N

4U7

GND GND GND

3V3

4U7

22U

GND GND

GND

RST_N

DEBUG_N

TCK

TMS

TDI

TDO

GND

MSEL

3V3A

USB_DP

USB_DN

M25P40

4MBIT

HOLD_N

7WP_N

VCC 8

GND 4

SO 2

SCK

CS_N

3V3

GND

10K

3V3

X0D0

X0D11

X0D10

X0D1

X0D0

X0D1

X0D10

100N

GND

HEADER_RA

11 12

GND

MSEL

TDI

TMS

TCK

DEBUG_N

TDO

RST_N

100N

C10

GND

USB_B

DP3

VBUS1

DM2

S1 5

GND 4

S2 6

C13

100N

C11

100N

C12

330R

1700mA

FB1

GND GND

GND

USB_DN

USB_DP

TPD2E001

VCC

NC2

IO13

GND

IO2

GND

X0D11

X0D12

X0D13

X0D14

X0D15

X0D16

X0D17

X0D18

X0D19

X0D20

X0D21

X0D22

X0D24

X0D35

X0D43

X0D49

X0D50

X0D51

X0D52

X0D53

X0D54

X0D55

X0D56

X0D57

X0D58

X0D61

X0D62

X0D63

X0D64

X0D65

X0D66

X0D67

X0D68

X0D69

X0D70

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

X0D12

X0D13

X0D14

X0D15

X0D16 X0D17

X0D18 X0D19

X0D20 X0D21

X0D22

X0D24 X0D35

X0D43

X0D49

X0D50 X0D51

X0D52 X0D53

X0D54 X0D55

X0D56 X0D57

X0D58 X0D61

X0D62 X0D63

X0D64 X0D65

X0D66 X0D67

X0D68 X0D69

X0D70

NCP699SN33

GND

VIN

1VOUT5

NC4

GND

100N

C14

2U2

C15

GND GND

3V3

1V8

HEADER_17X2

3433

3231

3029

2827

2625

2423

2221

2019

1817

1615

1413

1211

109

1 2

GND

VCC 4

OUT3

GND

24MASDMB

10N

GND

1V8

NCP699SN33

GND

VIN

1VOUT5

NC4

GND

100N

2U2

C16

GND GND

3V3A

Notes:

External oscillator = 24 MHz (supplied by internal 1V8)

Mode [1:0] = 1 0 (internal pullup)

Analogue supply and LDO U4 may be ommited if ADC is

not required

Design assumes external 5V supply from USB

SU1 Power

SU1 IO and Analogue

(only required if ADC is used)

Program Flash

XSYS Link

USB and Input Protection

5V to 3V3 LDO IO Power

5V to 3V3 LDO Analogue Power

(only required if ADC is used)

For prototype designs it is recommended that

one fo the three available xlink connections

is bought out to the XSYS to enable XSCOPE

debugging

Figure 19:

Example

Oscillator

schematic,

with top and

bottom

layout of a

2-layer PCB

X6319,

XS1-U8A-64-FB96 Datasheet 29

Project Name

Size Sheet Name Rev

Sheet ofDate 14/05/2013

1V1

1 1

SU1 Reference Design Minimal

SU1_MINIMAL.PrjPCB

XS1_U8A_FB96

VDDIO M6

VDDIO M7

VDDIO L6

VSS

SW1 J1

VSUP

VDDCORE K1

PGND L1

SW2 M5

VDD1V8 M4

PGND M3

SW1 J2

VSUP

VDDCORE K2

PGND L2

VSUP

U1A

XS1_U8A_FB96

XI/CLK

DEBUG_N

MODE0

MODE1

MODE2

MODE3

RST_N

TCK

TDI

D2 TDO

TMS

X0D0 A9

X0D10 A10

X0D11 B10

X0D12 A11

X0D13 M12

X0D14 L11

X0D15 M11

X0D16 L10

X0D17 M10

X0D18 L9

X0D1 B9

X0D19 M9

X0D20 L8

X0D21 M8

X0D35 A8

X0D49 A12

X0D50 B11

X0D51 B12

X0D52 C11

X0D53 C12

X0D54 D11

X0D55 D12

X0D56 E11

X0D57 E12

X0D58 F11

X0D61 F12

X0D62 G11

X0D63 G12

X0D64 H11

X0D65 H12

X0D66 J11

X0D67 J12

X0D68 K11

X0D69 K12

X0D70 L12

USB_DP

USB_DN

USB_VBUS

USB_ID

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

AVDD

X0D24 B8

X0D43/WAKE G1

OSC_EXT_N

X0D22 L7

U1B

GND GND

100N

4U7

3V3

GND GND

3V3

4U7

22U

GND GND

3V3A

X0D0

X0D1

X0D10

100N

C10

GND

X0D11

X0D12

X0D13

X0D14

X0D15

X0D16

X0D17

X0D18

X0D19

X0D20

X0D21

X0D22

X0D24

X0D35

X0D43

X0D49

X0D50

X0D51

X0D52

X0D53

X0D54

X0D55

X0D56

X0D57

X0D58

X0D61

X0D62

X0D63

X0D64

X0D65

X0D66

X0D67

X0D68

X0D69

X0D70

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

X0D12

X0D13

X0D14

X0D15

X0D16 X0D17

X0D18 X0D19

X0D20 X0D21

X0D22

X0D24X0D35

X0D43

X0D49

X0D50 X0D51

X0D52 X0D53

X0D54 X0D55

X0D56 X0D57

X0D58 X0D61

X0D62 X0D63

X0D64 X0D65

X0D66 X0D67

X0D68 X0D69

X0D70

GND

X0D0 X0D1

X0D10 X0D11

3V3

GND

3635

3433

3231

3029

2827

2625

2423

2221

2019

1817

1615

1413

1211

109

1 2

HEADER_19X2

10U

4U7

100N

GND GND GND

3V3A3V3

Analogue Supply Filter

SU1 Power SU1 IO and Analogue

(only required if ADC is used) (only required if ADC is used)

Notes:

Internal oscillator = 20 MHz

Mode [1:0] = 1 0 (internal pullups)

Analogue supply and filter may be ommited if ADC is not

required

Design assumes external 3V3 supply

GND

3V3

Figure 20:

Example

minimal

system

schematic,

with top and

bottom

layout of a

2-layer PCB

X6319,

XS1-U8A-64-FB96 Datasheet 30

18 DC and Switching Characteristics

18.1 Operating Conditions

Symbol Parameter MIN TYP MAX UNITS Notes

VSUP Power Supply (3.3V Mode) 3.00 3.30 3.60 V

Power Supply (5V Mode) 4.50 5.00 5.50 V

VDDIO I/O supply voltage 3.00 3.30 3.60 V

AVDD Analog Supply and Reference

Voltage

3.00 3.30 3.60 V

Cl xCORE Tile I/O load capacitance 25 pF

Ta Ambient operating temperature 0 70 °C

Tj Junction temperature 125 °C

Tstg Storage temperature -65 150 °C

Figure 21:

Operating

conditions

18.2 DC1 Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

VDDCORE Tile Supply Voltage 0.95 1.00 1.05 V

V(RIPPLE) Ripple Voltage (peak to

peak)

10 40 mV

V(ACC) Voltage Accuracy -1 1 %

F(S) Switching Frequency 1 MHz

F(SVAR) Variation in Switching

Frequency

-10 10 %

Eﬃc Eﬃciency 80 %

PGT(HIGH) Powergood Threshold

(High)

95 %/VDDCORE

PGT(LOW) Powergood Threshold

(Low)

80 %/VDDCORE

Figure 22:

DC1 charac-

teristics

X6319,

XS1-U8A-64-FB96 Datasheet 31

18.3 DC2 Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

VDD1V8 1V8 Supply Voltage 1.80 V

V(RIPPLE) Ripple Voltage (peak to

peak)

10 40 mV

V(ACC) Voltage Accuracy -1 1 %

F(S) Switching Frequency 1 MHz

F(SVAR) Variation in Switching

Frequency

-10 10 %

Eﬃc Eﬃciency 80 %

PGT(HIGH) Powergood Threshold

(High)

95 %/VDD1V8

PGT(LOW) Powergood Threshold

(Low)

80 %/VDD1V8

Figure 23:

DC2 charac-

teristics

18.4 ADC Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

N Resolution 12 bits

Fs Conversion Speed 1 MSPS

Nch Number of Channels 4

Vin Input Range 0 AVDD V

DNL Diﬀerential Non Linearity -1 1.5 LSB

INL Integral Non Linearity -4 4 LSB

E(GAIN) Gain Error -10 10 LSB

E(OFFSET) Oﬀset Error -3 3 mV

T(PWRUP) Power time for ADC Clock Fclk 7 1/Fclk

ENOB Eﬀective Number of bits 10

Figure 24:

ADC charac-

teristics

18.5 USB Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

Figure 25:

USB charac-

teristics

Contact XMOS for further details on USB characteristics.

X6319,

XS1-U8A-64-FB96 Datasheet 32

18.6 Digital I/O Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

V(IH) Input high voltage 2.00 3.60 V

V(IL) Input low voltage -0.30 0.70 V

V(OH) Output high voltage 2.70 V

V(OL) Output low voltage 0.60 V

R(PU) Pull-up resistance 35K Ω

R(PD) Pull-down resistance 35K Ω

Figure 26:

Digital I/O

characteris-

tics

18.7 ESD Stress Voltage

Symbol Parameter MIN TYP MAX UNITS Notes

HBM Human body model 2.00 kV

CDM Charged Device Model 500 V

Figure 27:

ESD stress

voltage

18.8 Device Timing Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

T(RST) Reset pulse width 5 µs

T(INIT)

Initialisation (On Silicon Oscillator)

TBC ms

Initialisation (Crystal Oscillator) TBC ms

T(WAKE) Wake up time (Sleep to Active) TBC ms

T(SLEEP) Sleep Time (Active to Sleep) TBC ms

Figure 28:

Device timing

characteris-

tics

18.9 Crystal Oscillator Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

F(FO) Input Frequency 5 30 MHz

Figure 29:

Crystal

oscillator

characteris-

tics

18.10 External Oscillator Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

F(EXT) External Frequency 100 MHz

V(IH) Input high voltage 1.60 1.80 2.00 V

V(IL) Input low voltage 0.4 V

V(ACC) Voltage Accuracy TBC TBC %

Figure 30:

External

oscillator

characteris-

tics

X6319,

XS1-U8A-64-FB96 Datasheet 33

18.11 Power Consumption

Symbol Parameter MIN TYP MAX UNITS Notes

P(AWAKE) Active Power for awake states TBC 300 TBC mW

P(SLEEP) Power when asleep TBC 500 TBC µW

Figure 31:

xCORE Tile

currents

18.12 Clock

Symbol Parameter MIN TYP MAX UNITS Notes

f(MAX) Processor clock frequency 500 MHz

Figure 32:

Clock

18.13 Processor I/O AC Characteristics

Symbol Parameter MIN TYP MAX UNITS Notes

T(XOVALID) Input data valid window 8 ns

T(XOINVALID) Output data invalid window 9 ns

T(XIFMAX) Rate at which data can be sampled

with respect to an external clock

60 MHz

Figure 33:

I/O AC char-

acteristics

The input valid window parameter relates to the capability of the device to capture

data input to the chip with respect to an external clock source. It is calculated as the

sum of the input setup time and input hold time with respect to the external clock

as measured at the pins. The output invalid window speciﬁes the time for which

an output is invalid with respect to the external clock. Note that these parameters

are speciﬁed as a window rather than absolute numbers since the device provides

functionality to delay the incoming clock with respect to the incoming data.

Information on interfacing to high-speed synchronous interfaces can be found in

the XS1 Port I/O Timing document, X5821.

18.14 xConnect Link Performance

Symbol Parameter MIN TYP MAX UNITS Notes

B(2blinkP) 2wire link bandwidth

(packetized)

103 MBit/s

B(5blinkP) 5wire link bandwidth

(packetized)

271 MBit/s

B(2blinkS) 2wire link bandwidth

(streaming)

125 MBit/s

B(5blinkS) 5wire link bandwidth

(streaming)

313 MBit/s

Figure 34:

Link

performance

The asynchronous nature of links means that the relative phasing of CLK clocks is

not important in a multi-clock system, providing each meets the required stability

criteria.

X6319,

XS1-U8A-64-FB96 Datasheet 34

18.15 JTAG Timing

Symbol Parameter MIN TYP MAX UNITS Notes

f(TCK_D) TCK frequency (debug) TBC MHz

f(TCK_B) TCK frequency (boundary scan) TBC MHz

T(SETUP) TDO to TCK setup time TBC ns

T(HOLD) TDO to TCK hold time TBC ns

T(DELAY) TCK to output delay TBC ns

Figure 35:

JTAG timing

X6319,

XS1-U8A-64-FB96 Datasheet 35

19 Package Information

X6319,

XS1-U8A-64-FB96 Datasheet 36

19.1 Part Marking

Wafer lot code

CC - Number of logical cores

F - Product family

R - RAM (in log-2)

T - Temperature grade

M - MIPS grade

MC - Manufacturer

YYWW - Date

XX - Reserved

CCFRTM

MCYYWWXX

LLLLLL.LL

Figure 36:

Part marking

scheme

20 Ordering Information

Product Code Marking Qualiﬁcation Speed Grade

XS1–U8A–64–FB96–C5 8U6C5 Commercial 500 MIPS

XS1–U8A–64–FB96–I5 8U6I5 Industrial 500 MIPS

Figure 37:

Orderable

part numbers

X6319,

XS1-U8A-64-FB96 Datasheet 37

Appendices

A Conﬁguring the device

The device is conﬁgured through ten banks of registers, as shown in Figure 38.

I/O pins

DC-DC PMIC

Multichannel ADC

Oscillator

Real-time clock

Supervisor

Watchdog, brown out

PowerOnRST

USB 2.0 PHY

xCONNECT: channels, links

USB PHY registers

ADC registers

Oscillator registers

Real-time clock registers

Supervisor block registers

deep sleep, watchdog

Power control registers

Analog

node

registers

SRAM

64KB

Security

OTP ROM

JTAG

debug

I/O pins

Hardware

response

ports

xCORE logical core 0

xCORE logical core 1

xCORE logical core 2

xCORE logical core 3

xCORE logical core 4

xCORE logical core 5

xCORE logical core 6

xCORE logical core 7

xTIME: schedulers

timers, clocks

PLL

Channels

xCONNECT Links

Processor status

registers

xCORE

tile

registers

Digital

node

registers

Figure 38:

Registers

A.1 Accessing a processor status register

The processor status registers are accessed directly from the processor instruction

set. The instructions GETPS and SETPS read and write a word. The register number

should be translated into a processor-status resource identiﬁer by shifting the

getps(reg) and setps(reg,value) can be used from XC.

A.2 Accessing an xCORE Tile conﬁguration register

xCORE Tile conﬁguration registers can be accessed through the interconnect using

the functions

write_tile_config_reg(tileref, ...)

and

read_tile_config_reg(tile

>ref, ...)

, where

tileref

is the name of the xCORE Tile, e.g.

tile[1]

. These

functions implement the protocols described below.

Instead of using the functions above, a channel-end can be allocated to communi-

cate with the xCORE tile conﬁguration registers. The destination of the channel-end

should be set to 0xnnnnC20C where nnnnnn is the tile-identiﬁer.

A write message comprises the following:

control-token 24-bit response 16-bit 32-bit control-token

192 channel-end identiﬁer register number data 1

The response to a write message comprises either control tokens 3 and 1 (for

success), or control tokens 4 and 1 (for failure).

A read message comprises the following:

control-token 24-bit response 16-bit control-token

193 channel-end identiﬁer register number 1

X6319,

XS1-U8A-64-FB96 Datasheet 38

The response to the read message comprises either control token 3, 32-bit of data,

and control-token 1 (for success), or control tokens 4 and 1 (for failure).

A.3 Accessing digital and analogue node conﬁguration registers

Node conﬁguration registers can be accessed through the interconnect using

the functions

write_node_config_reg(device, ...)

and

read_node_config_reg(device,

>...)

, where

device

is the name of the node. These functions implement the

protocols described below.

Instead of using the functions above, a channel-end can be allocated to commu-

nicate with the node conﬁguration registers. The destination of the channel-end

should be set to 0xnnnnC30C where nnnn is the node-identiﬁer.

A write message comprises the following:

control-token 24-bit response 16-bit 32-bit control-token

192 channel-end identiﬁer register number data 1

The response to a write message comprises either control tokens 3 and 1 (for

success), or control tokens 4 and 1 (for failure).

A read message comprises the following:

control-token 24-bit response 16-bit control-token

193 channel-end identiﬁer register number 1

The response to a read message comprises either control token 3, 32-bit of data,

and control-token 1 (for success), or control tokens 4 and 1 (for failure).

A.4 Accessing a register of an analogue peripheral

Peripheral registers can be accessed through the interconnect using the functions

write_periph_32(device, peripheral, ...)

read_periph_32(device, peripheral, ...)

write_periph_8(device, peripheral, ...)

, and

read_periph_8(device, peripheral

>, ...)

; where device is the name of the analogue device, and peripheral is the

number of the peripheral. These functions implement the protocols described

below.

A channel-end should be allocated to communicate with the conﬁguration registers.

The destination of the channel-end should be set to

0xnnnnpp02

where

nnnn

is the

node-identiﬁer and pp is the peripheral identiﬁer.

A write message comprises the following:

control-token 24-bit response 8-bit 8-bit data control-token

36 channel-end identiﬁer register number size 1

The response to a write message comprises either control tokens 3 and 1 (for

success), or control tokens 4 and 1 (for failure).

A read message comprises the following:

X6319,

XS1-U8A-64-FB96 Datasheet 39

control-token 24-bit response 8-bit 8-bit control-token

37 channel-end identiﬁer register number size 1

The response to the read message comprises either control token 3, data, and

control-token 1 (for success), or control tokens 4 and 1 (for failure).

X6319,

XS1-U8A-64-FB96 Datasheet 40

B Processor Status Conﬁguration

The processor status control registers can be accessed directly by the processor

using processor status reads and writes (use

getps(reg)

and

setps(reg,value)

for

reads and writes).

Number Perm Description

0x00 RW RAM base address

0x01 RW Vector base address

0x02 RW xCORE Tile control

0x03 RO xCORE Tile boot status

0x05 RO Security conﬁguration

0x06 RW Ring Oscillator Control

0x07 RO Ring Oscillator Value

0x08 RO Ring Oscillator Value

0x09 RO Ring Oscillator Value

0x0A RO Ring Oscillator Value

0x10 DRW Debug SSR

0x11 DRW Debug SPC

0x12 DRW Debug SSP

0x13 DRW DGETREG operand 1

0x14 DRW DGETREG operand 2

0x15 DRW Debug interrupt type

0x16 DRW Debug interrupt data

0x18 DRW Debug core control

0x20 .. 0x27 DRW Debug scratch

0x30 .. 0x33 DRW Instruction breakpoint address

0x40 .. 0x43 DRW Instruction breakpoint control

0x50 .. 0x53 DRW Data watchpoint address 1

0x60 .. 0x63 DRW Data watchpoint address 2

0x70 .. 0x73 DRW Data breakpoint control register

0x80 .. 0x83 DRW Resources breakpoint mask

0x90 .. 0x93 DRW Resources breakpoint value

0x9C .. 0x9F DRW Resources breakpoint control register

Figure 39:

Summary

X6319,

XS1-U8A-64-FB96 Datasheet 41

B.1 RAM base address: 0x00

This register contains the base address of the RAM. It is initialized to 0x00010000.

Bits Perm Init Description

31:2 RW Most signiﬁcant 16 bits of all addresses.

1:0 RO - Reserved

0x00:

RAM base

address

B.2 Vector base address: 0x01

Base address of event vectors in each resource. On an interrupt or event, the 16

most signiﬁcant bits of the destination address are provided by this register; the

least signiﬁcant 16 bits come from the event vector.

Bits Perm Init Description

31:16 RW The most signiﬁcant bits for all event and interrupt vectors.

15:0 RO - Reserved

0x01:

Vector base

address

B.3 xCORE Tile control: 0x02

Bits Perm Init Description

31:6 RO - Reserved

5 RW 0

Set to 1 to select the dynamic mode for the clock divider when

the clock divider is enabled. In dynamic mode the clock divider is

only activated when all active logical cores are paused. In static

mode the clock divider is always enabled.

4 RW 0

Set to 1 to enable the clock divider. This slows down the xCORE

tile clock in order to use less power.

3:0 RO - Reserved

0x02:

xCORE Tile

control

B.4 xCORE Tile boot status: 0x03

This read-only register describes the boot status of the xCORE tile.

X6319,

XS1-U8A-64-FB96 Datasheet 42

Bits Perm Init Description

31:24 RO - Reserved

23:16 RO xCORE tile number on the switch.

15:9 RO - Reserved

8 RO Set to 1 if boot from OTP is enabled.

7:0 RO

The boot mode pins MODE0, MODE1, ..., specifying the boot

frequency, boot source, etc.

0x03:

xCORE Tile

boot status

B.5 Security conﬁguration: 0x05

Copy of the security register as read from OTP.

Bits Perm Init Description

31:0 RO Value.

0x05:

Security

conﬁguration

B.6 Ring Oscillator Control: 0x06

There are four free-running oscillators that clock four counters. The oscillators

can be started and stopped using this register. The counters should only be read

when the ring oscillator is stopped. The counter values can be read using four

subsequent registers. The ring oscillators are asynchronous to the xCORE tile clock

and can be used as a source of random bits.

Bits Perm Init Description

31:2 RO - Reserved

1 RW 0 Set to 1 to enable the xCORE tile ring oscillators

0 RW 0 Set to 1 to enable the peripheral ring oscillators

0x06:

Ring

Oscillator

Control

B.7 Ring Oscillator Value: 0x07

This register contains the current count of the xCORE Tile Cell ring oscillator. This

value is not reset on a system reset.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RO - Ring oscillator counter data.

0x07:

Ring

Oscillator

Value

X6319,

XS1-U8A-64-FB96 Datasheet 43

B.8 Ring Oscillator Value: 0x08

This register contains the current count of the xCORE Tile Wire ring oscillator. This

value is not reset on a system reset.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RO - Ring oscillator counter data.

0x08:

Ring

Oscillator

Value

B.9 Ring Oscillator Value: 0x09

This register contains the current count of the Peripheral Cell ring oscillator. This

value is not reset on a system reset.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RO - Ring oscillator counter data.

0x09:

Ring

Oscillator

Value

B.10 Ring Oscillator Value: 0x0A

This register contains the current count of the Peripheral Wire ring oscillator. This

value is not reset on a system reset.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RO - Ring oscillator counter data.

0x0A:

Ring

Oscillator

Value

B.11 Debug SSR: 0x10

This register contains the value of the SSR register when the debugger was called.

Bits Perm Init Description

31:0 RO - Reserved

0x10:

Debug SSR

B.12 Debug SPC: 0x11

This register contains the value of the SPC register when the debugger was called.

X6319,

XS1-U8A-64-FB96 Datasheet 44

Bits Perm Init Description

31:0 DRW Value.

0x11:

Debug SPC

B.13 Debug SSP: 0x12

This register contains the value of the SSP register when the debugger was called.

Bits Perm Init Description

31:0 DRW Value.

0x12:

Debug SSP

B.14 DGETREG operand 1: 0x13

The resource ID of the logical core whose state is to be read.

Bits Perm Init Description

31:8 RO - Reserved

7:0 DRW Thread number to be read

0x13:

DGETREG

operand 1

B.15 DGETREG operand 2: 0x14

Bits Perm Init Description

31:5 RO - Reserved

4:0 DRW Register number to be read

0x14:

DGETREG

operand 2

B.16 Debug interrupt type: 0x15

X6319,

XS1-U8A-64-FB96 Datasheet 45

Bits Perm Init Description

31:18 RO - Reserved

17:16 DRW

If the debug interrupt was caused by a hardware breakpoint

or hardware watchpoint, this ﬁeld contains the number of the

breakpoint or watchpoint. If multiple breakpoints or watch-

points trigger at once, the lowest number is taken.

15:8 DRW

If the debug interrupt was caused by a logical core, this ﬁeld

contains the number of that core. Otherwise this ﬁeld is 0.

7:3 RO - Reserved

2:0 DRW 0 Indicates the cause of the debug interrupt

1: Host initiated a debug interrupt through JTAG

2: Program executed a DCALL instruction

3: Instruction breakpoint

4: Data watch point

5: Resource watch point

0x15:

Debug

interrupt type

B.17 Debug interrupt data: 0x16

On a data watchpoint, this register contains the eﬀective address of the memory

operation that triggered the debugger. On a resource watchpoint, it countains the

resource identiﬁer.

Bits Perm Init Description

31:0 DRW Value.

0x16:

Debug

interrupt data

B.18 Debug core control: 0x18

This register enables the debugger to temporarily disable logical cores. When

returning from the debug interrupts, the cores set in this register will not execute.

This enables single stepping to be implemented.

Bits Perm Init Description

31:8 RO - Reserved

7:0 DRW

1-hot vector deﬁning which logical cores are stopped when not

in debug mode. Every bit which is set prevents the respective

logical core from running.

0x18:

Debug core

control

X6319,

XS1-U8A-64-FB96 Datasheet 46

B.19 Debug scratch: 0x20 .. 0x27

A set of registers used by the debug ROM to communicate with an external

debugger, for example over JTAG. This is the same set of registers as the Debug

Scratch registers in the xCORE tile conﬁguration.

Bits Perm Init Description

31:0 DRW Value.

0x20 .. 0x27:

Debug

scratch

B.20 Instruction breakpoint address: 0x30 .. 0x33

This register contains the address of the instruction breakpoint. If the PC matches

this address, then a debug interrupt will be taken. There are four instruction

breakpoints that are controlled individually.

Bits Perm Init Description

31:0 DRW Value.

0x30 .. 0x33:

Instruction

breakpoint

address

B.21 Instruction breakpoint control: 0x40 .. 0x43

This register controls which logical cores may take an instruction breakpoint, and

under which condition.

Bits Perm Init Description

31:24 RO - Reserved

23:16 DRW 0

A bit for each logical core in the tile allowing the breakpoint to

be enabled individually for each logical core.

15:2 RO - Reserved

1 DRW 0

Set to 1 to cause an instruction breakpoint if the PC is not

equal to the breakpoint address. By default, the breakpoint is

triggered when the PC is equal to the breakpoint address.

0 DRW 0 When 1 the instruction breakpoint is enabled.

0x40 .. 0x43:

Instruction

breakpoint

control

B.22 Data watchpoint address 1: 0x50 .. 0x53

This set of registers contains the ﬁrst address for the four data watchpoints.

X6319,

XS1-U8A-64-FB96 Datasheet 47

Bits Perm Init Description

31:0 DRW Value.

0x50 .. 0x53:

Data

watchpoint

address 1

B.23 Data watchpoint address 2: 0x60 .. 0x63

This set of registers contains the second address for the four data watchpoints.

Bits Perm Init Description

31:0 DRW Value.

0x60 .. 0x63:

Data

watchpoint

address 2

B.24 Data breakpoint control register: 0x70 .. 0x73

This set of registers controls each of the four data watchpoints.

Bits Perm Init Description

31:24 RO - Reserved

23:16 DRW 0

A bit for each logical core in the tile allowing the breakpoint to

be enabled individually for each logical core.

15:3 RO - Reserved

2 DRW 0

Set to 1 to enable breakpoints to be triggered on loads. Break-

points always trigger on stores.

1 DRW 0

By default, data watchpoints trigger if memory in the range

[Address1..Address2] is accessed (the range is inclusive of Ad-

dress1 and Address2). If set to 1, data watchpoints trigger if

memory outside the range (Address2..Address1) is accessed

(the range is exclusive of Address2 and Address1).

0 DRW 0 When 1 the instruction breakpoint is enabled.

0x70 .. 0x73:

Data

breakpoint

control

B.25 Resources breakpoint mask: 0x80 .. 0x83

This set of registers contains the mask for the four resource watchpoints.

X6319,

XS1-U8A-64-FB96 Datasheet 48

Bits Perm Init Description

31:0 DRW Value.

0x80 .. 0x83:

Resources

breakpoint

mask

B.26 Resources breakpoint value: 0x90 .. 0x93

This set of registers contains the value for the four resource watchpoints.

Bits Perm Init Description

31:0 DRW Value.

0x90 .. 0x93:

Resources

breakpoint

value

B.27 Resources breakpoint control register: 0x9C .. 0x9F

This set of registers controls each of the four resource watchpoints.

Bits Perm Init Description

31:24 RO - Reserved

23:16 DRW 0

A bit for each logical core in the tile allowing the breakpoint to

be enabled individually for each logical core.

15:2 RO - Reserved

1 DRW 0

By default, resource watchpoints trigger when the resource id

masked with the set Mask equals the Value. If set to 1, resource

watchpoints trigger when the resource id masked with the set

Mask is not equal to the Value.

0 DRW 0 When 1 the instruction breakpoint is enabled.

0x9C .. 0x9F:

Resources

breakpoint

control

X6319,

XS1-U8A-64-FB96 Datasheet 49

C xCORE Tile Conﬁguration

The xCORE Tile control registers can be accessed using conﬁguration reads and

writes (use

write_tile_config_reg(tileref, ...)

and

read_tile_config_reg(tileref,

>...) for reads and writes).

Number Perm Description

0x00 RO Device identiﬁcation

0x01 RO xCORE Tile description 1

0x02 RO xCORE Tile description 2

0x04 CRW Control PSwitch permissions to debug registers

0x05 CRW Cause debug interrupts

0x06 RW xCORE Tile clock divider

0x07 RO Security conﬁguration

0x10 .. 0x13 RO PLink status

0x20 .. 0x27 CRW Debug scratch

0x40 RO PC of logical core 0

0x41 RO PC of logical core 1

0x42 RO PC of logical core 2

0x43 RO PC of logical core 3

0x44 RO PC of logical core 4

0x45 RO PC of logical core 5

0x46 RO PC of logical core 6

0x47 RO PC of logical core 7

0x60 RO SR of logical core 0

0x61 RO SR of logical core 1

0x62 RO SR of logical core 2

0x63 RO SR of logical core 3

0x64 RO SR of logical core 4

0x65 RO SR of logical core 5

0x66 RO SR of logical core 6

0x67 RO SR of logical core 7

0x80 .. 0x9F RO Chanend status

Figure 40:

Summary

X6319,

XS1-U8A-64-FB96 Datasheet 50

C.1 Device identiﬁcation: 0x00

Bits Perm Init Description

31:24 RO Processor ID of this xCORE tile.

23:16 RO Number of the node in which this xCORE tile is located.

15:8 RO xCORE tile revision.

7:0 RO xCORE tile version.

0x00:

Device

identiﬁcation

C.2 xCORE Tile description 1: 0x01

This register describes the number of logical cores, synchronisers, locks and

channel ends available on this xCORE tile.

Bits Perm Init Description

31:24 RO Number of channel ends.

23:16 RO Number of locks.

15:8 RO Number of synchronisers.

7:0 RO - Reserved

0x01:

xCORE Tile

description 1

C.3 xCORE Tile description 2: 0x02

This register describes the number of timers and clock blocks available on this

xCORE tile.

Bits Perm Init Description

31:16 RO - Reserved

15:8 RO Number of clock blocks.

7:0 RO Number of timers.

0x02:

xCORE Tile

description 2

C.4 Control PSwitch permissions to debug registers: 0x04

This register can be used to control whether the debug registers (marked with

permission CRW) are accessible through the tile conﬁguration registers. When this

bit is set, write -access to those registers is disabled, preventing debugging of the

xCORE tile over the interconnect.

X6319,

XS1-U8A-64-FB96 Datasheet 51

Bits Perm Init Description

31:1 RO - Reserved

0 CRW

Set to 1 to restrict PSwitch access to all CRW marked registers to

become read-only rather than read-write.

0x04:

Control

PSwitch

permissions

to debug

registers

C.5 Cause debug interrupts: 0x05

This register can be used to raise a debug interrupt in this xCORE tile.

Bits Perm Init Description

31:2 RO - Reserved

1 RO 0 Set to 1 when the processor is in debug mode.

0 CRW 0 Set to 1 to request a debug interrupt on the processor.

0x05:

Cause debug

interrupts

C.6 xCORE Tile clock divider: 0x06

This register contains the value used to divide the PLL clock to create the xCORE

tile clock. The divider is enabled under control of the tile control register

Bits Perm Init Description

31:8 RO - Reserved

7:0 RW Value of the clock divider minus one.

0x06:

xCORE Tile

clock divider

C.7 Security conﬁguration: 0x07

Copy of the security register as read from OTP.

Bits Perm Init Description

31:0 RO Value.

0x07:

Security

conﬁguration

C.8 PLink status: 0x10 .. 0x13

Status of each of the four processor links; connecting the xCORE tile to the switch.

X6319,

XS1-U8A-64-FB96 Datasheet 52

Bits Perm Init Description

31:26 RO - Reserved

25:24 RO 00 - ChannelEnd, 01 - ERROR, 10 - PSCTL, 11 - Idle.

23:16 RO

Based on SRC_TARGET_TYPE value, it represents channelEnd ID

or Idle status.

15:6 RO - Reserved

5:4 RO Two-bit network identiﬁer

3 RO - Reserved

2 RO

1 when the current packet is considered junk and will be thrown

away.

1 RO 0

Set to 1 if the switch is routing data into the link, and if a route

exists from another link.

0 RO 0

Set to 1 if the link is routing data into the switch, and if a route

is created to another link on the switch.

0x10 .. 0x13:

PLink status

C.9 Debug scratch: 0x20 .. 0x27

A set of registers used by the debug ROM to communicate with an external

debugger, for example over the switch. This is the same set of registers as the

Debug Scratch registers in the processor status.

Bits Perm Init Description

31:0 CRW Value.

0x20 .. 0x27:

Debug

scratch

C.10 PC of logical core 0: 0x40

Value of the PC of logical core 0.

Bits Perm Init Description

31:0 RO Value.

0x40:

PC of logical

core 0

X6319,

XS1-U8A-64-FB96 Datasheet 53

C.11 PC of logical core 1: 0x41

Bits Perm Init Description

31:0 RO Value.

0x41:

PC of logical

core 1

C.12 PC of logical core 2: 0x42

Bits Perm Init Description

31:0 RO Value.

0x42:

PC of logical

core 2

C.13 PC of logical core 3: 0x43

Bits Perm Init Description

31:0 RO Value.

0x43:

PC of logical

core 3

C.14 PC of logical core 4: 0x44

Bits Perm Init Description

31:0 RO Value.

0x44:

PC of logical

core 4

C.15 PC of logical core 5: 0x45

Bits Perm Init Description

31:0 RO Value.

0x45:

PC of logical

core 5

X6319,

XS1-U8A-64-FB96 Datasheet 54

C.16 PC of logical core 6: 0x46

Bits Perm Init Description

31:0 RO Value.

0x46:

PC of logical

core 6

C.17 PC of logical core 7: 0x47

Bits Perm Init Description

31:0 RO Value.

0x47:

PC of logical

core 7

C.18 SR of logical core 0: 0x60

Value of the SR of logical core 0

Bits Perm Init Description

31:0 RO Value.

0x60:

SR of logical

core 0

C.19 SR of logical core 1: 0x61

Bits Perm Init Description

31:0 RO Value.

0x61:

SR of logical

core 1

C.20 SR of logical core 2: 0x62

Bits Perm Init Description

31:0 RO Value.

0x62:

SR of logical

core 2

X6319,

XS1-U8A-64-FB96 Datasheet 55

C.21 SR of logical core 3: 0x63

Bits Perm Init Description

31:0 RO Value.

0x63:

SR of logical

core 3

C.22 SR of logical core 4: 0x64

Bits Perm Init Description

31:0 RO Value.

0x64:

SR of logical

core 4

C.23 SR of logical core 5: 0x65

Bits Perm Init Description

31:0 RO Value.

0x65:

SR of logical

core 5

C.24 SR of logical core 6: 0x66

Bits Perm Init Description

31:0 RO Value.

0x66:

SR of logical

core 6

C.25 SR of logical core 7: 0x67

Bits Perm Init Description

31:0 RO Value.

0x67:

SR of logical

core 7

C.26 Chanend status: 0x80 .. 0x9F

These registers record the status of each channel-end on the tile.

X6319,

XS1-U8A-64-FB96 Datasheet 56

Bits Perm Init Description

31:26 RO - Reserved

25:24 RO 00 - ChannelEnd, 01 - ERROR, 10 - PSCTL, 11 - Idle.

23:16 RO

Based on SRC_TARGET_TYPE value, it represents channelEnd ID

or Idle status.

15:6 RO - Reserved

5:4 RO Two-bit network identiﬁer

3 RO - Reserved

2 RO

1 when the current packet is considered junk and will be thrown

away.

1 RO 0

Set to 1 if the switch is routing data into the link, and if a route

exists from another link.

0 RO 0

Set to 1 if the link is routing data into the switch, and if a route

is created to another link on the switch.

0x80 .. 0x9F:

Chanend

status

X6319,

XS1-U8A-64-FB96 Datasheet 57

D Digital Node Conﬁguration

The digital node control registers can be accessed using conﬁguration reads and

writes (use

write_node_config_reg(device, ...)

and

read_node_config_reg(device,

>...) for reads and writes).

Number Perm Description

0x00 RO Device identiﬁcation

0x01 RO System switch description

0x04 RW Switch conﬁguration

0x05 RW Switch node identiﬁer

0x06 RW PLL settings

0x07 RW System switch clock divider

0x08 RW Reference clock

0x0C RW Directions 0-7

0x0D RW Directions 8-15

0x10 RW DEBUG_N conﬁguration

0x1F RO Debug source

0x20 .. 0x27 RW Link status, direction, and network

0x40 .. 0x43 RW PLink status and network

0x80 .. 0x87 RW Link conﬁguration and initialization

0xA0 .. 0xA7 RW Static link conﬁguration

Figure 41:

Summary

D.1 Device identiﬁcation: 0x00

This register contains version and revision identiﬁers and the mode-pins as sampled

at boot-time.

Bits Perm Init Description

31:24 RO 0x00 Chip identiﬁer.

23:16 RO Sampled values of pins MODE0, MODE1, ... on reset.

15:8 RO SSwitch revision.

7:0 RO SSwitch version.

0x00:

Device

identiﬁcation

D.2 System switch description: 0x01

This register speciﬁes the number of processors and links that are connected to

this switch.

X6319,

XS1-U8A-64-FB96 Datasheet 58

Bits Perm Init Description

31:24 RO - Reserved

23:16 RO Number of links on the switch.

15:8 RO Number of cores that are connected to this switch.

7:0 RO Number of links per processor.

0x01:

System

switch

description

D.3 Switch conﬁguration: 0x04

This register enables the setting of two security modes (that disable updates to the

PLL or any other registers) and the header-mode.

Bits Perm Init Description

31 RO 0

Set to 1 to disable any write access to the conﬁguration registers

in this switch.

30:9 RO - Reserved

8 RO 0 Set to 1 to disable updates to the PLL conﬁguration register.

7:1 RO - Reserved

0 RO 0

Header mode. Set to 1 to enable 1-byte headers. This must be

performed on all nodes in the system.

0x04:

Switch

conﬁguration

D.4 Switch node identiﬁer: 0x05

This register contains the node identiﬁer.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RW 0

The unique 16-bit ID of this node. This ID is matched most-

signiﬁcant-bit ﬁrst with incoming messages for routing pur-

poses.

0x05:

Switch node

identiﬁer

D.5 PLL settings: 0x06

An on-chip PLL multiplies the input clock up to a higher frequency clock, used to

clock the I/O, processor, and switch, see Oscillator. Note: a write to this register

will cause the tile to be reset.

X6319,

XS1-U8A-64-FB96 Datasheet 59

Bits Perm Init Description

31:26 RO - Reserved

25:23 RW OD: Output divider value

The initial value depends on pins MODE0 and MODE1.

22:21 RO - Reserved

20:8 RW F: Feedback multiplication ratio

The initial value depends on pins MODE0 and MODE1.

7 RO - Reserved

6:0 RW R: Oscilator input divider value

The initial value depends on pins MODE0 and MODE1.

0x06:

PLL settings

D.6 System switch clock divider: 0x07

Sets the ratio of the PLL clock and the switch clock.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RW 0

Switch clock divider. The PLL clock will be divided by this value

plus one to derive the switch clock.

0x07:

System

switch clock

divider

D.7 Reference clock: 0x08

Sets the ratio of the PLL clock and the reference clock used by the node.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RW 3

Architecture reference clock divider. The PLL clock will be

divided by this value plus one to derive the 100 MHz reference

clock.

0x08:

Reference

clock

D.8 Directions 0-7: 0x0C

This register contains eight directions, for packets with a mismatch in bits 7..0 of

the node-identiﬁer. The direction in which a packet will be routed is goverened by

the most signiﬁcant mismatching bit.

X6319,

XS1-U8A-64-FB96 Datasheet 60

Bits Perm Init Description

31:28 RW 0 The direction for packets whose ﬁrst mismatching bit is 7.

27:24 RW 0 The direction for packets whose ﬁrst mismatching bit is 6.

23:20 RW 0 The direction for packets whose ﬁrst mismatching bit is 5.

19:16 RW 0 The direction for packets whose ﬁrst mismatching bit is 4.

15:12 RW 0 The direction for packets whose ﬁrst mismatching bit is 3.

11:8 RW 0 The direction for packets whose ﬁrst mismatching bit is 2.

7:4 RW 0 The direction for packets whose ﬁrst mismatching bit is 1.

3:0 RW 0 The direction for packets whose ﬁrst mismatching bit is 0.

0x0C:

Directions

0-7

D.9 Directions 8-15: 0x0D

This register contains eight directions, for packets with a mismatch in bits 15..8 of

the node-identiﬁer. The direction in which a packet will be routed is goverened by

the most signiﬁcant mismatching bit.

Bits Perm Init Description

31:28 RW 0 The direction for packets whose ﬁrst mismatching bit is 15.

27:24 RW 0 The direction for packets whose ﬁrst mismatching bit is 14.

23:20 RW 0 The direction for packets whose ﬁrst mismatching bit is 13.

19:16 RW 0 The direction for packets whose ﬁrst mismatching bit is 12.

15:12 RW 0 The direction for packets whose ﬁrst mismatching bit is 11.

11:8 RW 0 The direction for packets whose ﬁrst mismatching bit is 10.

7:4 RW 0 The direction for packets whose ﬁrst mismatching bit is 9.

3:0 RW 0 The direction for packets whose ﬁrst mismatching bit is 8.

0x0D:

Directions

8-15

D.10 DEBUG_N conﬁguration: 0x10

Conﬁgures the behavior of the DEBUG_N pin.

Bits Perm Init Description

31:2 RO - Reserved

1 RW 0

Set to 1 to enable signals on DEBUG_N to generate DCALL on the

core.

0 RW 0

When set to 1, the DEBUG_N wire will be pulled down when the

node enters debug mode.

0x10:

DEBUG_N

conﬁguration

X6319,

XS1-U8A-64-FB96 Datasheet 61

D.11 Debug source: 0x1F

Contains the source of the most recent debug event.

Bits Perm Init Description

31:5 RO - Reserved

4 RW

If set, the external DEBUG_N pin is the source of the most recent

debug interrupt.

3:1 RO - Reserved

0 RW

If set, the xCORE Tile is the source of the most recent debug

interrupt.

0x1F:

Debug source

D.12 Link status, direction, and network: 0x20 .. 0x27

These registers contain status information for low level debugging (read-only), the

network number that each link belongs to, and the direction that each link is part

of.

Bits Perm Init Description

31:26 RO - Reserved

25:24 RO

If this link is currently routing data into the switch, this ﬁeld

speciﬁes the type of link that the data is routed to:

0: external link

1: plink

2: internal control link

23:16 RO 0

If the link is routing data into the switch, this ﬁeld speciﬁes the

destination link number to which all tokens are sent.

15:12 RO - Reserved

11:8 RW 0

The direction that this this link is associated with; set for rout-

ing.

7:6 RO - Reserved

5:4 RW 0

Determines the network to which this link belongs, set for

quality of service.

3 RO - Reserved

2 RO 0

Set to 1 if the current packet is junk and being thrown away. A

packet is considered junk if, for example, it is not routable.

1 RO 0

Set to 1 if the switch is routing data into the link, and if a route

exists from another link.

0 RO 0

Set to 1 if the link is routing data into the switch, and if a route

is created to another link on the switch.

0x20 .. 0x27:

Link status,

direction, and

network

X6319,

XS1-U8A-64-FB96 Datasheet 62

D.13 PLink status and network: 0x40 .. 0x43

These registers contain status information and the network number that each

processor-link belongs to.

Bits Perm Init Description

31:26 RO - Reserved

25:24 RO

If this link is currently routing data into the switch, this ﬁeld

speciﬁes the type of link that the data is routed to:

0: external link

1: plink

2: internal control link

23:16 RO 0

If the link is routing data into the switch, this ﬁeld speciﬁes the

destination link number to which all tokens are sent.

15:6 RO - Reserved

5:4 RW 0

Determines the network to which this link belongs, set for

quality of service.

3 RO - Reserved

2 RO 0

Set to 1 if the current packet is junk and being thrown away. A

packet is considered junk if, for example, it is not routable.

1 RO 0

Set to 1 if the switch is routing data into the link, and if a route

exists from another link.

0 RO 0

Set to 1 if the link is routing data into the switch, and if a route

is created to another link on the switch.

0x40 .. 0x43:

PLink status

and network

D.14 Link conﬁguration and initialization: 0x80 .. 0x87

These registers contain conﬁguration and debugging information speciﬁc to exter-

nal links. The link speed and width can be set, the link can be initialized, and the

link status can be monitored.

X6319,

XS1-U8A-64-FB96 Datasheet 63

Bits Perm Init Description

31 RW 0

Write ’1’ to this bit to enable the link, write ’0’ to disable it. This

bit controls the muxing of ports with overlapping links.

30 RW 0

Set to 0 to operate in 2 wire mode or 1 to operate in 5 wire

mode

29:28 RO - Reserved

27 RO 0

Set to 1 on error: an RX buﬀer overﬂow or illegal token encoding

has been received. This bit clears on reading.

26 RO 0

1 if this end of the link has issued credit to allow the remote

end to transmit.

25 RO 0 1 if this end of the link has credits to allow it to transmit.

24 WO 0

Set to 1 to initialize a half-duplex link. This clears this end of

the link’s credit and issues a HELLO token; the other side of the

link will reply with credits. This bit is self-clearing.

23 WO 0

Set to 1 to reset the receiver. The next symbol that is detected

will be assumed to be the ﬁrst symbol in a token. This bit is

self-clearing.

22 RO - Reserved

21:11 RW 0

The number of system clocks between two subsequent transi-

tions within a token

10:0 RW 0

The number of system clocks between two subsequent transmit

tokens.

0x80 .. 0x87:

Link

conﬁguration

and

initialization

D.15 Static link conﬁguration: 0xA0 .. 0xA7

These registers are used for static (ie, non-routed) links. When a link is made static,

all traﬃc is forwarded to the designated channel end and no routing is attempted.

Bits Perm Init Description

31 RW 0 Enable static forwarding.

30:5 RO - Reserved

4:0 RW 0

The destination channel end on this node that packets received

in static mode are forwarded to.

0xA0 .. 0xA7:

Static link

conﬁguration

X6319,

XS1-U8A-64-FB96 Datasheet 64

E Analogue Node Conﬁguration

The analogue node control registers can be accessed using conﬁguration reads and

writes (use

write_node_config_reg(device, ...)

and

read_node_config_reg(device,

>...) for reads and writes).

Number Perm Description

0x00 RO Device identiﬁcation register

0x04 RW Node conﬁguration register

0x05 RW Node identiﬁer

0x50 RW Reset and Mode Control

0x51 RW System clock frequency

0x80 RW Link Control and Status

0xD6 RW 1 KHz Watchdog Control

0xD7 RW Watchdog Disable

Figure 42:

Summary

E.1 Device identiﬁcation register: 0x00

This register contains version information, and information on power-on behavior.

Bits Perm Init Description

31:24 RO 0x0F Chip identiﬁer

23:17 RO - Reserved

16 RO pin

Oscillator used on power-up. This is set by the OSC_EXT_N

pin:

0: boot from crystal;

1: boot from on-silicon 20 MHz oscillator.

15:8 RO 0x02 Revision number of the analogue block

7:0 RO 0x00 Version number of the analogue block

0x00:

Device

identiﬁcation

E.2 Node conﬁguration register: 0x04

This register is used to set the communication model to use (1 or 3 byte headers),

and to prevent any further updates.

X6319,

XS1-U8A-64-FB96 Datasheet 65

Bits Perm Init Description

31 RW 0

Set to 1 to disable further updates to the node conﬁguration and

link control and status registers.

30:1 RO - Reserved

0 RW 0 Header mode. 0: 3-byte headers; 1: 1-byte headers.

0x04:

Node

conﬁguration

E.3 Node identiﬁer: 0x05

Bits Perm Init Description

31:16 RO - Reserved

15:0 RW 0

16-bit node identiﬁer. This does not need to be set, and is

present for compatibility with XS1-switches.

0x05:

Node

identiﬁer

E.4 Reset and Mode Control: 0x50

The XS1-S has two main reset signals: a system-reset and an xCORE Tile-reset.

System-reset resets the whole system including external devices, whilst xCORE

Tile-reset resets the xCORE Tile(s) only. The resets are induced either by software

(by a write to the register below) or by one of the following:

* External reset on RST_N (System reset)

* Brown out on one of the power supplies (System reset)

* Watchdog timer (System reset)

* Sleep sequence (xCORE Tile reset)

* Clock source change (xCORE Tile reset)

The minimum system reset duration is achieved when the fastest permissible clock

is used. The reset durations will be proportionately longer when a slower clock

is used. Note that the minimum system reset duration allows for all power rails

except the VOUT2 to turn oﬀ, and decay.

The length of the system reset comes from an internal counter, counting 524,288

oscillator clock cycles which gives the maximum time allowable for the supply rails

to discharge. The system reset duration is a balance between leaving a long time

for the supply rails to discharge, and a short time for the system to boot. Example

reset times are 44 ms with a 12 MHz oscillator or 5.5 ms with a 96 MHz oscillator.

X6319,

XS1-U8A-64-FB96 Datasheet 66

Bits Perm Init Description

31:25 RO - Reserved

24 RW Tristate processor mode pins.

23:18 RO - Reserved

17:16 RW Processor mode pins.

15:4 RO - Reserved

3 RW 0 USB peripheral register access enable.

2 RW 0

USB interface block enable. Set to 1 to enable. Set to 0 to

disable and reset all USB interface registers

1 WO 0

xCORE Tile reset. Set to 1 to initiate a reset of the xCORE Tile.

This bit is self clearing. A write to this conﬁguration register

with this bit asserted results in no response packet being sent

to the sender regardless of whether or not a response was

requested.

0 WO 0

System reset. Set to 1 to initiate a reset whose scope includes

most conﬁguration and peripheral control registers. This bit is

self clearing. A write to this conﬁguration register with this bit

asserted results in no response packet being sent to the sender

regardless of whether or not a response was requested.

0x50:

Reset and

Mode Control

E.5 System clock frequency: 0x51

Bits Perm Init Description

31:7 RO - Reserved

6:0 RW 25

Oscillator clock frequency in MHz rounded up to the nearest

integer value. Only values between 5 and 100 MHz are valid -

writes outside this range are ignored and will be NACKed.

This ﬁeld must be set on start up of the device and any time that

the input oscillator clock frequency is changed. It must contain

the system clock frequency in MHz rounded up to the nearest

integer value. The following functions depend on the correct

frequency settings:

* Processor reset delay

* The watchdog clock

* The real-time clock when running in sleep mode

* The USB clock (USB requires a 12, 24, 48, or 96 MHz oscillator)

0x51:

System clock

frequency

X6319,

XS1-U8A-64-FB96 Datasheet 67

E.6 Link Control and Status: 0x80

Bits Perm Init Description

31:28 RO - Reserved

27 RO 0

Set to 1 on error: an RX buﬀer overﬂow or illegal token encoding

has been received. This bit clears on reading.

26 RO 0

1 if this end of the link has issued credit to allow the remote

end to transmit.

25 RO 0 1 if this end of the link has credits to allow it to transmit.

24 WO 0

Set to 1 to initialize a half-duplex link. This clears this end of

the link’s credit and issues a HELLO token; the other side of the

link will reply with credits. This bit is self-clearing.

23 WO 0

Set to 1 to reset the receiver. The next symbol that is detected

will be assumed to be the ﬁrst symbol in a token. This bit is

self-clearing.

22 RO - Reserved

21:11 RW 1

The number of system clocks between two subsequent transi-

tions within a token

10:0 RW 1

The number of system clocks between two subsequent transmit

tokens.

0x80:

Link Control

and Status

E.7 1 KHz Watchdog Control: 0xD6

The watchdog provides a mechanism to prevent programs from hanging by re-

setting the xCORE Tile after a pre-set time. The watchdog should be periodically

“kicked” by the application, causing the count-down to be restarted. If the watchdog

expires, it may be due to a program hanging, for example because of a (transient)

hardware issue.

The watchdog timeout is measured in 1 ms clock ticks, meaning that a time

between 1 ms and 65 seconds can be set for the timeout. The watchdog timer

is only clocked during the AWAKE power state. When writing the timeout value,

both the timeout and its one’s complement should be written. This reduces the

chances of accidentally setting kicking the watchdog. If the written value does

not comprise a 16-bit value with a 16-bit one’s complement, the request will be

NACKed, otherwise an ACK will be sent.

If the watchdog expires, the xCORE Tile is reset.

Bits Perm Init Description

31:16 RO 0 Current value of watchdog timer.

15:0 RW 1000

Number of 1kHz cycles after which the watchdog should ex-

pire and initiate a system reset.

0xD6:

1 KHz

Watchdog

Control

X6319,

XS1-U8A-64-FB96 Datasheet 68

E.8 Watchdog Disable: 0xD7

To enable the watchdog, write 0 to this register. To disable the watchdog, write

the value 0x0D1SAB1E to this register.

Bits Perm Init Description

31:0 RW 0x0D15AB1E

A value of 0x0D15AB1E written to this register resets

and disables the watchdog timer.

0xD7:

Watchdog

Disable

F USB PHY Conﬁguration

The USB PHY is connected to the following ports:

XS1_PORT_1J

Clk

XS1_PORT_1K

Tx ready out (Tx valid)

XS1_PORT_1H

Tx ready in

XS1_PORT_8A

Tx data

XS1_PORT_1M

Rx ready

XS1_PORT_8C

Rx data

XS1_PORT_1N

ﬂag1

XS1_PORT_1O

ﬂag2

XS1_PORT_1P

ﬂag3

The USB PHY is peripheral 1. The control registers are accessed using 32-bit

reads and writes (use

write_periph_32(device, 1, ...)

and

read_periph_32(device,

>1, ...) for reads and writes).

X6319,

XS1-U8A-64-FB96 Datasheet 69

Number Perm Description

0x00 WO UIFM reset

0x04 RW UIFM IFM control

0x08 RW UIFM Device Address

0x0C RW UIFM functional control

0x10 RW UIFM on-the-go control

0x14 RO UIFM on-the-go ﬂags

0x18 RW UIFM Serial Control

0x1C RW UIFM signal ﬂags

0x20 RW UIFM Sticky ﬂags

0x24 RW UIFM port masks

0x28 RW UIFM SOF value

0x2C RO UIFM PID

0x30 RO UIFM Endpoint

0x34 RW UIFM Endpoint match

0x38 RW UIFM power signalling

0x3C RW UIFM PHY control

Figure 43:

Summary

F.1 UIFM reset: 0x00

A write to this register with any data resets all UIFM state, but does not otherwise

aﬀect the phy.

Bits Perm Init Description

31:0 WO Value.

0x00:

UIFM reset

F.2 UIFM IFM control: 0x04

General settings of the UIFM IFM state machine.

X6319,

XS1-U8A-64-FB96 Datasheet 70

Bits Perm Init Description

31:8 RO - Reserved

7 RW 0 Set to 1 to enable XEVACKMODE mode.

6 RW 0 Set to 1 to enable SOFISTOKEN mode.

5 RW 0 Set to 1 to enable UIFM power signalling mode.

4 RW 0 Set to 1 to enable IF timing mode.

3 RO - Reserved

2 RW 0 Set to 1 to enable UIFM linestate decoder.

1 RW 0 Set to 1 to enable UIFM CHECKTOKENS mode.

0 RW 0 Set to 1 to enable UIFM DOTOKENS mode.

0x04:

UIFM IFM

control

F.3 UIFM Device Address: 0x08

The device address whose packets should be received. 0 until enumeration, it

should be set to the assigned value after enumeration.

Bits Perm Init Description

31:7 RO - Reserved

6:0 RW 0

The enumerated USB device address must be stored here. Only

packets to this address are passed on.

0x08:

UIFM Device

Address

F.4 UIFM functional control: 0x0C

Bits Perm Init Description

31:4 RO - Reserved

3:2 RW 1 Set to 0 to disable UIFM to UTMI+ OPMODE mode.

1 RW 0 Set to 1 to switch UIFM to UTMI+ TERMSELECT mode.

0 RW 0 Set to 1 to switch UIFM to UTMI+ XCVRSELECT mode.

0x0C:

UIFM

functional

control

F.5 UIFM on-the-go control: 0x10

This register is used to negotiate an on-the-go connection.

X6319,

XS1-U8A-64-FB96 Datasheet 71

Bits Perm Init Description

31:8 RO - Reserved

7 RW 0 Set to 1 to switch UIFM to EXTVBUSIND mode.

6 RW 0 Set to 1 to switch UIFM to DRVVBUSEXT mode.

5 RO - Reserved

4 RW 0 Set to 1 to switch UIFM to UTMI+ CHRGVBUS mode.

3 RW 0 Set to 1 to switch UIFM to UTMI+ DISCHRGVBUS mode.

2 RW 0 Set to 1 to switch UIFM to UTMI+ DMPULLDOWN mode.

1 RW 0 Set to 1 to switch UIFM to UTMI+ DPPULLDOWN mode.

0 RW 0 Set to 1 to switch UIFM to IDPULLUP mode.

0x10:

UIFM

on-the-go

control

F.6 UIFM on-the-go ﬂags: 0x14

Status ﬂags used for on-the-go negotiation

Bits Perm Init Description

31:6 RO - Reserved

5 RO 0 Value of UTMI+ Bvalid ﬂag.

4 RO 0 Value of UTMI+ IDGND ﬂag.

3 RO 0 Value of UTMI+ HOSTDIS ﬂag.

2 RO 0 Value of UTMI+ VBUSVLD ﬂag.

1 RO 0 Value of UTMI+ SESSVLD ﬂag.

0 RO 0 Value of UTMI+ SESSEND ﬂag.

0x14:

UIFM

on-the-go

ﬂags

X6319,

XS1-U8A-64-FB96 Datasheet 72

F.7 UIFM Serial Control: 0x18

Bits Perm Init Description

31:7 RO - Reserved

6 RO 0 1 if UIFM is in UTMI+ RXRCV mode.

5 RO 0 1 if UIFM is in UTMI+ RXDM mode.

4 RO 0 1 if UIFM is in UTMI+ RXDP mode.

3 RW 0 Set to 1 to switch UIFM to UTMI+ TXSE0 mode.

2 RW 0 Set to 1 to switch UIFM to UTMI+ TXDATA mode.

1 RW 1 Set to 0 to switch UIFM to UTMI+ TXENABLE mode.

0 RW 0 Set to 1 to switch UIFM to UTMI+ FSLSSERIAL mode.

0x18:

UIFM Serial

Control

F.8 UIFM signal ﬂags: 0x1C

Set of ﬂags that monitor line and error states. These ﬂags normally clear on the

next packet, but they may be made sticky by using PER_UIFM_FLAGS_STICKY, in

which they must be cleared explicitly.

Bits Perm Init Description

31:7 RO - Reserved

6 RW 0

Set to 1 when the UIFM decodes a token successfully (e.g. it

passes CRC5, PID check and has matching device address).

5 RW 0 Set to 1 when linestate indicates an SE0 symbol.

4 RW 0 Set to 1 when linestate indicates a K symbol.

3 RW 0 Set to 1 when linestate indicates a J symbol.

2 RW 0 Set to 1 if an incoming datapacket fails the CRC16 check.

1 RW 0 Set to the value of the UTMI_RXACTIVE input signal.

0 RW 0 Set to the value of the UTMI_RXERROR input signal

0x1C:

UIFM signal

ﬂags

F.9 UIFM Sticky ﬂags: 0x20

These bits deﬁne the sticky-ness of the bits in the UIFM IFM FLAGS register. A 1

means that bit will be sticky (hold its value until a 1 is written to that bitﬁeld),

or normal, in which case signal updates to the UIFM IFM FLAGS bits may be

over-written by subsequent changes in those signals.

X6319,

XS1-U8A-64-FB96 Datasheet 73

Bits Perm Init Description

31:7 RO - Reserved

6:0 RW 0 Stickyness for each ﬂag.

0x20:

UIFM Sticky

ﬂags

F.10 UIFM port masks: 0x24

Set of masks that identify how port 1N, port 1O and port 1P are aﬀected by changes

to the ﬂags in FLAGS

Bits Perm Init Description

31:23 RO - Reserved

22:16 RW 0

Bit mask that determines which ﬂags in UIFM_IFM_FLAG[6:0]

contribute to port 1P. If any ﬂag listed in this bitmask is high,

port 1P will be high.

15 RO - Reserved

14:8 RW 0

Bit mask that determines which ﬂags in UIFM_IFM_FLAG[6:0]

contribute to port 1O. If any ﬂag listed in this bitmask is high,

port 1O will be high.

7 RO - Reserved

6:0 RW 0

Bit mask that determines which ﬂags in UIFM_IFM_FLAG[6:0]

contribute to port 1N. If any ﬂag listed in this bitmask is high,

port 1N will be high.

0x24:

UIFM port

masks

F.11 UIFM SOF value: 0x28

USB Start-Of-Frame counter

Bits Perm Init Description

31:11 RO - Reserved

10:8 RW 0 Most signiﬁcant 3 bits of SOF counter

7:0 RW 0 Least signiﬁcant 8 bits of SOF counter

0x28:

UIFM SOF

value

F.12 UIFM PID: 0x2C

The last USB packet identiﬁer received

X6319,

XS1-U8A-64-FB96 Datasheet 74

Bits Perm Init Description

31:4 RO - Reserved

3:0 RO 0 Value of the last received PID.

0x2C:

UIFM PID

F.13 UIFM Endpoint: 0x30

The last endpoint seen

Bits Perm Init Description

31:5 RO - Reserved

4 RO 0 1 if endpoint contains a valid value.

3:0 RO 0 A copy of the last received endpoint.

0x30:

UIFM

Endpoint

F.14 UIFM Endpoint match: 0x34

This register can be used to mark UIFM endpoints as special.

Bits Perm Init Description

31:16 RO - Reserved

15:0 RW 0

This register contains a bit for each endpoint. If its bit is set,

the endpoint will be supplied on the RX port when ORed with

0x10.

0x34:

UIFM

Endpoint

match

F.15 UIFM power signalling: 0x38

Bits Perm Init Description

31:9 RO - Reserved

8 RW 0 Valid

7:0 RW 0 Data

0x38:

UIFM power

signalling

X6319,

XS1-U8A-64-FB96 Datasheet 75

F.16 UIFM PHY control: 0x3C

Bits Perm Init Description

31:19 RO - Reserved

18 RW 0 Set to 1 to disable pulldowns on ports 8A and 8B.

17:14 RO - Reserved

13 RW 0

After an auto-resume, this bit is set to indicate that the resume

signalling was for reset (se0). Set to 0 to clear.

12 RW 0

After an auto-resume, this bit is set to indicate that the resume

signalling was for resume (K). Set to 0 to clear.

11:8 RW 0

Log-2 number of clocks before any linestate change is propa-

gated.

7 RW 0

Set to 1 to use the suspend controller handle to resume from

suspend. Otherwise, the program has to poll the linestate_ﬁlt

ﬁeld in phy_teststatus.

6:4 RW 0 Control the the conf1,2,3 input pins of the PHY.

3:0 RO - Reserved

0x3C:

UIFM PHY

control

G ADC Conﬁguration

The device has a 12-bit Analogue to Digital Converter (ADC). It has multiple input

pins, and on each positive clock edge on port 1I, it samples and converts a value

on the next input pin. The data is transmitted to a channel-end that must be set

on enabling the ADC input pin.

The ADC is peripheral 2. The control registers are accessed using 32-bit reads and

writes (use

write_periph_32(device, 2, ...)

and

read_periph_32(device, 2, ...)

for

reads and writes).

Number Perm Description

0x00 RW ADC Control input pin 0

0x04 RW ADC Control input pin 1

0x08 RW ADC Control input pin 2

0x0C RW ADC Control input pin 3

0x20 RW ADC General Control

Figure 44:

Summary

G.1 ADC Control input pin 0: 0x00

Controls speciﬁc to ADC input pin 0.

X6319,

XS1-U8A-64-FB96 Datasheet 76

Bits Perm Init Description

31:8 RW 0

The node and channel-end identiﬁer to which data for this ADC

input pin should be send to. This is the top 24 bits of the

channel-end identiﬁer as allocated on an xCORE Tile.

7:1 RO - Reserved

0 RW 0 Set to 1 to enable this input pin on the ADC.

0x00:

ADC Control

input pin 0

G.2 ADC Control input pin 1: 0x04

Controls speciﬁc to ADC input pin 1.

Bits Perm Init Description

31:8 RW 0

The node and channel-end identiﬁer to which data for this ADC

input pin should be send to. This is the top 24 bits of the

channel-end identiﬁer as allocated on an xCORE Tile.

7:1 RO - Reserved

0 RW 0 Set to 1 to enable this input pin on the ADC.

0x04:

ADC Control

input pin 1

G.3 ADC Control input pin 2: 0x08

Controls speciﬁc to ADC input pin 2.

Bits Perm Init Description

31:8 RW 0

The node and channel-end identiﬁer to which data for this ADC

input pin should be send to. This is the top 24 bits of the

channel-end identiﬁer as allocated on an xCORE Tile.

7:1 RO - Reserved

0 RW 0 Set to 1 to enable this input pin on the ADC.

0x08:

ADC Control

input pin 2

G.4 ADC Control input pin 3: 0x0C

Controls speciﬁc to ADC input pin 3.

X6319,

XS1-U8A-64-FB96 Datasheet 77

Bits Perm Init Description

31:8 RW 0

The node and channel-end identiﬁer to which data for this ADC

input pin should be send to. This is the top 24 bits of the

channel-end identiﬁer as allocated on an xCORE Tile.

7:1 RO - Reserved

0 RW 0 Set to 1 to enable this input pin on the ADC.

0x0C:

ADC Control

input pin 3

G.5 ADC General Control: 0x20

General ADC control.

Bits Perm Init Description

31:25 RO - Reserved

24 RO 1

Indicates that an ADC sample has been dropped. This bit is

cleared on a read.

23:18 RO - Reserved

17:16 RW 1

Number of bits per ADC sample. The ADC values are always left

aligned:

0: 8 bits samples - the least signiﬁcant four bits of each sample

are discarded.

1: 16 bits samples - the sample is padded with four zero bits in

bits 3..0. The most signiﬁcant byte is transmitted ﬁrst.

2: reserved

3: 32 bits samples - the sample is padded with 20 zero bits in

bits 19..0. The most signiﬁcant byte is transmitted ﬁrst, hence

the word can be input with a single 32-bit IN instruction.

15:8 RW 1

Number of samples to be transmitted per packet. The value 0

indicates that the packet will not be terminated until interrupted

by an ADC control register access.

7:2 RO - Reserved

1 RW 0

Set to 1 to switch the ADC to sample a 0.8V signal rather than

the external voltage. This can be used to calibrate the ADC.

When switching to and from calibration mode, one sample

value should be discarded. If a sample value

is measured

in calibration mode, then a scale factor

800000/x

can be used

to translate subsequent measurements into microvolts (using

integer arithmetic).

0 RW 0

Set to 1 to enable the ADC. Note that when enabled, the ADC

control registers above are read-only. The ADC must be disabled

whilst setting up the per-input-pin control.

On enabling the ADC, six pulses must be generated to calibrate

the ADC. These pulses will not generate packets on the se-

lected channel-end. The seventh and further pulses will deliver

samples to the selected channel-end.

0x20:

ADC General

Control

X6319,

XS1-U8A-64-FB96 Datasheet 78

H Deep sleep memory Conﬁguration

This peripheral contains a 128 byte RAM that retains state whilst the main processor

is put to sleep.

The Deep sleep memory is peripheral 3. The control registers are accessed

using 8-bit reads and writes (use

write_periph_8(device, 3, ...)

and

read_periph_8

>(device, 3, ...) for reads and writes).

Number Perm Description

0x00 .. 0x7F RW Deep sleep memory

0xFF RW Deep sleep memory valid

Figure 45:

Summary

H.1 Deep sleep memory: 0x00 .. 0x7F

128 bytes of memory that can be used to hold data when the xCORE Tile is powered

down.

Bits Perm Init Description

7:0 RW User deﬁned data

0x00 .. 0x7F:

Deep sleep

memory

H.2 Deep sleep memory valid: 0xFF

One byte of memory that is reset to 0. The program can write a non zero value in

this register to indicate that the data in deep sleep memory is valid.

Bits Perm Init Description

7:0 RW 0 User deﬁned data, reset to 0.

0xFF:

Deep sleep

memory valid

I Oscillator Conﬁguration

The Oscillator is peripheral 4. The control registers are accessed using 8-bit reads

and writes (use

write_periph_8(device, 4, ...)

and

read_periph_8(device, 4, ...)

for reads and writes).

X6319,

XS1-U8A-64-FB96 Datasheet 79

Number Perm Description

0x00 RW General oscillator control

0x01 RW On-silicon-oscillator control

0x02 RW Crystal-oscillator control

Figure 46:

Summary

I.1 General oscillator control: 0x00

Bits Perm Init Description

7:2 RO - Reserved

1 RW 0

Set to 1 to reset the xCORE Tile when the value of the oscillator

select control register (bit 0) is changed.

0 RW pin Selects the oscillator to use:

0: Crystal oscillator

1: On-silicon oscillator

0x00:

General

oscillator

control

I.2 On-silicon-oscillator control: 0x01

This register controls the on-chip logic that implements an on-chip oscillator. The

on-chip oscillator does not require an external crystal, but does not provide an

accurate timing source. The nominal frequency of the on-silicon-oscillator is given

below, but the actual frequency are temperature, voltage, and chip dependent.

Bits Perm Init Description

7:2 RO - Reserved

1 RW 0 Selects the clock speed of the on-chip oscillator:

0: approximately 20 Mhz (fast clock)

1: approximately 31,250 Hz (slow clock)

0 RW 1

Set to 0 to disable the on-chip oscillator. Do not do this unless

the xCORE Tile is running oﬀ the crystal oscillator.

0x01:

On-silicon-

oscillator

control

I.3 Crystal-oscillator control: 0x02

This register controls the on-chip logic that implements the crystal oscillator; the

crystal-oscillator requires an external crystal.

X6319,

XS1-U8A-64-FB96 Datasheet 80

Bits Perm Init Description

7:2 RO - Reserved

1 RW 1

Set to 0 to disable the crystal bias circuit. Only switch the bias oﬀ

if an external oscillator rather than a crystal is connected.

0 RW 1

Set to 0 to disable the crystal oscillator. Do not do this unless the

xCORE Tile is running oﬀ the on-silicon oscillator.

0x02:

Crystal-

oscillator

control

J Real time clock Conﬁguration

The Real time clock is peripheral 5. The control registers are accessed using 32-bit

reads and writes (use

write_periph_32(device, 5, ...)

and

read_periph_32(device,

>5, ...) for reads and writes).

Number Perm Description

0x00 RW Real time counter least signiﬁcant 32 bits

0x04 RW Real time counter most signiﬁcant 32 bits

Figure 47:

Summary

J.1 Real time counter least signiﬁcant 32 bits: 0x00

This registers contains the lower 32-bits of the real-time counter.

Bits Perm Init Description

31:0 RO 0 Least signiﬁcant 32 bits of real-time counter.

0x00:

Real time

counter least

signiﬁcant 32

bits

J.2 Real time counter most signiﬁcant 32 bits: 0x04

This registers contains the upper 32-bits of the real-time counter.

Bits Perm Init Description

31:0 RO 0 Most signiﬁcant 32 bits of real-time counter.

0x04:

Real time

counter most

signiﬁcant 32

bits

X6319,

XS1-U8A-64-FB96 Datasheet 81

K Power control block Conﬁguration

The Power control block is peripheral 6. The control registers are accessed using

32-bit reads and writes (use

write_periph_32(device, 6, ...)

and

read_periph_32(

>device, 6, ...) for reads and writes).

Number Perm Description

0x00 RW General control

0x04 RW Time to wake-up, least signiﬁcant 32 bits

0x08 RW Time to wake-up, most signiﬁcant 32 bits

0x0C RW Power supply states whilst ASLEEP

0x10 RW Power supply states whilst WAKING1

0x14 RW Power supply states whilst WAKING2

0x18 RW Power supply states whilst AWAKE

0x1C RW Power supply states whilst SLEEPING1

0x20 RW Power supply states whilst SLEEPING2

0x24 RW Power sequence status

0x2C RW DCDC control

0x30 RW Power supply status

0x34 RW VDDCORE level control

0x40 RW LDO5 level control

Figure 48:

Summary

K.1 General control: 0x00

This register controls the basic settings for power modes.

X6319,

XS1-U8A-64-FB96 Datasheet 82

Bits Perm Init Description

31:10 RO - Reserved

9 RW 0

Set to 1 to switch USB suspend controller to USB power up

enable.

8 RW 0

Set to 1 to switch USB suspend controller to power down enable.

7 RW 0

By default, when waking up, the voltage levels stored in the

LEVEL CONTROL registers are used. Set to 1 to use the power-on

voltage levels.

6 WO

Set to 1 to re-apply the current contents of the AWAKE state.

Use this when the program has changed the contents of the

AWAKE state register. Self clearing.

5 RW 0 Set to 1 to use a 64-bit timer.

4 RW 0 Set to 1 to wake-up on the timer.

3 RW 1

If waking on the WAKE pin is enabled (see above), then by

default the device wakes up when the WAKE pin is pulled high.

Set to 0 to wake-up when the WAKE pin is pulled low.

2 RW 0 Set to 1 to wake-up when the WAKE pin is at the right level.

1 RW 0

Set to 1 to initiate sleep sequence - self clearing. Only set this

bit when in AWAKE state.

0 RW 0

Sleep clock select. Set to 1 to use the default clock rather than

the internal 31.25 kHz oscillator. Note: this bit is only eﬀective

in the ASLEEP state.

0x00:

General

control

K.2 Time to wake-up, least signiﬁcant 32 bits: 0x04

This register stores the time to wake-up. The value is only used if wake-up from

the real-time clock is enabled, and the device is asleep.

Bits Perm Init Description

31:0 RW 0 Least signiﬁcant 32 bits of time to wake-up.

0x04:

Time to

wake-up,

least

signiﬁcant 32

bits

K.3 Time to wake-up, most signiﬁcant 32 bits: 0x08

This register stores the time to wake-up. The value is only used if wake-up from

the real-time clock is enabled, if 64-bit comparisons are enabled, and the device is

asleep. In most cases, 32-bit comparisons suﬃce.

X6319,

XS1-U8A-64-FB96 Datasheet 83

Bits Perm Init Description

31:0 RW 0

Most signiﬁcant 32 bits of time to wake-up (ignored unless 64-bit

timer comparison is enabled).

0x08:

Time to

wake-up,

most

signiﬁcant 32

bits

K.4 Power supply states whilst ASLEEP: 0x0C

This register controls the state the power control block should be in when in the

ASLEEP state. It also deﬁnes the minimum time that the system shall stay in this

state. When the minimum time is expired, the next state may be entered if either

of the wake conditions (real-time counter or WAKE pin) happens. Note that the

minimum number of cycles is counted in according to the currently enabled clock,

which may be the slow 31 KHz clock.

Bits Perm Init Description

31:21 RO - Reserved

20:16 RW 16 Log2 number of cycles to stay in this state:

0: 1 clock cycles

1: 2 clock cycles

2: 4 clock cycles

...

31: 2147483648 clock cycles

15 RO - Reserved

14 RW 0 Set to 1 to disable clock to the xCORE Tile.

13:10 RO - Reserved

9 RW 0 Sets modulation used by DCDC2:

0: PWM modulation (max 475 mA)

1: PFM modulation (max 50 mA)

8 RW 0 Sets modulation used by DCDC1:

0: PWM modulation (max 700 mA)

1: PFM modulation (max 50 mA)

7:6 RO - Reserved

5 RW 0 Set to 1 to enable VOUT6 (IO supply).

4 RW 0 Set to 1 to enable LDO5 (core PLL supply).

3:2 RO - Reserved

1 RO 0 Set to 1 to enable DCDC2 (analogue supply).

0 RW 0 Set to 1 to enable DCDC1 (core supply).

0x0C:

Power supply

states whilst

ASLEEP

X6319,

XS1-U8A-64-FB96 Datasheet 84

K.5 Power supply states whilst WAKING1: 0x10

This register controls what state the power control block should be in when in the

WAKING1 state. It also deﬁnes the minimum time that the system shall stay in this

state. When the minimum time is expired, the next state is entered if all enabled

power supplies are good.

Bits Perm Init Description

31:21 RO - Reserved

20:16 RW 16 Log2 number of cycles to stay in this state:

0: 1 clock cycles

1: 2 clock cycles

2: 4 clock cycles

...

31: 2147483648 clock cycles

15 RO - Reserved

14 RW 0 Set to 1 to disable clock to the xCORE Tile.

13:10 RO - Reserved

9 RW 0 Sets modulation used by DCDC2:

0: PWM modulation (max 475 mA)

1: PFM modulation (max 50 mA)

8 RW 0 Sets modulation used by DCDC1:

0: PWM modulation (max 700 mA)

1: PFM modulation (max 50 mA)

7:6 RO - Reserved

5 RW 1 Set to 1 to enable VOUT6 (IO supply).

4 RW 0 Set to 1 to enable LDO5 (core PLL supply).

3:2 RO - Reserved

1 RO 0 Set to 1 to enable DCDC2 (analogue supply).

0 RW 0 Set to 1 to enable DCDC1 (core supply).

0x10:

Power supply

states whilst

WAKING1

K.6 Power supply states whilst WAKING2: 0x14

This register controls what state the power control block should be in when in the

WAKING2 state. It also deﬁnes the minimum time that the system shall stay in this

state. When the minimum time is expired, the next state is entered if all enabled

power supplies are good.

X6319,

XS1-U8A-64-FB96 Datasheet 85

Bits Perm Init Description

31:21 RO - Reserved

20:16 RW 16 Log2 number of cycles to stay in this state:

0: 1 clock cycles

1: 2 clock cycles

2: 4 clock cycles

...

31: 2147483648 clock cycles

15 RO - Reserved

14 RW 0 Set to 1 to disable clock to the xCORE Tile.

13:10 RO - Reserved

9 RW 0 Sets modulation used by DCDC2:

0: PWM modulation (max 475 mA)

1: PFM modulation (max 50 mA)

8 RW 0 Sets modulation used by DCDC1:

0: PWM modulation (max 700 mA)

1: PFM modulation (max 50 mA)

7:6 RO - Reserved

5 RW 1 Set to 1 to enable VOUT6 (IO supply).

4 RW 1 Set to 1 to enable LDO5 (core PLL supply).

3:2 RO - Reserved

1 RO 1 Set to 1 to enable DCDC2 (analogue supply).

0 RW 1 Set to 1 to enable DCDC1 (core supply).

0x14:

Power supply

states whilst

WAKING2

K.7 Power supply states whilst AWAKE: 0x18

This register controls what state the power control block should be in when in the

AWAKE state.

X6319,

XS1-U8A-64-FB96 Datasheet 86

Bits Perm Init Description

31:15 RO - Reserved

14 RW 0 Set to 1 to disable clock to the xCORE Tile.

13:10 RO - Reserved

9 RW 0 Sets modulation used by DCDC2:

0: PWM modulation (max 475 mA)

1: PFM modulation (max 50 mA)

8 RW 0 Sets modulation used by DCDC1:

0: PWM modulation (max 700 mA)

1: PFM modulation (max 50 mA)

7:6 RO - Reserved

5 RW 1 Set to 1 to enable VOUT6 (IO supply).

4 RW 1 Set to 1 to enable LDO5 (core PLL supply).

3:2 RO - Reserved

1 RO 1 Set to 1 to enable DCDC2 (analogue supply).

0 RW 1 Set to 1 to enable DCDC1 (core supply).

0x18:

Power supply

states whilst

AWAKE

K.8 Power supply states whilst SLEEPING1: 0x1C

This register controls what state the power control block should be in when in the

SLEEPING1 state. It also deﬁnes the time that the system shall stay in this state.

X6319,

XS1-U8A-64-FB96 Datasheet 87

Bits Perm Init Description

31:21 RO - Reserved

20:16 RW 16 Log2 number of cycles to stay in this state:

0: 1 clock cycles

1: 2 clock cycles

2: 4 clock cycles

...

31: 2147483648 clock cycles

15 RO - Reserved

14 RW 0 Set to 1 to disable clock to the xCORE Tile.

13:10 RO - Reserved

9 RW 0 Sets modulation used by DCDC2:

0: PWM modulation (max 475 mA)

1: PFM modulation (max 50 mA)

8 RW 0 Sets modulation used by DCDC1:

0: PWM modulation (max 700 mA)

1: PFM modulation (max 50 mA)

7:6 RO - Reserved

5 RW 1 Set to 1 to enable VOUT6 (IO supply).

4 RW 0 Set to 1 to enable LDO5 (core PLL supply).

3:2 RO - Reserved

1 RO 1 Set to 1 to enable DCDC2 (analogue supply).

0 RW 0 Set to 1 to enable DCDC1 (core supply).

0x1C:

Power supply

states whilst

SLEEPING1

K.9 Power supply states whilst SLEEPING2: 0x20

This register controls what state the power control block should be in when in the

SLEEPING2 state. It also deﬁnes the time that the system shall stay in this state.

X6319,

XS1-U8A-64-FB96 Datasheet 88

Bits Perm Init Description

31:21 RO - Reserved

20:16 RW 16 Log2 number of cycles to stay in this state:

0: 1 clock cycles

1: 2 clock cycles

2: 4 clock cycles

...

31: 2147483648 clock cycles

15 RO - Reserved

14 RW 0 Set to 1 to disable clock to the xCORE Tile.

13:10 RO - Reserved

9 RW 0 Sets modulation used by DCDC2:

0: PWM modulation (max 475 mA)

1: PFM modulation (max 50 mA)

8 RW 0 Sets modulation used by DCDC1:

0: PWM modulation (max 700 mA)

1: PFM modulation (max 50 mA)

7:6 RO - Reserved

5 RW 0 Set to 1 to enable VOUT6 (IO supply).

4 RW 0 Set to 1 to enable LDO5 (core PLL supply).

3:2 RO - Reserved

1 RO 1 Set to 1 to enable DCDC2 (analogue supply).

0 RW 0 Set to 1 to enable DCDC1 (core supply).

0x20:

Power supply

states whilst

SLEEPING2

K.10 Power sequence status: 0x24

This register deﬁnes the current status of the power supply controller.

X6319,

XS1-U8A-64-FB96 Datasheet 89

Bits Perm Init Description

31:30 RO - Reserved

29 RO 0 1 if VOUT6 was enabled in the previous state.

28 RO 0 1 if LDO5 was enabled in the previous state.

27:26 RO - Reserved

25 RO 1 1 if DCDC2 was enabled in the previous state.

24 RO 0 1 if DCDC1 was enabled in the previous state.

23:19 RO - Reserved

18:16 RO Current state of the power sequence state machine

0: Reset

1: Asleep

2: Waking 1

3: Waking 2

4: Awake Wait

5: Awake

6: Sleeping 1

7: Sleeping 2

15 RO - Reserved

14 RO 0 Set to 1 to disable clock to the xCORE Tile.

13:10 RO - Reserved

9 RO 0 Sets modulation used by DCDC2:

0: PWM modulation (max 475 mA)

1: PFM modulation (max 50 mA)

8 RO 0 Sets modulation used by DCDC1:

0: PWM modulation (max 700 mA)

1: PFM modulation (max 50 mA)

7:6 RO - Reserved

5 RO 0 Set to 1 to enable VOUT6 (IO supply).

4 RO 0 Set to 1 to enable LDO5 (core PLL supply).

3:2 RO - Reserved

1 RO 0 Set to 1 to enable DCDC2 (analogue supply).

0 RO 0 Set to 1 to enable DCDC1 (core supply).

0x24:

Power

sequence

status

K.11 DCDC control: 0x2C

This register controls the two DC-DC converters.

X6319,

XS1-U8A-64-FB96 Datasheet 90

Bits Perm Init Description

31:26 RO - Reserved

25:24 RW 2 Sets the power good level for VDDCORE and VDD1V8:

0: 0.80 x VDDCORE, 0.80 x VDD1V8

1: 0.85 x VDDCORE, 0.85 x VDD1V8

2: 0.90 x VDDCORE, 0.90 x VDD1V8

3: 0.75 x VDDCORE, 0.75 x VDD1V8

23:17 RO - Reserved

16 RW 0 Clear DCDC1 and DCDC2 error ﬂags, not self clearing.

15 RO - Reserved

14:13 RW 0 Sets the DCDC2 current limit:

0: 1A

1: 1.5A

2: 2A

3: 0.5A

12:10 RO - Reserved

9:8 RW 1 Sets the clock used by DCDC2 to generate VDD1V8:

0: 0.9 MHz

1: 1.0 MHz

2: 1.1 MHz

3: 1.2 MHz

7 RO - Reserved

6:5 RW 0 Sets the DCDC1 current limit:

0: 1.2A

1: 1.8A

2: 2.5A

3: 0.8A

4:2 RO - Reserved

1:0 RW 1 Sets the clock used by DCDC1 to generate VDDCORE:

0: 0.9 MHz

1: 1.0 MHz

2: 1.1 MHz

3: 1.2 MHz

0x2C:

DCDC control

K.12 Power supply status: 0x30

This register provides the current status of the power supplies.

X6319,

XS1-U8A-64-FB96 Datasheet 91

Bits Perm Init Description

31:25 RO - Reserved

24 RO 1 if on-silicon oscillator is stable.

23:20 RO - Reserved

19 RO 1 if VDDPLL is good.

18:17 RO - Reserved

16 RO 1 if VDDCORE is good.

15:10 RO - Reserved

9 RO 1 if DCDC2 is in current limiting mode.

8 RO 1 if DCDC1 is in current limiting mode.

7:2 RO - Reserved

1 RO 1 if DCDC2 is in soft-start mode.

0 RO 1 if DCDC1 is in soft-start mode.

0x30:

Power supply

status

K.13 VDDCORE level control: 0x34

This register can be used to set the desired voltage on VDDCORE. If the level is

to be raised or lowered, it should be raised in steps of no more than 10 mV per

microsecond in order to prevent overshoot and undershoot. The default value

depends on the MODE pins.

Bits Perm Init Description

31:7 RO - Reserved

6:0 RW pin The required voltage in 10 mV steps:

0: 0.60V

1: 0.61V

2: 0.62V

...

69: 1.29V

70: 1.30V

0x34:

VDDCORE

level control

K.14 LDO5 level control: 0x40

This register can be used to set the desired voltage on LDO5. If the level is to be

raised, it should be raised in steps of 1 (100 mV). The default value depends on

the MODE pins.

X6319,

XS1-U8A-64-FB96 Datasheet 92

Bits Perm Init Description

31:3 RO - Reserved

2:0 RW pin The required voltage in 100 mV steps:

0: 0.6V

1: 0.7V

2: 0.8V

...

6: 1.2V

7: 1.3V

0x40:

LDO5 level

control

X6319,

XS1-U8A-64-FB96 Datasheet 93

L Device Errata

This section describes minor operational diﬀerences from the data sheet and

recommended workarounds. As device and documentation issues become known,

this section will be updated the document revised.

To guarantee a logic low is seen on the pins DEBUG_N, MODE[3:0], TMS, TCK and

TDI, the driving circuit should present an impedance of less than 100

Ω

to ground.

Usually this is not a problem for CMOS drivers driving single inputs. If one or more

of these inputs are placed in parallel, however, additional logic buﬀers may be

required to guarantee correct operation.

For static inputs tied high or low, the relevant input pin should be tied directly to

GND or VDDIO.

M JTAG, xSCOPE and Debugging

If you intend to design a board that can be used with the XMOS toolchain and

xTAG debugger, you will need an xSYS header on your board. Figure 49 shows a

decision diagram which explains what type of xSYS connectivity you need. The

three subsections below explain the options in detail.

Is debugging

required?

Does the SPI

flash need to be

programmed?

Is xSCOPE

required

Is fast printf

required ?

YES

Use full xSYS header

See section 3

Use JTAG xSYS header

See section 2

No xSYS header required

See section 1

Figure 49:

Decision

diagram for

the xSYS

header

M.1 No xSYS header

The use of an xSYS header is optional, and may not be required for volume

production designs. However, the XMOS toolchain expects the xSYS header; if you

do not have an xSYS header then you must provide your own method for writing to

ﬂash/OTP and for debugging.

X6319,

XS1-U8A-64-FB96 Datasheet 94

M.2 JTAG-only xSYS header

The xSYS header connects to an xTAG debugger, which has a 20-pin 0.1" female

IDC header. The design will hence need a male IDC header. We advise to use a

boxed header to guard against incorrect plug-ins. If you use a 90 degree angled

header, make sure that pins 2, 4, 6, ..., 20 are along the edge of the PCB.

Connect pins 4, 8, 12, 16, 20 of the xSYS header to ground, and then connect:

·TDI to pin 5 of the xSYS header

·TMS to pin 7 of the xSYS header

·TCK to pin 9 of the xSYS header

·DEBUG_N to pin 11 of the xSYS header

·TDO to pin 13 of the xSYS header

·RST_N to pin 15 of the xSYS header

If MODE2 is conﬁgured high, connect MODE2 to pin 3 of the xSYS header. Do

not connect to VDDIO.

If MODE3 is conﬁgured high, connect MODE3 to pin 3 of the xSYS header. Do

not connect to VDDIO.

The RST_N net should be open-drain, active-low, and have a pull-up to VDDIO.

M.3 Full xSYS header

For a full xSYS header you will need to connect the pins as discussed in Section M.2,

and then connect a 2-wire xCONNECT Link to the xSYS header. The links can be

found in the Signal description table (Section 4): they are labelled XLA, XLB, etc in

the function column. The 2-wire link comprises two inputs and outputs, labelled

out

, and

, . For example, if you choose to use XLB of tile 0 for xSCOPE

I/O, you need to connect up XLB1

out, XLB0

in, XLB1

in as follows:

XLB

out

(X0D16) to pin 6 of the xSYS header with a 33R series resistor close to

the device.

XLB

out

(X0D17) to pin 10 of the xSYS header with a 33R series resistor close to

the device.

·XLB0

in (X0D18) to pin 14 of the xSYS header.

·XLB1

in (X0D19) to pin 18 of the xSYS header.

X6319,

XS1-U8A-64-FB96 Datasheet 95

N Schematics Design Check List

This section is a checklist for use by schematics designers using the

XS1-U8A-64-FB96. Each of the following sections contains items to

check for each design.

N.1 Clock

If you use USB, then your clock frequency is one of 12, 24, 48, or 96

MHz (Section 8).

Pins MODE0 and MODE1 are set to the correct value for the chosen

frequency. The MODE settings are shown in the Oscillator section,

Section 8. If you have a choice between two values, choose the value

with the highest multiplier ratio since that will boot faster.

OSC_EXT_N is tied to ground (for use with a crystal or oscillator) or

tied to VDDIO (for use with the internal oscillator). If using the internal

oscillator, set MODE0 and MODE1 to be for the 20-48 MHz range

(Section 8).

If you have used an oscillator, it is a 1V8 oscillator. (Section 17)

N.2 Boot

The device is connected to a SPI ﬂash for booting, connected to X0D0,

X0D01, X0D10, and X0D11 (Section 9). If not, you must boot the

device through OTP or JTAG.

The device that is connected to ﬂash has both MODE2 and MODE3 NC

(Section 9).

The SPI ﬂash that you have chosen is supported by

xﬂash

, or you have

created a speciﬁcation ﬁle for it.

N.3 JTAG, XScope, and debugging

You have decided as to whether you need an XSYS header or not

(Section M)

If you included an XSYS header, you connected pin 3 to any

MODE2/MODE3 pin that would otherwise be NC (Section M).

If you have not included an XSYS header, you have devised a method

to program the SPI-ﬂash or OTP (Section M).

X6319,

XS1-U8A-64-FB96 Datasheet 96

N.4 Multi device designs

Skip this section if your design only includes a single XMOS device.

One device is connected to a SPI ﬂash for booting.

Devices that boot from link have MODE2 grounded and MODE3 NC.

These device must have link XLB connected to a device to boot from

(see 9).

If you included an XSYS header, you have included buﬀers for RST_N,

TMS, TCK, MODE2, and MODE3 (Section L).

X6319,

XS1-U8A-64-FB96 Datasheet 97

O PCB Layout Design Check List

This section is a checklist for use by PCB designers using the XS1-U8A-

64-FB96. Each of the following sections contains items to check for

each design.

O.1 Ground Balls and Ground Plane

There is one via for each ground ball to minimize impedance and

conduct heat away from the device (Section 16.1).

There are only few non-ground vias around the square of ground balls,

to creating a good, solid, ground plane. Examples of a good and bad

designs are shown in Figure XXX.

O.2 Power supply decoupling

VSUP has a ceramic X5R or X7R bulk decoupler as close as possible

to the VSUP and PGND (VDDCORE) pins; right next to the device

(Section 16).

The 1V0 decoupling cap is close to the VDDCORE and PGND pins

(Section 16).

The 1V8 decoupling cap is close to the VDD1V8 and PGND pins (Sec-

tion 16).

All PGND nets are connected together prior to connection to the main

ground plane (Section 16).

An example PCB layout is shown in Section 17. Placing the decouplers too far away

may lead to the device not coming up, or not operating properly.

X6319,

XS1-U8A-64-FB96 Datasheet 98

P Associated Design Documentation

Document Title Information Document Number

Programming XC on XMOS Devices Timers, ports, clocks, cores and

channels

X9577

xTIMEcomposer User Guide Compilers, assembler and

linker/mapper

X3766

Timing analyzer, xScope, debugger

Flash and OTP programming utilities

Q Related Documentation

Document Title Information Document Number

The XMOS XS1 Architecture ISA manual X7879

XS1 Port I/O Timing Port timings X5821

XS1-L System Speciﬁcation Link, switch and system information X1151

XS1-L Link Performance and Design

Guidelines

Link timings X2999

XS1-L Clock Frequency Control Advanced clock control X1433

X6319,

XS1-U8A-64-FB96 Datasheet 99

R Revision History

Date Description

2013-01-30 New datasheet - revised part numbering

2013-02-26 New multicore microcontroller introduction

Moved conﬁguration sections to appendices

2013-03-27 Added connection details for USB_VBUS/USB_ID - Section 11

VDDCORE parameters - Section 18.2

2013-04-16 OSC_REF_EXT_N Properties - Section 4

Sleep mode requirements include JTAG - Section 14.4

2013-07-19 Updated Features list with available ports and links - Section 2

Simpliﬁed link bits in Signal Description - Section 4

New JTAG, xSCOPE and Debugging appendix - Section M

New Schematics Design Check List - Section N

New PCB Layout Design Check List - Section O

Updated USB_VBUS pin connection - Section 11

Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and

is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in

relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation

thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any

such claims.

X6319,