InventraTM MUSBLSFC USB 1.1 Low-Speed Function Controller Soft Core (RTL IP) D A T A S H E E T Endpoint Control EP0 Control EP1 - 2 Control IN IN OUTIN Combine Endpoints Major Product Features: MCU Interface Interrupt Control Interrupts EP Reg. Decoder Low-speed (1.5 Mbps) functions Common Regs SIE RAM Controller DPLL USB NRZI Bit Stuff CRC Packet Enc/Dec Shift Register Address Generator Cycle Control * Complies with USB standard for VCI * Configurable for up to 2 IN endpoints and 2 OUT endpoints in addition to Endpoint 0 FIFO Decoder Cycle Control * 8-byte FIFOs for each endpoint * High-level 8-bit synchronous PVCI *-compatible CPU interface RAM * Synchronous RAM interface for FIFOs MUSBLSFC Block Diagram * Suspend and Resume signaling supported * Fully synthesizable Overview * Scan test ready The MUSBLSFC core provides a USB function controller that complies with the * Graphical User Interface provided for core configuration USB 1.1 and 2.0 specifications for Low-speed (1.5 Mbps) functions. The core is user-configurable for one or two IN endpoints and/or one or two OUT endpoints in addition to Endpoint 0. These additional endpoints can be used Deliverables: for either Bulk or Interrupt transfers. * Verilog/VHDL source code Both Endpoint 0 and each of these additional endpoints can be associated with a separate 8-byte FIFO. Alternatively a single 8-byte FIFO can be shared between an IN endpoint and the OUT endpoint with the same Endpoint number. The MUSBLSFC has a RAM interface for connecting to a single block of synchronous single-port RAM which is used for all the endpoint FIFOs (added * Synthesis script for Design Compiler * Verilog/VHDL testbench * Sample firmware * Product Specification; User Guide; Programmer's Guide by the user). Access to the FIFOs and the internal control/status registers is via an 8-bit synchronous CPU interface which conforms to the Peripheral Virtual Component Interface (PVCI) defined by VSIA. The MUSBLSFC provides all the USB packet encoding, decoding and checking Related Products * MUSBFSFC USB 1.1 Full-Speed - interrupting the CPU only when endpoint data has been successfully transferred. A graphical user interface script is provided for configuring the core to the user's Function Controller * MUSBHSFC USB 2.0 High/Full- requirements. (Note: Configuration GUI developed and tested using Tcl/Tk 8.3. Speed Function Controller Use with an earlier version of Tcl/Tk may give unpredictable results.) * Peripheral Virtual Component Interface, as defined by VSIA (OCB 2 v1.0) www.mentor.com/inventra InventraTM MUSBLSFC USB1.1 Low-Speed Function Controller Structure Signal Description The MUSBLSFC function controller consists of a The MUSBLSFC has a maximum of 63 external signals, Serial Interface Engine (SIE), a RAM Controller, an 28 inputs and 35 outputs. MCU Interface, and a control block for each endpoint. SIGNAL TYPE DESCRIPTION USB INTERFACE SIGNALS Serial Interface Engine DIP Input D+ single-ended input. The SIE handles NRZI encoding/decoding, bit DIM Input D- single-ended input. Differential input. DIDIF Input stuffing/unstuffing, and CRC generation/checking. It DOP Output D+ output. generates a 1.5 MHz USB clock from the 6 MHz input DOM Output D- output. NDOE Output Output enable for DOP, DOM. Active low. clock to the core, and synchronizes this clock to the incoming data stream when receiving data from the USB. It generates headers for packets to be transmitted and decodes the headers of received packets. RAM Controller The RAM Controller provides an interface to the single MCU INTERFACE SIGNALS MC_ADDR[3:0] Input Address bus. MC_DI[7:0] Input Data bus input. MC_DO[7:0] Output Data bus output. MC_NOE Output Data bus output enable. Active low. MC_VAL Input MCU access validate. MC_RNW Input Read not write. MC_ACK Output MCU access acknowledge. MC_NINT Output MCU interrupt. Active low. FCLK Input CLKOUT Output CLK Input NRST Input USB_NRSTO Output USB function reset output. Active low. USB_SUSPEND Output This signal goes high when the function is in Suspend mode. RAM_NCE Output RAM Enable. Active low. RAM_ADDR[n:0] Output RAM address bus. Bus width is dependent on the number and type of endpoints configured. block of synchronous single-port RAM that is used to buffer packets between the CPU and USB. It takes the FIFO pointers from the endpoint controllers, converts them to address pointers within the RAM block and generates the RAM access control signals. SYSTEM SIGNALS MCU Interface Input clock. This clock should be 6 MHz. System clock output (1.5 MHz ). Buffered version of CLKOUT. Power-up reset. Active low. RAM INTERFACE SIGNALS The MCU Interface provides an 8-bit synchronous VCI-compliant CPU interface to allow access to the control/status registers and FIFOs for each endpoint. It generates an interrupt to the CPU when a packet has been RAM_DATAI[7:0] Input RAM_DATAO[7:0] Output Data output bus - to RAM. Data input bus - from RAM. RAM_NWR Output RAM write enable. Active low. successfully transmitted or received, or when the core enters Configurable Options or resumes from Suspend mode. The MUSBLSFC is user-configurable for: Endpoint Controllers 1. The number of IN endpoints and/or OUT endpoints that Two controller state machines are used. One for control transfers over Endpoint 0, and one for bulk/interrupt transactions over Endpoints 1 and 2. are required in addition to Endpoint 0 (1 or 2). 2. Whether these endpoints have separate FIFOs or share a FIFO between an IN endpoint and the corresponding OUT endpoint. Reference Technology Gate Count: 5000 Note: All endpoints configured to work with 8-byte FIFOs. (c) 2000-2001 Mentor Graphics Corporation, All Rights Reserved. TM Mentor Graphics and Inventra are trademarks of Mentor Graphics Corporation. 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