Inventra™ MUSBLSFC
USB 1.1 Low-Speed Function Controller
Soft Core (RTL IP)
DATASHEET
www.mentor.com/inventra
MUSBLSFC Block Diagram
Overview
The MUSBLSFC core provides a USB function controller that complies with the
USB 1.1 and 2.0 specifications for Low-speed (1.5 Mbps) functions.
The core is user-configurable for one or two IN endpoints and/or one or two
OUT endpoints in addition to Endpoint 0. These additional endpoints can be used
for either Bulk or Interrupt transfers.
Both Endpoint 0 and each of these additional endpoints can be associated with
a separate 8-byte FIFO. Alternatively a single 8-byte FIFO can be shared between
an IN endpoint and the OUT endpoint with the same Endpoint number.
The MUSBLSFC has a RAM interface for connecting to a single block of
synchronous single-port RAM which is used for all the endpoint FIFOs (added
by the user). Access to the FIFOs and the internal control/status registers is via an
8-bit synchronous CPU interface which conforms to the Peripheral Virtual
Component Interface (PVCI) defined by VSIA.
The MUSBLSFC provides all the USB packet encoding, decoding and checking
– interrupting the CPU only when endpoint data has been successfully transferred.
A graphical user interface script is provided for configuring the core to the user’s
requirements. (Note: Configuration GUI developed and tested using Tcl/Tk 8.3.
Use with an earlier version of Tcl/Tk may give unpredictable results.)
Major Product Features:
• Complies with USB standard for
Low-speed (1.5 Mbps) functions
• Configurable for up to 2 IN
endpoints and 2 OUT endpoints
in addition to Endpoint 0
• 8-byte FIFOs for each endpoint
• High-level 8-bit synchronous
PVCI *-compatible CPU interface
• Synchronous RAM interface for
FIFOs
• Suspend and Resume signaling
supported
• Fully synthesizable
• Scan test ready
• Graphical User Interface provided
for core configuration
Deliverables:
• Verilog/VHDL source code
• Synthesis script for Design Compiler
• Verilog/VHDL testbench
• Sample firmware
• Product Specification; User Guide;
Programmer’s Guide
Related Products
• MUSBFSFC USB 1.1 Full-Speed
Function Controller
• MUSBHSFC USB 2.0 High/Full-
Speed Function Controller
* Peripheral Virtual Component Interface,
as defined by VSIA (OCB 2 v1.0)
Endpoint Control
IN
IN
MCU Interface
S I E RAM Controller VCI
RAM
EP0
Control EP1 - 2
Control
IN
OUT
Combine Endpoints
Interrupt
Control
EP Reg.
Decoder
Common
Regs
Cycle
Control
FIFO
Decoder
Cycle Control
DPLL Address
Generator
NRZI Bit
Stuff CRC
Packet
Enc/Dec
Shift
Register
USB
Interrupts
Inventra™ MUSBLSFC USB1.1 Low-Speed Function Controller
© 2000-2001 Mentor Graphics Corporation, All Rights Reserved.
™Mentor Graphics and Inventra are trademarks of Mentor Graphics Corporation.
All other trademarks are the property of their respective owners.
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Structure
The MUSBLSFC function controller consists of a
Serial Interface Engine (SIE), a RAM Controller, an
MCU Interface, and a control block for each endpoint.
Serial Interface Engine
The SIE handles NRZI encoding/decoding, bit
stuffing/unstuffing, and CRC generation/checking. It
generates a 1.5 MHz USB clock from the 6 MHz input
clock to the core, and synchronizes this clock to the
incoming data stream when receiving data from the USB.
It generates headers for packets to be transmitted and
decodes the headers of received packets.
RAM Controller
The RAM Controller provides an interface to the single
block of synchronous single-port RAM that is used to buffer
packets between the CPU and USB. It takes the FIFO
pointers from the endpoint controllers, converts them to
address pointers within the RAM block and generates the
RAM access control signals.
MCU Interface
The MCU Interface provides an 8-bit synchronous
VCI-compliant CPU interface to allow access to the
control/status registers and FIFOs for each endpoint. It
generates an interrupt to the CPU when a packet has been
successfully transmitted or received, or when the core enters
or resumes from Suspend mode.
Endpoint Controllers
Two controller state machines are used. One for control
transfers over Endpoint 0, and one for bulk/interrupt
transactions over Endpoints 1 and 2.
Reference Technology Gate Count: 5000
Signal Description
The MUSBLSFC has a maximum of 63 external signals,
28 inputs and 35 outputs.
SIGNAL TYPE DESCRIPTION
USB INTERFACE SIGNALS
DIP Input D+ single-ended input.
DIM Input D- single-ended input.
DIDIF Input Differential input.
DOP Output D+ output.
DOM Output D- output.
NDOE Output Output enable for DOP, DOM. Active low.
MCU INTERFACE SIGNALS
MC_ADDR[3:0] Input Address bus.
MC_DI[7:0] Input Data bus input.
MC_DO[7:0] Output Data bus output.
MC_NOE Output Data bus output enable. Active low.
MC_VAL Input MCU access validate.
MC_RNW Input Read not write.
MC_ACK Output MCU access acknowledge.
MC_NINT Output MCU interrupt. Active low.
SYSTEM SIGNALS
FCLK Input Input clock. This clock should be 6 MHz.
CLKOUT Output System clock output (1.5 MHz ).
CLK Input Buffered version of CLKOUT.
NRST Input Power-up reset. Active low.
USB_NRSTO Output USB function reset output. Active low.
USB_SUSPEND Output This signal goes high when the function is in
Suspend mode.
RAM INTERFACE SIGNALS
RAM_NCE Output RAM Enable. Active low.
RAM_ADDR[n:0] Output RAM address bus. Bus width is dependent on the
number and type of endpoints configured.
RAM_DATAI[7:0] Input Data input bus – from RAM.
RAM_DATAO[7:0] Output Data output bus – to RAM.
RAM_NWR Output RAM write enable. Active low.
Configurable Options
The MUSBLSFC is user-configurable for:
1. The number of IN endpoints and/or OUT endpoints that
are required in addition to Endpoint 0 (1 or 2).
2. Whether these endpoints have separate FIFOs or share a
FIFO between an IN endpoint and the corresponding OUT
endpoint.
Note: All endpoints configured to work with 8-byte FIFOs.
