FEATURES @ Greater than 70 dB Stopband Rejection e Operation at +5 VDC @ Precise Filter Positioning @ Low Power Consumption @ No External Components Required for Filter te EXAR Aan. ...the analog plus company XR-1015/1016 Seventh Order Elliptic Low Pass Filters September 1996-4 APPLICATIONS @ General Purpose Filtering e Anti-alias Filters (for analog-to-digital converters) e@ Reconstruction Filters (for digital-to-analog converters) @ Band Limiting of Voice e@ Digital Signal Processing Front End @ Filtering of Voice for Music for Special Effects (echo, phasing, etc.) GENERAL DESCRIPTION The XR-1015 and XR-1016 are seven pole and six zero elliptic low pass switched capacitor filters. The position of the passband of the filter is set by the frequency of the clock which allows for easy adjustment. The use of switched capacitor filters reduces the amount of variation in the filter response that occurs with discrete use of capacitors, inductors and resistors. The XR-1015 and XR-1016 also provide synchronized sampled inputs and outputs that allows the device to be cascaded without the need of an additional sample-and-hold. The XR-1015 and XR-1016 are produced with a 3 um polysilicon gate dual metal CMOS process for low power consumption. The XR-1015 is an eight pin device that can operate from +3, -2.0 VDC to --5VDC. The device can also be biased so that it can be operated with a single +5 to +10 VDC supply. It is pin-for-pin compatible with the Reticon R5609 with the added advantage of operating to +5 VDC single supply. The clock to corner ratio of the XR-1015 is fixed at 100:1. The XR-1016 is a 14 pin device which provides two uncommitted operational amplifiers for use as a reconstruction filter, anti-aliasing filters or for additional pre-filter gain. The XR-1016, as does the XR-1015, provides a clock output with the voltage output from rail to rail. The XR-1016 has the ability to change the clock to corner ratio from 100:1 to 50:1. The output clock can be used to strobe an analog-to-digital converter or to synchronize any additional circuits in the system. ORDERING INFORMATION Operating Part No. Package Temperature Range XR-1015CN 8 Lead 300 Mil CDIP 0C to 70C XR-1015CP 8 Lead 300 Mil PDIP 0C to 70C XR-1016CN 14 Lead 300 Mil CDIP 0C to 70C XR-1016CP 14 Lead 300 Mil PDIP 0C to 70C XR-1016CD 16 Lead 300 Mil JEDEC SOIC 0C to 70C 1995 TOM EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 @ (510) 668-7000 @ FAX (510) 668-7017XR-1015/1016 7 EXAR BLOCK DIAGRAM 7 Pole Elliptic . Filter Low Pass $$ > Filter In Filter Out Clock Level 9 Clock In Shift 7 Generator 5 10 o_T Clock+2 OUT Figure 1. XR-1015 Block Diagram 2 TOM#2 EXAR PIN CONFIGURATION XR-1015/1016 OU _ 5/10 Co 16 [Filter In 5/10 Filter In Filter Out CS] 2 15 |F Analog Ref. Filter Out Analog Ref. NC Coy] 3 4 NC Clock In Vss Clock In Coy] 4 3/3 Vss 5/10 Filter In CLK OUT / Vpp Clock Out--2 Co) 5 XR-1016 ;2 [E> Vpp Filter Out Analog Ref. CS (out), B (Out) A(Out) CC] 6 1 [-] B (Out) Clock In Vss Acin) Le] B (-In) A(-In) Coy] 7 io [|B (-In) Clock Vppb A (4In) Clock A(+iIn) Coy 8 9 |-4 Clock 2 Out Select Select 8 Lead PDIP, CDIP (0.300) 14 Lead PDIP, CDIP (0.300) 16 Lead SOIC (Jedec, 0.300) PIN DESCRIPTION 1015 | 1016 Pin# | Pin# Symbol Description 1 1 5/10 This controls the reference level of the internal level shifters of the XR-1015 or XR-1016 in order to determine the point at which the device considers the digital inputs to be a logic 1 or a logic 0. When this input is at Vgg, the decision level is at 2/3 of the sum of the magnitudes of the Vpp and Vgsg levels relative to Vgg. When the 5/10 pin is tied high, then the decision level is set for 2/3 of the sum of the magnitudes of the Vpp and Vgg in voltage relative to Vpp. Table 1 shows some of the possibilities of the input logic thresholds. The level at pin 1 does not affect the clock output amplitude. This output is always from near Vpp to near Vsg in amplitude. Vpp/Vss Level at Pin 1 Logic Decision Level +5/-5 VDC -5 VDG 1.8 VDC +5 -1.8 VDC +5/0 VDC 0 3.7 VDC +5 1.8 VDC +2.5/-2.5 VDC -2.5 1.2 VDC +2.5 -0.7 VDC +10/0 VDC 0 6.8 VDC +10 3.2 VDC Table 1. 2 2 OUTPUT | The filter output. This output will drive a 10kQ load. The signal will be centered around the voltage set by ANALOG REFERENCE. 3 - CLOCKIN | The input clock is applied at this point. The input clock controls the position of the corner fre- quency of the filter using the ratio: f paock = 100:1 foomer The logic threshold level needed at this point is controlled by pin 1, 5/10. Please see the pin description of 5/10 for details. - 3 CLOCKIN | The input clock is applied to this point. The XR-1016 has an internal divider which provides either a clock to corner ratio of 100:1 or 50:1. This is controlled by pin 8 (CLOCK SELECT). If CLOCKIN is low, fclock/fcorner = 100:1. 3 TOMXR-1015/1016 #2 EXAR PIN DESCRIPTION (CONTD) 1015 Pin # 1016 Pin # Symbol Description 4 4 10 11 12 13 14 CLOCK/2 A (OUT) A (-INPUT) A (+INPUT) CLOCK SELECT B (-INPUT) B (OUT) Vpp Vss ANALOG REF. FILTER IN This output is the same frequency as the sampling frequency of the XR-1015 or XR-1016. It can be used to synchronize an analog-to-digital converter to the filters output. The failing edge of the CLOCK/2 output is the edge which the output (pin 2) should be sampled in order to ensure that the output has settled. Operational amplifier A output. This is provided for creating additional filtering if desired. This output can drive a load of typically 10kQ. Operational amplifier A negative input. This is a CMOS gate input with virtually infinite input impedance. Operational amplifier A positive input. This is a CMOS gate input with virtually infinite input impedance. This pin on the XR-1016 will select the clock to corner ratio of the filter. When this pin is at logic 0, the filter will have a clock to corner of 100:1. When this pin is tied to a logic 1, the clock to corner ratio will be 50:1. The CLOCK/CLOCK~2 will always represent the sampling frequency of the XR-1016. The logic level control of this digital input is controlled by pin 1 5/10 as described under that pin description. Operational amplifier B negative input. Notice that the positive input of this operational amplifi- er 8 is tied internally to the ANALOG REFERENCE. Operational amplifier B output. Positive supply input. The range of voltages of this point is from +2.5 VDC to +5 VDC when used with dual supplies of equal magnitude. If a single supply is used, the range is from +5 VDC to +10 VDC. It is recommended that a 0.47uF capacitor be tied from this pin to ground to decouple the noise on the supply line which can degrade the performance of the filter. If very low clock frequencies are used, then the size of the capacitor should be increased to keep the noise on the supply at a minimum. This capacitor should be located as close to the Vpp pin as possible. It is suggested that a 100 resistor from the positive supply to Vpp be used to filter system supply noise from the filter. Negative supply input. The range of the input is from -5 VDC to 0 VDC depending on the volt- age present at Vpp. It is recommended that the pin be decoupled with a 0.47uF capacitor located as physically close as possible to the Vgs pin and tied from Vgg to ground. It is rec- ommended that a 10Q resistor from the negative supply to Vsg be used to filter system sup- ply noise from the filter. This pin provides the level at which the analog signals will be referenced. If equal split sup- plies are used, then this point is tied to ground. If unequal supplies or a single supply is used, then this point should be tied to a resistor divider circuit to provide a voltage at the analog reference pin that is 1/2 of the algebraic sum of the two supplies. Since this point is used as analog ground inside the device, it is recommended that a 0.47uF capacitor be tied from this pin to ground. As with the Vpp and Vgg decoupling, the size of this capacitor should be made larger if the clock frequency is decreased. Filter input: The signal that needs to be filtered is applied to this point. It has an input imped- ance of 4MQ at 1MHz clock frequency. It should be noted that any signal applied to this input greater than 1/2 of the sampling frequency will be aliased into the band of interest. 4 TOM#2 EXAR XR-1015/1016 ELECTRICAL CHARACTERISTICS Test Conditions: V+ = 5 VDC, V- = -5 VDC, fo. ocx = 2MHz, R; = 1 MQ, C, = 40pF, Ta = 25C Unless Otherwise Specified. XR-1015 XR-1016 Symbol Parameters Min. | Typ. | Max. | Min. | Typ. | Max. | Units Conditions General Characteristics Supply Voltage Single Supply 5 10.5 Vv See Figure 2. 5 10.5 Vv See Figure 4. Split Supply +3, -2 15.25 Vv See Figure 3. +3, -2 5.25 Vv See Figure 5. Supply Current Single Supply 10 11 mA See Figure 2. 10 11 mA See Figure 4. Split Supply Positive 10 12 mA See Figure 3. Negative 10 12 mA Positive 10 12 mA See Figure 5. Negative 10 12 mA Filter Section foLock Upper Frequency 2 2.5 MHz See Figure 3. Limit 2 2.5 MHz See Figure 5. fcLockMIN _ | Lowest Practical 1 kHz See Figure 3. 1 kHz See Figure 5. Input Impedance Pin 8 1 mQ See Figure 3., fotock = 1MHz Pin 14 1 See Figure 5. fotock = 1MHz tpw Minimum fetock 200 ns See Figure 3. Pulse Width 200 ns See Figure 5. THD Total Harmonic Vin = 2 Vpp Distortion 0.02% 0.02% foLock = 500kHz 0.1% 0.1% foLock = 2MHz Clock Feedthrough 30 30 mVpp VINMAX Maximum Input 8 8 Vpp Above which distortion Voltage increases. Corner Freq. 40.5 1 40.5 1 % feLtock = 2MHz Accuracy 5 TOMXR-1015/1016 7 EXAR ELECTRICAL CHARACTERISTICS (CONTD) XR-1015 XR-1016 Symbol Parameters Min. Typ. Max. Min. Typ. Max. Units Conditions Ay Passband Gain -0.5 0 +0.5 -0.5 0 +0.5 dB Tested at fix = 293Hz, 3.9kHz, 8.6kHz, 12.1kHz -4 0 +1 -1 0 +1 dB Tested at fiy = 15.3kHz, 17.1kHz Ripple Passband 40.1 -0.1 dB foLock = 500kHz 0.5 1 0.5 1 dB foLock = 2MHz Vos Voltage Offset -0.5 -0.2 +0.5 -0.5 -0.2 +0.5 VDC Output Noise 0.6 0.6 mvVrms_ | 1Hz-20Hz, Figure 9. Operation Amplifier Unity Gain 1.2 1.2 MHz Bandwidth CMRR Common Mode 50 50 dB Rejection Ratio (2 Vpp Input) Vio Input Offset -30 30 -30 30 mV Voltage Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Derate Above Ta = +25C ......... 7mW/PC Power Dissipation - XR-1015 ..................... Power SUPPIY 6-2 seein ens 1aV Coramia Package 385mW Input Signal Level ............ V+ +0.3 to V- -+0.3V Go nr " Power Dissipation - XR-1016 (Package Limitation) .. Derate Above Ta = +25C ....... 8.3mW/'C Ceramic Package ............... 1000mw Plastic Package .................. 300mW Derate Above Tg = +25C ......... 6mW/C Derate Above Ta =+25C ...... 8.3mMW/"C Plastic Package .................. 800mW Storage Temperature ............ -65C to +150C 6 TOM#2 EXAR XR-1015/1016 SYSTEM DESCRIPTION The XR-1015 and XR-1016 General Purpose Seventh Order Elliptic Switched Capacitor Low Pass Filters are usually used as the first or last stage in any sampled signal system. Any signal from the -3dB point of the low pass response to 1/2 of the sampling frequency (1/4 of the clock frequency) will be attenuated by typically 75dB, referenced to the passband. This allows its use with analog-to-digital converters to prevent the A-to-D from aliasing signals that are above 1/2 of the sampling frequency of the analog-to-digital converter. A simple second order active filter can be used in front of the XR-1015 or XR-1016 if it is known that some input signals will be above the Nyquist frequency of the XR-1015 or XR-1016. The reverse of the above circuit can be used for digital-to-analog converters, to prevent the sampling frequency from causing difficulties with other stages in the system. Application Information The XR-1015 and XR-1016 are fabricated in P-well CMOS. This uses a N-substrate and requires the Vpp to be applied first before Vsg in order to prevent latchup of the device. In addition to the above caution, the input signals should not be applied above the power supply levels, to prevent latchup. The same is true of the input clock. The input signal should not have any traces or wires near the clock or other system clocks. The same is true of the output. This will help to reduce the clock feedthrough and provide measurements equal to the datasheet values, or better. PRINCIPLES OF OPERATION The XR-1015 and XR-1016 are switched capacitor filters with seven poles and six zeros with an elliptic response. With the elliptic response of the filter, the stop band rejection is greater than 75dB. The elliptic filter response is called an equal-ripple response, where the ripple in the stop band is an approximation of the ripple in the pass band. In this way the rolloff of the filter response is very fast as shown in Figure 6. The use of zeros to obtain the stop band attenuation does cause some change in the linearity of the group delay of the elliptic filter. The rapid change in group delay occurs near the corner frequency as shown in Figure 7. This would only be a factor in situations where the output signal must not be delayed by different times for different input frequencies. For applications where the distortion of the phase information is important, the corner frequency of the filter can be placed higher in frequency so that the linear portion of the group delay response of the filter can be located within the information band. Since the XR-1015 and XR-1016 are sample data filters in that they divide the continuous time signal into an amount of charge at a given time, certain limitations must be made on the signals placed on the input of the filters. The frequency of the signal applied to this input must have a period so that at least two samples of the signal are made during the period of the signal. This is true even if the signal is in the stop band response of the filter. The reason for this is that it would take a minimum of two samples of the frequency being applied to establish the period of the signal as well as an approximation of the amplitude. If this sampling criteria is not followed, then the output of the filter will be an aliased signal of the input since the period of the signal would be not accurately known and the frequency would not be known. If this situation may occur, a simple second order filter can be added to the input. With the XR-1016, operational amplifier A could be used to create this filter. The precision of the location of the corner frequency of the filter is not critical in this situation so that precision resistors and capacitors would not be needed. TOMXR-1015/1016 7 EXAR Oscilloscope 5/10 L/ 3 IN Signal J 42V 45 V_ | Generator OUT [rer <o 7 XR-1015 T 10 CLK IN Vss = 3 6 l Spectrum = OTHE Analyzer CLK + 2 OUT Vv o, 5 oD I Pulse Generator Figure 2. XR-1015 Test Circuit: 5 V Operation (Vpp = +5 V, Vsg = 0 V, Ref = +2 V) : 0.68; pot Oscilloscope Hl I 5/10 \/ a LN Signal J = Vpp = +5V Generator OUT REF <o 2 To XR-1015 = 10 CLKIN] | 5 Vss Spectrum = OTHE Analyzer CLK + 2 OUT Vv Oo. 5 oD I Pulse Generator Figure 3. XR-1015 Test Circuit: 10 V Operation (Vpp = +5 V, Vss = -5 V) 8 TOM7 EXAR XR-1015/1016 Vg = -5V 10 : otra a~K Oscilloscope TL 5/10 LJ 1s IN Signal J = 42V Generator OUT REF _o? 1 UF XR-1016 Ti t CLKIN] 2 ss Vong * Spectrum _CLKOUT_| + Anal CLK + 2 OUT ~ nalyzer O 4 a1 LYpp = ' A (QUT) B (OUT) pL 0.1 WF Oo 5 10 eO L , 6 9 -_O CLK + 2 A (+ IN) OUT o7 8 o CLK CLK SELECT OUT Pulse Generator Figure 4. XR-1016 Test Circuit: 5 V Operation (Vpp = +5 V, Vsg = 0 V, Ref = +2 V) Veg = -5V 10 ; 0.68)F = Oscilloscope L 5/10 LJ 1s IN Signal J = Generator OUT REF t O 2 6B Vpp = +5V XR-1016 = CLK IN Vss 3 12 10 Spectrum _ CLKOUT _ , Analyzer CLK + 2 OUT V y 4, 4 Oe | oO 0.1 WF A (OUT) B (OUT) L Oo5 io -O = A (-IN) B (-IN) OJ 9-O CLK +2 A (+IN) * OUT Oo 7 8 Oo CLK CLK SELECT OUT Pulse Generator Figure 5. XR-1016 Test Circuit: 10 V Operation (Vpp = +5 V, Vsg = -5VDC) 9 TOMXR-1015/1016 | 4 EXAR X25. OOBKHZ Yb=-3.1358 dB FREO RESP oO. O 10.0 dB/Div dB \ . AA -s0.0 Fxd Y & Hz 25. OOSKHz SO. OO6K Figure 6. Amplitude Response X25. OOGKHz Ya=106. 6lip M: FREQ RESP 200 u 25.0 ray SEC/Div Real Th Vv \ .o.0 FxdxY 6 Hz 35. OO6KHz Figure 7. Group Delay Response 10 TOM7 EXAR XR-1015/1016 FREQ RESP 0.0 so. 0 mdB/Div NS dB -400 Feadxy 68 S. OO6KH=z SO. OO6K Figure 8. Typical Passband Ripple Avg=4. 70076uV/s SHz POWE PEC2 n M MVerms/Oiv Mag FxdxY O 25kKHz Sok Figure 9. Typical Output Noise 11 TOMXR-1015/1016 7 EXAR 7 Pole Elliptic . Filter Low Pass pl Filter In Filter Out Clock O ) Level . Clock In Shift , + Generator 5 10 oT Clock+2 OUT Figure 10. XR-1015 Block Diagram 7 Pole Elliptic . Filter Low Pass EE ) Filter In Filter Out Clock Oo Level 9 Clock In Shift 7 Generator 5 70 O CLOCKOUT MUX >| Buffer OR CLOCK/2 Clock Oo Level * Select Shift O A(-IN) > OQ A(OQUT) O A (+IN) O B(-IN) Analog => O B (OUT) Reference TOM Figure 11. XR-1016 Block Diagram 12XR-1015/1016 #2 EXAR 8 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 SO os 8 5] F D E; 1 4] oy LI bay La La b> 4 A Seating Plane L capt IL? Cc =e B e By INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.145 0.210 3.68 5.33 Ay 0.015 0.070 0.38 1.78 Ao 0.015 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 By 0.030 0.070 0.76 1.78 Cc 0.008 0.014 0.20 0.38 D 0.348 0.430 8.84 10.92 E 0.300 0.325 7.62 8.26 Ey 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC ep 0.310 0.430 7.87 10.92 L 0.115 0.160 2.92 4.06 a 0 15 0 15 Note: The control dimension is the inch column 13 TOMXR-1015/1016 7 EXAR 8 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev. 1.00 E EY Base Ay Plane , Plane all> J L | alee B B, a INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.100 0.200 2.54 5.08 Ay 0.015 0.060 0.38 1.52 B 0.014 0.026 0.36 0.66 By 0.045 0.065 1.14 1.65 0.008 0.018 0.20 0.46 D 0.305 0.405 7.75 10.29 Ey 0.250 0.310 6.35 7.87 E 0.300 BSC 7.62 BSC e 0.100 BSC 2.54 BSC L 0.125 0.200 3.18 5.08 a 0 15 0 15 Note: The control dimension is the inch column 14 TOM7 EXAR XR-1015/1016 14 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 Seating _A Plane L INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.145 0.210 3.68 5.33 Ay 0.015 0.070 0.38 1.78 Ao 0.115 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 By 0.030 0.070 0.76 1.78 Cc 0.008 0.014 0.20 0.38 0.725 0.795 18.42 20.19 0.300 0.325 7.62 8.26 Ey 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC ep 0.310 0.430 7.87 10.92 L 0.115 0.160 2.92 4.06 a 0 15 0 15 Note: The control dimension is the inch column 15 TOMXR-1015/1016 7 EXAR 14 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev. 1.00 Base AY Plane =a Hy Seating Lh F STW TA me ole halk af es INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.100 0.200 2.54 5.08 Ay 0.015 0.060 0.38 1.52 B 0.014 0.026 0.36 0.66 Bt 0.045 0.065 1.14 1.65 0.008 0.018 0.20 0.46 D 0.685 0.785 17.40 19.94 E1 0.250 0.310 6.35 7.87 E 0.300 BSC 7.62 BSC e 0.100 BSC 2.54 BSC L 0.125 0.200 3.18 5.08 a 0 15 0 15 Note: The control dimension is the inch column 16#2 EXAR XR-1015/1016 16 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) < D _ Rev. 1.00 HARARE | | E H 2 | O 8 HHEHHHHH Cc Beating UHHH + + SH A ane ~~ Teoker oT Wi L INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 Ay 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 D 0.398 0.413 10.10 10.50 E 0.291 0.299 7.40 7.60 e 0.050 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 a 0 8 0 8 Note: The control dimension is the millimeter column 17 TOM