[AK4121A] AK4121A Asynchronous Sample Rate Converter GENERAL DESCRIPTION The AK4121A is a stereo asynchronous sample rate converter. The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. Since the internal PLL eliminates the need for a master clock in slave mode, the AK4121 simplifies the system design. Therefore, the AK4121A is suitable for applications requiring multiple sample rates, such as Car Audio, DVD recorders, and digital audio recording. FEATURES Stereo asynchronous sample rate converter Input sample rate range (FSI): 8kHz to 96kHz Output sample rate (FSO): 32kHz/44.1kHz/48kHz/96kHz Input to output Sample rate ratio: FSO/FSI = 0.33 to 6 THD+N: -113dB I/F format: MSB justified, LSB justified (24/20/16bit) and I2S Clock for Master mode: 256/384/512/768fso De-emphasis filter: 32kHz/44.1kHz/48kHz SRC Bypass mode Soft Mute function Power Supply: VDD: 3.0 to 3.6V, TVDD: 3.0 to 5.5V (for input tolerant) Ta: -40 to +85C PDN DEM0 DEM1 SMUTE TVDD VDD DVSS (MCLK) SDTI ILRCK Serial Audio I/F IBICK De-em filter Sample Rate Converter soft mute Serial Audio I/F SDTO OLRCK OBICK CMODE2 AVSS CMODE1 PLL CMODE0 FILT IDIF2 IDIF1 IDIF0 ODIF1 MS0337-E-06 ODIF0 2010/04 -1- [AK4121A] Ordering Guide AK4121AVF AKD4121A -40 +85C 24pin VSOP (0.65mm pitch) Evaluation Board for AK4121A Pin Layout FILT 1 24 VDD AVSS 2 23 DVSS PDN 3 22 TVDD SMUTE 4 21 MCLK DEM0 5 20 OLRCK DEM1 6 19 OBICK ILRCK 7 18 SDTO IBICK 8 17 ODIF1 SDTI 9 16 ODIF0 IDIF0 10 15 CMODE2 IDIF1 11 14 CMODE1 IDIF2 12 13 CMODE0 Top View Difference between AK4121 and AK4121A The AK4121A has a better performance than the AK4121 regarding of the tracking capability to the change of the input sampling frequency (FSI) which normally takes long settling time. Refer to "Tracking to the Input Sampling Frequency". MS0337-E-06 2010/04 -2- [AK4121A] PIN/FUNCTION No. 1 2 Pin Name FILT AVSS 3 PDN 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SMUTE DEM0 DEM1 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 CMODE0 CMODE1 CMODE2 ODIF0 ODIF1 SDTO OBICK OLRCK MCLK TVDD DVSS VDD I/O O I I I I I I I I I I I I I I I I O I/O I/O I I I I Function Loop-Filter Pin for PLL Analog Ground Pin Power-Down pin When "L", the AK4121A is powered-down and reset. Soft Mute Pin De-emphasis Filter Control Pin #0 De-emphasis Filter Control Pin #1 L/R Clock Pin for Input Audio Serial Data Clock Pin for Input Audio Serial Data Input Pin Input Data Format pin #0 Input Data Format pin #1 Input Data Format pin #2 Clock Mode Select Pin #0 Clock Mode Select Pin #1 Clock Mode Select Pin #2 Output Data Format pin #0 Output Data Format pin #1 Audio Serial Data Output Pin Audio Serial Data Clock Pin for Output L/R Clock Pin for Output Master Clock Pin for Output Input Buffer Power Supply Pin, 3.3V or 5V Digital Ground Pin Power Supply Pin, 3.3V MS0337-E-06 2010/04 -3- [AK4121A] ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=0V; Note 1) Parameter Symbol min max Units Power Supplies: VDD TVDD GND IIN VIN Ta Tstg -0.3 -0.3 4.6 6.0 0.3 10 TVDD+0.3 85 150 V V V mA V C C Core Input Buffer |AVSS-DVSS| (Note 1) Input Current, Any Pin Except Supplies Input Voltage Ambient Temperature (Power applied) Storage Temperature Note 1. All voltages with respect to ground. -0.3 -40 -65 WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=DVSS=0V; Note 2) Parameter Symbol min typ Power Supplies: Core VDD 3.0 3.3 Input Buffer TVDD VDD 5 Note 2. All voltages with respect to ground. max 3.6 5.5 SRC PERFORMANCE (Ta=-4085C; VDD=3.03.6V; TVDD=3.0~5.5V; data=20bit; measurement bandwidth=20Hz~FSO/2; unless otherwise specified.) Parameter Symbol min typ max Resolution 20 Input Sample Rate FSI 8 96 Output Sample Rate FSO 32 96 Dynamic Range (Input= 1kHz, -60dBFS, Note 3) FSO/FSI=44.1kHz/48kHz 114 FSO/FSI=48kHz/44.1kHz 114 FSO/FSI=32kHz/48kHz 114 FSO/FSI=96kHz/32kHz 115 112 Worst Case (FSO/FSI=48kHz/96kHz) Dynamic Range (Input= 1kHz, -60dBFS, A-weighted, Note 3) 117 FSO/FSI=44.1kHz/48kHz THD+N (Input= 1kHz, 0dBFS, Note 3) -113 FSO/FSI=44.1kHz/48kHz FSO/FSI=48kHz/44.1kHz -112 FSO/FSI=32kHz/48kHz -113 FSO/FSI=96kHz/32kHz -111 Worst Case (FSO/FSI=48kHz/8kHz) -103 Ratio between Input and Output Sample Rate FSO/FSI (FSO/FSI, Note 4, Note 5) 0.33 6 Note 3. Measured by Rohde & Schwarz UPD04, Rejection Filter= wide, 8192point FFT. Note 4. The "0.33" is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz Note 5. The "6" is the ratio when FSI is 8kHz and FSO is 48kHz. MS0337-E-06 Units V V Units Bits kHz kHz dB dB dB dB dB dB dB dB dB dB dB - 2010/04 -4- [AK4121A] DIGITAL FILTER (Ta=-4085C; VDD=3.03.6V; TVDD=3.0~5.5V) Parameter Symbol min typ max Units Digital Filter Passband -0.001dB 0.985 FSO/FSI 6.000 PB 0 0.4583FSI kHz 0.905 FSO/FSI < 0.985 PB 0 0.4167FSI kHz 0.714 FSO/FSI < 0.905 PB 0 0.3195FSI kHz 0.656 FSO/FSI < 0.714 PB 0 0.2852FSI kHz 0.536 FSO/FSI < 0.656 PB 0 0.2245FSI kHz 0.492 FSO/FSI < 0.536 PB 0 0.2003FSI kHz 0.452 FSO/FSI < 0.492 PB 0 0.1781FSI kHz 0.333 FSO/FSI < 0.452 PB 0 0.1092FSI kHz Stopband 0.985 FSO/FSI 6.000 SB 0.5417FSI kHz 0.905 FSO/FSI < 0.985 SB 0.5021FSI kHz 0.714 FSO/FSI < 0.905 SB 0.3965FSI kHz 0.656 FSO/FSI < 0.714 SB 0.3643FSI kHz 0.536 FSO/FSI < 0.656 SB 0.2974FSI kHz 0.492 FSO/FSI < 0.536 SB 0.2732FSI kHz 0.452 FSO/FSI < 0.492 SB 0.2510FSI kHz 0.333 FSO/FSI < 0.452 SB 0.1822FSI kHz Passband Ripple PR 0.01 dB Stopband Attenuation SA 96 dB Group Delay (Note 6) GD 57.5 1/fs Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input.(at 20bit MSB justified, 16bit and 20bit LSB justified) DC CHARACTERISTICS (Ta=-4085C; VDD=3.0~3.6V; TVDD=3.0~5.5V) Parameter Symbol Power Supply Current (VDD+TVDD) Normal operation: FSI=FSO=48kHz at Slave Mode: VDD=TVDD=3.3V FSI=FSO=96kHz at Master Mode: VDD=TVDD=3.3V : VDD=TVDD=3.6V Power down: PDN = "L" (Note 7) High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-400A) VOH VOL Low-Level Output Voltage (Iout=400A) Input Leakage Current Iin Note 7. All digital inputs including clock pins are held DVSS. MS0337-E-06 min 0.7xVDD VDD-0.4 - typ max Units 10 20 40 100 0.3xVDD 0.4 10 mA mA mA A V V V V A 10 - 2010/04 -5- [AK4121A] SWITCHING CHARACTERISTICS (Ta=-4085C; VDD=3.0~3.6V; TVDD=3.0~5.5V; CL=20pF) Parameter Symbol min Master Clock Input (MCLK) Frequency fCLK 8.192 Duty Cycle dCLK 40 L/R clock for Input data (ILRCK) Frequency fs 8 Duty Cycle Duty 48 L/R clock for Output data (OLRCK) Frequency (Note 8) fs 32 Duty Cycle Slave Mode Duty 48 Master Mode Duty Audio Interface Timing Input IBICK Period tBCK 1/64fs IBICK Pulse Width Low tBCKL 65 IBICK Pulse Width High tBCKH 65 ILRCK Edge to IBICK "" (Note 9) ILRCK Frequency = 8kHz ~ 32kHz tLRB 1/256fs+45 ILRCK Frequency = 32kHz ~ 48kHz tLRB 1/256fs+25 ILRCK Frequency = 48kHz ~ 96kHz tLRB 1/256fs+15 tBLR 30 BICK "" to ILRCK Edge (Note 9) tSDH 30 SDTI Hold Time from IBICK "" tSDS 30 SDTI Setup Time to IBICK "" Output (Slave Mode) OBICK Period tBCK 1/64fs OBICK Pulse Width Low tBCKL 65 OBICK Pulse Width High tBCKH 65 OLRCK Edge to OBICK "" (Note 9) tLRB 30 tBLR 30 OBICK "" to OLRCK Edge (Note 9) tLRS OLRCK to SDTO (MSB) tBSD OBICK "" to SDTO Output (Master Mode) BICK Frequency fBCK BICK Duty dBCK tMBLR BICK "" to LRCK -20 tBSD BICK "" to SDTO -20 Power-down & Reset Timing tPD 150 PDN Pulse Width (Note 10) Note 8. Min is 8kHz when BYPASS="H". Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4121A must be reset by bringing PDN pin "H" to "L" upon power-up. MS0337-E-06 typ max Units - 36.864 60 MHz % 50 96 52 kHz % 96 52 kHz % % 50 50 ns ns ns 16/256fs 16/256fs 16/256fs ns ns ns ns ns ns 30 30 ns ns ns ns ns ns ns 20 30 Hz % ns ns 64fs 50 ns 2010/04 -6- [AK4121A] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD 70%VDD SDTO 30%VDD tSDS tSDH VIH SDTI VIL Figure 2. Audio Interface Timing at Slave Mode MS0337-E-06 2010/04 -7- [AK4121A] LRCK 50%VDD tMBLR dBCK 50%VDD BICK tBSD 50%VDD SDTO Figure 3. Audio Interface Timing at Master Mode tPD VIH PDN VIL Figure 4. Power-down & Reset Timing Note 11. BICK means IBICK and OBICK. Note 12. LRCK means ILRCK and OLRCK. MS0337-E-06 2010/04 -8- [AK4121A] OPERATION OVERVIEW System Clock The input port works in slave mode only. The output port works in slave and master mode. An internal system clock is created by the internal PLL using ILRCK. The MCLK is not needed when the output port is in slave mode, and the MCLK pin should be connected to DVSS. The CMODE2-0 pins must be controlled when PDN pin ="L". Mode 0 1 2 3 4 5 6 7 CMODE2 L L L L H H H H CMODE1 L L H H L L H H CMODE0 MCLK L 256fso (fso~96kHz) H 384fso (fso~96kHz) L 512fso (fso~48kHz) H 768fso (fso~48kHz) L Not used. Set to DVSS H L H Not used. Set to DVSS Table 1. Master/Slave control Master/Slave (Output Port) Master Master Master Master Slave (Reserved) (Reserved) Master (BYPASS mode) Audio Interface Format The IDIF2-0 pins select the data mode for the input port. The ODIF1-0 pins select the data mode for the output port. In all modes the audio data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of OBICK. Select these modes when PDN pin="L". In BYPASS mode, both IBICK and OBICK are fixed to 64fs. Mode 0 1 2 3 4 IDIF2 L L L L H IDIF1 L L H H L IDIF0 SDTI Format L 16bit LSB Justified H 20bit LSB Justified L 20bit MSB Justified H 20/16bit I2S Compatible L 24bit LSB Justified Table 2. Input Audio Data Formats IBICK (Slave) 32fs 40fs 40fs 40fs or 32fs 48fs Mode ODIF1 ODIF0 SDTO Format OBICK (Slave) 0 L L 16bit LSB Justified 64fs 1 L H 20bit LSB Justified 64fs 2 H L 20/16bit MSB Justified (Note 13) 40fs or 32fs 3 H H 20/16bit I2S Compatible (Note 13) 40fs or 32fs Note 13. The 16bit output is available only when the OBICK = 32fs. Table 3. Output Audio Data Formats MS0337-E-06 OBICK (Master) 64fs 64fs 64fs 64fs 2010/04 -9- [AK4121A] LRCK 0 1 12 13 14 15 16 31 0 1 12 13 14 15 16 31 0 1 0 1 BICK (64fs) SDTI 16bit Don't care 15 0 Don't care 15 0 Don't care 15 0 15 0 15:MSB, 0:LSB SDTI 20bit 19 Don't care 18 17 16 19 18 16 17 19:MSB, 0:LSB Lch Data Rch Data Figure 5. 16bit/20bit LSB justified Timing LRCK 0 1 2 18 19 20 30 31 0 1 2 18 19 20 30 31 BICK (64fs) SDTI 19 18 1 0 Don't care 19 18 1 0 Don't care 19 18 0 1 20:MSB, 0:LSB Lch Data Rch Data Figure 6. 20bit MSB justified Timing LRCK 0 1 2 3 19 20 21 31 0 1 2 3 19 20 21 31 BICK (64fs) SDTI 19 18 1 0 Don't care 19 18 1 0 Don't care 19 19:MSB, 0:LSB Lch Data Rch Data 2 Figure 7. 20bit I S Timing MS0337-E-06 2010/04 - 10 - [AK4121A] Soft Mute Operation When the SMUTE pin changes to "H", the output signal is attenuated from 0dB to -dB during 1024 OLRCK cycles. When the SMUTE pin returns to "L", the attenuation is cancelled and the output signal gradually changes to 0dB during 1024 OLRCK cycles. If the soft mute is cancelled before attenuating to -, the attenuation is discontinued and returns to 0dB by the same cycles. The soft mute is effective for changing the signal source. SMUTE 0dB Attenuation Level at SDTO -dB (2) (1) (1) Notes: (1) Transition time. 1024 OLRCK cycles (1024/fso). (2) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to 0dB by the same number of clock cycles. Figure 8. Soft Mute De-emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc=50/15s) and is enabled or disabled with DEM0 and DEM1. Mode 0 1 2 3 DEM1 L L H H DEM0 L H L H De-emphasis filter 44.1kHz OFF 48kHz 32kHz Table 4. De-emphasis Filter Control MS0337-E-06 2010/04 - 11 - [AK4121A] System Reset Bringing the PDN pin="L" places the AK4121A in the power-down mode and initializes the digital filter. This reset should always be done after power-up. When the PDN pin = "L", the SDTO output is "L". Regarding the SDTO valid time, please refer to the Table 5. Until the output data becomes valid, the SDTO pin outputs "L". Case 1 External clocks (input port) don't care (state1) (state2) don't care SDTI don't care (state1) (state2) don't care External clocks (output port) don't care (state1) (state2) don't care PDN ta tb (1) (internal state) Power-down SDTO PLL lock & fs detection "0" data normal operation normal data PLL lock & fs detection PD "0" data normal operation Power-down normal data "0" data Case 2 External clocks (input port) (no clock) (state1) don't care SDTI (don't care) (state1) don't care External clocks (output port) (don't care) (state1) don't care PDN (1) PLL Unlock (internal state) Power-down SDTO PLL lock & fs detection "0" data normal operation Power-down normal data "0" data Note: (1) <100ms for recommended value 2, <200ms for recommended value 1. (Figure 11) Figure 9. System Reset Data valid time Reset time tb ta <100ms 10ms 10ms< <200ms Table 5. Reset time ta and Data valid time tb. MS0337-E-06 2010/04 - 12 - [AK4121A] Internal Reset Function for Clock Change The AK4121A is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms. Sequence of changing clocks The recommended sequence for changing clocks is shown in Figure 10. External clocks (Input port or Output port) Clocks 1 Don't care Clocks 2 < 10msec PDN pin < 100ms (Internal state) Normal operation Power-down PLL lock & fs detection SDTO Normal data SMUTE (recommended) Att.Level Note1 Note2 Normal operation Normal data 1024/fso 1024/fso 0dB - dB Figure 10. Sequence of changing clocks Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to "0" from GD before the PDN pin changes to "L", which will cause the data on SDTO to remain "0". Note 2. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to "0" for 1024/fso+100ms or more from the timing PDN pin changes to "H" while the SMUTE pin = "H". Note 3. When the PDN pin is not used for this clock change, a distorted signal may output for about 10ms ~ 100ms (typ) after changing clocks. MS0337-E-06 - 13 - 2010/04 [AK4121A] Grounding and Power Supply Decoupling The AK4121A requires careful attention to power supply and grounding arrangements. VDD are usually supplied from the system's analog supply. AVSS and DVSS of the AK4121A must be connected to the analog ground plane. System analog ground and digital ground should be connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors especially a 0.1F ceramic capacitor for high frequency noise should be placed as near to VDD as possible. PLL Loop-Filter The C1 (4.7F) and R (560ohms) should be connected in series and attached between FILT pin and AVSS in parallel with C2 (1.0nF). A Care should be taken to ensure that noise on the FILT pin is minimized. AK4121A FILT R C2 C1 AVSS Parameter Recommended value 1 Recommended value 2 R 560ohm +/-8% 1.2kohm +/-8% C1 4.7F +/-40% 2.2F +/-40% C2 1.0nF +/-40% 2.2nF +/-40% FSI range 8k ~ 96kHz 16k ~ 96kHz Note 14. Those recommended values include temperature dependence. Figure 11. PLL Loop-Filter MS0337-E-06 2010/04 - 14 - [AK4121A] Jitter Tolerance Figure 12 shows the jitter tolerance to ILRCK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 12. When the jitter amplitude is 0.01UIpp or less, the AK4121A operates normally regardless of the jitter frequency. AK4121A Jitter Tolerance 10.00 Amplitude [UIpp] 1.00 (3) 0.10 (2) 0.01 (1) 0.00 1 10 100 1000 10000 Jitter Frequency [Hz] (1) Normal operation (2) There is a possibility that the distortion degrades. (It may degrade up to about -50dB.) (3) There is a possibility that the output data is lost. Note 15. The jitter amplitude for 1UI (Unit Interval) is one cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8s. Figure 12. Jitter Tolerance Tracking to the Input Sampling Frequency When the ILRCK is generated by an external PLL, it may take a time to settle after changing the input sampling frequency because the response of an external PLL to the frequency change is slow. In case of the AK4121, the output data becomes incorrect when the speed of the frequency change exceeds 0.14%/sec. The AK4121A operates normally up to 23%/sec speed and the output data becomes incorrect at the speed of the frequency change over 23%/sec. MS0337-E-06 2010/04 - 15 - [AK4121A] SYSTEM DESIGN Figure 13 and Figure 14 illustrate typical system connection diagrams. The evaluation board [AKD4121A] demonstrates this application circuit, the optimum layout, and power supply arrangement and performance measurement results. + 10u 0.1u 4.7u 560 +3.3V Analog 1.0n VDD FILT 0.1u AVSS DVSS PDN TVDD +3.3~5V Digital (*1) MCLK SMUTE Control DEM0 fsi DSP1 Mode setting (fix to "H" or "L") AK4121A fso OLRCK DEM1 OBICK ILRCK SDTO IBICK ODIF1 SDTI ODIF0 IDIF0 CMODE2 IDIF1 CMODE1 IDIF2 CMODE0 DSP2 Figure 13. Example of a typical design (Slave Mode) + 10u 0.1u 4.7u 560 1.0n VDD FILT 0.1u AVSS DVSS PDN TVDD SMUTE MCLK Control DEM0 fsi DSP1 Mode setting (fix to "H" or "L") +3.3V Analog AK4121A OLRCK DEM1 OBICK ILRCK SDTO IBICK ODIF1 SDTI ODIF0 IDIF0 CMODE2 IDIF1 CMODE1 IDIF2 CMODE0 +3.3~5V Digital (*1) 256fso fso 64fso DSP2 Figure 14. Example of a typical design (Master Mode; MCLK=256fso) *1. TVDD should be the same as the maximum input voltage. MS0337-E-06 2010/04 - 16 - [AK4121A] PACKAGE 24pin VSOP (Unit: mm) 1.250.2 *7.90.2 13 A 7.60.2 *5.60.2 24 12 1 0.65 0.220.1 0.15 +0.1 -0.05 0.10.1 0.50.2 Detail A Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10 Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate (Pb free) MS0337-E-06 2010/04 - 17 - [AK4121A] MARKING AKM AK4121AVF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code MS0337-E-06 2010/04 - 18 - [AK4121A] REVISION HISTORY Date (YY/MM/DD) 04/09/01 Revision 00 Reason First Edition Page 07/06/05 01 Error Correct 4 Description Change 6 07/07/25 02 Description Change 13 07/09/14 03 Add Spec 6 Error Correct 6 Description Addition 9 08/03/05 04 Contents SRC PERFORMANCE Dynamic Range, Worst Case FSO/FSI=32kHz/44.1kHz 48kHz/96kHz SWITCHING CHARACTERISTICS Audio Interface timing ILRCK Edge to IBICK "" is changed to ILRCK period (8kHz ~ 32kHz): 1/256fs+45 ILRCK period (32kHz ~ 48kHz): 1/256fs+25 ILRCK period (48kHz ~ 96kHz): 1/256fs+15 Internal Reset Function for Clock Change Sequence of Changing Clocks Max values of ILRCK Edge to IBICK "" were added. ILRCK Frequency =8kHz ~ 32kHz: 16/256fs ILRCK Frequency =32kHz ~ 48kHz: 16/256fs ILRCK Frequency =48kHz ~ 96kHz: 16/256fs The Symbol of ILRCK Edge to IBICK "" tBLR tLRB The Symbol of IBICK "" to ILRCK Edge tLRB tBLR The Symbol of OLRCK Edge to OBICK "" tBLR tLRB The Symbol of OBICK "" to OLRCK Edge tLRB tBLR Note 13. was added. 08/04/05 05 Description Change 5 10/04/30 06 Description Addition 13 MS0337-E-06 DC CHARACTERISTICS Power Supply Current (VDD+TVDD) description was added. VDD =3.3V VDD=TVDD=3.3V VDD= 3.6V VDD=TVDD=3.6V Sequence of changing clocks Description is added in notes. 2010/04 - 19 - [AK4121A] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0337-E-06 2010/04 - 20 -