S-35710M www.ablic.com www.ablicinc.com FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 (c) ABLIC Inc., 2017 The convenience timer is a CMOS timer IC which operates with low current consumption, and is suitable for the time management of the relative time. The S-35710M compares the timer value and the value written to the internal register, and outputs an interrupt signal when the values match each other. The timer is a 24-bit binary-up counter. The internal register data can be set freely by users via a 2-wire serial interface. Consequently, the time before the occurrence of an interrupt signal can be set freely. Since the S-35710M has a built-in quartz crystal, a matching assessment of the IC and the quartz crystal is unnecessary. Moreover, the number of external parts can also be reduced. Caution This product can be used in vehicle equipment and in-vehicle equipment. Before using the product in the purpose, contact to ABLIC Inc. is indispensable. Features * Built-in 32.768 kHz quartz crystal * Alarm interrupt function: Settable on the second time scale from 1 second to 194 days (Approximately half a year) * Low current consumption: 0.25 A typ. (VDD = 3.0 V, Ta = +25C) * Wide range of operation voltage: 1.8 V to 5.5 V * 2-wire (I2C-bus) CPU interface * Operation temperature range: * Lead-free (Sn 100%), halogen-free * AEC-Q100/Q200 qualified*1 *1. Ta = -40C to +125C Contact our sales office for details. Application * Time management of various systems during the sleep period Package * HSOP-8Q 1 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Block Diagram Pull-up RST 32.768 kHz Quartz crystal Oscillation circuit Divider, Timing generator Chattering elimination circuit Internal reset signal INT pin controller INT Wake-up time register Comparator Timer (24-bit) VDD Power-on detection circuit Constant voltage circuit Time register SDA Serial interface VSS SCL Figure 1 2 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M AEC-Q100/Q200 Qualified This IC supports AEC-Q100/Q200 for operation temperature grade 1. Contact our sales office for details of AEC-Q100/Q200 reliability specification. Product Name Structure 1. Product name S-35710M 01 A - E8T3 U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specification*1 E8T3: HSOP-8Q, Tape Operation temperature A: Ta = -40C to +125C Option code Product name *1. Refer to the tape drawing. 2. Package Table 1 Package Name HSOP-8Q Dimension FU008-A-P-SD Package Drawing Codes Tape FU008-A-C-SD Reel FU008-A-R-SD Land FU008-A-L-SD 3 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Pin Configuration 1. HSOP-8Q Table 2 Top view Pin No. 1 8 2 7 3 6 4 5 Symbol 1 SCL 2 VDD _______ Bottom view Description Input pin for serial clock Pin for positive power supply Input pin for reset signal List of Pins I/O Input Configuration CMOS input - - CMOS input (With pull-up resistor) 3 RST 4 NC*2 No connection - - 5 *2 NC No connection - 6 VSS GND pin Output pin for interrupt signal I/O pin for serial data - - - 8 1 7 2 7 INT 6 3 8 SDA 5 4 Input Output CMOS output Bi-directional Nch open-drain output, CMOS input *1 Figure 2 *1. *2. Connect the heat sink of backside at shadowed area to the board, and set electric potential GND. However, do not use it as the function of electrode. The NC pin is electrically open. Therefore, leave it open or connect it to the VDD pin or the VSS pin. Caution 4 Do not place a wiring on the backside of the package. FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Pin Functions 1. SDA (I/O for serial data) pin This is a data input / output pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with a clock pulse from the SCL pin. This pin has CMOS input and Nch open-drain output. Generally in use, the SDA pin is pulled up to VDD potential via a resistor, and is used with wired-OR connection of other device of Nch open-drain output or open collector output. 2. SCL (Input for serial clock) pin This is a clock input pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with this clock pulse. _______ 3. RST (Input for reset signal) pin _______ This pin inputs the reset signal. The timer is reset when inputting "L" to _______ the RST pin. The INT pin is set to "H" when _______ inputting "H" to the RST pin, and the timer starts the operation. The RST pin has a built-in chattering elimination _______ circuit. Regarding the chatterging elimination circuit, refer to " RST Pin". _______ Also, the RST pin has a pull-up resistor. 4. INT (Output for interrupt signal) pin This pin outputs an interrupt signal. The interrupt signal is output when the time written to the wake-up time register comes. Regarding the operation of the interrupt signal output, refer to " INT Pin Interrupt Signal Output". Also, the INT pin output form is CMOS output. 5. VDD (Positive power supply) pin Connect this pin with a positive power supply. Regarding the values of voltage to be applied, refer to " Recommended Operation Conditions". 6. VSS pin Connect this pin to GND. 5 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Equivalent Circuits of Pins SDA SCL Figure 3 SCL Pin Figure 4 SDA Pin _______ INT RST Figure 5 6 _______ RST Pin Figure 6 INT Pin FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Absolute Maximum Ratings Table 3 Item Power supply voltage Input voltage Symbol VIN Output voltage Applied Pin Absolute Maximum Rating Unit - _______ VSS - 0.3 to VSS + 6.5 VSS - 0.3 to VSS + 6.5 V V VSS - 0.3 to VDD + 0.3 VSS + 6.5 VSS - 0.3 to VSS + 6.5 V SDA VDD VOUT SDA, SCL RST INT V V VSS - 0.3 to VDD + 0.3 VSS + 6.5 Operation ambient temperature*1 Topr - -40 to +125 C Storage temperature Tstg - -55 to +125 C *1. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a malfunction. Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operation Conditions Table 4 Item Operation power supply voltage Symbol VDD Condition Ta = -40C to +125C Min. Typ. Max. 1.8 - 5.5 (VSS = 0 V) Unit V Oscillation Characteristics Table 5 Item Oscillation start voltage Oscillation start time Frequency deviation Symbol VSTA tSTA f/f (Ta = +25C, VDD = 3.0 V, VSS = 0 V unless otherwise specified) Condition Min. Typ. Max. Unit Within 10 seconds 1.8 - 5.5 V - - - 1 s Ta = -40C to +125C -1 - +1 % 7 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M DC Electrical Characteristics Table 6 Item Current consumption 1 Current consumption 2 High level input leakage current Low level input leakage current High level output leakage current Low level output leakage current High level input voltage Low level input voltage High level output voltage Low level output voltage Low level input current 8 Symbol Applied Pin VDD = 3.0 V, Ta = -40C to +85C, Out of communication, _______ RST pin = VDD, INT pin = no load VDD = 3.0 V, Ta = +125C, Out of communication, _______ RST pin = VDD, INT pin = no load VDD = 3.0 V, fSCL = 1 MHz, During communication, _______ RST pin = VDD, INT pin = no load - IDD1 - IDD2 (Ta = -40C to +125C, VSS = 0 V unless otherwise specified) Condition Min. Typ. Max. Unit _______ - 0.25 0.5 A - 0.75 1.2 A - 170 300 A IIZH SDA, SCL, RST VIN = VDD -0.5 - 0.5 A IIZL SDA, SCL VIN = VSS -0.5 - 0.5 A IOZH SDA VOUT = VDD -0.5 - 0.5 A IOZL SDA VOUT = VSS -0.5 - 0.5 A VIH SDA, SCL, RST - 0.7 x VDD - VSS + 5.5 V VIL SDA, SCL, RST - VSS - 0.3 - 0.3 x VDD V VOH INT IOH = -0.4 mA 0.8 x VDD - - V VOL SDA, INT IOL = 2.0 mA - - 0.4 V _______ VDD = 3.0 V, VIN = VSS -100 -30 -5 A IIL _______ _______ RST FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M AC Electrical Characteristics Table 7 Measurement Conditions Input pulse voltage Input pulse rise / fall time Output reference voltage Output load VIH = 0.8 x VDD, VIL = 0.2 x VDD 20 ns VOH = 0.7 x VDD, VOL = 0.3 x VDD 100 pF Input pulse voltage 0.8 x VDD 0.7 x VDD 0.3 x VDD 0.2 x VDD Figure 7 Table 8 Output reference voltage Input / Output Waveform during AC Measurement AC Electrical Characteristics (Ta = -40C to +125C) VDD = 1.8 V to 2.5 V VDD = 2.5 V to 5.5 V Symbol Unit Item Min. Max. Min. Max. SCL clock frequency fSCL 0 400 0 1000 kHz SCL clock "L" time tLOW 1.3 - 0.4 - s SCL clock "H" time tHIGH 0.6 - 0.3 - s SDA output delay time*1 - 0.9 - 0.5 s tAA Start condition set-up time tSU.STA 0.6 - 0.25 - s Start condition hold time tHD.STA 0.6 - 0.25 - s Data input set-up time tSU.DAT 100 - 80 - ns Data input hold time tHD.DAT 0 - 0 - ns Stop condition set-up time tSU.STO 0.6 - 0.25 - s SCL, SDA rise time tR - 0.3 - 0.3 s SCL, SDA fall time tF - 0.3 - 0.3 s Bus release time tBUF 1.3 - 0.5 - s Noise suppression time tl - 50 - 50 ns *1. Since the output form of the SDA pin is Nch open-drain output, the SDA output delay time is determined by the values of the load resistance and load capacitance outside the IC. Figure 9 shows the relationship between the output load values. 9 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M tF tHIGH tR tLOW SCL tHD.DAT tHD.STA tSU.STA tSU.STO tSU.DAT SDA (S-35710M input) tBUF tAA SDA (S-35710M output) Figure 8 Bus Timing Maximum pull-up resistance [k] 15 13 11 9 fSCL = 400 kHz 7 5 3 fSCL = 1.0 MHz 1 100 10 Load capacitance [pF] Figure 9 10 Output Load 1000 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M INT Pin Interrupt Signal Output _______ After the RST pin changes from "L" to "H", the timer starts the operation. Then, the INT pin outputs "H" level when the timer value matches the value written to the wake-up time register. When the INT pin outputs "H" level, the timer stops and maintains the timer value. _______ _______ The timer is reset by inputting "L" to the RST pin. After that, if "H" is input to the RST pin, the INT pin is set to "L" and the timer restarts the count-up action. 1. Write mode If write operation is performed to the wake-up time register during the count-up action, the action will be restarted after resetting the timer. This operation is called "write mode". Before the timer value matches the value written to the _______ wake-up time register, if "L" is input to the RST pin, the timer is reset. RST Timer Wake-up time register Timer and wake-up time register are reset "0 h" "1 h" "2 h" "0 h" Count-up action stops "1 h" "2 h" Count-up action stops "0 h" "1 h" Count-up action starts Timer is reset and count-up action restarts Timer is reset and the count-up actionrestarts "000000 h" "000002 h" "000001 h" INT 2s Figure 10 Timer and wake-up time register are reset "0 h" Count-up action starts "000000 h" 1s Output Timing of Handshake Time-out 2. Read mode After the timer starts to operate, if write operation is not performed to the wake-up time register, the interrupt signal is not output from the INT pin. The timer stops at "FFFFFF h". The timer value during timing can be confirmed by reading the time register. This operation is called "read _______ mode". In order for the timer to operate again, set the RST pin from "L" to "H" or perform write operation to the wake-up time register. Regarding the detail when write operation is not performed to the wake-up time register, refer to Figure 11. Regarding the status transition for the S-35710M, refer to Figure 12. RST Timer Timer and wake-up time register are reset "0 h" "1 h" "2 h" Count-up action starts Wake-up time register "FFFFFE h" Timer reset "FFFFFF h" Count-up action stops "0 h" "1 h" Timer reset "2 h" Count-up action starts "0 h" "1 h" "FFFFFE h" "FFFFFF h" Count-up action starts Count-up action stops "000000 h" No INT pin interrupt signal output when not writting to wake-up time register INT Figure 11 When Write Operation is not Performed to the Wake-up Time Register 11 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Write Power-on RST pin = "L" Initial status Wake-up time register = "0 h" Timer = "0 h" INT pin = "L" RST pin = "H" RST pin = "L" Timer reset Timer = "0 h" INT pin = "L" Automatic migration Count up every second Write Timing status INT pin = "L" Read Write Write Timing status INT pin = "L" Read Timer = "FFFFFF h" RST pin = "L" Write Timing stop status INT pin = "L" RST pin = "L" Timer = Wake-up time register Timing stop status INT pin = "H" Count up every second Read Read mode Read RST pin = "L" Write Timer reset Wake-up time register = "0 h" Timer = "0 h" INT pin = "H" Read Write mode Figure 12 12 RST pin = "H" Remark Write: Wake-up time register write command Read: Time register read command Status Transition Diagram for S-35710M FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Configuration of Registers 1. Time register The time register is a 3-byte register that stores the timer value in the binary code. The time register is read-only. Perform the read operation of the time register in 3-byte unit from TM23 to TM0. Example: 3 seconds (0000_0000_0000_0000_0000_0011) 45 minutes (0000_0000_0000_1010_1000_1100) 5 hours 30 minutes (0000_0000_0100_1101_0101_1000) TM23 TM22 TM21 TM20 TM19 TM18 TM17 TM16 B7 B0 TM15 TM14 TM13 TM12 TM11 TM10 TM9 B7 TM7 TM8 B0 TM6 TM5 TM4 TM3 TM2 TM1 B7 TM0 B0 Figure 13 2. Wake-up time register The wake-up time register is a 3-byte register that stores the wake-up time of the microcontroller in the binary code. The wake-up time register is possible for write and read. Perform the write and read operation of the wake-up time register in 3-byte unit from WU23 to WU0. _______ _______ When performing the read operation of the wake-up time register, set the RST pin to "H". If the RST pin is set to "L", the time register data is read. WU23 WU22 WU21 WU20 WU19 WU18 WU17 WU16 B7 B0 WU15 WU14 WU13 WU12 WU11 WU10 WU9 B7 WU7 WU8 B0 WU6 WU5 WU4 WU3 B7 WU2 WU1 WU0 B0 Figure 14 13 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Serial Interface The S-35710M transmits and receives various commands via I2C-bus serial interface to read / write data. 1. Start condition When SDA changes from "H" to "L" with SCL at "H", the S-35710M recognizes start condition and the access operation is started. 2. Stop condition When SDA changes from "L" to "H" with SCL at "H", the S-35710M recognizes stop condition and the access operation is completed. The S-35710M enters standby mode, consequently. tSU.STA tHD.STA tSU.STO SCL SDA Start condition Stop condition Figure 15 Start / Stop Condition 3. Data transmission and acknowledge The data transmission is performed at every 1 byte after the start condition detection. Pay attention to the specification of tSU.DAT and tHD.DAT when changing SDA, and perform the operation when SCL is "L". If SDA changes when SCL is "H", the start / stop condition is recognized even during the data transmission, and the access operation will be interrupted. Whenever a 1-byte data is received during data transimmion, the receiving device returns an acknowledge. For example, as shown in Figure 16, assume that the S-35710M is a receiving device, and the master device is a transmitting device. If the clock pulse at the 8th bit falls, the master device releases SDA. Consequently, the S-35710M, as an acknowledge, sets SDA to "L" during the 9th bit pulse. The access operation is not performed properly when the S-35710M does not output an acknowledge. SCL (S-35710M input) 1 tSU.DAT 8 9 tHD.DAT SDA (Master device output) Release SDA High-Z SDA (S-35710M output) Acknowledge output (Active "L") High-Z Start condition Figure 16 14 tAA Acknowledge Output Timing FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M 4. Data transmission format After the start condition transmission, the 1st byte is a slave address and a command (read / write bit) that shows the transmission direction of the data at the 2nd byte or subsequent bytes. The slave address of the S-35710M is specified to "0110010". The data can be written to the wake-up time register when read / write bit is "0", and the data of the wake-up time register or the time register can be read when read / write bit is "1". When the data can be written to the wake-up time register, input the data from the master device in order of B7 to B0. The acknowledge ("L") is output from the S-35710M whenever a 1-byte data is input. When the data of the wake-up time register or the time register can be read, the data from the S-35710M is output in order of B7 to B0 in byte unit. Input the acknowledge ("L") from the master device whenever a 1-byte data is input. However, do not input the acknowledge for the last data byte (NO_ACK). By this, the end of the data read is informed. After the master device receives / transmits the acknowledge for the last data byte, input the stop condition to the S-35710M to finish the access operation. When the master device inputs start condition without inputting stop condition at this time, the S-35710M becomes restart condition, and can transmit / receive the data continuously if the master device inputs the slave address continuously. 9 1 18 27 36 45 SCL Data write format SDA ST Slave address 0 A Data read format SDA ST Slave address 1 A B7 B7 B7 B0 B0 : Master device input data ST : S-35710M output data A Figure 17 B0 B0 A SP B0 SP B0 A Data B7 B0 A Data B7 A Data B7 : Start condition A Data B7 A Data A Data B7 B0 B7 A Data B7 A Data B0 A Data B7 A Data A B0 B1 R/W B7 B0 B7 Data A Data B7 A Data B1 R/W B7 ST Slave address 1 A B7 B0 B1 R/W B7 Restart format SDA ST Slave address 0 A A Data B1 R/W B7 B0 SP B0 SP : Stop condition A : Acknowledge Data Transmission Format of Serial Interface 15 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M 5. Read operation of time register Transmit the start condition and slave address from the master device. The slave address of the S-35710M is specified to "0110010". Next, the data of the time register can be read when the read / write bit is "1". The 2nd byte to the 4th byte are used as the time register. Each byte from B7 is transmitted. When the read operation of the time register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 is output from the master device, and then transmit the stop condition. The time register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes of the time register. Regarding the time register, refer to " Configuration of Registers". 1 9 18 27 36 SCL B7 B0 Slave address (0110010) B7 B0 B7 STOP B1 R/W B7 NO_ACK TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 0 1 1 0 0 1 0 1 ACK TM8 TM9 TM10 TM11 TM12 TM13 TM14 TM15 ACK TM16 TM17 TM18 TM19 TM20 TM21 TM22 TM23 ACK START SDA B0 Time register (3-byte) Take in the counter value at this timing and transmit it as a serial data. : Master device input data Input NO_ACK after the 3rd byte data is transmitted. : S-35710M output data Figure 18 Read Timing of Time Register 6. Write operation of wake-up time register Transmit the start condition and slave address from the master device. The slave address of the S-35710M is specified to "0110010". Next, transmit "0" to the read / write bit. Transmit the 2nd byte data. Set B7 to "1" since it is an address pointer. Set B6 to B1 to "0" or "1" since they are dummy data. Make sure to set B0 to "1" since it is a test bit. The 3rd byte to the 5th byte are used as the wake-up time register. Transmit the stop condition from the master device to finish the access operation. Regarding the wake-up time register, refer to " Configuration of Registers". Write operation of the wake-up time register is performed each byte, so transmit the data in 3-byte unit. Note that the S-35710M may not operate as desired if the the data is not transmitted in 3-byte unit. 1 9 18 27 36 45 SCL WU[23:16] Write timing B1R/W Slave address (0110010) 1 1 B7 B0 Dummy data B7 *1 B0 B7 B0 Wake-up time register (3-byte) Make sure to set B0 to "1" since it is a test bit. Set B7 as an address pointer. : Master device input data : S-35710M output data *1. Set B6 to B1 to "0" or "1" since they are dummy data. Figure 19 16 B7 Write Timing of Wake-up Time Register B0 STOP B7 WU[7:0] Write timing ACK WU0 WU1 WU2 WU3 WU4 WU5 WU6 WU7 ACK WU8 WU9 WU10 WU11 WU12 WU13 WU14 WU15 ACK WU16 WU17 WU18 WU19 WU20 WU21 WU22 WU23 ACK 01100100 ACK START SDA WU[15:8] Write timing FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M 7. Read operation of wake-up time register Perform the read operation of the wake-up time register with the restart format. Regarding the restart format, refer to "4. Data transmission format". _______ _______ When performing the read operation of the wake-up time register, set the RST pin to "H". If the RST pin is set to "L", the time register data is read. Transmit the start condition and the slave address from the master device. The slave address of the S-35710M is specified to "0110010". Next, transmit "0" to the read / write bit. B7 in the 2nd byte is an address pointer. Set B7 to "0" when reading the wake-up time register. Next, transmit the dummy data to B6 to B1. Make sure to set B0 to "1" since it is a test bit. This processing is called "dummy write". Then transmit the start condition, the slave address and the read / write bit. The data of the wake-up time register can be read when the read / write bit is set to "1". Consequently, the data of the wake-up time register is output from the S-35710M. Each byte from B7 is transmitted. When the read operation of the wake-up time register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 output from the master device, and then transmit the stop condition. The wake-up time register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes of the wake-up time register. Regarding the wake-up time register, refer to " Configuration of Registers". Moreover, the internal address pointer is reset if recognizing the stop condition. Therefore, do not transmit the stop condition after dummy write operation. The time register is read if performing the read operation of the register after transmitting the stop condition. 1 9 18 1 9 18 27 36 SCL B7 B0 Slave address (0110010) Dummy data *1 01100101 B7 B1R/W Slave address (0110010) B7 B0 B7 B0 B7 STOP 1 NO_ACK WU0 WU1 WU2 WU3 WU4 WU5 WU6 WU7 ACK WU8 WU9 WU10 WU11 WU12 WU13 WU14 WU15 ACK WU16 WU17 WU18 WU19 WU20 WU21 WU22 WU23 ACK B1 R/W 0 START B7 ACK 01100100 ACK START SDA B0 Wake-up time register (3-byte) Make sure to set B0 to "1" since it is a test bit. Input NO_ACKafter the 3rd byte transmission. Set B7 as an address pointer. Dummy write : Master device input data : S-35710M output data *1. Set B6 to B1 to "0" or "1" since they are dummy data. Figure 20 Read Timing of Wake-up Time Register 17 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Release of SDA _______ The RST pin of the S-35710M does not perform the reset operation of the communication interface. Therefore, the stop condition is input to reset the internal interface circuit usually. However, the S-35710M does not accept the stop condition from the master device when in the status that SDA outputs "L" (at the time of acknowledge outputting or reading). Consequently, it is necessary to finish the acknowledge output or read operation. Figure 21 shows the SDA release method. First, input the start condition from the master device (since SDA of the S-35710M outputs "L", the S-35710M can not detect the start condition). Next, input the clocks for 1-byte data access (9 clocks) from SCL. During the time, release SDA of the master device. By this, the SDA input / output before communication interrupt is completed, and SDA of the S-35710M becomes release status. Continuously, if the stop condition is input, the internal circuit resets and the communication returns to normal status. It is strongly recommended that the SDA release method is performed at the time of system initialization after the power supply voltage of the master device is raised. Start condition Clocks for 1-byte data access 1 SCL 2 8 Stop condition 9 SDA (Master device output) SDA (S-35710M output) SDA "L" "L" Figure 21 18 "L" or High-Z "L" or High-Z SDA Release Method High-Z FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Power-on Detection Circuit In order for the power-on detection circuit to operate normally, raise the power supply voltage of the IC from 0.2 V or lower so that it reaches 1.8 V of the operation power supply voltage minimum value within 10 ms, as shown in Figure 22. Within 10 ms 1.8 V (Operation power supply voltage min.) 0.2 V or lower 0V *1. *1 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35710M. Figure 22 How to Raise Power Supply Voltage If the power supply voltage of the S-35710M cannot be raised under the above conditions, the power-on detection circuit may not operate normally and an oscillation may not start. In such case, perform the operations shown in _______ "1. When _______ power supply voltage is raised at RST pin = "L" " and "2. When power supply voltage is raised at RST pin = "H" ". _______ 1. When power supply voltage is raised at RST pin = "L" _______ _______ Set the RST pin to "L" until the power supply voltage reaches 1.8 V or higher. While the RST_______ pin is set to "L", the oscillation start signal becomes "H", and the crystal oscillation circuit normally oscillates. If the RST pin is set to "H" after the power supply voltage reaches 1.8 V, the oscillation start signal becomes "L" within 500 ms, and the oscillation status is maintained. _______ The current consumption increases while the RST pin is set to "L" (30 A typ.). 10 ms 1.8 V (Operation power supply voltage min.) 0.2 V or lower 0 V*1 Oscillation start signal "H" "L" within 500 ms RST pin input Oscillation start signal Oscillation circuit output *1. 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35710M. _______ Figure 23 When Power Supply Voltage is Raised at RST Pin = "L" 19 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M _______ 2. When power supply voltage is raised at RST pin = "H" _______ _______ Set the RST pin to "L" after the power supply voltage reaches 1.8 V or higher. If the RST pin is set to "L" for 500 ms or longer, the oscillation start signal becomes "H", and the crystal oscillation circuit normally oscillates. After that, if the _______ RST pin is set to "H", the oscillation start signal becomes "L" within 500 ms, and the oscillation status is maintained. _______ The current consumption increases while the RST pin is set to "L" (30 A typ.). 10 ms 1.8 V (Operation power supply voltage min.) 0.2 V or lower 0V*1 RST pin input Oscillation start signal "H" "L" within 500 ms Oscillation start signal Oscillation circuit output *1. 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35710M. _______ Figure 24 _______ When Power Supply Voltage is Raised at RST Pin = "H" _______ communication The RST pin has a built-in chattering elimination circuit. To determine the RST pin "H" input, perform _______ subsequent to setting the interval of 3.5 periods (0.438 seconds) of clock (8 Hz) or longer after the RST pin changes from "L" to "H". _______ _______ Regarding the chattering elimination of the RST pin, refer to " RST Pin". 20 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M ________ RST Pin 1. Chattering elimination _______ The RST pin has a built-in chattering elimination circuit, and the output logic is active "L". Figure 25 is a timing chart of chattering elimination. Perform sampling at 8 Hz and operate the shift register circuit. Perform the shift operation for 3 times, and reset the counter when DF1 to DF3 are all "L". During the charttering elimination, the pulse width, 2 periods_______ (approximately 0.25 seconds) of clock (8 Hz), can be eliminated. To determine _______ pin "L" input during the period _______ longer than 3.5 periods (0.438 seconds) of the RST pin "L" input, maintain the RST _______ clock (8 Hz). Similarly, to determine the RST pin "H" input, maintain the RST pin "H" input during the period longer than 3.5 periods (0.438 seconds) of clock (8 Hz). Clock (8 Hz) ________ RST pin input signal Shift register_DF1 Shift register_DF2 Shift register_DF3 Chattering elimination width Reset signal after chattering elimination 2 periods Figure 25 Counter reset Count-up action starts 3.5 periods 3.5 periods Timing Chart of Chattering Elimination 2. Operation at power-on _______ At power-on, the reset signal after chattering elimination is "L" regardless of the RST pin status. Consequently, the S-35710M becomes initial status (Refer to "Figure 12 Status Transition Diagram for S-35710M") and can not perform write operation to the wake-up time register. When the reset signal after chattering elimination is "L", the no acknowledge is output in the 2nd or subserquent bytes if write operation is performed to the wake-up time register. If the crystal oscillation circuit starts to oscillate after power-on, the clock operates and the reset signal after chattering elimination becomes "H", the S-35710M then migrates to read mode. This makes the write operation to the wake-up time register possible. Figure 26 shows the timing chart at power-on. The write-disable time period of the wake-up time register showed in Figure 26 changes according to the oscillation start time. If the no acknowledge is output from the S-35710M at the time of write operation to the wake-up time register immediately after power-on, it is recommended to set a time interval of approximately 0.5 seconds to 1 second for the next communication until the oscillation is stabilized. VDD Clock (8 Hz) RST pin input signal Shift register_DF1 Shift register_DF2 Shift register_DF3 Migrate to read mode Reset signal after chattering elimination Write-disable time period of wake-up time register Figure 26 Timing Chart at Power-on 21 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M VIN 12 V VOUT VR S-35710M VDD SCL 1 k S-19xxx 1 k Example of Application Circuit VCC VCC SDA RST VSS VSS CPU INT VSS Figure 27 Caution 1. 2. Start communication under stable condition after turnig on the system power supply. The above connection diagrams do not guarantee operation. Set the constants after performing sufficient evaluation using the actual application. 22 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Precautions * Do not apply excessive impact or vibration since this IC has a built-in quartz crystal. Also, do not locate a device which generates high level of electronic noise near this IC. * Depending on the device, the usage condition and other reasons, the built-in quartz crystal may be damaged due to the impact or vibration at the time of board splitting and mounting. Perform thorough evaluation with the actual application. * The built-in quartz crystal may be damaged due to the resonance when executing the ultrasonic cleaning. Therefore, the operation of the IC is not guaranteed if the ultrasonic cleaning is executed. * Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. * ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 23 FOR AUTOMOTIVE 125C OPERATION 2-WIRE BUILT-IN QUARTZ CRYSTAL CONVENIENCE TIMER Rev.1.1_01 S-35710M Characteristics (Typical Data) 1. Current consumption 1 vs. Power supply voltage characteristics 2. Current consumption 2 vs. SCL frequency characteristics Ta = +25C 1.0 500 IDD2 [A] 0.8 IDD1 [A] Ta = +25C 600 0.6 0.4 0.2 VDD = 5.0 V 400 300 VDD = 3.0 V 200 100 0.0 0 2 4 0 6 0 VDD [V] 3. Current consumption 1 vs. Temperature characteristics f/f [ppm] IDD1 [A] VDD = 5.0 V 0.4 0.2 0.0 40 25 VDD = 3.0 V 0 25 50 Ta [C] 75 100 0 25 50 Ta [C] 75 100 4 6 INT pin, SDA pin, Ta = +25C 70 60 50 40 30 20 10 0 VDD = 5.0 V VDD = 3.0 V 0 125 2 4 6 VOUT [V] 8. Low level input current vs. Power supply voltage characteristics _______ RST pin, Ta = +25C 0 VDD = 3.0 V 10 IIL [A] 10 15 2 6. Low level output current vs. Output voltage characteristics INT pin, Ta = +25C 5 0 VDD [V] 7. High level output current vs. VDD - VOUT characteristics 0 10 0 IOL [mA] f/f [ppm] 50 0 50 100 150 200 250 300 350 400 450 40 25 20 10 125 5. Oscillation frequency vs. Temperature characteristics IOH [mA] Ta = +25C 30 0.6 1500 4. Oscillation frequency vs. Power supply voltage characteristics 0.8 VDD = 5.0 V 20 20 30 40 50 25 60 0 24 500 1000 SCL frequency [kHz] 2 4 VDD VOUT [V] 6 0 2 4 VDD [V] 6 5.020.2 8 5 1 4 1.27 1 0.220.05 3.0 8 4 5 0.420.05 No. FU008-A-P-SD-1.0 TITLE HSOP8Q-A-PKG Dimensions No. FU008-A-P-SD-1.0 ANGLE UNIT mm ABLIC Inc. 4.00.1(10 pitches:40.00.2) 2.00.05 o1.5 +0.1 -0.0 0.30.05 o2.00.05 8.00.1 2.10.1 6.70.1 1 8 4 5 Feed direction No. FU008-A-C-SD-1.0 TITLE HSOP8Q-A-Carrier Tape No. FU008-A-C-SD-1.0 ANGLE UNIT mm ABLIC Inc. 60 13.41.0 Enlarged drawing in the central part o210.8 17.41.0 20.5 o130.2 No. FU008-A-R-SD-1.0 TITLE HSOP8Q-A-Reel No. FU008-A-R-SD-1.0 ANGLE UNIT QTY. mm ABLIC Inc. 4,000 0.76 3.2 1.27 1.27 1.27 No. FU008-A-L-SD-1.0 TITLE HSOP8Q-A -Land Recommendation No. FU008-A-L-SD-1.0 ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein. 4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the products outside their specified ranges. 5. When using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc. Especially, the products cannot be used for life support devices, devices implanted in the human body and devices that directly affect human life, etc. Prior consultation with our sales office is required when considering the above uses. ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products. 9. Semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system must be sufficiently evaluated and applied on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party without the express permission of ABLIC Inc. is strictly prohibited. 14. For more details on the information described herein, contact our sales office. 2.2-2018.06 www.ablic.com