High Voltage, Latch-Up Proof,
8-/16-Channel Multiplexers
Data Sheet
ADG5206/ADG5207
Rev. A Document Feedback
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FEATURES
Latch-up proof
3.5 pF off source capacitance
Off drain capacitance
ADG5206: 64 pF
ADG5207: 33 pF
0.35 pC typical charge injection
±0.02 nA on channel leakage
Low on resistance: 155 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
VSS to VDD analog signal range
Human body model (HBM) ESD rating
ADG5206: 8 kV all pins
ADG5207: 8 kV I/O port to supplies
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Battery monitoring
Communication systems
FUNCTIONAL BLOCK DIAGRAMS
Figure 1.
Figure 2.
GENERAL DESCRIPTION
The ADG5206 and ADG5207 are monolithic CMOS analog
multiplexers comprising 16 single channels and 8 differential
channels, respectively. The ADG5206 switches one of sixteen
inputs to a common output, as determined by the 4-bit binary
address lines, A0, A1, A2, and A3. The ADG5207 switches one
of eight differential inputs to a common differential output, as
determined by the 3-bit binary address lines, A0, A1, and A2.
An EN input on both devices enables or disables the device. When
EN is low, the device is disabled and all channels switch off. The
ultralow capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make these
devices suitable for video signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
The ADG5206/ADG5207 do not have VL pins; instead, an on-chip
voltage generator generates the logic power supply internally.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up. A dielectric trench
separates the P and N channel transistors to prevent latch-up
even under severe overvoltage conditions.
2. Optimal switch design for low charge injection, low switch
capacitance, and low leakage currents.
3. The ADG5206 achieves 8 kV HBM ESD specification on
all external pins, while the ADG5207 achieves 8 kV on the
I/O port to supply pins, 2 kV on the I/O port to I/O port
pins, and 8 kV on all other pins.
4. Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5206/ADG5207 can be operated
from dual supplies of up to ±22 V.
5. Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5206/ADG5207 can be
operated from a single rail power supply of up to 40 V.
ADG5206
S1
S16
D
1-OF-16
DECODER
A0 A1 A2 A3 EN
10714-001
ADG5207
S1A
S8B
DA
DB
S8A
S1B
1-OF-8
DECODER
A0 A1 A2 EN
10714-002
ADG5206/ADG5207 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 4
12 V Single Supply ........................................................................ 6
36 V Single Supply ........................................................................ 8
Continuous Current per Channel, Sx, D, or Dx ..................... 10
Absolute Maximum Ratings ......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 16
Test Circuits ..................................................................................... 21
Terminology .................................................................................... 23
Applications Information .............................................................. 24
Trench Isolation .......................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
5/13—Rev. 0 to Rev. A
Added 32-Lead LFCSP ....................................................... Universal
Changes to Features Section and Product Highlights Section .......... 1
Moved Continuous Current per Channel, Sx, D, or Dx Section,
Table 5, and Table 6 ......................................................................... 10
Changes to Table 7 ........................................................................... 11
Changes to Figure 3 ......................................................................... 12
Changes to Figure 5 ......................................................................... 13
Changes to Figure 30, Figure 32, and Figure 33 .......................... 22
7/12—Revision 0: Initial Version
Data Sheet ADG5206/ADG5207
Rev. A | Page 3 of 28
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 155 Ω typ VS = ±10 V, IS = −1 mA;
see Figure 32
200 225 250 285 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between Channels,
ΔRON
4 Ω typ VS = ±10 V, IS = −1 mA
12 13 14 15 Ω max
On Resistance Flatness, RFL AT (ON) 48 Ω typ VS = ±10 V, IS = −1 mA
65 73 80 90 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.005 nA typ VS = ±10 V, VD =
10 V;
see Figure 33
±0.1 ±0.15 ±0.2 ±0.4 nA max
Match Between Channels, ΔLeakage,
IS (Off )1
0.01 0.015 nA typ VS = ±10 V, VD =
10 V
Drain Off Leakage, ID (Off ) VS = ±10 V, VD =
10 V;
see Figure 33
ADG5206 ±0.02 nA typ
±0.1 ±0.25 ±0.6 ±3.3 nA max
ADG5207
±0.02
nA typ
±0.1 ±0.25 ±0.4 ±1.7 nA max
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
0.015 0.015 nA typ VS = ±10 V, VD =
10 V
Channel On Leakage, ID (On), IS (On) VS = VD = ±10 V; see Figure 34
ADG5206 ±0.02 nA typ
±0.1
±0.6
±3.3
nA max
ADG5207 ±0.02 nA typ
±0.1 ±0.2 ±0.4 ±1.7 nA max
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01 0.03 nA typ VS = VD = ±10 V
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS
3
Transition Time, tTRANSITION 200 ns typ RL = 300 Ω, CL = 35 pF
260 300 320 360 ns max VS = 10 V; see Figure 35
tON (EN) 180 ns typ RL = 300 Ω, CL = 35 pF
245 260 270 285 ns max VS = 10 V; see Figure 36
tOFF (EN) 140 ns typ RL = 300 Ω, CL = 35 pF
200 220 240 270 ns max VS = 10 V; see Figure 36
Break-Before-Make Time Delay, tD 85 ns typ RL = 300 Ω, CL = 35 pF
27 ns min VS1 = VS2 = 10 V; see Figure 37
ADG5206/ADG5207 Data Sheet
Rev. A | Page 4 of 28
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
Charge Injection, QINJ 0.35 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
±1.8 ±2 pC typ VS = ±10 V, RS = 0 Ω, CL = 1 nF
Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
Channel-to-Channel Crosstalk −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF;
see Figure 41
ADG5206 60 MHz typ
ADG5207 140 MHz typ
Insertion Loss 6.4 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
CS (Off ) 3.5 pF typ VS = 0 V, f = 1 MHz
C
D
(Off )
ADG5206 64 pF typ VS = 0 V, f = 1 MHz
ADG5207 33 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On)
ADG5206 68 pF typ VS = 0 V, f = 1 MHz
ADG5207
36
pF typ
V
S
= 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 45 µA typ Digital inputs = 0 V or VDD
55 70 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD
1 µA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = +10 V and VD = −10 V, or VS = −10 V and VD = +10 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = +10 V, or VS = VD = −10 V.
3 Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 130 Ω typ VS = ±15 V, IS = −1 mA;
see Figure 32
160 180 200 230 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match Between Channels, ∆RON 4 Ω typ VS = ±15 V, IS = −1 mA
12 13 14 15 Ω max
On-Resistance Flatness, RFL AT (ON) 35 Ω typ VS = ±15 V, IS = −1 mA
50 58 65 75 Ω max
Data Sheet ADG5206/ADG5207
Rev. A | Page 5 of 28
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Source Off Leakage, IS (Off) ±0.005 nA typ VS = ±15 V, VD =
15 V;
see Figure 33
±0.1 ±0.15 ±0.2 ±0.4 nA max
Match Between Channels, ΔLeakage, IS (Off )1 0.01 0.015 nA typ
Drain Off Leakage, ID (Off ) VS = ±15 V, VD =
15 V;
see Figure 33
ADG5206 ±0.02 nA typ
±0.1 ±0.25 ±0.6 ±3.3 nA max
ADG5207 ±0.02 nA typ
±0.1 ±0.25 ±0.4 ±1.7 nA max
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
0.015 0.015 nA typ
Channel On Leakage, ID (On), IS (On) VS = VD = ±15 V;
see Figure 34
ADG5206 ±0.02 nA typ
±0.1 ±0.25 ±0.6 ±3.3 nA max
ADG5207 ±0.02 nA typ
±0.1 ±0.2 ±0.4 ±1.7 nA max
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01
0.03
nA typ
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±0.002 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION 185 ns typ RL = 300 Ω, CL = 35 pF
240 270 290 320 ns max VS = 10 V; see Figure 35
t
ON
(EN)
175
ns typ
R
L
= 300 Ω, C
L
= 35 pF
230 245 255 270 ns max VS = 10 V; see Figure 36
tOFF (EN) 135 ns typ RL = 300 Ω, CL = 35 pF
185 205 220 245 ns max VS = 10 V; see Figure 36
Break-Before-Make Time Delay, tD 75 ns typ RL = 300 Ω, CL = 35 pF
27 ns min VS1 = VS2 = 10 V; see Figure 37
Charge Injection, QINJ 0.45 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
±4 ±4 pC typ VS = ±10 V, RS = 0 Ω, CL = 1 nF
Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 39
Channel-to-Channel Crosstalk −76 dB typ RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 40
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF;
see Figure 41
ADG5206 65 MHz typ
ADG5207 145 MHz typ
Insertion Loss 5.6 dB typ RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 41
CS (Off ) 3.3 pF typ VS = 0 V, f = 1 MHz
ADG5206/ADG5207 Data Sheet
Rev. A | Page 6 of 28
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
CD (Off )
ADG5206 62 pF typ VS = 0 V, f = 1 MHz
ADG5207 32 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On)
ADG5206 67 pF typ VS = 0 V, f = 1 MHz
ADG5207 35 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +22 V, VSS = −22 V
IDD 50 µA typ Digital inputs = 0 V or VDD
70 110 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD
1 µA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = +15 V and VD = −15 V, or VS = −15 V and VD = +15 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = +15 V, or VS = VD = −15 V.
3 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 350 Ω typ VS = 0 V to 10 V, IS = −1 mA;
see Figure 32
500
560
610
700
Ω max
V
DD
= 10.8 V, V
SS
= 0 V
On-Resistance Match Between
Channels, ∆RON
5 Ω typ VS = 0 V to 10 V, IS = −1 mA
20 21 22 24 Ω max
On-Resistance Flatness, RFL AT (ON) 170 Ω typ VS = 0 V to 10 V, IS = −1 mA
280 310 335 370 Ω max
LEAKAGE CURRENTS VDD = +13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.005 nA typ VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 33
±0.1 ±0.15 ±0.2 ±0.4 nA max
Match Between Channels, ΔLeakage,
IS (Off )1
0.01 0.015 nA typ
Drain Off Leakage, ID (Off ) VS = 1 V/10 V, VD = 1 V/10 V;
see Figure 33
ADG5206
±0.02
nA typ
±0.1 ±0.25 ±0.6 ±3.3 nA max
ADG5207 ±0.02 nA typ
±0.1 ±0.25 ±0.4 ±1.7 nA max
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
0.015 0.015 nA typ
Channel On Leakage, ID (On), IS (On) VS = VD = 1 V/10 V; see Figure 34
ADG5206 ±0.02 nA typ
±0.1 ±0.25 ±0.6 ±3.3 nA max
ADG5207 ±0.02 nA typ
±0.1
±0.2
±0.4
±1.7
nA max
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01 0.03 nA typ
Data Sheet ADG5206/ADG5207
Rev. A | Page 7 of 28
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION 290 ns typ RL = 300 Ω, CL = 35 pF
290 440 480 550 ns max VS = 8 V; see Figure 35
tON (EN) 230 ns typ RL = 300 Ω, CL = 35 pF
290 320 340 370 ns max VS = 8 V; see Figure 36
tOFF (EN) 230 ns typ RL = 300 Ω, CL = 35 pF
315 360 390 450 ns max VS = 8 V; see Figure 36
Break-Before-Make Time Delay, tD 170 ns typ RL = 300 Ω, CL = 35 pF
45 ns min VS1 = VS2 = 8 V; see Figure 37
Charge Injection, QINJ 0.25 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
±0.6 ±0.7 pC typ VS = 0 V to 10 V, RS = 0 Ω, CL = 1 nF
Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
Channel-to-Channel Crosstalk −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
−3 dB Bandwidth
R
L
= 50 Ω, C
L
= 5 pF; see Figure 41
ADG5206 50 MHz typ
ADG5207 105 MHz typ
Insertion Loss 8.55 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 41
CS (Off ) 3.6 pF typ VS = 6 V, f = 1 MHz
CD (Off )
ADG5206 71 pF typ VS = 6 V, f = 1 MHz
ADG5207 36 pF typ VS = 6 V, f = 1 MHz
CD (On), CS (On)
ADG5206 75 pF typ VS = 6 V, f = 1 MHz
ADG5207
40
pF typ
V
S
= 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
I
DD
40
µA typ
Digital inputs = 0 V or V
DD
50 65 µA max
VDD 9/40 V min/V max GND = 0 V, VSS = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = 1 V and VD = 10 V, or VS = 10 V and VD = 1 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = 1 V, or VS = VD = 10 V.
3 Guaranteed by design; not subject to production test.
ADG5206/ADG5207 Data Sheet
Rev. A | Page 8 of 28
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 140 Ω typ VS = 0 V to 30 V, IS = −1 mA;
see Figure 32
170 195 215 245 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match Between Channels, ∆RON 4 Ω typ VS = 0 V to 30 V, IS = −1 mA
12 13 14 15 Ω max
On-Resistance Flatness, RFL AT (ON) 40 Ω typ VS = 0 V to 30 V, IS = −1 mA
55 63 70 80 Ω max
LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.005 nA typ VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 33
±0.1 ±0.15 ±0.2 ±0.4 nA max
Match Between Channels, ΔLeakage, IS (Off )1 0.01 0.015 nA typ
Drain Off Leakage, ID (Off ) VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 33
ADG5206 ±0.02 nA typ
±0.1
±0.25
±0.6
±3.3
nA max
ADG5207 ±0.02 nA typ
±0.1 ±0.25 ±0.4 ±1.7 nA max
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
0.015 0.015 nA typ
Channel On Leakage, ID (On), IS (On) VS = VD = 1 V/30 V;
see Figure 34
ADG5206 ±0.02 nA typ
±0.1 ±0.25 ±0.6 ±3.3 nA max
ADG5207 ±0.02 nA typ
±0.1 ±0.2 ±0.4 ±1.7 nA max
Match Between Channels, ΔLeakage,
ID (On), IS (On)2
0.01
0.03
nA typ
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION 225 ns typ RL = 300 Ω, CL = 35 pF
290 310 320 350 ns max VS = 18 V; see Figure 35
tON (EN) 215 ns typ RL = 300 Ω, CL = 35 pF
265 285 285 295 ns max VS = 18 V; see Figure 36
tOFF (EN) 170 ns typ RL = 300 Ω, CL = 35 pF
215 230 245 270 ns max VS = 18 V; see Figure 36
Break-Before-Make Time Delay, tD 90 ns typ RL = 300 Ω, CL = 35 pF
28 ns min VS1 = VS2 = 18 V; see Figure 37
Charge Injection, Q
INJ
0.7
pC typ
V
S
= 18 V, R
S
= 0 Ω, C
L
= 1 nF;
see Figure 38
±3 ±3 pC typ VS = 0 V to 30 V, RS = 0 Ω,
CL = 1 nF
Data Sheet ADG5206/ADG5207
Rev. A | Page 9 of 28
Parameter 25°C
−40°C to
+60°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 39
Channel-to-Channel Crosstalk −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 40
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF;
see Figure 41
ADG5206 55 MHz typ
ADG5207 115 MHz typ
Insertion Loss
5.65
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 41
CS (Off ) 3.4 pF typ VS = 18 V, f = 1 MHz
CD (Off )
ADG5206 62 pF typ VS = 18 V, f = 1 MHz
ADG5207 32 pF typ VS = 18 V, f = 1 MHz
CD (On), CS (On)
ADG5206 66 pF typ VS = 18 V, f = 1 MHz
ADG5207 35 pF typ VS = 18 V, f = 1 MHz
POWER REQUIREMENTS VDD = 39.6 V
IDD 80 µA typ Digital inputs = 0 V or VDD
100 130 µA max
VDD 9/40 V min/V max GND = 0 V, VSS = 0 V
1 The off channel leakage delta is calculated using the maximum of VS = 1 V and VD = 30 V, or VS = 30 V and VD = 1 V.
2 The on channel leakage delta is calculated using the maximum of VS = VD = 1 V, or VS = VD = 30 V.
3 Guaranteed by design; not subject to production test.
ADG5206/ADG5207 Data Sheet
Rev. A | Page 10 of 28
CONTINUOUS CURRENT PER CHANNEL, Sx, D, OR Dx
Table 5. ADG5206
Parameter 25°C 60°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 67.7°C/W) 44 32 23 12 mA maximum
LFCSP (θJA = 27.27°C/W) 62 42 28 13 mA maximum
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 67.7°C/W) 47 33 24 12 mA maximum
LFCSP (θJA = 27.27°C/W) 66 44 29 13 mA maximum
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W) 31 24 19 11 mA maximum
LFCSP (θJA = 27.27°C/W) 45 33 24 12 mA maximum
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W) 46 33 24 12 mA maximum
LFCSP (θJA = 27.27°C/W) 65 43 28 13 mA maximum
Table 6. ADG5207
Parameter 25°C 60°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx
V
DD
= +15 V, V
SS
= −15 V
TSSOP (θJA = 67.7°C/W) 33 25 19 11 mA maximum
LFCSP (θJA = 27.27°C/W) 48 34 24 12 mA maximum
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 67.7°C/W) 35 27 20 11 mA maximum
LFCSP (θJA = 27.27°C/W) 51 36 25 12 mA maximum
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W) 23 19 15 12 mA maximum
LFCSP (θJA = 27.27°C/W) 34 26 20 12 mA maximum
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 67.7°C/W) 34 26 20 11 mA maximum
LFCSP (θJA = 27.27°C/W) 50 35 25 12 mA maximum
Data Sheet ADG5206/ADG5207
Rev. A | Page 11 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, Sx, D, or Dx Pins
ADG5206 140 mA (pulsed at 1 ms, 10%
duty cycle maximum)
ADG5207 105 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx, D, or Dx
Pins2
Data + 15%
Temperature Range
Operating −40°C to +125°C
Storage −65°C to +150°C
Junction Temperature
150°C
Thermal Impedance, θJA
28-Lead TSSOP (4-Layer Board) 67.7°C/W
32-Lead LFCSP (4-Layer Board) 27.27°C/W
Reflow Soldering Peak
Temperature, Pb Free
As per JEDEC J-STD-020
HBM ESD
(ESDA/JEDEC JS-001-2011)
ADG5206
All Pins 8 kV
ADG5207
I/O Port to Supplies 8 kV
I/O Port to I/O Port 2 kV
All Other Pins 8 kV
1 Overvoltages at the Ax, EN, Sx, D, and Dx pins are clamped by internal
diodes. Limit current to the maximum ratings given.
2 See Table 5 and Table 6.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
ADG5206/ADG5207 Data Sheet
Rev. A | Page 12 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. ADG5206 Pin Configuration (TSSOP)
Figure 4. ADG5206 Pin Configuration (LFCSP)
Table 8. ADG5206 Pin Function Descriptions
Pin No.
Mnemonic Description
TSSOP LFCSP
1 31 VDD Most Positive Power Supply Potential.
2, 3, 13 12, 13, 26, 27,
28, 30, 32
NC No Connect. Not internally connected.
4 1 S16 Source Terminal 16. This pin can be an input or an output.
5 2 S15 Source Terminal 15. This pin can be an input or an output.
6 3 S14 Source Terminal 14. This pin can be an input or an output.
7 4 S13 Source Terminal 13. This pin can be an input or an output.
8 5 S12 Source Terminal 12. This pin can be an input or an output.
9 6 S11 Source Terminal 11. This pin can be an input or an output.
10 7 S10 Source Terminal 10. This pin can be an input or an output.
11 8 S9 Source Terminal 9. This pin can be an input or an output.
12 9 GND Ground (0 V) Reference.
14 10 A3 Logic Control Input.
15 11 A2 Logic Control Input.
16
14
A1
Logic Control Input.
17 15 A0 Logic Control Input.
18 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned
off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19 17 S1 Source Terminal 1. This pin can be an input or an output.
20 18 S2 Source Terminal 2. This pin can be an input or an output.
21 19 S3 Source Terminal 3. This pin can be an input or an output.
22 20 S4 Source Terminal 4. This pin can be an input or an output.
23 21 S5 Source Terminal 5. This pin can be an input or an output.
24 22 S6 Source Terminal 6. This pin can be an input or an output.
25 23 S7 Source Terminal 7. This pin can be an input or an output.
26 24 S8 Source Terminal 8. This pin can be an input or an output.
27 25 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
28 29 D Drain Terminal. This pin can be an input or an output.
NA Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
10714-003
1
VDD 28 D
2
NC 27 VSS
3
NC 26 S8
4
S16 25 S7
5
S15 24 S6
6
S14 23 S5
7
S13 22 S4
8
S12 21 S3
9
S11 20 S2
10
S10 19 S1
11
S9 18 EN
12
GND 17 A0
13
NC 16 A1
14
A3 15 A2
ADG5206
TOP VI EW
(No t t o Scal e)
NOTES
1. NO CONNECT . NO T I NTERNALLY CONNECTED.
10714-004
1S16 2S15 3S14 4S13 5S12 6S11 7S10 8S9
24 S8
23 S7
22 S6
21 S5
20 S4
19 S3
18 S2
17 S1
9GND 10A3 11A2 12NC 13NC 14A1 15A0 16EN
32 NC
31 VDD
30 NC
29 D
28 NC
27 NC
26 NC
25 VSS
TOP VI EW
(No t t o Scal e)
ADG5206
NOTES
1. NO CONNECT . NO T I NTERNALLY CONNECTED.
2. THE E X P OSED P AD IS CONNECTED INTE RNALL Y . F OR
INCRE AS E D RE LIABIL IT Y OF THE SOL DE R JOI NTS AND
MAXIMUM THERMAL CAPABILI T Y, I T I S RECOMMENDED
THAT THE P AD BE S OL DE RE D TO THE S UBS TRATE , VSS.
Data Sheet ADG5206/ADG5207
Rev. A | Page 13 of 28
Table 9. ADG5206 Truth Table
A3 A2 A1 A0 EN On Switch
X X X X 0 None
0 0 0 0 1 1
0 0 0 1 1 2
0 0 1 0 1 3
0 0 1 1 1 4
0 1 0 0 1 5
0 1 0 1 1 6
0 1 1 0 1 7
0 1 1 1 1 8
1 0 0 0 1 9
1 0 0 1 1 10
1 0 1 0 1 11
1 0 1 1 1 12
1 1 0 0 1 13
1 1 0 1 1 14
1
1
1
0
1
15
1 1 1 1 1 16
ADG5206/ADG5207 Data Sheet
Rev. A | Page 14 of 28
Figure 5. ADG5207 Pin Configuration (TSSOP)
Figure 6. ADG5207 Pin Configuration (LFCSP)
Table 10. ADG5207 Pin Function Descriptions
Pin No.
Mnemonic Description
TSSOP LFCSP
1 29 VDD Most Positive Power Supply Potential.
2 31 DB Drain Terminal B. This pin can be an input or an output.
3, 13,
14
11, 12, 12, 26,
28, 30, 32
NC No Connect. Not internally connected.
4 1 S8B Source Terminal 8B. This pin can be an input or an output.
5 2 S7B Source Terminal 7B. This pin can be an input or an output.
6 3 S6B Source Terminal 6B. This pin can be an input or an output.
7 4 S5B Source Terminal 5B. This pin can be an input or an output.
8 5 S4B Source Terminal 4B. This pin can be an input or an output.
9 6 S3B Source Terminal 3B. This pin can be an input or an output.
10 7 S2B Source Terminal 2B. This pin can be an input or an output.
11 8 S1B Source Terminal 1B. This pin can be an input or an output.
12
9
GND
Ground (0 V) Reference.
15 10 A2 Logic Control Input.
16 14 A1 Logic Control Input.
17 15 A0 Logic Control Input.
18 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned
off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19 17 S1A Source Terminal 1A. This pin can be an input or an output.
20 18 S2A Source Terminal 2A. This pin can be an input or an output.
21 19 S3A Source Terminal 3A. This pin can be an input or an output.
22 20 S4A Source Terminal 4A. This pin can be an input or an output.
23 21 S5A Source Terminal 5A. This pin can be an input or an output.
24
22
S6A
Source Terminal 6A. This pin can be an input or an output.
25 23 S7A Source Terminal 7A. This pin can be an input or an output.
26 24 S8A Source Terminal 8A. This pin can be an input or an output.
27 25 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
28 27 DA Drain Terminal A. This pin can be an input or an output.
NA Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
1
V
DD 28
DA
2
DB
27
V
SS
3
NC
26
S8A
4
S8B
25
S7A
5
S7B
24
S6A
6
S6B
23
S5A
7
S5B
22
S4A
8
S4B
21
S3A
9
S3B
20
S2A
10
S2B
19
S1A
11
S1B
18
EN
12
GND
17
A0
13
NC
16
A1
14
NC
15
A2
ADG5207
TOP VI EW
(No t t o Scal e)
NOTES
1. NO CONNECT . NO T I NTERNALLY CONNECTED.
10714-005
10714-006
1S8B 2S7B 3S6B 4S5B 5S4B 6S3B 7S2B 8S1B
24 S8A
23 S7A
22 S6A
21 S5A
20 S4A
19 S3A
18 S2A
17 S1A
9
GND 10
A2 11
NC 12
NC 13
NC 14
A1 15
A0 16
EN
32 NC
31 DB
30 V
DD
29 NC
28 NC
27 DA
26 NC
25 V
SS
TOP VI EW
(No t t o Scal e)
ADG5207
NOTES
1. NO CONNECT . NO T I NTERNALLY CONNECTED.
2. THE E X P OSED P AD IS CONNECTED INTE RNALL Y . F OR
INCRE AS E D RE LIABIL IT Y OF THE SOL DE R JOI NTS AND
MAXIMUM THERMAL CAPABILI T Y, I T I S RECOMMENDED
THAT THE P AD BE S OL DE RE D TO THE S UBS TRATE , V
SS
.
Data Sheet ADG5206/ADG5207
Rev. A | Page 15 of 28
Table 11. ADG5207 Truth Table
A2 A1 A0 EN On Switch Pair
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
ADG5206/ADG5207 Data Sheet
Rev. A | Page 16 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. RON as a Function of VS, VD (±20 V Dual Supply)
Figure 8. RON as a Function of VS, VD (±15 V Dual Supply)
Figure 9. RON as a Function of VS, VD (12 V Single Supply)
Figure 10. RON as a Function of VS, VD (36 V Single Supply)
Figure 11. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
Figure 12. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
–22.0 5.50–5.5 16.5–16.5 11.0–11.0 22.0
ON RESISTANCE (Ω)
VS, VD (V)
60
70
80
90
100
110
120
130
140 ±18V
±20V
±22V
10714-105
TA = 25° C
–17.00 –8.50–12.75 12.75–4.25 4.2508.50 17.0
ON RESISTANCE (Ω)
V
S
, V
D
(V)
60
70
80
90
100
110
120
130
160
150
140
±13.5V
±15V
±16.5V
10714-106
T
A
= 25° C
0 2 4 6 8 10 12
ON RESISTANCE (Ω)
V
S
, V
D
(V)
60
110
160
210
260
310
360 10.8V
12V
13.2V
10714-107
T
A
= 25° C
ON RESISTANCE (Ω)
V
S
, V
D
(V)
60
70
80
90
100
110
120
130
140
150
10714-108
0 5 10 15 20 25 30 35
32.4V
36V
39.6V
T
A
= 25° C
–15 –10 –5 0 5 10 15
ON RESISTANCE (Ω)
V
S
, V
D
(V)
60
200
180
160
140
120
100
80
+125°C
+85°C
+60°C
+25°C
–40°C
10714-109
V
DD
= +15V
V
SS
= –15V
–20 –15 –10 –5 0 5 10 2015
ON RESISTANCE (Ω)
V
S
, V
D
(V)
60
70
80
90
100
110
120
130
140
150
160 +125°C
+85°C
+60°C
+25°C
–40°C
10714-110
V
DD
= +20V
V
SS
= –20V
Data Sheet ADG5206/ADG5207
Rev. A | Page 17 of 28
Figure 13. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Figure 14. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
Figure 15. Leakage Currents vs. Temperature, ±15 V Dual Supply
Figure 16. Leakage Currents vs. Temperature, ±20 V Dual Supply
Figure 17. Leakage Currents vs. Temperature, 12 V Single Supply
Figure 18. Leakage Currents vs. Temperature, 36 V Single Supply
012108642
ON RESISTANCE (Ω)
V
S
, V
D
(V)
60
410
360
310
260
210
160
110
+125°C
+85°C
+60°C
+25°C
–40°C
10714-111
V
DD
= 12V
V
SS
= 0V
03530252015105
ON RESISTANCE (Ω)
V
S
, V
D
(V)
60
180
160
140
120
100
80
+125°C
+85°C
+60°C
+25°C
–40°C
10714-112
V
DD
= 36V
V
SS
= 0V
012010080604020
LE AKAGE CURRENT (pA)
TEMPERATURE (°C)
–160
–140
–120
–100
–80
–60
–40
–20
0
20
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
, I
D
(ON) + +
I
S
, I
D
(O N) – –
10714-113
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
012010080604020
LE AKAGE CURRENT (pA)
TEMPERATURE (°C)
–300
–250
–200
–150
–100
–50
0
50
100
150
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
, I
D
(ON) + +
I
S
, I
D
(O N) – –
10714-114
V
DD
= +20V
V
SS
= –20V
V
BIAS
= +15V/–15V
012010080604020
LE AKAGE CURRENT (pA)
TEMPERATURE (°C)
–450
–400
–350
–300
–250
–200
–150
–100
–50
0
50
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
IS, ID (ON) + +
IS, ID (O N) – –
10714-115
VDD = 12V
VSS = 0V
VBIAS = 1V /10V
012010080604020
LE AKAGE CURRENT (pA)
TEMPERATURE (°C)
–350
–300
–250
–200
–150
–100
–50
0
50
100
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
, I
D
(ON) + +
I
S
, I
D
(O N) – –
10714-116
V
DD
= 36V
V
SS
= 0V
V
BIAS
= 1V/ 30V
ADG5206/ADG5207 Data Sheet
Rev. A | Page 18 of 28
Figure 19. Off Isolation vs. Frequency, ±15 V Dual Supply
Figure 20. Crosstalk vs. Frequency, ±15 V Dual Supply
Figure 21. Charge Injection vs. Source Voltage, Drain to Source
Figure 22. ACPSRR vs. Frequency, ±15 V Dual Supply
Figure 23. Bandwidth
Figure 24. Charge Injection vs. Source Voltage, Source to Drain
10k 1G100M10M1M100k
OFF ISOLATION (dB)
FRE QUENCY ( Hz )
–140
–120
–100
–80
–60
–40
–20
0
ADG5206 ADG5207
10714-117
TA = 25° C
VDD = + 15V
VSS = –15V
10k 1G100M10M1M100k
CROS S TALK ( dB)
FRE QUENCY ( Hz )
–160
–140
–120
–100
–80
–60
–40
–20
0
10714-118
BET WEEN S 1A AND S 2A
BET WEEN S 16 AND S 1
BET WEEN S 1A AND S 8B
TA = 25° C
VDD = + 15V
VSS = –15V
–20 –10 010 20 30 40
CHARGE INJECT IO N ( pC)
V
S
(V)
0
5
10
15
20
25
30
35
40
45 V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
V
DD
= +12V, V
SS
= 0V
V
DD
= +36V, V
SS
= 0V
10714-119
T
A
= 25° C
DEMUX ( DRAIN TO SOURCE)
1k 10M1M100k10k
ACPSRR ( dB)
FRE QUENCY ( Hz )
–140
–120
–100
–80
–60
–40
–20
0
DECOUPLING
CAPACITORS
NO DE COUPL ING
CAPACITORS
10714-120
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
100k 1G100M10M1M
ATTENUAT IO N ( dB)
FRE QUENCY ( Hz )
–15
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
ADG5206
ADG5207
10714-121
TA = 25° C
VDD = + 15V
VSS = –15V
–20 –10 010 20 30 40
CHARGE INJECT IO N ( pC)
V
S
(V)
–2
–1
0
1
2
3
4
5
6
7
8V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
V
DD
= +12V, V
SS
= 0V
V
DD
= +36V, V
SS
= 0V
10714-122
T
A
= 25° C
MUX ( S OURCE T O DRAI N)
Data Sheet ADG5206/ADG5207
Rev. A | Page 19 of 28
Figure 25. QINJ as a Function of VS for Different Temperatures, ±15 V Dual Supply
Figure 26. QINJ as a Function of VS for Different Temperatures, ±20 V Dual Supply
Figure 27. tTRANSITION Time vs. Temperature
Figure 28. QINJ as a Function of VS for Different Temperatures, 12 V Single Supply
Figure 29. QINJ as a Function of VS for Different Temperatures, 36 V Single Supply
–10 1062–2–6–8 840–4
CHARGE INJECT IO N ( pC)
V
S
(V)
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
10714-200
–40°C
+25°C
+85°C
+125°C
MUX ( S OURCE T O DRAI N)
–15 150–5–10 510
CHARGE INJECT IO N ( pC)
V
S
(V)
–2
–1
0
1
2
3
4
5
6
10714-201
–40°C
+25°C
+85°C
+125°C
MUX ( S OURCE T O DRAI N)
–40 –20 020 40 60 80 100 120
TIME (n s)
TEMPERATURE (°C)
0
450
400
350
300
250
200
150
100
50
V
DD
= +12V, V
SS
= 0V
V
DD
= +36V, V
SS
= 0V
V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
10714-123
010987654321
CHARGE INJECT IO N ( pC)
V
S
(V)
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
10714-202
–40°C
+25°C
+85°C
+125°C
MUX ( S OURCE T O DRAI N)
030252015105
CHARGE INJECT IO N ( pC)
V
S
(V)
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
10714-203
–40°C
+25°C
+85°C
+125°C
MUX ( S OURCE T O DRAI N)
ADG5206/ADG5207 Data Sheet
Rev. A | Page 20 of 28
Figure 30. ADG5206 Capacitance vs. Source Voltage, ±15 V Dual Supply
Figure 31. ADG5207 Capacitance vs. Source Voltage, ±15 V Dual Supply
–15 –10 –5 0 5 10 15
CAPACI TANCE (pF )
V
S
(V)
0
100
80
60
40
20
DRAIN OFF
SO URCE OFF
SO URCE /DRAIN ON
10714-124
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
–15 –10 –5 0 5 10 15
CAPACI TANCE (pF )
V
S
(V)
0
60
50
40
30
20
10
DRAIN OFF
SO URCE OFF
SO URCE /DRAIN ON
10714-125
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
Data Sheet ADG5206/ADG5207
Rev. A | Page 21 of 28
TEST CIRCUITS
Figure 32. On Resistance
Figure 33. Off Leakage
Figure 34. On Leakage
Figure 35. Address to Output Switching Times, tTRANSITION
Figure 36. Enable Delay, tON (EN), tOFF (EN)
10714-300
I
DS
S D
V
S
V
R
ON
= V/I
DS
10714-301
S1 D
A A
S16
A
ID (OFF)
IS (OFF)
VSVD
10714-302
S2
S16
S1 A
D
NC
NC = NO CONNECT
ID (ON)
VDVD
3V
0V
OUTPUT
t
r < 20ns
t
f < 20ns
ADDRESS
DRIVE (V
IN
)
t
TRANSITION
t
TRANSITION
50% 50%
90%
90%
OUTPUT
ADG5206
1
50Ω
300Ω
GND
S1
S2
S3 T O S16
D
35pF
V
IN
3V EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SI M ILAR CONNECTI ON F OR ADG5207.
A0
A2
A1
A3
0V
10714-034
OUTPUT
ADG52061
A0
A1
A2
50Ω 300Ω
GND
S1
S2 T O S16
D
35pF
VIN
EN
VDD VSS
VDD VSS
VS
3V
0V
0V
OUTPUT
50% 50%
tOFF (EN)tON (EN)
0.9VOUT
0.1VOUT
ENABLE
DRIVE (VIN)
1SI M ILAR CONNECTI ON F OR ADG5207.
A3
10714-036
ADG5206/ADG5207 Data Sheet
Rev. A | Page 22 of 28
Figure 37. Break-Before-Make Time Delay, tD
Figure 38. Charge Injection
Figure 39. Off Isolation
Figure 40. Channel-to-Channel Crosstalk
Figure 41. Bandwidth
3V
0V
OUTPUT 80% 80%
ADDRESS
DRIVE (V
IN
)
t
BBM
OUTPUT
ADG5206
1
50Ω
300Ω
GND
S1
S2 T O S15
S16
D
35pF
V
IN
3V EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SI M ILAR CONNECTI ON F OR ADG5207.
A0
A2
A1
A3
10714-035
3V
VIN
VOUT
QINJ = CL × ΔVOUT
ΔVOUT DSx
EN GND CL
1nF
VOUT
VIN
RS
VS
VDD VSS
VDD VSS
A0
A1
A2
A3 ADG52061
1SI M ILAR CONNECTI ON F OR ADG5207.
0V
10714-037
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
OFF ISOLATION = 20 logV
OUT
V
S
10714-032
CHANNEL - TO- CHANNE L CRO S S TAL K = 20 lo g V
OUT
GND
S1
D
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
S
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
10714-030
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
D
INSERTION LOSS = 20 log V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
GND
10714-033
Data Sheet ADG5206/ADG5207
Rev. A | Page 23 of 28
TERMINOLOGY
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
RON
RON is the ohmic resistance between Terminal D and
Terminal S.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
RFLAT (ON) is the flatness defined as the difference between the
maximum and the minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
CIN
CIN represents digital input capacitance.
tON (EN)
tON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
tOFF (EN)
tOFF (EN) represents the delay time between the 50% and 90%
points of the digital input and switch off condition.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
Break-Before-Make Time Delay (tD)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin to
the output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
ADG5206/ADG5207 Data Sheet
Rev. A | Page 24 of 28
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persist until the power supply is turned
off. The ADG5206/ADG5207 high voltage switches allow single-
supply operation from 9 V to 40 V and dual-supply operation
from ±9 V to ±22 V.
TRENCH ISOLATION
In the ADG5206/ADG5207, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed and the result is a latch-
up proof switch.
Figure 42. Trench Isolation
NMOS PMOS
P WELL N WE LL
BURIE D OXIDE LAY E R
HANDLE WAF E R
TRENCH
10714-038
Data Sheet ADG5206/ADG5207
Rev. A | Page 25 of 28
OUTLINE DIMENSIONS
Figure 43. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
Figure 44. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 × 5 mm Body, Very Very Thin Quad (CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG5206BRUZ −40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28
ADG5206BRUZ-RL7 −40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28
ADG5206BCPZ-RL7 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADG5207BRUZ −40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28
ADG5207BRUZ-RL7 −40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28
ADG5207BCPZ-RL7 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
1 Z = RoHS Compliant Part.
COMPLIANT TO JEDEC STANDARDS MO-153-AE
28 15
141
8°
0°
SEATING
PLANE
COPLANARITY
0.10
1.20 MAX
6.40 BSC
0.65
BSC
PIN 1
0.30
0.19 0.20
0.09
4.50
4.40
4.30
0.75
0.60
0.45
9.80
9.70
9.60
0.15
0.05
08-16-2010-B
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR 32
9
16
17
2425
8
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 MIN
*3.75
3.60 SQ
3.55
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
ADG5206/ADG5207 Data Sheet
Rev. A | Page 26 of 28
NOTES
Data Sheet ADG5206/ADG5207
Rev. A | Page 27 of 28
NOTES
ADG5206/ADG5207 Data Sheet
Rev. A | Page 28 of 28
NOTES
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10714-0-5/13(A)