IS41C85120A
IS41LV85120A ISSI®
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
04/22/05
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
512K x 8 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs
• Refresh Interval: 1024 cycles/16 ms
• Refresh Mode : RAS-Only, CAS-before-RAS (CBR),
and Hidden
• JEDEC standard pinout
• Single power supply
5V ± 10% (IS41C85120A)
3.3V ± 10% (IS41LV85120A)
• Lead-free available
DESCRIPTION
The
ISSI
IS41C85120A and IS41LV85120A are 524,288 x 8-
bit high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access EDO
Page Mode. EDO Page Mode allows 512 random accesses
within a single row with access cycle time as short as 10ns per
8-bit word. The Byte Write control, of upper and lower byte,
makes the IS41C85120A and IS41LV85120A ideal for use in
16 and 32-bit wide data bus systems.
These features make the IS41C85120A and IS41LV85120A
ideally
suited for high
band-width
graphics,
digital signal
processing,
high-performance computing systems, and periph-
eral applications.
The IS41C85120A and IS41LV85120A are available in a
28-pin, 400-mil SOJ package.
KEY TIMING PARAMETERS
Parameter -60 Unit
Max. RAS Access Time (tRAC)
60 ns
Max. CAS Access Time (tCAC)
15 ns
Max. Column Address Access Time (tAA)
30 ns
Min. Fast Page Mode Cycle Time (tPC)
40 ns
Min. Read/Write Cycle Time (tRC)
110 ns
PIN DESCRIPTIONS
A0-A9 Address Inputs
I/O0-I/O7 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
CAS Column Address Strobe
VCC Power
GND Ground
NC No Connection
PIN CONFIGURATION
28-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
NC
A8
A7
A6
A5
A4
GND
APRIL 2005
IS41C85120A
IS41LV85120A ISSI
®
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
FUNCTIONAL BLOCK DIAGRAM
O
E
WE
CAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
524,288 x 8
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O7
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
04/22/05
TRUTH TABLE
Function RASRAS
RASRAS
RAS CASCAS
CASCAS
CAS WEWE
WEWE
WE OEOE
OEOE
OE Address tR/tCI/O
Standby H H X X X High-Z
Read: Word L L H L ROW/COL DOUT
Read: Lower Byte L L H L ROW/COL Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte L H H L ROW/COL Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write) L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L L X ROW/COL Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L X ROW/COL Lower Byte, High-Z
Upper Byte, DIN
Read-Write
(1,2)
LLH→LL→H ROW/COL DOUT, DIN
EDO Page-Mode Read
(2)
1st Cycle: L H→L H L ROW/COL
DOUT 2nd Cycle: L H→L H L NA/COL DOUT
Any Cycle: L L→H H L NA/NA DOUT
EDO Page-Mode Write
(1)
1st Cycle: L H→L L X ROW/COL DIN
2nd Cycle: L H→L L X NA/COL DIN
EDO Page-Mode 1st Cycle: L H→LH→LL→H ROW/COL
DOUT, DIN
Read-Write
(1,2)
2nd Cycle: L H→LH→LL→H NA/COL DOUT, DIN
Hidden Refresh
2)
Read L→H→L L H L ROW/COL
DOUT Write L→H→L L L X ROW/COL
DOUT
RAS-Only Refresh L H X X ROW/NA High-Z
CBR Refresh
(3)
H→L L X X X High-Z
Notes:
1 . These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2 . These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3 . At least one of the two CAS signals must be active (LCAS or UCAS).
IS41C85120A
IS41LV85120A ISSI
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
Functional Description
The IS41C85120A and IS41LV85120A is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 19 address bits. The first ten
address bits (A0-A9) are entered as row address and
latter nine bits nine address bits (A0-A8) are entered as
column address. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter nine bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci-
fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ig-
nored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
04/22/05
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
VTVoltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
3.3V -0.5 to 4.6 V
VCC Supply Voltage 5V –1.0 to +7.0 V
3.3V -0.5 to 4.6 V
IOUT Output Current 50 mA
PDPower Dissipation 1 W
TACommercial Operation Temperature 0 to +70 °C
TSTG Storage Temperature –55 to +125 ° C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
CIN1Input Capacitance: A0-A9 5 pF
CIN2Input Capacitance: RAS, CAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O7 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz,
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
3.3V 2.0 — VCC + 0.3
VIL Input Low Voltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
TACommercial Ambient Temperature 0 — 70 °C
IS41C85120A
IS41LV85120A ISSI
®
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –10 10 µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA
0V ≤ VOUT ≤ Vcc
VOH Output High Voltage Level IOH = –2 mA 2.4 — V
VOL Output Low Voltage Level IOL = +2 mA — 0.4 V
ICC1Stand-by Current: TTL RAS, CAS ≥ VIH Commercial 5V — 2 mA
ICC1Stand-by Current: TTL RAS, CAS ≥ VIH Commercial 3V — 2 mA
ICC2Stand-by Current: CMOS RAS, CAS ≥ VCC – 0.2V 5V — 2 mA
3V — 2
ICC3Operating Current: RAS, CAS, -60 — 170 mA
Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4Operating Current: RAS = VIL, CAS, -60 — 170 mA
EDO Page Mode(2,3,4) Cycling tPC = tPC (min.)
Average Power Supply Current
ICC5Refresh Current: RAS Cycling, CAS ≥ VIH -60 — 170 mA
RAS-Only(2,3) tRC = tRC (min.)
Average Power Supply Current
ICC6Refresh Current: RAS, CAS Cycling -6 0 — 17 0 mA
CBR(2,3,5) tRC = tRC (min.)
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
04/22/05
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-60
Symbol Parameter Min. Max. Units
tRC Random READ or WRITE Cycle Time 1 10 — ns
tRAC Access Time from RAS(6, 7) 60 — ns
tCAC Access Time from CAS(6, 8, 15) —15 ns
tAA Access Time from Column-Address(6) —30 ns
tRAS RAS Pulse Width 6 0 10 K ns
tRP RAS Precharge Time 40 — ns
tCAS CAS Pulse Width(26) 10 10K ns
tCP CAS Precharge Time(9, 25) 10 — ns
tCSH CAS Hold Time (21) 60 — ns
tRCD RAS to CAS Delay Time(10, 20) 20 45 ns
tASR Row-Address Setup Time 0 — ns
tRAH Row-Address Hold Time 10 — ns
tASC Column-Address Setup Time(20) 0— ns
tCAH Column-Address Hold Time(20) 10 — ns
tAR Column-Address Hold Time 40 — ns
(referenced to RAS)
tRAD RAS to Column-Address Delay Time(11) 15 30 ns
tRAL Column-Address to RAS Lead Time 3 0 — ns
tRPC RAS to CAS Precharge Time 5 — ns
tRSH RAS Hold Time(27) 15 10K ns
tCLZ CAS to Output in Low-Z(15, 29) 0— ns
tCRP CAS to RAS Precharge Time(21) 5— ns
tOD Output Disable Time(19, 28, 29) 312 ns
tOE / tOEA Output Enable Time(15, 16) —15 ns
tOEHC OE HIGH Hold Time from CAS HIGH 1 5 — ns
tOEP OE HIGH Pulse Width 1 0 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — ns
tRCS Read Command Setup Time(17, 20) 0— ns
tRRH Read Command Hold Time 0 — ns
(referenced to RAS)(12)
tRCH Read Command Hold Time 0 — ns
(referenced to CAS)(12, 17, 21)
tWCH Write Command Hold Time(17, 27) 10 — ns
tWCR Write Command Hold Time 50 — ns
(referenced to RAS)(17)
IS41C85120A
IS41LV85120A ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-60
Symbol Parameter Min. Max. Units
tWP Write Command Pulse Width(17) 10 — ns
tWPZ WE Pulse Widths to Disable Outputs 10 — ns
tRWL Write Command to RAS Lead Time(17) 15 — ns
tCWL Write Command to CAS Lead Time(17, 21) 15 — ns
tWCS Write Command Setup Time(14, 17, 20) 0— ns
tDHR Data-in Hold Time (referenced to RAS)40—ns
Precharge during WRITE Cycle
tOEH OE Hold Time from WE during 1 5 — ns
READ-MODIFY-WRITE cycle(18)
tDS Data-In Setup Time(15, 22) 0— ns
tDH Data-In Hold Time(15, 22) 15 — ns
tRWC READ-MODIFY-WRITE Cycle Time 155 — ns
tRWD RAS to WE Delay Time during 8 5 — ns
READ-MODIFY-WRITE Cycle(14)
tCWD CAS to WE Delay Time(14, 20) 40 — ns
tAWD Column-Address to WE Delay Time(14) 55 — ns
tPC EDO Page Mode READ or WRITE 4 0 — ns
Cycle Time(24)
tRASP RAS Pulse Width in EDO Page Mode 6 0 100K ns
tCPA Access Time from CAS Precharge(15) —35 ns
tPRWC EDO Page Mode READ-WRITE 56 — ns
Cycle Time(24)
tCOH/tDOH Data Output Hold after CAS LOW 5 — ns
tOFF Output Buffer Turn-Off Delay from 3 1 5 ns
CAS or RAS(13,15,19, 29)
tWHZ Output Disable Delay from WE 315 ns
tCLCH Last CAS going LOW to First CAS 10 — ns
returning HIGH(23)
tCSR CAS Setup Time (CBR REFRESH)(30, 20) 5— ns
tCHR CAS Hold Time (CBR REFRESH)(30, 21) 10 — ns
tORD OE Setup Time prior to RAS during 0 — ns
HIDDEN REFRESH Cycle
tREF Refresh Period (1024 Cycles) — 16 ms
tTTransition Time (Rise or Fall)(2, 3) 350 ns
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
04/22/05
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and V IL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear
the data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
IS41C85120A
IS41LV85120A ISSI
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
AC WAVEFORMS
READ CYCLE
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS tRC tRP
tAR
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC tOFF
(1)
tRAC
tCLC
tOES
tOE tOD
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. B
04/22/05
EARLY WRITE CYCLE (OEOE
OEOE
OE = DON'T CARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
CAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid DOUT Valid DIN
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. B
04/22/05
EDO-PAGE-MODE READ CYCLE
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
t
RASP
t
RP
ADDRESS
CAS
RAS
Row Row
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
(1)
t
ASR
t
RAH
t
RAD
t
AR
Column Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Open Ope
n
Valid Data
t
AA
t
AA
t
CPA
t
CAC
t
CAC
t
RAC
t
COH
t
CLZ
t
OEP
t
OE
t
OES
t
OES
t
OD
t
OE
t
OEHC
Valid Data
t
RCH
t
RRH
t
AA
t
CPA
t
CAC
t
OFF
t
CLZ
Valid Data
t
OD
t
ASC
t
RCS
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
ADDRESS
CAS
RAS
Row Row
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
t
ASR
t
RAH
t
RAD
t
AR
t
ACH
Column Column
t
ACH
t
ACH
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Valid Data
t
ASC
t
WCS
t
WCH
t
CWL
t
WP
t
WCS
t
WCH
t
CWL
t
WP
t
DS
t
DH
t
DHR
t
WCR
t
WCS
t
WCH
t
CWL
t
WP
Valid Data
t
DS
t
DH
Valid Data
t
DS
t
RWL
t
DH
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. B
04/22/05
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE an d READ-MODIFY WRITE Cycles)
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
t
RASP
t
RP
ADDRESS
CAS
RAS
Row Row
t
CRP
t
RCD
t
CSH
t
CP
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
RAH
t
RAD
t
AR
t
ASR
Column Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
t
CAS,
t
CLCH
t
CAS,
t
CLCH
OE
I/O
WE
t
ASC
t
RWD
t
RCS
t
CWL
t
WP
t
AWD
t
CWD
t
DH
t
DS
t
CAC
t
CLZ
t
AWD
t
CWD
t
CWL
t
WP
t
AWD
t
CWD
t
CWL
t
RWL
t
WP
Open Open
D
IN
D
OUT
t
OE
t
OE
t
OE
t
OD
t
OEH
t
OD
t
OD
t
DH
t
DS
t
CPA
t
AA
t
CAC
t
CLZ
D
IN
D
OUT
t
DH
t
DS
t
CAC
t
CLZ
D
IN
D
OUT
t
CPA
t
AA
t
RAC
t
AA
t
PC
/ t
PRWC
(1)
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASP tRP
ADDRESS
CAS
RAS
Row Row
tCRP tRCD
tPC
tCSH
tCP
tCAH
tCAS
tRAL
tRSH tCPtCP
tACH
tRAH
tRAD
tAR
tASR
Column (A) Column (N)
tCAHtCAH
Column (B)
tASCtASC
tCAS tCAS
OE
I/O
WE
tASC
tCAC
tRCH
tDH
Open Open
Valid Data (A)
tOE
tWCS
tCAC
tCOH
D
IN
tCPA
tWCH
tRAC tAA
tPC
Valid Data (B)
tWHZ
tDS
tRCS
tAA
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
Rev. B
04/22/05
READ CYCLE (With WEWE
WEWE
WE-Controlled Disable)
RASRAS
RASRAS
RAS-ONLY REFRESH CYCLE (OEOE
OEOE
OE, WEWE
WEWE
WE = DON'T CARE)
t
AR
t
CAH
t
ASC
t
ASC
t
RAD
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column
Open Open
Valid Data
t
CSH
t
CAS
t
CRP
t
RCD
t
CP
t
RAH
t
ASR
t
RCH
t
RCS
t
RCS
t
AA
t
CAC
t
WHZ
t
RAC
t
CLZ
t
CLZ
t
OE
t
OD
Column
tRAS tRC tRP
I/O
ADDRESS
CAS
RAS
Row Row
Open
tCRP
tRAHtASR
tRPC
Don't Care
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
HIDDEN REFRESH CYCLE (WEWE
WEWE
WE = HIGH; OEOE
OEOE
OE = LOW)(1)
CBRCBR
CBRCBR
CBR REFRESH CYCLE (Addresses; WEWE
WEWE
WE, OEOE
OEOE
OE = DON'T CARE)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS tRAStRP tRP
I/O
C
AS
R
AS
Open
tCP
tRPC tCSR
tCHR tRPC tCSR tCHR
tRAS tRAS
tRP
CAS
RAS
tCRP tRCD tRSH tCHR
tAR
tASC
tRAD
ADDRESS Row Column
tRAHtASR tRAL tCAH
I/O Open Open
Valid Data
tAA
tCAC
tRAC
tCLZ tOFF
(2)
OE
tOE tORD tOD
Don't Care
IS41C85120A
IS41LV85120A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
19
Rev. B
04/22/05
ORDERING INFORMATION : 5V
Commercial Range: 0oC to 70oC
Speed (ns) Order Part No. Package
60 IS41C85120A-60K 400-mil SOJ
ORDERING INFORMATION : 3.3V
Commercial Range: 0oC to 70oC
Speed (ns) Order Part No. Package
60 IS41LV85120A-60K 400-mil SOJ
IS41LV85120A-60KL 400-mil SOJ, Lead-free
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
400-mil Plastic SOJ
Package Code: K
Notes:
1. Controlling dimension:
millimeters.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
SEATING PLANE
1
N
E1
D
E2
E
B
eA1
A
C
A2
b
N/2+1
N/2
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 28 32 36
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
PA CKA GING INFORMATION ISSI
®
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 40 42 44
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
