IS41C85120A IS41LV85120A ISSI 512K x 8 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE (R) APRIL 2005 FEATURES DESCRIPTION * TTL compatible inputs and outputs * Refresh Interval: 1024 cycles/16 ms * Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden * JEDEC standard pinout * Single power supply 5V 10% (IS41C85120A) 3.3V 10% (IS41LV85120A) The ISSI IS41C85120A and IS41LV85120A are 524,288 x 8bit high-performance CMOS Dynamic Random Access Memory. Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 8-bit word. The Byte Write control, of upper and lower byte, makes the IS41C85120A and IS41LV85120A ideal for use in 16 and 32-bit wide data bus systems. * Lead-free available These features make the IS41C85120A and IS41LV85120A ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C85120A and IS41LV85120A are available in a 28-pin, 400-mil SOJ package. KEY TIMING PARAMETERS Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -60 60 15 30 40 110 Unit ns ns ns ns ns PIN DESCRIPTIONS PIN CONFIGURATION 28-Pin SOJ VCC 1 28 GND I/O0 2 27 I/O7 I/O1 3 26 I/O6 I/O2 4 25 I/O5 I/O3 5 24 I/O4 NC 6 23 CAS WE 7 22 OE RAS 8 21 NC A0-A9 Address Inputs I/O0-I/O7 Data Inputs/Outputs A9 9 20 A8 WE Write Enable A0 10 19 A7 OE Output Enable A1 11 18 A6 RAS Row Address Strobe A2 12 17 A5 CAS Column Address Strobe A3 13 16 A4 VCC Power VCC 14 15 GND GND Ground NC No Connection Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 1 IS41C85120A IS41LV85120A ISSI (R) FUNCTIONAL BLOCK DIAGRAM OE WE CAS CLOCK GENERATOR RAS RAS CLOCK GENERATOR WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE CAS RAS DATA I/O BUS SENSE AMPLIFIERS ADDRESS BUFFERS A0-A9 2 ROW DECODER REFRESH COUNTER DATA I/O BUFFERS COLUMN DECODERS I/O0-I/O7 MEMORY ARRAY 524,288 x 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) TRUTH TABLE Function RAS CAS WE Standby H H X X X Read: Word L L H L ROW/COL D OUT Read: Lower Byte L L H L ROW/COL Lower Byte, DOUT Upper Byte, High-Z Read: Upper Byte L H H L ROW/COL Lower Byte, High-Z Upper Byte, DOUT Write: Word (Early Write) L L L X ROW/COL D IN Write: Lower Byte (Early Write) L L L X ROW/COL Lower Byte, DIN Upper Byte, High-Z Write: Upper Byte (Early Write) L H L X ROW/COL Lower Byte, High-Z Upper Byte, DIN Read-Write (1,2) L L HL LH ROW/COL DOUT, DIN 1st Cycle: L HL H L ROW/COL 2nd Cycle: Any Cycle: L L HL LH H H L L NA/COL D OUT NA/NA D OUT EDO Page-Mode Write(1) 1st Cycle: 2nd Cycle: L L HL HL L L X X ROW/COL NA/COL D IN EDO Page-Mode DOUT, DIN Read-Write (1,2) 1st Cycle: L HL HL LH ROW/COL 2nd Cycle: L HL HL LH NA/COL DOUT, DIN Read LHL L H L ROW/COL Write LHL L L X ROW/COL L H X X ROW/NA High-Z HL L X X X High-Z EDO Page-Mode Read(2) D OUT Hidden Refresh D OUT 2) OE Address tR/tC I/O High-Z D IN D OUT RAS-Only Refresh CBR Refresh(3) Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS). Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 3 IS41C85120A IS41LV85120A Functional Description The IS41C85120A and IS41LV85120A is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 19 address bits. The first ten address bits (A0-A9) are entered as row address and latter nine bits nine address bits (A0-A8) are entered as column address. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter nine bits. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. ISSI (R) CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Extended Data Out Page Mode EDO page mode operation permits all 512 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle's falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Refresh Cycle To retain data, 1024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ignored. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters VT Voltage on Any Pin Relative to GND VCC Supply Voltage IOUT PD TA TSTG Output Current Power Dissipation Commercial Operation Temperature Storage Temperature 5V 3.3V 5V 3.3V Rating Unit -1.0 to +7.0 -0.5 to 4.6 -1.0 to +7.0 -0.5 to 4.6 50 1 0 to +70 -55 to +125 V V V V mA W C C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter VCC Supply Voltage VIH Input High Voltage VIL Input Low Voltage TA Commercial Ambient Temperature 5V 3.3V 5V 3.3V 5V 3.3V Min. Typ. Max. Unit 4.5 3.0 2.4 2.0 -1.0 -0.3 0 5.0 3.3 -- -- -- -- -- 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 V V V C CAPACITANCE(1,2) Symbol Parameter CIN1 CIN2 CIO Input Capacitance: A0-A9 Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O7 Max. Unit 5 7 7 pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 5 IS41C85120A IS41LV85120A ISSI (R) ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Max. Unit IIL Input Leakage Current Any input 0V VIN Vcc Other inputs not under test = 0V -10 10 A IIO Output Leakage Current Output is disabled (Hi-Z) 0V VOUT Vcc -10 10 A VOH Output High Voltage Level IOH = -2 mA 2.4 -- V VOL Output Low Voltage Level IOL = +2 mA -- 0.4 V ICC1 Stand-by Current: TTL RAS, CAS VIH Commercial 5V -- 2 mA ICC1 Stand-by Current: TTL RAS, CAS VIH Commercial 3V -- 2 mA ICC2 Stand-by Current: CMOS RAS, CAS VCC - 0.2V 5V 3V -- -- 2 2 mA ICC3 Operating Current: Random Read/Write(2,3,4) Average Power Supply Current RAS, CAS, Address Cycling, tRC = tRC (min.) -60 -- 170 mA ICC4 Operating Current: EDO Page Mode(2,3,4) Average Power Supply Current RAS = VIL, CAS, Cycling tPC = tPC (min.) -60 -- 170 mA ICC5 Refresh Current: RAS-Only(2,3) Average Power Supply Current RAS Cycling, CAS VIH tRC = tRC (min.) -60 -- 170 mA ICC6 Refresh Current: CBR(2,3,5) Average Power Supply Current RAS, CAS Cycling tRC = tRC (min.) -60 -- 170 mA Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -60 Symbol Parameter Min. Max. Units tRC Random READ or WRITE Cycle Time 110 -- ns tRAC Access Time from RAS(6, 7) 60 -- ns tCAC Access Time from CAS -- 15 ns (6, 8, 15) (6) tAA Access Time from Column-Address -- 30 ns tRAS RAS Pulse Width 60 10K ns tRP RAS Precharge Time 40 -- ns tCAS CAS Pulse Width 10 10K ns tCP CAS Precharge Time 10 -- ns tCSH CAS Hold Time (21) 60 -- ns tRCD RAS to CAS Delay Time 20 45 ns tASR Row-Address Setup Time 0 -- ns tRAH Row-Address Hold Time 10 -- ns tASC Column-Address Setup Time(20) 0 -- ns tCAH Column-Address Hold Time(20) 10 -- ns tAR Column-Address Hold Time (referenced to RAS) 40 -- ns tRAD RAS to Column-Address Delay Time(11) 15 30 ns tRAL Column-Address to RAS Lead Time 30 -- ns tRPC RAS to CAS Precharge Time 5 -- ns tRSH RAS Hold Time 15 10K ns tCLZ CAS to Output in Low-Z 0 -- ns tCRP CAS to RAS Precharge Time(21) 5 -- ns 3 12 ns -- 15 ns tOD (26) (9, 25) (10, 20) (27) (15, 29) (19, 28, 29) Output Disable Time (15, 16) tOE / tOEA Output Enable Time tOEHC OE HIGH Hold Time from CAS HIGH 15 -- ns tOEP OE HIGH Pulse Width 10 -- ns tOES OE LOW to CAS HIGH Setup Time 5 -- ns (17, 20) tRCS Read Command Setup Time 0 -- ns tRRH Read Command Hold Time (referenced to RAS)(12) 0 -- ns tRCH Read Command Hold Time (referenced to CAS)(12, 17, 21) 0 -- ns tWCH Write Command Hold Time(17, 27) 10 -- ns tWCR Write Command Hold Time (referenced to RAS)(17) 50 -- ns Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 7 IS41C85120A IS41LV85120A ISSI (R) AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -60 Symbol (17) Min. Max. Units 10 -- ns tWP Write Command Pulse Width tWPZ WE Pulse Widths to Disable Outputs 10 -- ns tRWL Write Command to RAS Lead Time(17) 15 -- ns tCWL Write Command to CAS Lead Time(17, 21) 15 -- ns 0 -- ns (14, 17, 20) tWCS Write Command Setup Time tDHR Data-in Hold Time (referenced to RAS) Precharge during WRITE Cycle 40 -- ns tOEH OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) 15 -- ns tDS Data-In Setup Time(15, 22) 0 -- ns (15, 22) tDH Data-In Hold Time 15 -- ns tRWC READ-MODIFY-WRITE Cycle Time 155 -- ns tRWD RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) 85 -- ns tCWD CAS to WE Delay Time(14, 20) 40 -- ns tAWD Column-Address to WE Delay Time 55 -- ns tPC EDO Page Mode READ or WRITE Cycle Time(24) 40 -- ns tRASP RAS Pulse Width in EDO Page Mode 60 100K ns tCPA Access Time from CAS Precharge(15) -- 35 ns tPRWC EDO Page Mode READ-WRITE Cycle Time(24) 56 -- ns tCOH/tDOH Data Output Hold after CAS LOW 5 -- ns tOFF Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) 3 15 ns tWHZ Output Disable Delay from WE 3 15 ns tCLCH Last CAS going LOW to First CAS returning HIGH(23) 10 -- ns tCSR CAS Setup Time (CBR REFRESH)(30, 20) 5 -- ns tCHR CAS Hold Time (CBR REFRESH)(30, 21) 10 -- ns tORD OE Setup Time prior to RAS during HIDDEN REFRESH Cycle 0 -- ns tREF Refresh Period (1024 Cycles) -- 16 ms 3 50 ns tT 8 Parameter (2, 3) Transition Time (Rise or Fall) (14) Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first CAS edge to transition LOW. 21. The last CAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling CAS edge to first rising CAS edge. 24. Last rising CAS edge to next cycle's last rising CAS edge. 25. Last rising CAS edge to first falling CAS edge. 26. Each CAS must meet minimum pulse width. 27. Last CAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 9 IS41C85120A IS41LV85120A ISSI (R) AC WAVEFORMS READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don't Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 10 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) OE = DON'T CARE) EARLY WRITE CYCLE (OE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don't Care Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 11 IS41C85120A IS41LV85120A ISSI (R) READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tRAH tASR tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tAWD tRCS tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don't Care 12 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) EDO-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tPC(1) tCAS, tCP tCLCH tRSH tCP tCAS, tCLCH tCP CAS tAR tRAD tASR ADDRESS tASC tCAH tASC Row Column tRAL tCAH tCAH tASC Column Column Row tRAH tRRH tRCS tRCH WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tCAC tCOH Valid Data tOE tOES tAA tCPA tCAC tCLZ tOFF Valid Data tOEHC Valid Data Open tOE tOD tOES tOD OE tOEP Don't Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 13 IS41C85120A IS41LV85120A ISSI (R) EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tCAS, tCLCH tRCD tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP CAS tAR tACH tCAH tASC tRAD tASR ADDRESS tASC Row Column tRAH tACH tRAL tCAH tACH tCAH tASC Column tCWL Column tCWL tWCS tWCS tWCH tWP Row tCWL tWCS tWCH tWCH tWP tWP WE tWCR tDHR tRWL tDS tDS tDH I/O Valid Data tDS tDH tDH Valid Data Valid Data OE Don't Care 14 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC / tPRWC(1) tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP CAS tASR tRAH ADDRESS tAR tRAD tASC tCAH Row tASC tCAH Column tRWD tRCS tRAL tCAH tASC Column tCWL tWP Column tRWL tCWL tWP tCWL tWP tAWD tCWD Row tAWD tCWD tAWD tCWD WE tAA tAA tCPA tDH tDS tRAC tCAC tCLZ I/O Open tAA tCPA tDH tDS tCAC tCLZ DOUT DIN DOUT tOD tOE DIN DOUT tOD tOE tDH tDS tCAC tCLZ Open DIN tOD tOE tOEH OE Don't Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 15 IS41C85120A IS41LV85120A ISSI (R) EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE) tRASP tRP RAS tCSH tPC tPC tCRP tCAS tRCD tCAS tCP tRSH tCAS tCP tCP CAS tASR tRAH ADDRESS tAR tRAD tASC Row tCAH tASC tCAH Column (A) tASC Column (B) tRCS tACH tRAL tCAH Column (N) Row tRCH tWCS tWCH WE tAA tRAC tCAC tCPA tCAC tAA tWHZ tCOH I/O Open Valid Data (A) tDS Valid Data (B) tDH DIN Open tOE OE Don't Care 16 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) READ CYCLE (With WE WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS CAS tAR tRAD tRAH tASR ADDRESS tCAH tASC Row tASC Column Column tRCS tRCH tRCS WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Don't Care RAS OE RAS-ONLY REFRESH CYCLE (OE OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS tASR ADDRESS tRAH Row I/O Row Open Don't Care Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 17 IS41C85120A IS41LV85120A ISSI (R) CBR REFRESH CYCLE (Addresses; WE WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tRPC tCP tCHR tCHR tRPC tCSR tCSR CAS Open I/O WE = HIGH; OE = LOW)(1) HIDDEN REFRESH CYCLE (WE tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR CAS tAR tRAD tRAH tASC tASR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Don't Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 18 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 IS41C85120A IS41LV85120A ISSI (R) ORDERING INFORMATION : 5V Commercial Range: 0oC to 70oC Speed (ns) 60 Order Part No. Package IS41C85120A-60K 400-mil SOJ ORDERING INFORMATION : 3.3V Commercial Range: 0oC to 70oC Speed (ns) 60 Order Part No. Package IS41LV85120A-60K IS41LV85120A-60KL 400-mil SOJ 400-mil SOJ, Lead-free Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 04/22/05 19 ISSI PACKAGING INFORMATION (R) 400-mil Plastic SOJ Package Code: K N Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027. N/2+1 E1 1 E N/2 SEATING PLANE D b A C A2 e Symbol No. Leads A A1 A2 B b C D E E1 E2 e B Millimeters Inches Min Max Min Max (N) 28 3.25 3.75 0.128 0.148 0.64 -- 0.025 -- 2.08 -- 0.082 -- 0.38 0.51 0.015 0.020 0.66 0.81 0.026 0.032 0.18 0.33 0.007 0.013 18.29 18.54 0.720 0.730 11.05 11.30 0.435 0.445 10.03 10.29 0.395 0.405 9.40 BSC 0.370 BSC 1.27 BSC 0.050 BSC A1 E2 Millimeters Min Max Inches Min Max Millimeters Min Max 32 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 20.82 21.08 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 0.820 0.830 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 23.37 23.62 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 36 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 0.920 0.930 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. F 10/29/03 ISSI PACKAGING INFORMATION Millimeters Inches Symbol Min Max Min Max No. Leads (N) 40 A 3.25 3.75 0.128 0.148 A1 0.64 -- 0.025 -- A2 2.08 -- 0.082 -- B 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 E 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC Millimeters Min Max Inches Min Max Millimeters Min Max 42 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 27.18 27.43 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 1.070 1.080 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 28.45 28.70 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC (R) Inches Min Max 44 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. F 10/29/03