IS61LP12832 IS61LP12836 ISSI (R) 128K x 32, 128K x 36 SYNCHRONOUS PIPELINED STATIC RAM FEATURES * Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Common data inputs and data outputs * JEDEC 100-Pin TQFP and 119-pin PBGA package * Single +3.3V, +10%, -5% power supply * Power-down snooze mode * 2.5V I/O supply voltage * Industrial temperature available PRELIMINARY INFORMATION SEPTEMBER 2001 DESCRIPTION The ISSI IS61LP12832 and IS61LP12836 is a high-speed synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. It is organized as 131,072 words by 32 bits and 36 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ t KC Parameter Clock Access Time Cycle Time Frequency -200 3.1 5 200 -166 3.5 6 166 -133 4 7.5 133 Units ns ns MHz This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B 1 IS61LP12832 IS61LP12836 ISSI (R) BLOCK DIAGRAM MODE Q0 CLK CLK A0' A0 BINARY COUNTER ADSC ADSP A16-A0 Q1 CE ADV A1' A1 128K x 32/128K x 36 MEMORY ARRAY CLR 17 D Q 15 17 ADDRESS REGISTER CE CLK 32 or 36 GW BWE BW4 D 32 or 36 Q DQd BYTE WRITE REGISTERS CLK BW3 D DQc Q BYTE WRITE REGISTERS CLK D BW2 Q DQb BYTE WRITE REGISTERS CLK BW1 D DQa Q BYTE WRITE REGISTERS CLK CE CE2 CE2 4 D Q ENABLE REGISTER INPUT REGISTERS CLK 32 or 36 OUTPUT REGISTERS CLK OE DQ[31:0] or DQ[35:0] CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 09/25/01 IS61LP12832 IS61LP12836 ISSI (R) PIN CONFIGURATION 100-Pin TQFP 1 2 3 4 5 6 7 VCCQ A6 A4 ADSP A8 A16 VCCQ NC CE2 A3 ADSC A9 CE2 NC NC A7 A2 VCC A12 A15 NC DQc1 NC GND NC GND NC DQb8 DQc2 DQc3 GND CE GND DQb6 DQb7 VCCQ DQc4 GND OE GND DQb5 VCCQ DQc5 DQc6 BW3 ADV BW2 DQb4 DQb3 DQc7 DQc8 GND GW GND DQb2 DQb1 VCCQ VCC NC VCC NC VCC VCCQ DQd1 DQd2 GND CLK GND DQa7 DQa8 DQd4 DQd3 BW4 NC BW1 DQa5 DQa6 VCCQ DQd5 GND BWE GND DQa4 VCCQ DQd6 DQd7 GND A1 GND DQa3 DQa2 DQd8 NC GND A0 GND NC DQa1 NC A5 MODE VCC NC A13 NC NC NC A10 A11 A14 NC ZZ VCCQ NC NC NC NC NC VCCQ A B A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 119-pin PBGA (Top View) NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC C D E F G H J K L M N P R T 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 U 128K x 32 PIN DESCRIPTIONS A0, A1 A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B GW CE, CE2, CE2 OE DQa-DQd MODE VCC GND Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground VCCQ ZZ Isolated Output Buffer Supply: 2.5V Snooze Enable 3 IS61LP12832 IS61LP12836 ISSI (R) PIN CONFIGURATION 100-Pin TQFP 1 2 3 4 5 6 7 VCCQ A6 A4 ADSP A8 A16 VCCQ NC CE2 A3 ADSC A9 CE2 NC NC A7 A2 VCC A12 A15 NC DQc1 DQPc GND NC GND DQPb DQb8 DQc2 DQc3 GND CE GND DQb6 DQb7 VCCQ DQc4 GND OE GND DQb5 VCCQ DQc5 DQc6 BW3 ADV BW2 DQb4 DQb3 DQc7 DQc8 GND GW GND DQb2 DQb1 VCCQ VCC NC VCC NC VCC VCCQ DQd1 DQd2 GND CLK GND DQa7 DQa8 DQd4 DQd3 BW4 NC BW1 DQa5 DQa6 VCCQ DQd5 GND BWE GND DQa4 VCCQ DQd6 DQd7 GND A1 GND DQa3 DQa2 DQd8 DQPd GND A0 GND DQPa DQa1 NC A5 MODE VCC NC A13 NC NC NC A10 A11 A14 NC ZZ VCCQ NC NC NC NC NC VCCQ A B A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 119-pin PBGA (Top View) DQPc DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd C D E F G H J K L M N P R T DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 U 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 128K x 36 PIN DESCRIPTIONS A0, A1 A2-A16 CLK ADSP ADSC ADV BW1-BW4 BWE 4 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VCC GND Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground VCCQ ZZ DQPa-DQPd Isolated Output Buffer Supply: 2.5V Snooze Enable Parity Data I/O Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 09/25/01 IS61LP12832 IS61LP12836 ISSI (R) TRUTH TABLE Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L X X L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP X L L H H L H H H H X X H X H H X X H X ADSC L X X L L X L L H H H H H H H H H H H H ADV X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X Read Write Read Read Read Read Write Write Read Read Read Read Write Write OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D ZZ L L L L L L L L L L L L L L L L L L L L -- X X X X X X X X High-Z H Snooze Mode PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B BW3 X H H L X BW4 X H H L X 5 IS61LP12832 IS61LP12836 ISSI (R) INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GND) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG Parameter Temperature Under Bias Storage Temperature PD IOUT VIN, VOUT VIN Power Dissipation 1.6 Output Current (per I/O) 100 Voltage Relative to GND for I/O Pins -0.5 to VCCQ + 0.5 Voltage Relative to GND for -0.5 to VCC + 0.5 for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND -0.5 to 4.6 VCC Value -40 to +85 -55 to +150 Unit C C W mA V V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 09/25/01 IS61LP12832 IS61LP12836 ISSI (R) OPERATING RANGE Range Ambient Temperature VCC VCCQ 0C to +70C -40C to +85C 3.3V, +10%, -5% 3.3V, +10%, -5% 2.5V 5% 2.5V 5% Commercial Industrial POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol ICC Parameter AC Operating Supply Current ISB Standby Current TTL IZZ Power-down Mode Current Test Conditions Device Selected, Com. All Inputs = VIL or VIH Ind. OE = VIH, Vcc = Max. Cycle Time tKC min. Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time tKC min. ZZ = VCC Com. Clock Running Ind. All Inputs GND + 0.2V or Vcc - 0.2V -200 Max. 300 310 -166 Max. 290 300 -133 Max. 230 240 Unit mA mA 70 80 70 80 70 80 mA mA 15 20 15 20 15 20 mA mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC. 2. The MODE pin could be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to GND + 0.2V or Vcc - 0.2V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = -1.0 mA 2.0 -- V VOL Output LOW Voltage IOL = 1.0 mA -- 0.4 V VIH Input HIGH Voltage 1.7 VCC + 0.3 V VIL Input LOW Voltage -0.3 0.7 V ILI Input Leakage Current GND VIN VCC -1 1 A ILO Output Leakage Current GND VOUT VCCQ, Outputs disabled -1 1 A Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B 7 IS61LP12832 IS61LP12836 ISSI (R) CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V. 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level for Input Pins Input Pulse Level for I/O Pins Input Rise and Fall Times Input Timing Reference Level I/O Timing Reference Level Output Load Unit 0V to 3.0V 0V to 2.5V 1.5 ns 1.5V 1.25V See Figures 1 and 2 I/O OUTPUT LOAD EQUIVALENT 1,667 +2.5V ZO = 50 OUTPUT OUTPUT 50 1,538 1.25V Figure 1 8 5 pF Including jig and scope Figure 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 09/25/01 IS61LP12832 IS61LP12836 ISSI (R) READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol fMAX(3) tKC(3) t KH tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tWS(3) tCES(3) tAVS(3) tAH(3) tSH(3) tWH(3) tCEH(3) tAVH(3) Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -200 Min. Max. -- 200 5 -- 2 -- 2 -- -- 3.1 1 -- 0 -- 1.5 2.8 -- 2.8 0 -- 0 -- 0 2.8 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- -166 Min. Max. -- 166 6 -- 2.4 -- 2.4 -- -- 3.5 1.5 -- 0 -- 1.5 3.5 -- 3.5 0 -- 0 -- 1.5 3.5 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- -133 Min. Max. -- 133 7.5 -- 2.8 -- 2.8 -- -- 4 1.5 -- 0 -- 1.5 3.5 -- 3.8 0 -- 0 -- 1.5 3.8 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B 9 IS61LP12832 IS61LP12836 ISSI (R) READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVH tAVS Suspend Burst ADV tAS A16-A0 tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 tOEHZ tOEQ OE tKQX tOEQX tOELZ DATAOUT High-Z 1a 2a 2b 2c 2d tKQLZ 3a tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read 10 Burst Read Unselected Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 09/25/01 IS61LP12832 IS61LP12836 ISSI (R) WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC(1) tKH(1) tKL(1) tAS(1) tSS(1) tWS(1) tDS(1) tCES(1) tAVS(1) tAH(1) tSH(1) tDH(1) tWH(1) tCEH(1) tAVH(1) Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -200 Min. Max. 5 -- 2.0 -- 2.0 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- -166 Min. Max. 6 -- 2.4 -- 2.4 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- -133 Min. Max. 7 -- 2.8 -- 2.8 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. Tested with load in Figure 1. Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B 11 IS61LP12832 IS61LP12836 ISSI (R) WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS A16-A0 tAH WR1 WR2 tWS tWH tWS tWH WR3 GW BWE tWS BW4-BW1 tWH WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write 12 tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 09/25/01 IS61LP12832 IS61LP12836 ISSI (R) SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC(3) tKH(3) tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tCES(3) tAH(3) tSH(3) tCEH(3) tZZS tZZREC Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery -200 Min. Max. 5 -- 2 -- 2 -- -- 3.1 1 -- 0 -- 1.5 2.8 -- 2.8 0 -- 0 -- 2 2.8 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 2 -- 2 -- -166 Min. Max. 6 -- 2.4 -- 2.4 -- -- 3.5 1.5 -- 0 -- 1.5 3.5 -- 3.5 0 -- 0 -- 2 3.5 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 2 -- 2 -- -133 Min. Max. 7.5 -- 2.8 -- 2.8 -- -- 4 1.5 -- 0 -- 1.5 3.5 -- 3.8 0 -- 0 -- 1.5 3.8 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 2 -- 2 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B 13 IS61LP12832 IS61LP12836 ISSI (R) SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP ADSC ADV tAS A16-A0 tAH RD1 RD2 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE CE2 CE2 tOEHZ tOEQ OE tOEQX tOELZ DATAOUT High-Z 1a tKQLZ tKQ DATAIN tKQX tKQHZ High-Z tZZS tZZREC ZZ Single Read 14 Snooze with Data Retention Read Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 09/25/01 IS61LP12832 IS61LP12836 ISSI (R) ORDERING INFORMATION Commercial Range: 0C to +70C Speed 200 MHz 166 MHz 133 MHz Order Part Number IS61LP12832-200TQ IS61LP12832-200B IS61LP12832-166TQ IS61LP12832-166B IS61LP12832-133TQ IS61LP12832-133B Commercial Range: 0C to +70C Package TQFP PBGA TQFP PBGA TQFP PBGA Industrial Range: -40C to +85C Speed 200 MHz 166 MHz 133 MHz Order Part Number IS61LP12832-200TQI IS61LP12832-200BI IS61LP12832-166TQI IS61LP12832-166BI IS61LP12832-133TQI IS61LP12832-133BI Speed 200 MHz 166 MHz 133MHz Order Part Number IS61LP12836-200TQ IS61LP12836-200B IS61LP12836-166TQ IS61LP12836-166B IS61LP12836-133TQ IS61LP12836-133B Package TQFP PBGA TQFP PBGA TQFP PBGA Industrial Range: -40C to +85C Package TQFP PBGA TQFP PBGA TQFP PBGA Speed 200 MHz 166 MHz 133 MHz Order Part Number IS61LP12836-200TQI IS61LP12836-200BI IS61LP12836-166TQI IS61LP12836-166BI IS61LP12836-133TQI IS61LP12836-133BI Package TQFP PBGA TQFP PBGA TQFP PBGA ISSI (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com Integrated Silicon Solution, Inc. -- 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00B 15