AMERICAN MICROSYSTEMS, INC.
September 2000
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
9.18.00
IntRGR
FS6233
FS6233FS6233
FS6233-01
-01-01
-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
1.0 Features
• Generates all clocks required for single-processor
platforms, including:
M Two differential current-mode Host clock pairs
M Three 66.67MHz 3.3V CK66 clock outputs
M Ten 33.3MHz 3.3V PCI clock outputs
M Two 3.3V Memory Reference clock outputs
M Two 48MHz 3.3V CK48 clock outputs
M Two buffered copies of the crystal reference
• Control of current-mode Host clocks via IREF current
programming pin and ISEL_0:1 current multiplier pins
• Host clock frequency selection via the SEL_A,
SEL_B, and SEL133/100# pins
• Active-low PWR_DWN# signal allows one complete
clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLLs, and outputs
• Spread-spectrum modulation (-0.5% at 31.5kHz) of
SSCG PLL clocks, enabled via SS_EN# input
• Supports test mode and tristate output control to fa-
cilitate board testing
• Available in a 48-pin SSOP and TSSOP
Table 1: Clock Parameters
CLOCK
GROUP #
PINS SUPPLY
VOLTAGE SUPPLY
GROUP FREQ.
(MHz) PHASE SKEW
HOST_P 2 0°
HOST_N 2 3.3V VDD_H 133.33
100.00 180°
150ps
Pair to
Pair
MREF_P 1 0°
MREF_N 1 3.3V VDD_M 66.67
50.00 180° -
CK66 3 3.3V VDD_66 66.67 0° 250ps
PCI 10 3.3V VDD_P 33.33 0° 300ps
CK48 2 3.3V VDD_48 48.008 0° -
REF 2 3.3V VDD_R 14.318 0° -
Table 2: Clock Offsets
RELATION PHASE MIN TYP MAX
CK66 leads PCI 0° 1.5ns 3.5ns
Figure 1: Block Diagram
Crystal
Oscillator
XOUT
XIN
PWR_DWN#
FS6233
CK66_0:2
adjust
IREF
REF_0:1
VDD_R
VSS_R
ISEL_0:1
÷3
÷4
÷4
VSS_M
VDD_M
MREF_P
MREF_N
VDD_66
VSS_66
÷1
÷2
VSS_H
VDD_H
HOST_P1:2
HOST_N1:2
SEL133/100#
SEL_A:B
PCI_0:7
÷2
VDD_P
VSS_P
CK48_0:1
VDD_48
VSS_48
delay
PLL
SSCG
PLL
Control
SS_EN#
Figure 2: Pin Configuration
1
40
2
3
4
5
6
7
8
39
38
37
36
35
34
33
REF_0 / ISEL_0
VDD_R VSS_R
XOUT
VSS_P
9
10
11
12
13
14
15
16
VSS_66SEL133/100#
VSS
17
18
19
20
21
22
23
MREF_P
MREF_N
32
31
30
29
28
27
26
25
SS_EN#
HOST_N1
VSS_H
HOST_P2
IREF
24
FS6233-01
VDD
HOST_P1
XIN
VSS_M
HOST_N2
VDD_66
PWR_DWN#
VDD_H
VDD_P
Pair 1 Pair 2
41
42
44
43
45
46
48
47
REF_1 / ISEL_1
PCI_0
PCI_1
PCI_2
PCI_3
VSS_P
VDD_P
PCI_4
PCI_5
PCI_6
PCI_7
VSS_P
VDD_P
PCI_8
PCI_9
VDD_48
CK48_0 / SEL_A
CK48_1 / SEL_B
VSS_48 CK66_2
CK66_1
CK66_0
VDD_66
VDD_M
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
2
FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
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ISO9001
Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN TYPE NAME DESCRIPTION SUPPLY
CK48_0 One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
48 DIO SEL_A One of two latched inputs that select the HOST and MREF output frequency VDD_48
CK48_1 One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
24 DIO SEL_B One of two latched inputs that select the HOST and MREF output frequency VDD_48
30, 29, 27 DO CK66_0:3 Three 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL VDD_66
41, 40 AO HOST_P1
HOST_N1
Host clock pair #1; one of two pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1 VDD_H
38, 37 AO HOST_P2
HOST_N2 Host clock pair #2; one of two pairs of current-steering differential current-mode outputs VDD_H
35 AI IREF A fixed precision resistor from this pin to ground provides a reference current used for the dif-
ferential current-mode HOST clock outputs VDD
44 DO MREF_N One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver VDD_M
45 DO MREF_P One clock in a pair of outputs provided as a reference clock to a memory clock driver VDD_M
6, 7, 9, 10,
12, 13, 15,
16, 18, 19
DO PCI_0:9 Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns VDD_P
32 DI PWR_DWN# Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins. VDD_48
REF_0 One of two 3.3V buffered copies of the crystal reference frequency clock
2DIO
ISEL_0 One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
VDD_R
REF_1 One of two 3.3V buffered copies of the crystal reference frequency clock
1DIO
ISEL_1 One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
VDD_R
21 DI SEL133/100# Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency VDD_48
42 DI SS_EN# Active low spread-spectrum enable turns on spread spectrum modulation VDD_M
34 P VDD 3.3V core power supply -
25 P VDD_48 3.3V power supply for CK48 clock outputs -
26, 31 P VDD_66 3.3V power supply for CK66 clock outputs -
39 P VDD_H 3.3V power supply for the differential HOST clock outputs -
46 P VDD_M 3.3V power supply for MREF clock outputs -
8, 14, 20 P VDD_P 3.3V power supply for PCI clock outputs -
2 P VDD_R 3.3V power supply for the REF clock output and the crystal oscillator -
33 P VSS Core ground -
22 P VSS_48 Ground for the CK48 clock outputs -
28 P VSS_66 Ground for the CK66 clock outputs
36 P VSS_H Ground for the differential HOST clock outputs -
43 P VSS_M Ground for the MREF clock outputs -
5, 11, 17 P VSS_P Ground for the PCI clock outputs -
47 P VSS_R Ground for the REF clock outputs and the crystal oscillator -
3 AI XIN 14.318MHz crystal oscillator input VDD_R
4 AO XOUT 14.318MHz crystal oscillator output VDD_R
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
3
FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
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ISO9001
2.0 Programming Information
Table 4: Function/Clock Enable Configuration
CONTROL INPUTS (1) CLOCK OUTPUTS (MHz)
PWR_
DWN#
SEL
133/100# SEL_A SEL_B HOST_P
1:2
HOST_N
1:2
MREF_P,
MREF_N
CK66_
0:2
PCI_
0:9
CK48_
0:1 REF
1 0 0 0 100.00 100.00 50.00 66.67 33.33 48.008 14.318
1 0 0 1 reserved reserved reserved reserved reserved reserved reserved
1 0 1 0 reserved reserved reserved reserved reserved reserved reserved
1 0 1 1 tristate tristate tristate tristate tristate tristate tristate
1 1 0 0 133.33 133.33 66.67 66.67 33.33 48.008 14.318
1 1 0 1 reserved reserved reserved reserved reserved reserved reserved
1 1 1 0 reserved reserved reserved reserved reserved reserved reserved
1 1 1 1 XIN ÷ 2 XIN ÷ 2 XIN ÷ 4 XIN ÷ 4 XIN ÷ 8 XIN ÷ 2 XIN
0XXX
2 × IREF tristate low low low low low
1. It is expected that the Control Inputs will be defined on power-up and will not change during normal operation.
Table 5: Synthesis Error
CLOCK TARGET
(MHz) ACTUAL
(MHz) DEVIATION
(ppm)
100.0000 99.9963 -36.657
HOST_P1:2,
HOST_N1:2 133.3333 133.3072 -195.924
50.0000 49.9982 -36.657
MREF_P,
MREF_N 66.6667 66.6536 -195.924
CK66 66.6667 66.6642 -36.657
PCI 33.3333 33.3321 -36.657
CK48 (1) 48.000 48.008 +167
1. 48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB
standards.
2. Spread spectrum is disabled
3.0 HOST Buffer Current Contr ol
The current supplied at the HOST outputs is controlled by
two parameters:
1) the value of the programming resistor from the IREF
pin to ground (VSS), and
2) the multiplier factor determined by the logic setting of
the ISEL_0 and ISEL_1 pins.
3.1 Current Reference
The HOST output current is a mirrored and scaled copy
of the reference current flowing through the programming
resistor on the IREF pin. Conceptually, the circuit given in
Figure 2 shows how the mirror current is generated.
The voltage that appears at the IREF pin is one-third of
the voltage at the VDD_I pin. The reference current is
IREF
REF R
I
×
=VDD_I
3
1
.
3.2 Current Scaling
The mirrored reference current can be increased by
adding one or more copies of the mirror current together.
The additional current is controlled by the logic settings
on the ISEL_0 and ISEL_1 pins.
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
4
FS6233-01
FS6233-01FS6233-01
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Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
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Table 6: Current Multiplier
ISEL_0 ISEL_1 MULTPLIER
00
IO = 5 × IREF
01
IO = 6 × IREF
10
IO = 4 × IREF
11
IO = 7 × IREF
Figure 2: Current Reference Circuit
R
IREF
IREF
Reference
Current I
REF
2R
R
Mirror
Current
Additional
Mirror
Current
HOST_N
ISEL_0:1
HOST_P
1.1V
R
P
R
S
R
P
R
S
VDD_I (3.3V)
Table 7: HOST Current Selection
PROGRAM
RESISTOR
RIREF
REFERENCE
CURRENT
IREF
CURRENT
MULTIPLIER TRACE
IMPEDANCE OUTPUT
VOLTAGE
60Ω0.71V
475Ω (1%) 2.32mA IO = 5 × IREF 50Ω0.59V
60Ω0.85V
475Ω (1%) 2.32mA IO = 6 × IREF 50Ω0.71V
60Ω0.56V
475Ω (1%) 2.32mA IO = 4 × IREF 50Ω0.47V
60Ω0.99V
475Ω (1%) 2.32mA IO = 7 × IREF 50Ω0.82V
30Ω0.75V
221Ω (1%) 5mA IO = 5 × IREF 25Ω0.62V
30Ω0.90V
221Ω (1%) 5mA IO = 6 × IREF 25Ω0.75V
30Ω0.60V
221Ω (1%) 5mA IO = 4 × IREF 25Ω0.50V
30Ω1.05V
221Ω (1%) 5mA IO = 7 × IREF 25Ω0.84V
NOTE: Shaded row indicates the Primary System Configuration
Table 8: HOST Buffer Clock Outputs
HIGH DRIVE CURRENT (mA)
AT PRIMARY SYSTEM CONFIGURATION
Output
Voltage (V) MIN. TYP. MAX.
3.30 0.00 0.00 0.00
3.14 -3.03 -4.22 -5.76
2.97 -5.66 -7.68 -9.86
2.81 -7.87 -10.30 -11.85
2.64 -9.67 -11.91 -12.45
2.48 -11.05 -12.56 -12.84
2.31 -11.98 -12.85 -13.16
2.14 -12.52 -13.07 -13.45
1.98 -12.77 -13.26 -13.72
1.81 -12.91 -13.42 -13.96
1.65 -12.99 -13.54 -14.17
1.48 -13.04 -13.64 -14.36
1.32 -13.07 -13.70 -14.52
1.15 -13.08 -13.73 -14.64
0.99 -13.09 -13.75 -14.71
0.82 -13.11 -13.76 -14.74
0.66 -13.12 -13.78 -14.76
0.49 -13.13 -13.79 -14.78
0.33 -13.13 -13.80 -14.80
0.16 -13.14 -13.81 -14.82
0.00 -13.15 -13.82 -14.83
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
0123
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Max VOH
Data in this table represents nominal characterization data only
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
5
FS6233-01
FS6233-01FS6233-01
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Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
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4.0 Power Management
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to each individual clock. As shown in
Figure 3, a falling-rising-falling edge sequence on any
individual clock output is required before that clock output
is disabled low. This edge sequence ensures that one
complete clock cycle will occur before the clock stops.
Table 9: Latency Table
LATENCY
SIGNAL SIGNAL
STATE MIN. MAX.
Output: 2 clocks 3 clocks
0Power
OFF Device: 2× REF
clocks 3× REF clocks
PWR_
DWN#
1Power
ON 3ms
Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.
Figure 3: PWR_DWN# Timing
Any Clock
(output)
PWR_DWN#
Any Clock
(internal)
VCO
Crystal
Oscillator
After REF
output shuts off... 3ms until clock is valid
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
5.0 Dual Function I/O Pins
Several pins on this device serve as dual function in-
put/output pins. During the initial application of VDD to
the device, this type of pin functions as an input pin.
Upon completion of power-up, the logic state present on
the pin is latched internally, and the pin is converted to an
output driver.
An external 10kΩ pull-down resistor to ground is required
for a logic low and a 10kΩ pull-up resistor to the clock
output VDD is required for a logic high. The 10kΩ resistor
presents an insignificant load to the output driver that
should not affect the output clock.
Note that the latching of the logic state occurs only on the
application of the chip supply voltage (VDD). The logic
state on the pin is not latched if the PWR_DWN# signal is
used to power-down the device with VDD still applied.
Figure 4: I/O Pin Programming
Clock Trace
Termination
Resistor
Device Solder
Pads
Ground or
Power Via
10k
Ω
Programming
Resistor
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
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FS6233-01
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Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
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6.0 Electrical Specifications
Table 10: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (VI < 0 or VI > VDD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ125 °C
Lead Temperature (soldering, 10s) 260 °C
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 11: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Core (VDD) 3.135 3.3 3.465
Supply Voltage VDD Clock Buffers (VDD_48, VDD_66, VDD_H,
VDD_M, VDD_P, VDD_R) 3.135 3.3 3.465 V
Operating Temperature Range TA070°C
Crystal Resonator Frequency fXTAL 14.316 14.318 14.32 MHz
Crystal Resonator Load Capacitance CXL XIN, XOUT pins 13.5 18 22.5 pF
MREF_P, MREF_N 10 30
PCI_0:9 10 30
CK66_0:2 10 30
CK48_0:1 10 20
Load Capacitance CL
REF_0:1 10 20
pF
Load Resistance RL
HOST_P1 to HOST_P2,
HOST_N1 to HOST_N2 20 105 Ω
Maximum High-Level Output Voltage VOH
HOST_P1 to HOST_P2,
HOST_N1 to HOST_N2 1.20 V
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
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FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
Tabl e 12: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs IDD
fHOST = 133MHz; all supplies = 3.465V,
RIREF= 475Ω, IOH = 6 × IREF mA
Supply Current, Static IDDs
PWR_DWN# low, all supplies = 3.465V,
RIREF= 475Ω, IOH = 6 × IREF µA
Digital Inputs (PWR_DWN#, SEL133/100#, SS_EN#)
High-Level Input Voltage VIH 2.0 VDD+0.3 V
Low-Level Input Voltage VIL VSS-0.3 0.8 V
Input Leakage Current IIL -5 +5 µA
Crystal Oscillator Feedback (XIN)
Threshold Bias Voltage VTH 1.5 V
High-Level Input Current IIH VIH = 3.3V 32 µA
Low-Level Input Current IIL VIL = 0V -32 µA
Crystal Loading Capacitance * CL(xtal)
As seen by an external crystal connected to
XIN and XOUT 13.5 18 22.5 pF
Input Loading Capacitance * CL(XIN)
As seen by an external clock driver on
XOUT; XIN unconnected 36 pF
Crystal Oscillator Drive (XOUT)
High Level Output Source Current IOH VI (XIN) = 3.3V, VO = 0V -8.0 mA
Low Level Output Sink Current IOL VI (XIN) = 0V, VO = 3.3V 8.7 mA
Current Reference (IREF)
Bias Voltage VOH no load 1.1 V
Short Circuit Output Source Current IOH VO = 0V mA
MREF_P, MREF_N, CK66_0:2, PCI_0:9 Clock Outputs (Type 5)
IOH min
VDD_M, VDD_66, VDD_P = 3.135V,
VO = 1.0V -33
High Level Output Source Current
IOH max
VDD_M, VDD_66, VDD_P = 3.465V,
VO = 3.135V -33
mA
IOL min
VDD_M, VDD_66, VDD_P = 3.135V,
VO = 1.95V 30
Low Level Output Sink Current
IOL max
VDD_M, VDD_66, VDD_P = 3.465V,
VO = 0.4V 38
mA
zOL Measured at 1.65V, output driving low 12 55
Output Impedance zOH Measured at 1.65V, output driving high 12 55 Ω
Tristate Output Current IOZ -10 10 µA
Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA
Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
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Motherboard Clock Generator IC
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Table 13: DC Electrical Specifications, continued
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
HOST_P1:2, HOST_N1:2 Clock Outputs (Type X1)
Crossover Voltage VX
RS = 33.2Ω, RP = 49.9Ω,
RIREF = 475Ω, IOH = 6 × IREF
45 55 %VOH
VO = 0.65V, RIREF = 475Ω, IOH = 6 × IREF 12.9
High-Level Output Source Current IOH VO = 0.74V, RIREF = 475Ω, IOH = 6 × IREF 14.9 mA
VDD = 3.3V, over settings in Table 7 -7 +7
Output Source Current Tolerance ∆IOH VDD_I = 3.3V±5%, over settings in Table 7 -12 +12 %IOH
Output Impedance zOH ∆VO/∆IO, where VO1 = 1.0V, VO2 = VSS,
RIREF = 475Ω, IOH = 6 × IREF
3000 Ω
Tristate Output Current IOZ -10 10 µA
REF_0 / ISEL_0, REF_1 / ISEL_1 Clock Driver I/O, (Type 3)
CK48_0 / SEL_A, CK48_1 / SEL_B Clock Driver I/O (Typ e 3)
High-Level Input Voltage VIH 2.0 VDD+0.3 V
Low-Level Input Voltage VIL VSS-0.3 0.8 V
High-Level Input Current IIH 5µA
Low-Level Input Current (pull-up)
Input
IIL VIL = 0.4V -9 µA
High Level Output Source Current IOH VDD_R, VDD_48 = 3.465V, VO = 2.4V -32 mA
Low Level Output Sink Current IOL VDD_R, VDD_48 = 3.465V, VO = 0.4V 13 mA
zOL Measured at 1.65V, output driving low 20 60
Output Impedance zOH Measured at 1.65V, output driving high 20 60 Ω
Tristate Output Current IOZ -10 10 µA
Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -41 mA
Short Circuit Output Sink Current
Output
IOSL VO = 3.3V; shorted for 30s, max. 40 mA
Figure 5: DC Measurement Points
3.3V
V
IH
= 2.0V
V
IL
= 0.8V
V
OH
= 2.4V
V
OL
= 0.4V
Figure 6: Timing Diagram
1.5V
2.4V
0.4V
d
t
t
r
t
f
3.3V
Figure 7: HOST Clock Measurement Point
HOST_P
HOST_N
V
X
Figure 8: HOST Clock Test Point
R
P
R
S
Test node
From output
under test
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September 2000
9.18.00
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Table 14: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Spread Spectrum Modulation
Frequency * fmSS_EN# low 31.5 kHz
Spread Spectrum Modulation
Index * δmSS_EN# low -0.5 %
Clock Offset tpd
CK66 leads @ 1.5V, CL=30pF to PCI @ 1.5V,
CL = 30pF (measured on rising edges) 1.5 3.5 ns
Output Tristate Enable Delay * tDZL, tDZH SEL_A:B = 00, SEL133/100# = 0 1.0 10 ns
Output Tristate Disable Delay * tDLZ, tDHZ SEL_A:B = 11, SEL133/100# = 0 1.0 10 ns
Power-up PLL Lock Time tLvia PWR_DWN# 3.0 ms
HOST_P1:2, HOST_N1:2 Clock Outputs
Clock Skew * tsk(o)
HOST pair to HOST pair @ VX, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω150 ps
Duty Cycle * dt
Ratio of high pulse width to one clock period at VX,
RIREF = 475Ω, IOH = 6 × IREF, RS=33.2Ω, RP=49.9Ω45 55 %
Jitter, Period (peak-peak) * tj(∆P)
Rising edge to rising edge at VX, RIREF = 475Ω,
IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω200 ps
Rise Time * tr
Measured at 20% – 80% of VOH; RIREF = 475Ω,
IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω175 450 ps
Rise/Fall Time Matching* Measured at 20% – 80% of VOH; RIREF = 475Ω,
IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω20 %
MR EF_P, MR EF_N C l ock Outputs
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL=30pF 250 ps
tr min Measured @ 0.4V – 2.4V; CL=10pF 0.4
Rise Time * tr max Measured @ 0.4V – 2.4V; CL=30pF 1.6 ns
tf min Measured @ 2.4V – 0.4V; CL=10pF 0.4
Fall Time * tf max Measured @ 2.4V – 0.4V; CL=30pF 1.6 ns
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
10
FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
Table 15: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
PC I_0:9 C lock Outputs
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Clock Skew * tsk(o) One clock output relative to another at 1.5V 500 ps
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 30pF 500 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 0.5
Rise Time * tr max Measured at 0.4V – 2.4V; CL = 30pF 2.0 ns
tf min Measured at 2.4V – 0.4V; CL = 10pF 0.5
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 30pF 2.0 ns
CK66_0:2 Clock Outputs
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Clock Skew * tsk(o) One clock output relative to another at 1.5V 250 ps
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 30pF 300 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 0.5
Rise Time * tr max Measured at 0.4V – 2.4V; CL = 30pF 2.0 ns
tf min Measured at 2.4V – 0.4V; CL = 10pF 0.5
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 30pF 2.0 ns
REF_0:1 Clock Outputs
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 20pF 1000 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 1.0
Rise Time * tr max Measured at 0.4V – 2.4V; CL = 20pF 4.0 ns
tf min Measured at 2.4V – 0.4V; CL = 10pF 1.0
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 20pF 4.0 ns
CK48_0:1 Clock Outputs
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 20pF 350 ps
tr min Measured at 0.4V – 2.4V; CL = 10pF 1.0
Rise Time * tr max Measured at 0.4V – 2.4V; CL = 20pF 4.0 ns
tf min Measured at 2.4V – 0.4V; CL = 10pF 1.0
Fall Time * tf max Measured at 2.4V – 0.4V; CL = 20pF 4.0 ns
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
11
FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
Table 16: MCLK_P, MCLK_N, PCI_0:9, CK66_0:2 Clock Outputs
High Drive Current (mA) Low Drive Current (mA)
Voltage
(V) MIN. TYP. MAX.
Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -49 -83 -132
0.2 11 17 24 0.2 -48 -83 -131
0.4 21 32 45 0.4 -48 -82 -130
0.6 30 45 64 0.6 -47 -81 -129
0.8 37 56 79 0.8 -47 -80 -127
1.0 43 65 92 1.0 -46 -79 -126
1.2 47 73 103 1.2 -46 -78 -124
1.4 50 78 112 1.4 -45 -76 -121
1.6 53 82 117 1.6 -43 -74 -117
1.8 54 84 120 1.8 -41 -70 -112
2.0 55 85 121 2.0 -37 -65 -105
2.2 55 85 122 2.2 -33 -59 -97
2.4 55 86 123 2.4 -28 -52 -87
2.6 56 86 123 2.6 -22 -43 -74
2.8 56 86 124 2.8 -14 -32 -60
3.0 56 87 124 3.0 -6 -20 -45
3.2 87 124 3.2 -7 -27
3.4 125 3.4 -7
-150
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
00.511.522.533.5
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Data in this table represents nominal characterization data only
Table 17: REF_0:1, CK48_0:1 Clock Outputs
High Drive Current (mA) Low Drive Current (mA)
Voltage
(V) MIN. TYP. MAX.
Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -38 -64 -102
0.2 8 13 18 0.2 -37 -64 -101
0.4 15 24 33 0.4 -37 -63 -100
0.6 223347 0.6-37-63-99
0.8 274158 0.8-36-62-98
1.0 314868 1.0-36-61-97
1.2 355376 1.2-35-60-95
1.4 375782 1.4-34-59-93
1.6 396086 1.6-33-57-90
1.8 396188 1.8-31-54-87
2.0 406289 2.0-29-50-81
2.2 406390 2.2-25-46-75
2.4 416390 2.4-21-40-67
2.6 416390 2.6-17-33-57
2.8 416391 2.8-11-25-47
3.0 416491 3.0 -5-16-34
3.2 64 91 3.2 -6 -21
3.4 91 3.4 -5
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
00.511.522.533.5
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Data in this table represents nominal characterization data only
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
12
FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
7.0 Package Information
Table 18: 48-pin SSOP (0.300") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.095 0.110 2.41 2.79
A10.008 0.016 0.20 0.41
b 0.008 0.0135 0.20 0.34
c 0.005 0.010 0.13 0.25
D 0.620 0.630 15.75 16.00
E 0.395 0.420 10.03 10.67
E10.291 0.299 7.39 7.59
e 0.025 BSC 0.64 BSC
h 0.015 0.025 0.38 0.64
L 0.020 0.040 0.51 1.01
θ0°8°0°8°
E
E
1
48
1
AMERICAN MICROSYSTEMS, INC.
b
DA
1
SEATING PLANE
A
e
c
L
θ
h × 45°
Table 19: 48-pin SSOP (0.300") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 93 °C/W
Lead Inductance, Self L11 Longest lead 5.5 nH
L12 Longest lead to any 1st adjacent lead 3.0
Lead Inductance, Mutual L13 Longest lead to any 2nd adjacent lead 2.1 nH
Lead Capacitance, Bulk C11 Longest lead to VSS 0.94 pF
C12 Longest lead to any 1st adjacent lead 0.46
Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.05 pF
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
13
FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
Table 20: 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A - 0.047 - 1.20
A10.002 0.006 0.05 0.15
b 0.0067 0.011 0.17 0.27
c 0.0035 0.008 0.09 0.20
D 0.488 0.496 12.40 12.60
E 0.318 BSC 8.10 BSC
E10.236 0.244 6.00 6.20
e 0.019 BSC 0.50 BSC
L 0.018 0.030 0.45 0.75
S 0.008 - 0.20 -
θ10°8°0°8°
θ212° REF 12° REF
θ312° REF 12° REF
E
1
AMERICAN MI CROSY STEM S, IN C.
E
1
48
be
DA
1
SEATING PLANE
Ac
L
θ
1
θ
3
θ
2
S
Table 21: 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 89 °C/W
Lead Inductance, Self L11 Longest lead 3.50 nH
L12 Longest lead to any 1st adjacent lead 1.82
Lead Inductance, Mutual L13 Longest lead to any 2nd adjacent lead 1.17 nH
Lead Capacitance, Bulk C11 Longest lead to VSS 0.63 pF
C12 Longest lead to any 1st adjacent lead 0.30
Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.03 pF
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
14
FS6233-01
FS6233-01FS6233-01
FS6233-01
Motherboard Clock Generator IC
Motherboard Clock Generator ICMotherboard Clock Generator IC
Motherboard Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
8.0 Ordering Information
Table 22: Device Ordering Codes
DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
11995-202 Tape and Reel
11995-212 48-pin (0.300”) SSOP
Tubes
11995-203 Tape and Reel
FS6233-01
11995-213 48-pin (6.1mm) TSSOP
0°C to 70°C (Commercial)
Tubes
Copyright © 2000 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: tgp@amis.com
