Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2006 REV. 1.0.1
GENERAL DESCRIPTION
The XRT83L30 is a fully integrated single-channel
long-haul and short-haul line interface unit for
T1(1.544Mbps) 100Ω, E1(2.048Mbps) 75Ω or 120Ω
and J1 110Ω applications.
In long-haul applications the XRT83L30 accepts
signals that have passed through cables from 0 feet
to over 6000 feet in length and have been attenuated
by 0 to 45dB at 772kHz in T1 mode or 0 to 43dB at
1024kHz in E1 mode. In T1 applications, the
XRT83L30 can generate five transmit pulse shapes
to meet the short-haul Digital Cross-Connect (DSX-1)
template requirements as well as for Channel Service
Units (CSU) Line Build Out (LBO) filters of 0dB,
-7.5dB, -15d B a nd -2 2. 5d B a s re q uir ed by FC C ru les .
It also provides programmable transmit pulse
generator that can be used for arbitrary output pulse
shaping allowing performance improvement over a
wide variety of conditions.
The XRT83L30 provides both Serial Host
microprocessor interface and Hardware Mode for
programming and control. Both B8ZS and HDB3
encoding and decoding functions are included and
can be disabled as requ ired. On-chip cryst al-less jitter
attenuator with a 32 or 64 bit FIFO can be placed
either in the receive or the transmit path with loop
bandwidths of less than 3Hz. The XRT83L30
provides a variety of loop-back and diagnostic
features as well as transmit driver short circuit
detection and receive loss of signal monitoring. It
support s internal impeda nce match ing for 75 Ω, 100Ω,
110Ω and 120Ω for both transmitter and receiv er. For
the receiver this is accomplished by internal re sistors
or through the combination of one single fixed value
external resistor and program mable internal resistors.
In the absence of the power supply, the transmit
output and receive input are tri-stated allowing for
redundancy applications. The chip includes an
integrated programmable clock multiplier that can
synthesize T1 or E1 master clocks from a variety of
external clock sources.
APPLICATIONS
•T1 Digital Cross-Connects (DSX-1)
•ISDN Primary Rate Interface
•CSU/DSU E1/T1/J1 Interface
•T1/E1/J1 LAN/WAN Routers
•Public switching Systems and PBX Interfaces
•T1/E1/J1 Mult iplexe r an d Ch an ne l Bank s
FEATURES
(See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83L30 T1/E1 /J1 LIU (HOST MODE)
HW/HOST
CS
INT
ICT
TXTEST[0:2]
INSBPV
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
RTIP
RRING
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO
TTIP
TRING
TXON
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
DRIVE
MONITOR
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
JA
SELECT
NLCD ENABLE
QRSS ENABLE
SDO
SCLK
SDI
RESET
Serial Interface
TEST
TAOS
ENABLE
MCLKE1
MCLKT1 MCLKOUT
AISD
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
FEATURES
•Fully integrated single-channel long-haul and short-haul transceiver for E1,T1 or J1 applicat ions.
•Adaptive Receive Equalizer for cable attenuation of u p to 45dB for T1 and 43dB for E1.
•Programmable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces.
•Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform
generator for transmit output pulse shaping.
•Programmable Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three
7.5dB steps.
•Tri-State transmit output and receive input capability for redundancy applications
•Selectable receiver sensitivity from 0 to 36dB or 0 to 45dB cable loss for T1 @772kHz and 0 to 43dB for E1
@1024kHz.
•High receiver interference immunity
•Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for
both T1 and E1 modes.
•Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω (J1) applications.
•Internal and exte rn al imp e da n ce ma tc hin g for 75Ω,100Ω, 110Ω and 120Ω.
•Transmit return loss meets or exceeds ETSI 300 166 standard
•On-chip digital clock recovery circuit for high input jitter tolerance
•Crystal-less digital jitter attenuator with 32 -b it or 64-b it FIFO Selectable either in transmit or receive path
•On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources
•On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO)
FIGURE 2. BLOCK DIAGRAM OF THE XRT83L30 T1/E1 /J1 LIU (HARDWARE MODE)
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
ICT
MCLKE1
MCLKT1
CLKSEL[2:0]
TXTEST[0:2]
INSBPV
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
RTIP
RRING
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO
TTIP
TRING
TXON
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
JA
SELECT
NLCD ENABLE
QRSS ENABLE
HARWARE CONTROL
TEST
JABW
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
DRIVE
MONITOR
DFM
MCLKOUT
LOOP1
LOOP0
AISD
RESET
TAOS
ENABLE
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
•Receive loss of signal (RLOS) output
•On-chip HDB3/B8ZS/AMI encoder/decoder
•QRSS pattern generation and detection for testing and monitoring
•Error and Bipolar Violation Insertion and Detection
•Receiver Line Attenuation Indication Output in 1dB steps
•Network Loop-Code De tection for automatic Loop-Back Activation/Deactivation
•Transmit All Ones (TAOS) and In-Band Network Loop Up and Down code generators
•Supports Analog, Remote, Digital and Dual Loop-Back Modes
•Meets or exceeds T1 and E1 short-haul and long-haul network access specifications in ITU G.703, G.775,
G.736 and G.823; TR-TSY-000499; ANSI T1.403 and T1.408; ETSI 300-166 and AT&T Pub 62411
•Supports both Hardware and serial Microprocessor interface for progr amming
•Programmable Interrup t
•Low power dissipation
•Logic inputs accept either 3. 3V or 5V leve ls
•Single +3.3V Supply Operation
•64 pin TQFP package
•-40°C to +85°C Temperature Range
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT83L30IV 64 Lead TQFP (10 x 10 x 1.4mm) -40°C to +85°C
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
FIGURE 3. PIN OUT OF THE XRT83L30
XRT83L30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RNEG / LCV
RPOS / RDATA
RAVDD
RTIP
RRING
RAGND
TAGND
TTIP
TAVDD
TRING
DMO
VDDPLL
MCLKE1
MCLKT1
GNDPLL
MCLKOUT
AGND
AVDD
LOOP0
LOOP1
SR / DR
ATAOS
TRATIO
EQC0 / INT
EQC1 / CS
EQC2 / SCLK
EQC3 / SDO
EQC4 / SDI
HW/HOST
CLKSEL0
CLKSEL1
CLKSEL2
JASEL0
JASEL1
JABW
TXTSEL
RXTSEL
TERSEL1
TERSEL0
RESET
QRPD
AISD
NLCD
DGND
DVDD
INSBPV
NLCDE0
NLCDE1
GAUGE
RXMUTE
RXRES1
RXRES0
RCLKE
TXTEST2
TXTEST1
TXTEST0
TCLKE
TXON
ICT
TCLK
TPO S / TD A TA
TNEG / CODE S
RLOS
RCLK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
APPLICATIONS ............................................. ............................. .................................................................... 1
FEATURES ............................................................................................................................................ ... .... 1
Figure 1. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Host Mode) .................... ................ ............. 1
Figure 2. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Hardware Mode) ........................................ 2
FEATURES ............................................................................................................................................ ... .... 2
ORDERING INFORMATION ............................................................................................................... 3
Figure 3. Pin Out of the XRT83L30 ......................................................................................................... 4
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS BY FUNCTION ................................................................................. 5
SERIAL INTERFACE ....................................................................................................................................... 5
RECEIVER .................................................................................................................................................... 6
TRANSMITTER .............................................................................................................................................. 7
JITTER ATTENUATOR .................................................................................................................................... 9
CLOCK SYNTHESIZER ................................................................................................................................... 9
REDUNDANCY SUPPORT ............................................................................................................................. 11
TERMINATIONS ........................................................................................................................................... 11
CONTROL FUNCTION ............. ....................... .......................... ......................... .......................... .................. 13
ALARM FUNCTION/OTHER ........................................................................................................................... 14
POWER AND GROUND ................................................................................................................................. 16
FUNCTIONAL DESCRIPTION .......................................................................................... 17
MASTER CLOCK GENERATOR ..................................................................................................................... 17
Figure 4. Two Input Clock Source ........................................................................................................ 17
Figure 5. One Input Clock Source ........................................................................................................ 17
TABLE 1: MASTER CLOCK GENERATOR ..................................................................................................... 18
RECEIVER ......................................................................................................................... 18
RECEIVER INPUT ........................................................................................................................................ 18
RECEIVE MONITOR MODE .................. ....... ...... ...... ....... ...... ....... ... ....... ...... ...... ....... ...... ....... ...... ....... ...... ..... 19
RECEIVER LOSS OF SIGNAL (RLOS) .. ... .... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ................ ... ... ... .... ... ... ... .. 19
Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ..................... 19
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ............................... 20
Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ..................... 20
Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ..................................................... 21
RECEIVE HDB3/B8ZS DECODER ............................................................................................................... 21
RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 21
Figure 10. Receive Clock and Output Data Timing ............................................................................. 21
JITTER ATTENUATOR .................................................................................................................................. 22
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................ 22
TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .............................................. 22
ARBITRARY PULSE GENERATOR ................................................................................................................. 23
Figure 11. Arbitrary Pulse Segment Assignment .................... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ........ 23
TRANSMITTER ................................................................................................................. 23
DIGITAL DATA FORMAT ................ ................... ................... .................... ................... ................... ............... 23
TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 23
Figure 12. Transmit Clock and Input Data Timing ...................... ... ... ... ... .... ... ................ ... ... .... ... ... ... .. 24
TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 24
TABLE 3: EXAMPLES OF HDB3 ENCODING ................................................................................................. 24
TABLE 4: EXAMPLES OF B8ZS ENCODING ................................................................................................. 24
DRIVER FAILURE MONITOR (DMO) ............................................................................................................. 24
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ................................. ............................. ........ 25
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ................................. 25
TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 27
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
RECEIVER ............................................................................................................................................... 27
Internal Receive Termination Mode .................................................................................................................. 27
TABLE 6: RECEIVE TERMINATION CONTROL ................................................................................................ 27
Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode ............... 27
TABLE 7: RECEIVE TERMINATIONS .............................................................................................................. 28
Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) .................... 28
Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) .......................... 29
TRANSMITTER ........................................................................................................................................ 29
Transmit Termination Mode .............................................................................................................................. 29
TABLE 8: TRANSMIT TERMINATION CONTROL .............................................................................................. 29
TABLE 9: TERMINATION SELECT CONTROL ................................................................................................. 29
External Transmit Termination Mode ............................................................................................................... 29
TABLE 10: TRANSMIT TERMINATION CONTROL ............................................................................................ 30
TABLE 11: TRANSMIT TERMINATIONS .......................................................................................................... 30
REDUNDANCY APPLICATIONS ............................................................................................................. 30
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 31
Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy .............. 32
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .................... 32
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy ................................ 33
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy ................................. 34
PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 35
TABLE 12: PATTERN TRANSMISSION CONTROL ............................................................................................ 35
TRANSMIT ALL ONES (TAOS) ..................................................................................................................... 35
NETWORK LOOP CODE DETECTION AND TRANSMISSION ... ......... .......... .......... ......... .......... ....... ......... .......... .. 35
TABLE 13: LOOP-CODE DETECTION CONTROL ............................................................................................ 36
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 36
LOOP-BACK MODES ................. ................ ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... ................ ......... 38
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ............................................................................... 38
TABLE 15: LOOP-BACK CONTROL IN HOST MODE ........................................................................................ 38
LOCAL ANALOG LOOP-BACK (ALOOP) ........................................................................................................ 38
Figure 20. Local Analog Loop-back signal flow .................................................................................. 38
REMOTE LOOP-BACK (RLOOP) .................................................................................................................. 39
Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path ....................... 39
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path ..................... 39
DIGITAL LOOP-BACK (DLOOP) ................................................................................................................... 40
Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ....................... 40
DUAL LOOP-BACK ...................................................................................................................................... 40
Figure 24. Signal flow in Dual loop-back mode ... .... ... ................ ... .... ... ... ... ... .... ... ... ... .... ... .................. 40
HOST MODE SERIAL INTERFACE OPERATION .......................................................... 41
USING THE MICROPROCESSOR SERIAL INTERFACE ...................................................................................... 41
Figure 25. Microprocessor Serial Interface Data Structure ................................................................ 42
TABLE 16: MICROPROCESSOR REGISTER ADDRESS .................................................................................... 43
TABLE 17: MICROPROCESSOR REGISTER BIT MAP ..................................................................................... 43
TABLE 18: MICROPROCESSOR REGISTER #0 BIT DESCRIPTION .................................................................... 45
TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION .................................................................... 46
TABLE 20: MICROPROCESSOR REGISTER #2 BIT DESCRIPTION .................................................................... 48
TABLE 21: MICROPROCESSOR REGISTER #3 BIT DESCRIPTION .................................................................... 50
TABLE 22: MICROPROCESSOR REGISTER #4 BIT DESCRIPTION .................................................................... 52
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION .................................................................... 53
TABLE 24: MICROPROCESSOR REGISTER #6 BIT DESCRIPTION .................................................................... 55
TABLE 25: MICROPROCESSOR REGISTER #7 BIT DESCRIPTION .................................................................... 56
TABLE 26: MICROPROCESSOR REGISTER #8 BIT DESCRIPTION .................................................................... 56
TABLE 27: MICROPROCESSOR REGISTER #9 BIT DESCRIPTION .................................................................... 57
TABLE 28: MICROPROCESSOR REGISTER #10 BIT DESCRIPTION .................................................................. 57
TABLE 29: MICROPROCESSOR REGISTER #11 BIT DESCRIPTION .................................................................. 58
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 30: MICROPROCESSOR REGISTER #12 BIT DESCRIPTION .................................................................. 58
TABLE 31: MICROPROCESSOR REGISTER #13 BIT DESCRIPTION .................................................................. 59
TABLE 32: MICROPROCESSOR REGISTER #14 BIT DESCRIPTION .................................................................. 59
TABLE 33: MICROPROCESSOR REGISTER #15 BIT DESCRIPTION .................................................................. 60
TABLE 34: MICROPROCESSOR REGISTER #16 BIT DESCRIPTION .................................................................. 61
TABLE 35: MICROPROCESSOR REGISTER #17 BIT DESCRIPTION .................................................................. 62
TABLE 36: MICROPROCESSOR REGISTER #18 BIT DESCRIPTION .................................................................. 63
ELECTRICAL CHARACTERISTICS .................................................................................................................. 65
TABLE 37: ABSOLUTE MAXIMUM RATINGS ................................................................................................. 65
TABLE 38: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS .............................................. 65
TABLE 39: XRT83L30 POWER CONSUMPTION .......................................................................................... 65
TABLE 40: E1 RECEIVER ELECTRICAL CHARACTERISTICS ............ ....... ...... ...... .... ...... ....... ...... ...... ....... ...... .. 66
TABLE 41: T1 RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................... 67
TABLE 42: E1 TRANSMIT RETURN LOSS REQUIREMENT ............... ................ ................ ................ ............... 67
TABLE 43: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ..................................................................... 68
TABLE 44: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS ..................................................................... 68
Figure 26. ITU G.703 Pulse Template ................................................................................................... 69
TABLE 45: TRANSMIT PULSE MASK SPECIFICATION .................................................................................... 69
Figure 27. DSX-1 Pulse Template (normalized amplitude) ................................................................. 70
TABLE 46: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS .......... ................ ... ... .... ... ... ... .. 70
TABLE 47: AC ELECTRICAL CHARACTERISTICS .......................................................................................... 71
Figure 28. Transmit Clock and Input Data Timing ...................... ... ... ... ... .... ... ................ ... ... .... ... ... ... .. 71
Figure 29. Receive Clock and Output Data Timing ............................................................................. 72
PACKAGE DIMENSIONS ................................................................................................. 73
64 LEAD THIN QUAD FLAT PACK ............................................................................................ 73
(10 X 10 X 1.4 MM TQFP) ............................................................................................................. 73
REV. 3.00 ..................................................................................................................................... 73
ORDERING INFORMATION ............................................................................................. 74
TABLE 48. ....... ... ... ... .... ... ... ... ................. ... ... ... ... ................. ... ... ... .... ................ ... ... ... .... ........................... 74
REVISION HISTORY ............... ....... ...... ....... ...... ...... ....... ... ....... ...... ....... ...... ...... ....... ...... ....... ... ...... ....... ........ 74
NOTES .............................................................................................................................................. 75
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
PIN DESCRIPTIONS BY FUNCTION
SERIAL INTERFACE
SIGNAL NAME PIN # TYPE DESCRIPTION
HW/HOST 20 IMode Control Input
This pin is used for selecting Hardware or Host mode to control the device.
Leave this pin unconnected or tie “High” to select Hardware mode. For Host
mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50kΩ resistor.
SDI
EQC4
21 ISerial Data Input
In Host mode, this pin is the data input for the Serial Interface.
Equalizer Co ntrol Input 4
Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13.
SDO
EQC3
22 O
I
Serial Data Output
In Host mode, this pin is the output “Read” da ta for the serial interface.
Equalizer Co ntrol Input 3
Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13.
SCLK
EQC2
23 ISerial Interface Clock Input
In Host mode, this clock signal is used to control data “Read” or “Write” oper-
ation for the Serial Interface. Maximum clock frequency is 20MHz.
Equalizer Co ntrol Input 2
Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13.
CS
EQC1
24 IChip Select Input
In Host mode, tie this pin “Low” to enable communication with the device via
the Serial Interface.
Equalizer Co ntrol Input 1
Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13.
INT
EQC0
25 O
I
Interrupt Output (active "Low")
In Host mode, this pin goes “Low” to indicate an alarm condition has
occurred within the device. Inte rrupt generation can be globally disabl ed by
setting the GIE bit to “0” in the command control register.
Equalizer Co ntrol Input 0
Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13.
NOTE: This pin is an open d rain output and requires an externa l 10kΩ pull-
up resistor.
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
RECEIVER
SIGNAL NAME PIN # TYPE DESCRIPTION
RLOS 63 OReceiver Loss of Signal
This signal is asserted ‘High’ for at least one RCLK cycle to indicate loss of
signal at the receive input.
RCLK 64 OReceiver Clock Output
RNEG
LCV
1OReceiver Negative Data Output
In dual-rail mode, this signal is the receiver negative-rail output data.
Line Code Violation Output
In single-rail mode, this signal goes ‘High’ for one RCLK cycle to indicate a
code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go “High”.
RPOS
RDATA
2OReceiver Positive Data Output
In dual-rail mode, this signal is the receive positive-rail output data sent to the
Framer.
Receiver NRZ Data Output
In single-rail mode, this signal is the receive NRZ format output data sent to
the Framer.
RTIP 4IReceiver Differential Tip Positive Input
Positive differential receive input from the line.
RRING 5IReceiver Differential Ring Negative Input
Negative differential receive input from the line.
RXMUTE 50 IReceive Muting
In Hardware mode, connect this pin ‘High’ to mute RPOS and RNEG outputs
to a “Low” state upon receipt of LOS condi tion to prevent data chattering.
Connect this pin to ‘Low’ to disable muting function.
NOTE: Internally pulled "Low" with 50kΩ resistor.
RCLKE 53 IReceive Clock Edge
In Hardware mode, with this pin set to ‘High’ the output receive data is
updated on the falling edge of RCLK. With this pin tied ‘Low’, output data is
updated on the rising edge of RCLK.
NOTE: Internally pulled “Low” with a 50kΩ resistor .
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TRANSMITTER
SIGNAL NAME PIN # TYPE DESCRIPTION
TTIP 8OTransmitter Tip Output
Positive differential transmit output to the line.
TRING 10 OTransmitter Ring Output
Negative differential transmit output to the line.
TPOS
TDATA
61 ITransmitter Positive Dat a Input
In dual-rail mode, this signal is the positive-rail input data for the transmitter.
Transmitter Data Input
In single-rail mode, this pin is used as the NRZ input data for the transmitter.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
TNEG
CODES
62 ITransmitter Negative NRZ Data Input
In dual-rail mode, this signal is the negative-rail input data for the transmitter.
In single-rail mode, this pi n can be left unconnected.
Coding Select
In Hardware mode and with single-rail mode sel ected, connecting this pin
"Low" enables HDB3 in E1 or B8ZS in T1 encoding and decoding. Connect-
ing this pin "High" selects AMI data format.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
TCLK 60 ITransmitter Clock Input
E1 rate at 2.048MHz ± 50ppm
T1 rate at 1.544MHz ± 32ppm
During normal operation, both in Host mode and Hardware mode, TCLK is
used for sampling input data at TPOS/TDATA and TNEG/CODES while
MCLK is used as the timing reference for the transmit pulse shaping circuit.
TCLKE 57 ITransmit Clock Edge
In Hardware mode, with this pin set to a "High", transmit input data is sam-
pled at the rising edge of TCLK. With this pin tied "Low", input data are sam-
pled at the falling edge of TCLK.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
TXON 58 ITransmitter Turn On
In Hardware mode, setting this pin "High" turns on the Transmit Section. In
this mode, when TXON = “0”, TTIP and TRING driver outputs will be tri-
stated.
NOTES:
1. Internally pulled "Low" with a 50kΩ resistor.
2. In Hardware mode only, the receiver is turned on at power-up.
XRT83L30
8
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TXTEST2
TXTEST1
TXTEST0
54
55
56
ITransmit Test Pattern pin 2
Transmit Test Pattern pin 1
Transmit Test Pattern pin 0
TXTEST[2:0] pins are used to generate and transmit test patterns according
to the following table:
TAOS (Transmit All Ones): Activating this condition enables the transmis-
sion of an All Ones Pattern.TCLK must not be tied "Low".
TLUC (Transmit Network Loop-Up Code): Activating this condition
enables the Network Loop-Up Code of "00001" to be transmitted to the line.
When Network Loop-Up code is being transmitted, the XRT83L30 will ignore
the Automatic Loop-Code de tection and Remote Loop-back activation
(NLCDE1=”1 ”, NLCDE0= ”1”, if act ivated) in order to avo id acti vating Re mote
Digital Loop-back automatically when the remote terminal responds to the
Loop-back request.
TLDC (Transmit Network Loop-Down Code): Activating this condition
enables the network Loop-Down Code of "001" to be transmitted to the line.
TDQRSS (T ransmit/Detect Quasi-Random Signal): Setting TXTEST2=”1”,
regardless of the state of TXTEST1 and TXTEST0, enables Quasi-Random
Signal Source generation and detection. In a T1 system QRSS pattern is a
220-1 pseudo-random bit sequence (PRBS) with no more than 14 consecu-
tive zeros. In a E1 system, QRSS is a 215-1 PRBS pattern.
When TXTEST2 is “1” and TDQRSS is active, setting TXTEST0 to “1” inverts
the polarity of transmitted QRSS pattern. Resetting to "0" sends the QRSS
pattern with no inversion.
When TXTEST2 is “1” and TDQRSS is active, transitions of TXTEST1 from
"0" to "1" results in a bit error to be inserted in the transmitted QRSS pattern.
The state of this pin is sampled on the rising edge of TCLK. To ensure the
insertion of a bit error, th is pin should be reset to a "0" before setting to a "1".
When TXTEST2 is “1”, TXTEST1 and TXTEST0 affect the transmitted QRSS
bit pattern independently.
TRANSMITTER
SIGNAL NAME PIN #TYPE DESCRIPTION
0 1
1 0
1 1
0 0
0
0
0
1
0 00 Transmit Data
TAOS
TLUC
TLDC
Test PatternTXTEST1 TXTEST0TXTEST2
1 0
1 1
1
1
0 11
TDQRSS
TDQRSS & INVQRSS
TDQRSS & INSBER
TDQRSS & INVQRSS & IN
S
XRT83L30
9
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
JITTER ATTENUATOR
SIGNAL NAME PIN # TYPE DESCRIPTION
JABW 46 IJitter Attenuator Bandwidth
In Hardware and E1 mode, when JABW=”0” the jitter attenuator bandwidth
is 10Hz (normal mode). Setting JABW to “1” selects a 1.5Hz Bandwidth for
the Jitter Attenuator and the FIFO length will be automatically set to 64 bits.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz, and the
state of this pin has no effect on the Bandwidth. See t able under JASEL1 pin,
below.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
JASEL1
JASEL0 47
48 IJitter Attenuator select pin 1
Jitter Attenuator select pin 0
In Hardware mode, JASEL0, JASEL1 and JABW pins are used to place the
jitter attenuator in the transmit path, the receive path or to disable it and set
the jitter attenuator bandwidth and FIFO size per the following table.
NOTE: These pins are internally pulled "Low" with 50kΩ resistors.
CLOCK SYNTHESIZER
SIGNAL NAME PIN # TYPE DESCRIPTION
MCLKE1 13 IE1 Master Clock Input
This input signal is an independent 2.048MHz clock for E1 system with
required accuracy of better than ±50ppm and a duty cycle of 40% to 60%.
MCLKE1 is used in the E1 mode. Its function is to provide internal timing for
the PLL clock recovery circuit, transmit pulse shaping, jitter attenuator block,
reference clock during transmit all ones data and timing reference for the
microprocessor in Host mode operation.
MCLKE1 is also input to a programmable frequency synthesizer that under
the control of the C LKSEL[2:0] inputs can b e used to ge n erate a master
clock from an accurate external source. In systems that have only one mas-
ter clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation.
NOTES:
1. See pin descriptions for pins CLKSEL[2:0].
2. Internally pulled “Low” with a 50kΩ resistor.
Disabled
Transmit
Receive
Receive
------
32/32
32/32
64/64
------
3
3
3
------
10
10
10
0
0
1
1
0
1
0
1
0
0
0
0
Disabled
Transmit
Receive
Receive
--------
32/64
32/64
64/64
------
3
3
3
------
1.5
1.5
1.5
0
0
1
1
0
1
0
1
1
1
1
1
JA Path JA BW (Hz) FIFO Size
T1/E1
JASEL1 JASEL0JABW T1 E1
XRT83L30
10
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MCLKT1 14 IT1 Master Cloc k In put
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.
NOTES:
1. See MCLKE1 description for further explanation for the usage of
this pin.
2. Internally pulled “Low” with a 50kΩ resistor.
MCLKOUT 16 OSynthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based on the mode of operation.
CLKSEL2
CLKSEL1
CLKSEL0
17
18
19
IClock Select input for Master Clock Synthesizer pin 2
Clock Select input for Master Clock Synthesizer pin 1
Clock Select input for Master Clock Synthesizer pin 0
In Hardware mode, CLKSEL[2:0] are input signals to a programmable fre-
quency synthesizer that can be used to generate a master clock from an
external accurate clock source according to the following table. The
MCLKRATE control signal is generated from the state of EQC[4:0] inputs.
See Table 5 for description of Transmit Equalizer Control bits.
In Host mode, the state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
CLOCK SYNTHESIZER
SIGNAL NAME PIN #TYPE DESCRIPTION
2048
2048
2048
1544
MCLKE1
(kHz)
8
16
16
56
8
56
64
64
128
256
256
128
2048
2048
1544
1544
MCLKT1
(kHz)
1544
X
X
X
1544
X
X
X
X
X
X
X
2048
1544
2048
CLKOUT
(KHz)
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
0
1
1
CLKSEL0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
CLKSEL1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
CLKSEL2
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
1544
2048
X
X
2048
1544
0
1
0
1
MCLKRATE
1
0
1
0
0
1
0
1
1
0
1
0
0
1
XRT83L30
11
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
REDUNDANCY SUPPORT
SIGNAL NAME PIN # TYPE DESCRIPTION
DMO 11 ODriver Failure Monitor
This pin transitions "High" if a sh ort circuit condition is detected in the trans-
mit driver, or no transmit output pu lse is detected for more than 128 TCLK
cycles.
TERMINATIONS
SIGNAL NAME PIN # TYPE DESCRIPTION
GAUGE 49 ITwisted Pair Cable Wire Gauge Select
In Hardware mode, connect this pin "High" to select 26 Gauge wire. Connect
this pin “Low” to select 22 and 24 gauge wire.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
TRATIO 26 ITransmitter Transformer Ratio Select
In external termination mode, setting this pin "High" selects a transformer
ratio of 1:2 for the transmitter. A "Low" on this pin sets the transmitter trans-
former ratio to 1:2.45. In the internal termination mode the transmitter trans-
former ratio is permanently set to 1:2 and the state of this pin is ignored.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
RXTSEL 44 IReceiver Termination Select
In Hardware mode when this pin is “Low” the receive line termination is
determined only by the external resistor. When “High”, the receive termina-
tion is realized by internal resistors or the combination of internal and exter-
nal resistors according to RXRES[1:0]. These conditions are described in the
following table:
NOTE: This pin is internally pulled "Low" with a 50kΩ resistor.
TXTSEL 45 ITransmit Termination Select
In Hardware mode when this pin is “Low” the tran smit line termination is
determined only by external resistor . When “High”, the transmit termination is
realized only by an internal resistor. These conditions are summarized in the
following table:
NOTE: This pin is internally pulled "Low" with a 50kΩ resistor.
RXTSEL RX Termination
0
1
External
Internal
TXTSEL TX Termination
0
1
External
Internal
XRT83L30
12
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TERSEL1
TERSEL0 43
42 ITermination Impedance Select pin 1
Termination Impedance Select pin 0
In the Hardware mode and in the Internal Termination mode (TXTSEL=”1”
and/or RXTSEL=”1”) TERSEL[1:0] control the transmit and receive termina-
tion impedance according to the following table:
In the Internal Termination mode, the receive termination is realized com-
pletely by internal resistors or the combination of internal and one fixed exter-
nal resistor (see description for RXRES[1:0] pins). In the internal termination
mode the transformer ratio of 1:2 and 2:1 is required for the transmitter and
receiver respectively with the transmitter output AC coupled to the trans-
former.
NOTE: This pin is internally pulled "Low" with a 50kΩ resistor.
RXRES1
RXRES0 51
52 IReceive External Resistor Control pin 1
Receive External Resistor Control pin 0
In Hardware mode, RXRES[1:0] pins selects the required value of the exter-
nal fixed resistor for the receiver according to the following table. This mode
is only available in the internal impedance mode by pulling RXTSEL “High”.
NOTE: Internally pulled “Low” with 50kΩ resistor.
TERMINATIONS
SIGNAL NAME PIN #TYPE DESCRIPTION
TERSEL1
0
1
Ω
75 Ω
0
1
0
TerminationTERSEL0
0
11
100Ω
120Ω
110
RXRES1
0
0
RX Fixed Resistor
No External Fixed Resistor
240Ω
RXRES0
0
1
1
1
210Ω
150Ω
0
1
XRT83L30
13
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
CONTROL FUNCTION
RESET 41 IHardware Reset (Active "Low")
When this pin is tied “Low” for more than 10µs, the device is put in the reset
state.
Pulling RESET “Low” while the ICT pin is also “Low” will put the chip in fac-
tory test mode. This condition should never happe n during normal operation.
NOTE: Internally pulled “High” with a 50kΩ resistor.
SR/DR 28 ISingle-Rail/Dual-Rail Data Format
In Hardware mode, connect this pin "Low" to select transmit and receive
data format in dual-rail mode. In this mode, HDB3 or B8ZS encoder and
decoder are not available.
Connect this pin "High" to select single-rail data format.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
LOOP1
LOOP0 29
30 ILoop-back Cont rol pin 1
Loop-back Cont rol pin 0
In Hardware mode, LOOP[1:0] pins are used to control the Loop-back fun c-
tions according to the following table:
NOTE: Internally pulled "Low" with a 50kΩ resistor.
EQC4
SDI
21 IEqualizer Co ntrol Input pin 4
In Hardware mode, this pin together with EQC[3:0] are used for controlling
the transmit pulse shapi ng, transmit line build-out (LBO), receive monitoring
and also to select T1, E1 or J1 modes of operation. See Table 5 for descrip-
tion of Transmit Equalizer Control bits.
Serial Data Input
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
EQC3
SDO
22 I
O
Equalizer Co ntrol Input pin 3
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Data Output
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
EQC2
SCLK
23 IEqualizer Co ntrol Input pin 2
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Interface Clock Input
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
LOOP1 LOOP0
0 0
0 1
1 0
1 1
MODE
Normal Mode
Local Loop-Back
Remote Loop-Ba
c
Digital Loop-Back
XRT83L30
14
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
EQC1
CS
24 IEqualizer Control Inp ut pin 1
See EQC4/SDI description for further explanation for the usage of this pin.
Chip Select Input
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
EQC0
INT
25 I
O
Equalizer Control Inp ut pin 0
See EQC4/SDI description for further explanation for the usage of this pin.
Interrupt Output
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
ALARM FUNCTION/OTHER
SIGNAL NAME PIN # TYPE DESCRIPTION
ATAOS 27 IAutomatic Transmit “All On es” Pattern
In Hardware mode, a "High" level on this pin enables the automatic trans-
mission of an "All Ones" AMI pattern from the transmitter when the receiver
has detected an LOS condition. A "Low" level on this pin disables this func-
tion.
NOTE: This pin is internally pulled “Low” with a 50kΩ resistor.
ICT 59 IIn-Circuit Testing (active "Low")
When this pin is tied “Low”, all outp ut pi ns ar e forced to a “High” impedance
state for in-circuit testing.
Pulling RESET “Low” while ICT pin is also “Low” will put the chip in factory
test mode. This condition sh ould never happen during normal operation.
NOTE: Internally pulled “High” with a 50kΩ resistor.
CONTROL FUNCTION
XRT83L30
15
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
NLCDE1
NLCDE0 33
34 INetwork Loop Code Detec t io n Ena bl e pi n 1
Network Loop Code Detec t io n Ena bl e pi n 0
NLCDE[1:0] pins are used to control the Loop-Code detection according to
the following table:
When NLCDE1=”0” and NCLDE0=”1”, or NLCDE1=”1” and NLCDE0=”0”, the
chip is manually programed to monitor the receive data for the Loop-Up or
Loop-Down code respectively. When the presence of the “00001” or “001”
pattern is detected for more than 5 seconds, the NLCD pin is set to “1” and
the host has the option to activate the loop-back function manually.
Setting the NLCDE1=”1” and NLCDE0= ”1” enables the Automati c Loop-
Code detection and Remote-Loop-Back activation mode. As this mode is ini-
tiated, the state of the NLCD pin is reset to “0” and the chip is programmed to
monitor the receive data for the Loop-Up Code. If the “00001” pattern is
detected for longer than 5 seconds, the NLCD pin is set to “1”, Remote Loop-
Back is activated and the chip is automatically programed to monitor the
receive data for the Loop-Down code. The NLCD pin stays “High” even after
the chip stops receiving the Loop-Up code. The remote Loop-Back condition
is removed when the chip receives the Loop-Down code for more than 5 sec-
onds or if the Automatic Loop-Code detection mode is terminated.
INSBPV 35 IInsert Bipolar Violation
When this pin transitions from "0" to "1", a bipolar violation is inserted in the
transmitted data stream. Bipolar violation can be inserted either in the QRSS
pattern, or input data when operating in single-rail mode. The state of this pin
is sampled on the rising edg e of TCLK.
NOTE: To ensure the insertion of a bipolar viol ation, this pin should be reset
to a "0" prior to setting to a "1".
ALARM FUNCTION/OTHER
SIGNAL NAME PIN #TYPE DESCRIPTION
NLCDE1 NLCDE0 Function
0 0 Disable Loop-Code
Detection
0 1 Detect Loop-Up Code in
Receive Data
1 1 Automatic Loop-Code
Detection
1 0 Detect Loop-Down Code in
Receive Data
XRT83L30
16
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
NLCD 38 ONetwork Loop-Code De te c t io n Outp ut pin
This pin operates differently in the Manual or the Automatic Network Loop-
Code detection modes.
In the Manual Loop-Code detection mode (NLCDE1 =”0” and NLCDE0 =”1”,
or NLCDE1 =”1” and NLCDE0 =”0”) this pin gets set to “1” as soon as the
Loop-Up (“00001”) or Loop-Down (“001”) code is detected in the receive data
for longer than 5 seconds. The NLCD pin stays in the “1” state for as long as
the chip detects the presence of the Loop -Code in the receive data and it is
reset to “0” as soon as it stops receiving it.
When the Automatic Loop-Code detection mode (NLCDE1 =”1” and
NLCDE0 =”1”) is initiated, the NLCD output pin is reset to “0” and the chip is
programmed to monitor the receive input data for the Loop-Up Code. The
NLCD pin is set to a “1” to indicate that the Network Loop Code is detected
for more than 5 seconds. Simultaneously the Remote Loop-Back condition is
automatically activated and the chip is programmed to monitor the receive
data for the Network Loop-Down Code. Th e NLCD pin stays in the “1” state
for as long as the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up Code. Remote Loop-Back is removed if the chip
detects the “001” pattern for longer than 5 seconds in the receive data.
Detecting the “001” pattern also results in resetting the NLCD output pin.
AISD 39 OAlarm Indication Signal Detect Output pin
This pin is set to "1" to indicate that an All Ones Signal is detected by the
receiver. The value of this pin is based on th e cu rre nt status of Alarm Indica-
tion Signal detector.
QRPD 40 OQuasi-random Pattern Detection Output pin
This pin is set to "1" to indicate that the receiver is currently in synchroniza-
tion with the QRSS pattern. The value of this pin is based on the current sta-
tus of Quasi-random pattern detector.
POWER AND GROUND
SIGNAL NAME PIN # TYPE DESCRIPTION
TAGND 7**** Transmitter Analog Ground
TAVDD 9**** Transmitter Analog Positive Supply (3.3V + 5%)
RAGND 6**** Receiver Analog Ground
RAVDD 3**** Receiver Analog Positive Supply (3.3V± 5%)
VDDPLL 12 **** Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%)
GNDPLL 15 **** Analog Ground for Master Clock Synthesizer PLL
DVDD 36 **** Digital Positive Supply (3.3V± 5%)
AVDD 31 **** Analog Positive Supply (3.3V± 5%)
DGND 37 **** Digital Ground
AGND 32 **** Analog Ground
ALARM FUNCTION/OTHER
SIGNAL NAME PIN #TYPE DESCRIPTION
XRT83L30
17
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
FUNCTIONAL DESCRIPTION
The XRT83L30 is a fully integrated single channel long-haul and short-haul transceiver intended for T1, J1 or
E1 systems. Simplified block diagrams of the device are shown in Figure 1, Host mode and Figure 2,
Hardware mode. Th e XRT83L30 can rece ive signals th at have be en attenuate d from 0 t o 36dB at 772 kHz (0
to 6000 feet cable loss) for T1 and from 0 to 43dB at 1024kHz for E1 systems.
In T1 applications, the XR T83L30 can generate five tr ansmit pulse shapes to meet th e short-haul Digit al Cross-
connect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, -15dB
and -22.5dB as required by FCC rules. It also provid es progr ammabl e transmit output pulse generato r that can
be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The
operation and co nfiguratio n of th e XRT83L30 can be controlled through a serial microprocessor Host interface
or, by Hardware control.
MASTER CLOCK GENERATOR
Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or
E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit.
There are two master clock input s MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are
available these clocks can be connected to the respective pins.
In systems that have only one master clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz,
16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according
to Table 1.
NOTE: EQC[4:0] determine the T1/E1 operating mode. See Table 5 for details.
FIGURE 4. TWO INPUT CLOCK SOURCE
FIGURE 5. ONE INPUT CLOCK SOURCE
MCLKE1
MCLKT1
MCLKOUT 1.544MHz
or
2.048MHz
2.048MHz
+/-50ppm
1.544MHz
+/-50ppm
Two Inp ut Clock Sources
MCLKE1
MCLKT1
MCLKOUT 1.544MHz
or
2.048MHz
One Input C lock Source
Input Clock O ptions
8kHz
16kHz
56kHz
64kHz
128kHz
256kHz
1.544MHz
2.048MHz
XRT83L30
18
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal ca n be coup led to th e r eceiver throug h a ca pacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS/RDATA and RNEG/LCV pins. Clock recovery is accomplished by a digital phase-
locked loop (DPLL) which does no t require any external components and can tolerate high levels of input jitter
that meets or exceeds the ITU- G.823 and TR-TSY0004 99 standards.
In Hardware mode only, this receive channel is turned on upon power-up and is always on. In Host mode, the
receiver can be turned on or off with the RXON bit. SEE”MICROPROCESSOR REGISTER #2 BIT
DESCRIPTION” ON PAGE 48.
TABLE 1: MASTER CLOCK GENERATOR
MCLKE1
KHZ
MCLKT1
KHZCLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE MASTER CLOCK
KHZ
2048 2048 0 0 0 0 2048
2048 2048 0 0 0 1 1544
2048 1544 0 0 0 0 2048
1544 1544 0 0 1 1 1544
1544 1544 0 0 1 0 2048
2048 1544 0 0 1 1 1544
8 x 0 1 0 0 2048
8 x 0 1 0 1 1544
16 x 0 1 1 0 2048
16 x 0 1 1 1 1544
56 x 1 0 0 0 2048
56 x 1 0 0 1 1544
64 x 1 0 1 0 2048
64 x 1 0 1 1 1544
128 x 1 1 0 0 2048
128 x 1 1 0 1 1544
256 x 1 1 1 0 2048
256 x 1 1 1 1 1544
XRT83L30
19
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
RECEIVE MONITOR MODE
In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles
input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1
applications, refer to Table 5 for details. This feature is available in both Hardware and Host modes.
RECEIVER LOSS OF SIGNAL (RLOS)
For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both
analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to
count for 32 consecutive ze ros in E1 (40 96 bit s in Ex tended Los mode, EXLOS = “1” ) or 175 consecutive zeros
in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above
the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more
than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in
hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more
than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and
register status will change. If the RLOS register enable is set high (en abled), the alarm will trigger an interrupt
causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically
reset upon read (RUR), and the INT pin will return high.
Analog RLOS
Setting the Rece iv e r In pu t to -15d B T1 /E1 Short Haul Mode
By setting the receiver input to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal.
NOTE: This setting refers to cable loss (frequency), not flat loss (resistive).
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See Figure 6 for a
simplified diagram.
Setting the Rece iv e r Inpu t to -29dB T1/E1 Ga in Mode
By setting the receiver input to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and
make adjustments by adding gain up to a maximum of +29d B normalizing the T1/E1 input signal.
NOTE: This is the only setting that refers to flat loss (resistive). All other mo des refer to cable loss (frequency).
FIGURE 6. SIMPLIFIED DIAGRAM OF -15dB T1/E1 SHORT HAUL MODE AND RLOS CONDITION
Normalized up to +15dB Max
Normalized up to +15dB Max
Declare LO S
Clear LOS
-9dB
+3dB
Clear LOS
Declare LO S
+3dB
-9dB
XRT83L30
20
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See Figure 7 for a simplified diagram.
Setting the Receiver Input to -36dB T1/E1 Long Haul Mode
By setting the receiver input to -36dB T1/E1 long haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +3 6d B no r malizin g th e T1 input signal. This setting
refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to
0dB by adding the maximum gain (+36dB), the receiver will declare RLOS if the signal is attenuated by an
additional -9dB. The total cable loss at RLOS declaration is typically -4 5dB (-36dB + -9dB). A 3dB hysteresis
was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a
total cable attenuation of -42dB. See Figure 8 for a simplified diagram.
E1 Extended RLOS
E1: Setting the Receiver Input to Extended RLOS
By setting the receiver input to extended RLOS, the equalizer will detect the incoming amplitude and make
adjustments by adding gain up to a maximum of +43dB normalizing the E1 input signal. This setting refers to
FIGURE 7. SIMPLIFIED DIAGRAM OF -29dB T1/E1 GAIN MODE AND RLOS CONDITION
FIGURE 8. SIMPLIFIED DIAGRAM OF -36dB T1/E1 LONG HAUL MODE AND RLOS CONDITION
Normalized up to +29dB Max
Normalized up to +29dB Max
Declare LO S
Clear LOS
-9dB
+3dB
Clear LOS
Declare LO S
+3dB
-9dB
Normalized up to +36dB Max
Normalized up to +36dB Max
Declare LO S
Clear LOS
-9dB
+3dB
Clear LOS
Declare LO S
+3dB
-9dB
XRT83L30
21
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
cable loss (frequency), no t flat loss (resistive ). Once the E1 input signal has been normali zed to 0dB by adding
the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB.
The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See Figure 9 for a simplified diagram.
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes by controlling the TNEG/CODE pin or
the CODE interface bit. The decoder function is only active in single-rail Mode. When selected, receive data in
this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1 systems. Bipolar violations that do
not conform to the coding scheme will be reported as Line Code Violation at the RNEG/LCV pin. The length of
the LCV pulse is one RCLK cycle for each code violation. Excessive number of zeros in the receive data
stream is also reported as an error at the same output pin. If AMI decoding is selected in single rail mode,
every bipolar violation in the receive data stream will be reported as an error at the RNEG/LCV pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes. In Host mode, the samp ling edge of RCLK outp ut
can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE interface bit, receive
data output at RPOS/RDATA and RNEG/LCV are updated on the falling edge of RCLK. Writing a “0” to the
RCLKE register, updates the receive data on the rising edge of RCLK. In Hardware mode the same feature is
available under the control of the RCLKE pin.
FIGURE 9. SIMPLIFIED DIAGRAM OF EXTENDED RLOS MODE (E1 ONLY)
FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING
Normalized up to +45dB Max
Normalized up to +45dB Max
Declare LO S
Clear LOS
-9dB
+3dB
Clear LOS
Declare LO S
+3dB
-9dB
RCLKRRCLKF
RCLK
RPOS
or
RNEG
RDY
RHO
XRT83L30
22
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JITTER ATTENUATOR
To re duce phase and freque ncy jitter in the recover ed clock, the jitter attenua tor can be placed in the r eceive
signal path. The jitter at te nu ator uses a d a ta FIFO (F irs t In F irst Out) with a pr og ra m ma b l e d e pth th a t ca n vary
between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled
altogether depending upon system requirements. The jitter attenuator, other than using the master clock as
reference, requires no external components. With the jitter attenuator selected, the typical throughput delay
from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write
pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or u nder-flowing, the bandwid th of
the jitter attenuator is widened to track the short term input jitter, thereby avoiding da ta corruption. When this
situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside
the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth
requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced
through the JABW control signal. When JABW is set “High” the bandwidth of the jitter attenuator is reduced
from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FI FO
length will not be available in this mode.
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH)
The XRT83L30 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed
which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the
32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap
width is shown in Table 2.
NOTE: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path.
TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH MAXIMUM GAP WIDTH
32-Bit 20 UI
64-Bit 50 UI
XRT83L30
23
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
ARBITRARY PULSE GENERATOR
In T1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. Each segment
is set by a 7-Bit binary word by programming the appropriate register. This allows the syst em designer to set
the overshoot, amplitude, and undersh oot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit
is set to “1”, the segment will move in a positive direct ion relative to a flat line (zero) condition. If this sign-bit is
set to “0”, the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 11.
NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter output will result in an all zero pattern
to the line.
TRANSMITTER
DIGITAL DATA FORMAT
Both the transmitter and receiver can b e configured to ope rate in dual or single-rail data formats. This feature is
available under both Hardware and Host control modes. The dual or single-rail data format is determined by
the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In single-rail mode,
transmit clock and NRZ data are applied to TCLK and TPOS/TDATA pins respectively. In single-rail and
Hardware mode the TNEG/CODE input can be used as the CODES function. With TNEG/CODE tied “Low”,
HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes respectively. With TNEG /C ODE tied
“High”, the AMI coding scheme is selected. In both dual or single-rail modes of operations, the transmitter
converts digital input d ata to a bipolar format before being transmitted to the line.
TRANSMIT CLOCK (TCLK) SAMPLING EDGE
Serial transmit data at TPOS/TDATA and TNEG/CODE are clocked into the XRT83L30 under the
synchronization of TCLK. With a “0” written to the TCLKE interface bit, or by pulling the TCLKE pin “Low”, input
data is sampled on the falling edge of TCLK. The sampling edge is inverted with a “1” written to TCLKE
interface bit, or by connecting the TCLKE pin “High”.
FIGURE 11. ARBITRARY PULSE SEGMENT ASSIGNMENT
1
234
5
678
Segment Register
1 0xn8
2 0xn9
3 0xna
4 0xnb
5 0xnc
6 0xnd
7 0xne
8 0xnf
XRT83L30
24
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TRANSMIT HDB3/B8ZS ENCODER
The Encoder function is availab le in both Hardware and Host modes basis by controlling the TNEG/CODE pin
or CODES interface bit. The encod er is only availa ble in single- rail mode. In E1 m ode and with HDB3 encoding
selected, any sequence with four or more consecutive zeros in the input serial data from TPOS/TDATA, will be
removed and r epl aced with 000V or B00 V, where “B” indicates a pulse con f ormi ng with the bipo lar ru le and “V”
representing a pulse violating the rule. An example of HDB3 Encoding is shown in Table 3. In a T1 system, an
input data sequence with eight or more consecutive zeros will be removed and replaced using the B8ZS
encoding rule . An example of Bipolar with 8 Zero Substitution (B8ZS) encoding scheme is shown in Table 4.
Writing a “1” into the CODES interface bit or connecting the TNEG/CODE pin to a “High” level selects the AMI
coding for both E1 or T1 systems.
DRIVER FAILURE MONITOR (DMO)
FIGURE 12. TRANSMIT CLOCK AND INPUT DATA TIMING
TABLE 3: EXAMPLES OF HDB3 ENCODING
NUMBER OF PULSE BEFORE NEXT 4 ZEROS NEXT 4 BITS
Input 0000
HDB3 (case1) odd 000V
HDB3 (case2) even B00V
TABLE 4: EXAMPLES OF B8ZS ENCODING
CASE 1 PRECEDING PULSE NEXT 8 BITS
Input + 00000000
B8ZS 000VB0VB
AMI Output + 000+ -0- +
CASE 2
Input - 00000000
B8ZS 000VB0VB
AMI Output - 000- +0+ -
TCLKRTCLKF
TCLK
TPOS/TDATA
or
TNEG
TSU THO
XRT83L30
25
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and
TRING. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter has no output for more than 128 clock cycles, the corresponding DMO pin
goes “High” and remains “Hig h” until a valid transmit pulse is detected. In Host mode, the failure of the transmit
channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any transition on the
DMO interface bit will generate an interrupt. The driver failure monitor is supported in both Hardware and Host
modes.
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT
The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the EQC[4:0] pins determine the transmit pulse shape. In Host mode transmit pulse shape can be
controlled using the interface b its EQC[4:0]. The chip supports five fixed transmit pulse settings for T1 Short-
haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes.
Transmit Line Build-Outs for T1 long-haul application are supported from 0 dB to -22. 5dB in three 7 .5dB steps.
The choice of the transmit pulse shape and LBO under the control of the interface bits are summarized in
Table 5. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-to-Customer
Installation specification, Annex-E.
NOTE: EQC[4:0] determine the T1/E1 operating mode of the XRT83L30. When EQC4 = “1” and EQC3 = “1”, the XRT83L30
is in the E1 mode, otherwise it is in the T1/J1 mode.
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS
EQC4 EQC3 EQC2 EQC1 EQC0 E1/T1 MODE & RECEIVE
SENSITIVITY TRANSMIT LBO CABLE CODING
0 0000T1 Long Haul/36dB 0dB 100Ω/ TP B8ZS
0 0001T1 Long Haul/36dB -7.5dB 100Ω/ TP B8ZS
0 0010T1 Long Haul/36dB -15dB 100Ω/ TP B8ZS
0 0011T1 Long Haul/36dB -22.5dB 100Ω/ TP B8ZS
0 0100T1 Long Haul/45dB 0dB 100Ω/ TP B8ZS
0 0101T1 Long Haul/45dB -7.5dB 100Ω/ TP B8ZS
0 0110T1 Long Haul/45dB -15dB 100Ω/ TP B8ZS
0 0111T1 Long Haul/45dB -22.5dB 100Ω/ TP B8ZS
0 1000T1 Short Haul/15dB 0-133 ft./ 0.6dB 100Ω/ TP B8ZS
0 1001T1 Short Haul/15dB 133-266 ft./ 1.2dB 100Ω/ TP B8ZS
0 1010T1 Short Haul/15dB 266-399 ft./ 1.8dB 100Ω/ TP B8ZS
0 1011T1 Short Haul/15dB 399-533 ft./ 2.4dB 100Ω/ TP B8ZS
0 1100T1 Short Haul/15dB 533-655 ft./ 3.0dB 100Ω/ TP B8ZS
0 1101T1 Short Haul/15dB Arbitrary Pulse 100Ω/ TP B8ZS
XRT83L30
26
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
0 1110T1 Gain Mode/29dB 0-133 ft./ 0.6dB 100Ω/ TP B8ZS
0 1111T1 Gain Mode/29dB 133-266 ft./ 1.2dB 100Ω/ TP B8ZS
1 0000T1 Gain Mode/29dB 266-399 ft./ 1.8dB 100Ω/ TP B8ZS
1 0001T1 Gain Mode/29dB 399-533 ft./ 2.4dB 100Ω/ TP B8ZS
1 0010T1 Gain Mode/29dB 533-655 ft./ 3.0dB 100Ω/ TP B8ZS
1 0011T1 Gain Mode/29dB Arbitrary Pulse 100Ω/ TP B8ZS
1 0100T1 Gain Mode/29dB 0dB 100Ω/ TP B8ZS
1 0101T1 Gain Mode/29dB -7.5dB 100Ω/ TP B8ZS
1 0110T1 Gain Mode/29dB -15dB 100Ω/ TP B8ZS
1 0111T1 Gain Mode/29dB -22.5dB 100Ω/ TP B8ZS
1 1000E1 Long Haul/36dB ITU G.703 75Ω Coax HDB3
1 1001E1 Long Haul/36dB ITU G.703 120Ω TP HDB3
1 1010E1 Long Haul/43dB ITU G.703 75Ω Coax HDB3
1 1011E1 Long Haul/43dB ITU G.703 120Ω TP HDB3
1 1100 E1 Short Haul ITU G.703 75Ω Coax HDB3
1 1101 E1 Short Haul ITU G.703 120Ω TP HDB3
1 1110 E1 Gain Mode ITU G.703 75Ω Coax HDB3
1 1111 E1 Gain Mode ITU G.703 120Ω TP HDB3
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS
EQC4 EQC3 EQC2 EQC1 EQC0 E1/T1 MODE & RECEIVE
SENSITIVITY TRANSMIT LBO CABLE CODING
XRT83L30
27
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83L30 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal t erminations can be disabled to allo w the
use of existing components and/or designs.
RECEIVER
INTERNAL RECEIVE TERMINATION MODE
In Hardware mode, RXTSEL (Pin 44) can be tied “High” to select internal termination mode or tied “Low” to
select external termination mode. By default the XR T8 3L30 is set fo r exter nal termina tion mod e at power up or
at Hardware reset.
In Host mode, bit 7 in the appropriate register, (Table 20, “Microprocessor Register #1, Bit Description,”
on page 47), is set “High” to select the internal termination mode for the receive channel.
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and exter nal resistors as shown in Table 7.
TABLE 6: RECEIVE TERMINATION CONTROL
RXTSEL RX TERMINATION
0EXTERNAL
1INTERNAL
FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE
T1 TTIP
TRING
5
8
1:2
75 Ω, 100 Ω
110 Ω or 120 Ω
4
1
0.68µF
Rint
Rint
TTIP
TRING
TX
Line Driver
T2 RTIP
RRING
1
4
1:1
8
5
RTIP
RRING
RX
Equalizer Rint
TPOS
TNEG
TCLK
RPOS
RNEG
RCLK 75 Ω, 100 Ω
110 Ω or 120 Ω
XRT83L30
28
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Figure 14 is a simplified diagram for T1 (100Ω) in the external receive termination mode. Figure 15 is a
simplified diagram for E1 (75Ω) in the external receive te rmination mode.
TABLE 7: RECEIVE TERMINATIONS
RXTSEL TERSEL1 TERSEL0 RXRES1 RXRES0 Rext Rint MODE
0 x x x x Rext ∞T1/E1/J1
1 0 0 0 0 ∞100ΩT1
1 0 1 0 0 ∞110ΩJ1
1 1 0 0 0 ∞75ΩE1
1 1 1 0 0 ∞120ΩE1
1 0 0 0 1 240Ω172ΩT1
1 0 1 0 1 240Ω204ΩJ1
1 1 0 0 1 240Ω108ΩE1
1 1 1 0 1 240Ω240ΩE1
1 0 0 1 0 210Ω192ΩT1
1 0 1 1 0 210Ω232ΩJ1
1 1 0 1 0 210Ω116ΩE1
1 1 1 1 0 210Ω280ΩE1
1 0 0 1 1 150Ω300ΩT1
1 0 1 1 1 150Ω412ΩJ1
1 1 0 1 1 150Ω150ΩE1
1 1 1 1 1 150Ω600ΩE1
FIGURE 14. SIMPLIFIED DIAGRAM FOR T1 IN THE EXTERNAL TERMINATION MODE (RXTSEL= 0)
3.1Ω
3.1Ω
TTIP
TRING
RTIP
RRING
XRT83L30 LIU
100Ω
100Ω
100Ω
1:2 or
1:2.45
1:1
XRT83L30
29
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TRANSMITTER
TRANSMIT TERMINATION MODE
In Hardware mode, TXTSEL (Pin 45) can be tied “High” to select internal termination mode or tied “Low” for
external termination. In Host mode, bit 6 in the appropriate register is set “High” to select the internal
termination mode for the transmit channel, see Table 19, “Microprocessor Register #1 bit description,” on
page 46.
For internal termination, the transformer turns ratio is always 1:2. In internal mode, no external resistors are
used. An external capacitor of 0.68µF is used for proper operation of the internal termination circuitry, see
Figure 13.
EXTERNAL TRANSMIT TERMINATION MODE
By default the XRT83L30 is set for external termination mode at power up or at Hardware reset.
When external transm it termina tion mode is selected, the interna l termination circuitry is disab led. The value of
the extern al resistors is chosen for a specific applica tion according to the turns ratio selected by TRATIO (Pin
26) in Hardware mode or bit 0 in the appropriate register in Host mode, see Table 10 and Table 21,
“Microprocessor Register #3 bit description,” on page 50. Figure 14 is a simplified block diagram for T1
(100Ω) in t he external termin ation mode. Figure 15 is a simplified block diagram for E1 (75Ω) in the external
termination mode.
FIGURE 15. SIMPLIFIED DIAGRAM FOR E1 IN EXTERNAL TERMINATION MODE (RXTSEL= 0)
TABLE 8: TRANSMIT TERMINATION CONTROL
TXTSEL TX TERMINATION TX TRANSFORMER RATIO
0EXTERNAL 1:2.45
1INTERNAL 1:2
TABLE 9: TERMINATION SELECT CONTROL
TERSEL1 TERSEL0 TERMINATION
0 0 100Ω
0 1 110Ω
1 0 75Ω
1 1 120Ω
9.1Ω
9.1Ω
TTIP
TRING
RTIP
RRING
75Ω
XRT83L30 LIU
75Ω
75Ω
1:2
1:1
XRT83L30
30
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Table 11 summarizes the transmit terminations.
REDUNDANCY APPLICATIONS
Telecommunication s ystem design requires signal integrity and reliability. When a T1/E1 primary line card has
a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without
losing data. System designers can achieve this by implementing common redundancy schemes with the
XRT83 L30 Line In terface Unit (LIU) . The XR T83L30 of fers features that are t ailored to redun dancy applications
while reducing the number of components and providing system designers with solid reference designs. These
features allow system designers to implement redundancy applications that ensure reliability. The Internal
Impedance mode eliminates the need for external relays when using the 1: 1 an d 1+ 1 re du n da nc y sche m e s.
TABLE 10: TRANSMIT TERMINATION CONTROL
TRATIO TURNS RATIO
01:2
11:2.45
TABLE 11: TRANSMIT TERMINATIONS
TERSEL1 TERSEL0 TXTSEL TRATIO Rint ΩnRext ΩCext
0=EXTERNAL SET BY
CONTROL
BITS
n, Rext, AND Cext ARE SUGGESTED
SETTINGS
1=INTERNAL
T1
100 Ω
0 0 0 0 0Ω2.45 3.1Ω0
0 0 0 1 0Ω23.1Ω0
0 0 1 x 25Ω2 0Ω0.68µF
J1
110 Ω
0 1 0 0 0Ω2.45 3.1Ω0
0 1 0 1 0Ω23.1Ω0
0 1 1 x 27.5Ω2 0Ω0.68µF
E1
75 Ω
1 0 0 0 0Ω2.45 6.2Ω0
1 0 0 1 0Ω29.1Ω0
1 0 1 x 18.75Ω2 0Ω0.68µF
E1
120 Ω
1 1 0 0 0Ω2.45 6.2Ω0
1 1 0 1 0Ω29.1Ω0
1 1 1 x 30Ω2 0Ω0.68µF
XRT83L30
31
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
PROGRAMMING CONSIDERATIONS
In many applications switching the control of the transmitter outputs and the receiver line impedance to
hardware control will provide faster transmitter ON/OFF switching.
In Host Mode, there are two bits in register 18 (12H) that control the transmitter outputs and the Rx line
impedance select, TXONCNTL (Bit 5) and TERCNTL (Bit 4).
Setting bit-5 (TXONCNTL) to a “1” transfers the control of the T ransmit On/Of f function to the TXON Hardware
control pin (pin 58 ).
Setting bit-4 (TERCNTL) to a “1” transfers the control of the Rx line impedance select (RXTSEL) to the
RXTSEL Hardware control pin (pin 44).
Either mode works well with redundancy applications. The user can determine which mode has the fastest
switching time for a unique application.
TYPICAL REDUNDANCY SCHEMES
■·1:1 One backup card for every primary card (Facility Protection)
■·1+1 One backup card for every primary card (Line Protection)
■·N+1One backup card for N primar y cards
1:1 REDUNDANCY
A 1:1 facility protection redundancy scheme has one backup card for every primary card. When using 1:1
redundancy, the backup card has its transmitters tri-st at ed an d it s rece ivers in high imped ance . This eliminates
the need for external relays and provides one bill of materials for all interface modes of operation. The transmit
and receive sections of the LIU device are descri bed separately.
1+1 REDUNDANCY
A 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on
the backup card are monitoring the receiver inputs. Therefore, the receivers on both cards need to be active.
The transmit outputs require no external resistors. The transmit and receive sections of the LIU device are
described separately.
TRANSMIT 1:1 & 1+1 REDUNDANCY
For 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for
Internal Impedance mode. The transmitters on the backup card should be tri-stated. Select the appropriate
impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for
blocking DC bias. See Figure 16 for a simplified block diagram of the transmit section for 1:1 and 1+1
redundancy scheme.
NOTE: For simplificatio n , th e over voltage protection circuitry was omitted.
XRT83L30
32
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
RECEIVE 1:1 & 1+1 REDUNDANCY
For 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for Internal Impedance
mode. The receivers on the backup card should be programmed for External Impedance mode. Since there is
no external resistor in the circuit, the receivers on the backup card will be high impedance. This key design
feature eliminates the need for relays and provides one bill of materials for all interface modes of operation.
Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup
card to Internal Impedance mode, then the primary card to External Impedance mode. See Figure 17 for a
simplified block diagram of the receive section for a 1:1 and 1+1 redundancy scheme.
NOTE: For simplification, the over vo ltage protection circuitry was omitted.
N+1 REDUNDANCY
FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT SECTION FOR 1:1 & 1+1 REDUNDANCY
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR 1:1 AND 1+1 REDUNDANCY
T1/E1 Line
Backplane Interface
Primary Card
Backup Card XRT83L30
XRT83L30
Tx
Tx
Line Interface Card
0.68µF
0.68µF
TxTSEL=1, Internal
TxTSEL=1, Internal
1:2
RxTSEL=0, External
RxTSEL=1, Internal
Backplane Interface
Primary Card
Backup Card XRT83L30
XRT83L30
Rx
Line Interface Card
T1/E1 LineRx
1:1
XRT83L30
33
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
N+1 redundancy has one ba ckup card for N pr imary cards. Due to impedance mismatch and signa l contention,
external relays are necessa ry when using this redun dancy scheme. The ad vant age of relays is that they crea te
complete isolation between the primary cards and the backup card. This allows all transmitters and receivers
on the primary cards to be configured in internal impedance mode, providing one bill of materials for all
interface modes of operation. The transmit and receive sections of the XRT83L30 are described separately.
TRANSMIT
For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode
providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To
swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A
0.68µF capacitor is used in series with TTIP for blocking DC bias. See Figure 18 for a simplified block diagram
of the transmit section for an N+1 redundancy sch eme.
NOTE: For simplificatio n , th e over voltage protection circuitry was omitted.
FIGURE 18. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY
Backplane Interface
Primary Card XRT83L30
Tx
Line Interface Card
0.68µFT1/E1 Line
Primary Card XRT83L30
Tx
Primary Card XRT83L30
Tx
Backup Card XRT83L30
Tx
T1/E1 Line
T1/E1 Line
TxTSEL=1, Internal
TxTSEL=1, Internal
TxTSEL=1, Internal
TxTSEL=1, Inte rna l
1:2
0.68µF
0.68µF
0.68µF
1:2
1:2
XRT83L30
34
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
RECEIVE
For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode.
The receivers on the backup card should be programmed for external impedance mode. Since there is no
external resistor in the circuit, th e receivers on the backup card will be high impedance. Select the impedance
for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal
impedance mode, then the primary card to external impedance mode. See Figure 19. for a simplified block
diagram of the receive section for a N+1 redundancy scheme.
NOTE: For simplification, the over vo ltage protection circuitry was omitted.
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR N+1 REDUNDANCY
Backplane Interface
Primary Card XRT83L30
Rx
Line Interface Card
Primary Card XRT83L30
Rx
Primary Card XRT83L30
Rx
Backup Card XRT83L30
Rx
RxTSEL=1, Internal
RxTSEL=1, Internal
RxTSEL=1, Internal
RxTSEL=1, External
T1/E1 Line
T1/E1 Line
T1/E1 Line
1:1
1:1
1:1
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
PATTERN TRANSMIT AND DETECT FUNCTION
Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode the
channel can be programmed to transmit an All Ones pattern by applying a “High” level to the corresponding
TAOS pin. In Host mode, the three interface bits TXTEST[2:0] control the pattern generation and detection
according to Table 12.
TRANSMIT ALL ONES (TAOS)
This feature is available in both Hardware and Host modes. When the Hardware pins or interface bits
TXTEST2="0", TXTEST1="0" and TXTEST0="1", the transmitter igno res input from TPOS/TDATA and TNEG
pins and sends a continu ous AMI e ncoded all o nes signal to th e lin e u sing TCL K clock as the refe re nce. When
TCLK is not available, MCLK is used. In addition, when the Hardware pin or the interface bit ATAOS is
activated, the chip will automatically tr ansmit the All Ones data when the receiver detects an RLOS condition.
The operation of this feature requires that TCLK not be tied "Low".
NETWORK LOOP CODE DETECTION AND TR ANSMISS ION
This feature is available in both Hardware and Host modes. When the Hardware pins or interface bits
TXTEST2="0", TXTEST1="1" and TXTEST0="0" the chip is ena bled to transmit the "0 0001" Network Loop-Up
Code from a request for a loop-back condition from the remote terminal. Simultaneously setting the interface
bits NLCDE1="0" and NLCDE0="1" enables the Network Loop-Up code detection in the receiver . If th e "00001"
Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD bit in the interface
register is set indicating that the remote terminal has activated remote Loop-back and the chip is receiving its
own transmitted data. When Network Loop-Up code is being transmitted the XRT83L30 will ignore the Auto-
matic Loop-Code detection and Remote Loop-back activation (NLCDE1=”1”, NLCDE0=”1”, if activated) in
order to avoid activating Remote Digital Loop-back automatically when the remote terminal responds to the
Loop-back requ est.
When TXTEST2="0", TXTEST1="1" and TXTEST0="1" the chip is enabled to transmit the Ne twork Loop-Down
Code "001" from the transmitter requestin g the remote terminal the removal of the Loop- Back condition.
In both Hardware and Host modes the receiver is capable of mon itoring the contents of the receive data for
the presence of Loop-Up or Loop-Down code from the remote terminal. The Hardware pins or interface bits
TABLE 12: PATTERN TRANSMISSION CONTROL
TXTEST2 TXTEST1 TXTEST0 TEST PATTERN
000 Transmit Data
001 TAOS
010 TLUC
011 TLDC
100 TDQRSS
101 TDQRSS & INVQRSS
110 TDQRSS & INSBER
111TDQRSS & INVQRSS & INSBER
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
NLCDE[1:0] control the Loop -Code detection according to Table 13.
Setting the Hardware pins or interface bits NLCDE1="0" and NLCDE0="1" activates the detection of the Loop-
Up code in the receive data. If the "00001" Network Loop-Up code is detected in the receive data for longer
than 5 seconds the NLCD interface bit is set to "1" and stays in this state for as long as the receiver continues
to receive the Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an
interrupt on every transit ion of NLCD. T he host has the option to igno re the reques t from the remo te terminal,
or to respond to th e request and manu ally activate Remote Loop-Ba ck. The host can su bsequently activate the
detection of the Loop-Down Code by setting NLCDE1="1" and NLCD E0="0". In this case, receiving the "001"
Loop-Down Code for longer than 5 seconds will set the NLCD bit to "1" and if the NLCD interrupt is enabled,
the chip will initiate an interrupt on every transition of NLCD. The host can respond to the request from the
remote terminal and remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1="0" and
NLCDE0="1") and Loop-Down (NLCDE1="1" and NLCDE0="0") Code detection modes, the NLCD pin or
interface bit will be set to "1" upon receiving the corresponding code in excess of 5 seconds in the receive data.
In Host mode the chip will initiate an interrupt any time the status of the NLCD bit changes and the Network
Loop-code interrupt is enabled.
Setting the Hardware pins or interface bits NLCDE1="1" and NLCDE0="1" enables the automatic Loop-Code
detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to “110”. As this mode is
initiated, the state of the NLCD pin or interface bit is reset to "0" and the chip is programmed to monitor the
receive input data for the Loop-Up Code. If the "00001" Network Loop-Up Code is detected in the receive data
for longer than 5 seconds in addition to setting the NLCD pin or interface bit, Remote loop-back is
automatically activated. The ch ip stays in r em ote lo o p- ba ck eve n if it st ops receivin g t he "0 00 01" patter n. After
the chip detects the Loop-Up code, sets the NLCD pin (bit) and enters Remote loop-back, it automatically
starts monitoring the receive data for the Loop-Down code. In this mode however, the NLCD pin (bit) stays set
even if the receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote loop-
back is still in effect. Remote loop-back is removed if the chip detects the "001" Loop-Down code for longer
than 5 seconds. Detecting the "001" code also results in resettin g the NLCD pin (bit) and initiating an interrupt.
The Remote loop-back can also be removed by taking the chip out of the Automatic detection mode by
programming it to operate in a different state. The chip will not respond to remote loop-back request if an
Analog loop-back is activated locally. When programmed in Automatic detection mode th e NLCD pin (bit) st ays
"High" for the whole time the Remote loop-back is activated and in the Host mode it initiates an interrupt any
time the status of the NLCD bit changes provided th e Network Loop-code interrupt is enabled.
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)
The XRT83L30 includes a QRSS pattern generation and detection block for diagnostic purposes that can be
activated only in th e Host mode by setting the interface bits TXTEST 2=”1”, TXT EST1=”0” and TXTEST0=” 0”.
For T1 systems, the QRSS pattern is a 220-1pseudo-random bit sequence (PRBS) with no more than 14
consecutive zeros. For E1 systems, the QRSS pattern is 215 -1 PRBS with an inverted output. With QRSS and
Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD interface bit, all
main functional blocks within the transceiver can be verified.
When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD
changes from “Low” to “High”. After pattern synchronization, any bit error will cause QRPD to go “Low” for one
clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt.
TABLE 13: LOOP-CODE DETECTION CONTROL
NLCDE1 NLCDE0 CONDITION
0 0 Disable Loop-Code Detect ion
0 1 Detect Loop-Up Code in Receive Data
1 0 Detect Loop-Down Code in Receive Data
1 1 Automatic Loop-Code detection and Remote Loop-Back Activation
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the
INSBER interface bit from “0” to “1”. B ipolar violation can also be inserted either in the QRSS pattern, or input
data when operating in the single-rail mode by transitioning the INSBPV interface bit from “0” to “1”. The state
of INSBER and INSBPV bits are sampled on the rising edge of the TCLK. To insure the insertion of the bit error
or bipolar violation, a “ 0” should be written in these bit location s before writing a “1”.
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
LOOP-BACK MODES
The XRT83L30 supports several Loop-Back modes under both Hardware and Host control. In Hardware
mode the two LOOP[1:0] pins control the Loop-Back functions according to Table 14.
In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. The LIU can be
programmed according to Table 15.
LOCAL ANALOG LOOP-BACK (ALOOP)
With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog
input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data
continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the
XRT83L30 including the jitter attenuator which can be selected in either the transmit or receive paths. Local
Analog Loop-Back is shown in Figure 20.
In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path.
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE
LOOP1 LOOP0 LOOP-BACK MODE
0 0 None
0 1 Analog
1 0 Remote
1 1 Digital
TABLE 15: LOOP-BACK CONTROL IN HOST MODE
LOOP2 LOOP1 LOOP0 LOOP-BACK MODE
0 X X None
100 Dual
101 Analog
110Remote
111 Digital
FIGURE 20. LOCAL ANALOG LOOP-BACK SIGNAL FLOW
Rx
Data &
Clock
Recovery
Decoder
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
TxEncoder Timing
Control
JA TTIP
TRING
RTIP
RRING
XRT83L30
39
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
REMOTE LOOP-BACK (RLOOP)
With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is
looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are
ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote
Loop-Back with jitter attenuator selected in the receive path is shown in Figure 21.
In the Remote Loop-Back mode if the jitter attenu ator is selected in the transmit path, the receive data from the
Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using
RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received
data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator
selected in the transmit path is shown in Figure 22.
FIGURE 21. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH
FIGURE 22. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder TTIP
TRING
RTIP
RRING
JA
Tx
Decoder
Timing
Control
Rx
Clock &
Data
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder TTIP
TRIN
G
RTIP
RRIN
G
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
DIGITAL LOOP-BACK (DLOOP)
Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data w ill be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in Figure 23.
DUAL LOOP-BACK
Figure 24 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit
path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back throug h the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.
FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder TTIP
TRING
RTIP
RRING
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder TTIP
TRING
RTIP
RRING
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
HOST MODE SERIAL INTERFACE OPERATION
XRT83 L30 has a simple four wire Serial Interface that is comp atible with ma ny of the microcontroller s available
in the market. The Host mode operation is enabled by connecting pin 20 (HW/HOST) to a “Low”. The Serial
Interface provides a total of 32 “Read/Write” 8-bit registers that consists of the following signals:
CS - Chip Select (Active "Low")
SCLK - Serial Clock
SDI - Serial Data Input
SDO - Serial Data Output
USING THE MICROPROCESSOR SERIAL INTERFACE
The following instructions for using the Microprocessor Serial Interface are best understood by referring to the
diagram in Figure 25.
In order to use the Serial interface, a clock signal must be applied to the SCLK input pin. The maximum SCLK
clock frequency is 20MHz. A Read or Write operation can then be initiated by asserting the active-low Chip
Select (CS) input pin. For proper operation the CS must be a ssert ed “Low” at leas t 50n s prior to the firs t rising
edge of the SCLK. Once the CS pin has been asserted, the Read/Write Operation and the target register can
be specified through the Serial Interface by writing eight serial bits into the SDI input. Each bit will be clocked
on the rising edge of SCLK.The function of the eig ht bits are identified and described below:
Bit 1: R/W (Read/Write) Bit
This bit is clocked into the SDI input on the first rising edge of the SCLK after CS has been asserted. This bit
indicates whether the current operation is a “Read” or a “Write”. A “1” in this bit specifies a Read operation,
whereas a “0” spe cif ies a “Write” op er at ion .
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Bit 2 through 6:The five (5) Address Values (labeled A0, A1, A2, A3 and A4)
The next five rising edges of the SCLK signal, clock in the 5-bit address value for the Read or Write operation.
These five bits define the register address within XRT83L30 that the user has selected to read data from or
write data to. The address bits must be supplied to the SDI input in ascending order with LSB (Least Significant
Bit) first.
Bit 7: (A5)
The next bit A5 must be set to “0” as shown in Figure 25.
Bit 8: (A6)
The value of A6 is a “don’t care”.
Once the first eight bits have been written into the Serial interface, the subsequent action depends on the
whether the current op eration is a “Read” or “Write” instruction.
Read Operation
With the last address bit “A4” written into the SDI input, the “Read” operation will proceed through an idle
period lasting two SCLK periods. On the rising edge of the 9th SCLK the serial data output (SDO) becomes
active (see Figure 25). At this point the user can begin reading the 8-bit data (D0 through D7) stored in the
interface register at address [A4,A3,A2,A1,A0], in ascending order (LSB first), on the falling edge of SCLK.
Write Operation
With the last address bit (A4) written into the SDI input, the “Write” operation will proceed through an idle
period lasting two SCLK periods. Prior to the rising edge of the 9th SCLK, the user must begin to apply the
eight bit data word to the SDI input. The Serial Interface will latch this data on the rising edge of SCLK. The
serial dat a (D0 through D7) should enter the SDI input in ascending order with the LSB first.
Serial Interface Register Description
The serial Interface consists of 32 8-bit register locations. The Microprocessor register address map and Bit
map are described in Table 16 and Table 17 respectively. The function of the individual bits are described in
Table 18 through Table 36.
FIGURE 25. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
5 6 7 81 2 3 4 13 14 15 169 10 11 12
R/W Ao A1 A2 A3 A4 0 A6 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
CS
SCLK
SDI
SDO High Z High Z
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 16: MICROPROCESSOR REGISTER ADDRESS
REGISTER NUMBER REGISTER ADDRESS FUNCTION
HEX BINARY
0 - 18 0x00 - 0x12 00000 - 10010 Command and Control Registers
19 - 21 0x13 - 0x15 10011 - 10101 Reserved
22 - 29 0x16 - 0x1D 10110 - 11101 R/W registers reserved for testing purpose
30 0x1E 11110 Device "ID"
31 0x1F 11111 Device "Revision ID"
TABLE 17: MICROPROCESSOR REGISTER BIT MAP
REG. # ADDRESS REG.
TYPE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Control Registers
000000
Hex 0x00 R/W Reserved Reserved Reserved EQC4 EQC3 EQC2 EQC1 EQC0
100001
Hex 0x01 R/W RXTSEL TXTSEL TERSEL1 TERSEL0 JASEL1 JASEL0 JABW FIFOS
200010
Hex 0x02 R/W RXON TXTEST2 TXTEST1 TXTEST0 TXON LOOP2 LOOP1 LOOP0
300011
Hex 0x03 R/W NLCDE1 NLCDE0 CODES RXRES1 RXRES0 INSBPV Reserved TRATIO
400100
Hex 0x04 R/W GIE DMOIE FLSIE LCVIE NLCDIE AISDIE RLOSIE QRPDIE
500101
Hex 0x05 RO Reserved DMO FLS LCV NLCD AISD RLOS QRPD
600110
Hex 0x06 RUR Reserved DMOIS FLSIS LCVIS NLCDIS AISDIS RLOSIS QRPDIS
700111
Hex 0x07 RO Reserved Reserved CLOS5 CLOS4 CLOS3 CLOS2 CLOS1 CLOS0
801000
Hex 0x08 R/W X B6S1 B5S1 B4S1 B3S1 B2S1 B1S1 B0S1
901001
Hex 0x09 R/W X B6S2 B5S2 B4S2 B3S2 B2S2 B1S2 B0S2
10 01010
Hex 0x0A R/W X B6S3 B5S3 B4S3 B3S3 B2S3 B1S3 B0S3
11 01011
Hex 0x0B R/W X B6S4 B5S4 B4S4 B3S4 B2S4 B1S4 B0S4
12 01100
Hex 0x0C R/W X B6S5 B5S5 B4S5 B3S5 B2S5 B1S5 B0S5
13 01101
Hex 0x0D R/W X B6S6 B5S6 B4S6 B3S6 B2S6 B1S6 B0S6
14 01110
Hex 0x0E R/W X B6S7 B5S7 B4S7 B3S7 B2S7 B1S7 B0S7
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
15 01111
Hex 0x0F R/W X B6S8 B5S8 B4S8 B3S8 B2S8 B1S8 B0S8
16 10000
Hex 0x10 R/W SR/DR ATAOS RCLKE TCLKE DATAP Reserved Reserved SRESET
17 10001
Hex 0x11 R/W Reserved CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE RXMUTE EXLOS ICT
18 10010
Hex 0x12 R/W GAUGE1 GAUGE0 TXONCNTL TERCNTL SL_1 SL_0 EQG_1 EQG_0
Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0
Unused Registers
19 10011
Hex 0x13 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
20 10100
Hex 0x14 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
21 10101
Hex 0x15 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Test Registers
22 10110
Hex 0x16 R/W Test byte 0
23 10111
Hex 0x17 R/W Test byte 1
24 11000
Hex 0x18 R/W Test byte 2
25 11001
Hex 0x19 R/W Test byte 3
26 11010
Hex 0x1A R/W Test byte 4
27 11011
Hex 0x1B R/W Test byte 5
28 11100
Hex 0x1C R/W Test byte 6
29 11101
Hex 0x1D R/W Test byte 7
ID Registers
30 11110
Hex 0x1E DEVICE ID ⇒ F9
31 11111
Hex 0x1F DEVICE "Revision ID"
TABLE 17: MICROPROCESSOR REGISTER BIT MAP
REG. # ADDRESS REG.
TYPE BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 18: MICROPROCESSOR REGISTER #0 BIT DESCRIPTION
REGISTER ADDRESS
00000 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6 Reserved R/W 0
D5 Reserved R/W 0
D4 EQC4 Equalizer Control bit 4: This bit together with EQC[3:0] are
used for controlling transmit pulse shaping, transmit line build-out
(LBO), receive monitoring and also T1 or E1 mode of operation.
See Table 5 for description of Equalizer Control bits.
R/W 0
D3 EQC3 Equalizer Control bit 3: See bit D4 description for function of
this bit R/W 0
D2 EQC2 Equalizer Control bit 2: See bit D4 description for function of
this bit R/W 0
D1 EQC1 Equalizer Control bit 1: See bit D4 description for function of
this bit R/W 0
D0 EQC0 Equalizer Control bit 0: See bit D4 description for function of
this bit R/W 0
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION
REGISTER ADDRESS
00001 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 RXTSEL Receiver Termination Select: In Host mode, this bit is used to
select between the int ernal and external line termination modes
for the receiver according t o the following table:
R/W 0
D6 TXTSEL Transmit Termination Select: In Host mode, this bit is used to
select between the int ernal and external line termination modes
for the transmitter according to the following table:
R/W 0
D5 TERSEL1 Termination Impedance Select bit 1:
In the Host mode and in the internal terminat ion mode (TXT-
SEL=”1” and RXTSEL=”1”), TERSEL[1:0] control the transmit
and receive termination impedance accord ing to the following
table:
In the internal termination mode, the receiver termination of each
receiver is realized completely by internal resisto r s or by the
combination of internal and one fixed resistor (see description for
RXRES[1:0] bits).
In the internal termination mode, the transmitter output should be
AC coupled to the transfo rmer.
R/W 0
D4 TERSEL0 Termination Impedance Select bit 0:
See description of bit D5 for the function of this bit. R/W 0
RXTSEL RX Termination
0
1
External
Internal
TXTSEL TX Termination
0
1
External
Internal
0 1
1 0
1 1
0 0 100Ω
110Ω
75Ω
120Ω
TerminationTERSEL1 TERSEL0
XRT83L30
47
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
D3 JASEL1 Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are
used to disable or place t he jitter attenuator in the transmit or
receive path.
R/W 0
D2 JASEL0 Jitter Attenuator select bit 0: See description of bit D3 for the
function of this bit. R/W 0
D1 JABW Jitter Attenuator Bandwidth Select:
In E1 mode, set this bit to "1" to select a 1.5Hz Bandwidth for the
Jitter Attenuator In E1 mode. The FIFO length will be automati-
cally set to 64 bits.
Set this bit to "0" to select 10Hz Bandwidth for the Jitter Attenua-
tor in E1 mode.
In T1 mode the Jitter Attenuator Bandwidth is permanently set to
3Hz, and the state of this bit has no effect on the Bandwidth.
R/W 0
D0 FIFOS FIFO Size Select: See table of bit D1 above for the function of
this bit. R/W 0
TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION
JASEL1
bit D3 JASEL0
bit D2
0 0
0 1
1 0
1 1
JA Path
JA Disabled
JA in Transmit Path
JA in Receive Path
JA in Receive Path
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
0
1
1
0
0
1
1
JABW
bit D1
T1
T1
T1
T1
E1
E1
E1
E1
Mode
32
64
32
64
32
64
64
64
FIFO
Size
3
3
3
3
10
10
1.5
1.5
JA B-W
Hz
XRT83L30
48
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 20: MICROPROCESSOR REGISTER #2 BIT DESCRIPTION
REGISTER ADDRESS
00010 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 RXON Receiver ON: Writing a “1” into this bit location turns on the
Receive Section. Writing a “0” shuts off the Receiver Section. In
this mode, RTIP and RRING driver outputs will be tri-stated for
power reduction or redund ancy applications. Default is "0", off.
R/W 0
D6 TXTEST2 Transmit Test Pattern bit 2: This bit together with TXTEST1
and TXTEST0 are used to generate and transmit test patterns
according to th e following table:
TDQRSS (Transmit/Detect Quasi-Random Signal): This con-
dition, when activated, enables Quasi-Random Signal Source
generation and detection. In a T1 system QRSS pattern is a 220-
1 pseudo-random bit sequence (PRBS) with no more than 14
consecutive zeros. In a E1 system, QRSS is a 215-1 PRBS pat-
tern.
TAOS (T ransmit All Ones): Activating this condition enables the
transmission of an All Ones Pattern. TCLK must no t be tied
"Low".
TLUC (Transmi t Network Loop-Up Code): Activating this con-
dition enables the Network Loop-Up Code of "00001" to be trans-
mitted to the line. When Network Loop-Up code is being
transmitted, the XRT83L30 will ignore the Automatic Loop-Code
detection and Remote Loop-Back activation (NLCDE1 =“1”,
NLCDE0 =“1”, if activated) in order to avoid activating Remote
Digital Loop-Back automatically when the remote terminal
responds to the Loop-Ba c k request.
TLDC (Transmit Network LOOP-Down Code): Activating this
condition enables th e network Loop-Down Code of "001" to be
transmitted to the line.
R/W 0
D5 TXTEST1 Transmit Test pattern bit 1: See description of bit D6 for the
function of this bit. R/W 0
D4 TXTEST0 Transmit Test Pattern bit 0: See description of bit D6 for the
function of this bit. R/W 0
0 1
1 0
1 1
0 0
0
0
0
1
0 00 Transmit Data
TAOS
TLUC
TLDC
Test PatternTXTEST1 TXTEST0TXTEST2
1 0
1 1
1
1
0 11
TDQRSS
TDQRSS & INVQRSS
TDQRSS & INSBER
TDQRSS & INVQRSS & IN
S
XRT83L30
49
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
D3 TXON Transmitter ON: Writing a "1" into this bit location turns on the
Transmit Section. A ‘0’ in this bit location, shuts off the transmit-
ter. In this mode the TTIP and TRING driver outputs will be tri-
stated for power reduction or redundancy app lications.
R/W 0
D2 LOOP2 Loop-Back control bit 2: This bit together with the LOOP1 and
LOOP0 bits control the Loop-Back modes of the chip according
to the followi ng table:
R/W 0
D1 LOOP1 Loop-Back control bit 1: See description of bit D2 for the func-
tion of this bit. R/W 0
D0 LOOP0 Loop-Back control bit 0: See description of bit D2 for the func-
tion of this bit. R/W 0
TABLE 20: MICROPROCESSOR REGISTER #2 BIT DESCRIPTION
LOOP2
0
1
1
1
1
LOOP1
X
0
0
1
1
LOOP0
X
0
1
0
1
Loop-Back Mode
No Loop-Back
Dual Loop-Back
Analog Loop-Back
Remote Loop-Back
Digital Loop-Back
XRT83L30
50
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 21: MICROPROCESSOR REGISTER #3 BIT DESCRIPTION
REGISTER ADDRESS
00011 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 NLCDE1 Network Loop Code Detection Enable bi t 1:
This bit together with NLCDE0, Control the Loop-Code detection
according to th e following table:
When NLCDE1=”0” and NCLDE0 =”1”, or NLCDE1= ”1” and
NLCDE0=”0”, the chip is manually programed t o monit or the
receive data for the Loop-Up or Loop-Down code respectively.
When the presence of the “00001” or “001” pattern is detected for
more than 5 seconds, the status of the NLCD bit is set to “1” and
if the NLCD interrupt is enabled an interrupt is initiated. The Host
has the option to control the Loop-Back function manually.
Setting the NLCDE1=”1” and NLCDE0=”1” enables the Auto-
matic Loop-Code detection and Remote-Loop-Back activation
mode. As this mode is initiated, the state of the NLCD interf ace
bit is reset to “0” and the chip is programmed to monitor th e
receive data for the Loop-Up Code. If the “00001” pattern is
detected for longer than 5 secon ds, the NLCD bit is set to “1”,
Remote Loop-Back is activated and the chip is automatically pro-
gramed to monitor the receive data for the Loop-Down code. The
NLCD bit stays set even after the chip stops receiving the Loop-
Up code. The remote Loop-Back co ndition is removed whe n the
chip receives the Loop-Down code for more than 5 seconds or if
the Automatic Loop-Code detection mode is terminated.
R/W
R/W 0
0
D6 NLCDE0 Network Loop Code Detection Enable bit 0: See description
of bit D7 for the function of this bit. R/W 0
D5 CODES ENCODING and DECODING SELECT:
Writing a “0” to this bit selects HDB3 or B8ZS encoding and
decoding. Writing a “1” selects an AMI coding scheme.This bit is
only active when single-rail mode is selected.
R/W 0
NLCDE1 NLCDE0 Function
0 0 Disable Loop-Code
Detection
0 1 Detect Loop-Up Code in
Receive Data
1 1 Automatic Loop-Code
Detection
1 0 Detect Loop-Down Code in
Receive Data
XRT83L30
51
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
D4 RXRES1 Receive External Resistor Control pin 1: In Host mode, this
bit along with the RXRES0 bit selects the value of the external
Receive fixed resistor according to the f ollowing table:
R/W 0
D3 RXRES0 Receive External Resistor Control bit 0: For function of this bit
see description of D4 the RXRES1 bit. R/W 0
D2 INSBPV Insert Bipolar Violation: When this bit transitions from "0" to
"1", a bipolar violation is inserted in the transmitted data stream.
Bipolar violation can be inserted either in the QRSS pattern, or
input data when operating in single-rail mode. The state of this bit
is sampled on the rising edge of TCL K .
NOTE: To ensure the insertion of a bipolar violation, a "0" should
be written in this bit location before writing a "1".
R/W 0
D1 Reserved R/W 0
D0 TRATIO Transformer Ratio Select: In the external term in ation mode,
writing a “1” to this bit selects a transformer ratio of 1:2 for the
transmitter. Writing a “0” sets the transmitter transformer ratio to
1: 2.45. In the internal termination mode the transmitter trans-
former ratio is permanently set to 1:2 and the state of this bit has
no effect.
R/W 0
TABLE 21: MICROPROCESSOR REGISTER #3 BIT DESCRIPTION
Required Fixed External
RX Resistor
No External Fixed Resistor
60Ω
52.5Ω
37.5Ω
RXRES0
0
1
0
1
RXRES1
0
0
1
1
XRT83L30
52
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 22: MICROPROCESSOR REGISTER #4 BIT DESCRIPTION
REGISTER ADDRESS
00100 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 GIE Global Interrupt Enable : Writing a "1" into this bit, globally
enables interrupt generation on the INT pin. Writing a "0" into this
bit, globally masks all interrupt requests.
R/W 0
D6 DMOIE DMO Interrupt Enab le: Writing a "1" to this bit enables DMO
interrupt generation, writi ng a "0" masks it. R/W 0
D5 FLSIE FIFO Limit Status Interrupt Enable: Writing a "1" to this bit
enables interrupt gene ration when the FIFO limit is withi n 3 bits,
writing a "0" to masks it.
R/W 0
D4 LCVIE Line Code Violation Interrupt Enable: Writing a "1" to this bit
enables Line Code Violation interrupt generation, writing a "0"
masks it.
R/W 0
D3 NLCDIE Network Loop-Code Detec tion Interrupt Enable: Writing a "1"
to this bit enables Network Loop-code detection interrupt genera-
tion, writing a "0" masks it.
R/W 0
D2 AISDIE AIS Detection Interrupt Enable: Writing a "1" to this bit enables
Alarm Indicati on Signal detection interrupt generation, wri ting a
"0" masks it.
R/W 0
D1 RLOSIE Receive Loss of Signal Interrupt Enable: Writing a "1" to this
bit enables Loss of Receive Signal interrupt generation, writing a
"0" masks it.
R/W 0
D0 QRPDIE QRSS Pattern Detection Interrupt Enable: Writing a "1" to this
bit enables QRSS pattern detection interrupt generation, writing
a "0" masks it.
R/W 0
XRT83L30
53
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION
REGISTER ADDRESS
00101 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved RO 0
D6 DMO Driver Monitor Output: This bit is set to a "1" to indicate tran s-
mit driver failure is detected. The value of this bit is based on the
current status of DMO. If the DMOIE bit is enabled, any transition
on this bit will generate an Interrupt.
RO 0
D5 FLS FiFO Limit S t atus: This bit is set to a "1" to indicate that the jitter
attenuator read/write FIFO pointers are within +/- 3 bits. If the
FLSIE bit is enabled, any tr ansition on this bit will generat e an
Interrupt.
RO 0
D4 LCV Line Code Violation: This bit is set to a "1" to indicate that the
receiver is currently detecting a Line Code Violation or an exces-
sive number of zeros in the B8ZS or HDB3 modes. If the LCVIE
bit is enabled, any transition on this bit will generate an Interrupt.
RO 0
XRT83L30
54
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
D3 NLCD Network Loop -Code Detection:
This bit operates differently in the Manual or the Automatic Net-
work Loop-Code detection modes.
In the Manual Loop-Code detection mo de (NLCDE1 =”0” and
NLCDE0 =”1”, or NLCDE1 =”1” and NLCDE0 =”0”) this bit gets
set to “1” as soon as the Loop-Up (“00001”) or Loop-Down
(“001”) code is detected in the receive data for longer than 5 sec-
onds. The NLCD bit stays in the “1” state for as long as the chip
detects the presence of the Loop-Code in the receive data and it
is reset to “0” as soon as it stops receiving it. In this mode if the
NLCD interrupt is enabled the chip will initiate an interrupt on
every transition of the NLCD.
When the Automatic Loop-Code detection mode (NLCDE1 =”1”
and NLCDE0 =”1”) is initiated, the state of the NLCD interface bit
is reset to “0” and the chip is programmed to monitor the receive
input data for the Loop-Up Code. This bit is set to a “1” to indicate
that the Network Loop Code is detected for more than 5 sec-
onds. Simultaneously the Remote Loop-Back condition is auto-
matically activa ted and the chip is programmed to monitor the
receive data for the Network Loop-Down Code . The NLCD bit
stays in the “1” state for as long as the Remote Loop-Back condi-
tion is in effect even if the chip stops receiving the Loop-Up
Code. Remote Loop-Back is removed if the chip detects the
“001” pattern for longer than 5 seconds in the receive data.
Detecting th e “001” pattern also results in resetting the NLCD
interface bit and initiating an interrupt provided the NLCD inter -
rupt enable bit it active. When programmed in the Automatic
detection mode, the NLCD interface bit stays “High” for the entire
time the Remote Loop-Back is active and initiates an int errupt
anytime the status of the NLCD bit changes. In this mode the
host can monitor the state of the NLCD bit to determine if the
Remote Loop-Back is activated.
RO 0
D2 AISD Alarm Indication Signal Detect: This bit is set to a "1" to indi-
cate All Ones Signal is detected by the receiver . The value of this
bit is based on the current status of Alarm Indication Signal
detector . If the AISDIE bit is enabled, any transition on this bit will
generate an Interrupt.
RO 0
D1 RLOS Receive Loss of Signal: This bit is set to a "1" to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal. If the RLOSIE bit is
enabled, any transition on this bit will generate an Interrupt.
RO 0
D0 QRPD Quasi-ran dom Pattern Detection: This bit is set to a "1" to indi-
cate the receiver is currently in synchronization with QRSS pat-
tern. The value of this bit is based on the current status of Quasi-
random pattern detector of. If the QRPDIE bit is enabled, any
transition on this bit will generate an Interrupt.
RO 0
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION
XRT83L30
55
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 24: MICROPROCESSOR REGISTER #6 BIT DESCRIPTION
REGISTER ADDRESS
00110 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved RUR 0
D6 DMOIS Driver Monitor Output Interrupt Status: This bit is set to a "1"
every time when DMO status has changed since l ast read. RUR 0
D5 FLSIS FIFO Limit Interrupt Status: This bit is set to a "1" every time
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) status
has changed since last read.
RUR 0
D4 LCVIS Line Code Violation Interrupt Status: This bit is set to a "1"
every time when LCV status has changed since last read. RUR 0
D3 NLCDIS Network Loop-Code Detection In terrupt S tatus: This bit is set
to a "1" every time when NLCD status has changed since last
read.
RUR 0
D2 AISDIS AIS Detection Interrupt Status: This bit is set to a "1" every
time when AISD status has changed since last read. RUR 0
D1 RLOSIS Receive Loss of Signal Interrupt Status: This bit is set to a "1 "
every time RLOS status has changed since last read . RUR 0
D0 QRPDIS Quasi-R andom Pattern Detection Interrupt Status: This bit is
set to a "1" every time when QRPD status has changed since
last read.
RUR 0
XRT83L30
56
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 25: MICROPROCESSOR REGISTER #7 BIT DESCRIPTION
REGISTER ADDRESS
00111 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved RO 0
D6 Reserved RO 0
D5 CLOS5 Cable Loss bit 5: CLOS[5:0] are the six bits receiver for selec-
tive equalizer setting which is also a binary word that represents
the cable attenuation indication withi n ±1dB. CLOS5 is the most
significant bit (MSB) and CLOS0 is the least significant bit (LSB).
RO 0
D4 CLOS4 Cable Loss bit 4: See description of D5 for fu nction of this bit. RO 0
D3 CLOS3 Cable Loss bit 3: See description of D5 for fu nction of this bit. RO 0
D2 CLOS2 Cable Loss bit 2: See description of D5 for fu nction of this bit. RO 0
D1 CLOS1 Cable Loss bit 1: See description of D5 for fu nction of this bit. RO 0
D0 CLOS0 Cable Loss bit 0: See description of D5 for fu nction of this bit. RO 0
TABLE 26: MICROPROCESSOR REGISTER #8 BIT DESCRIPTION
REGISTER ADDRESS
01000 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S1 - B0S1 Arbitrary Transmit Pulse Shape, Segment 1
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCLK.
This 7 bit number represents the amplitude of the arbitrary pulse
during the first time segment . B6S1 -B0S1 is in signed magni-
tude format with B6 S1 as the sign bit and B0S1 as the least sig-
nificant bit (LSB).
R/W 0
XRT83L30
57
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 27: MICROPROCESSOR REGISTER #9 BIT DESCRIPTION
REGISTER ADDRESS
01001 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S2 - B0S2 Arbitrary Transmit Pulse Shape, Segment 2
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCL K .
This 7 bit number represents the amplitude of the arbitrary pulse
during the second time segment. B6S2 -B0S2 is in signed ma g-
nitude format with B6S2 as the sign bit and B0S2 as the least
significant bit (LSB).
R/W 0
TABLE 28: MICROPROCESSOR REGISTER #10 BIT DESCRIPTION
REGISTER ADDRESS
01010 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S3 - B0S3 Arbitrary Transmit Pulse Shape, Segment 3
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCL K .
This 7 bit number represents the amplitude of the arbitrary pulse
during the thrd time segment. B6S3 -B0S3 is in signed magni-
tude format with B6 S3 as the sign bit and B0S3 as the least sig-
nificant bit (LSB).
R/W 0
XRT83L30
58
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 29: MICROPROCESSOR REGISTER #11 BIT DESCRIPTION
REGISTER ADDRESS
01011 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S4 - B0S4 Arbitrary Transmit Pulse Shape, Segment 4
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCLK.
This 7 bit number represents the amplitude of the arbitrary pulse
during the fourth ti me segment. B6S4 -B0S4 is in signed magni-
tude format with B6 S4 as the sign bit and B0S4 as the least sig-
nificant bit (LSB).
R/W 0
TABLE 30: MICROPROCESSOR REGISTER #12 BIT DESCRIPTION
REGISTER ADDRESS
01100 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S5 - B0S5 Arbitrary Transmit Pulse Shape, Segment 5
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCLK.
This 7 bit number represents the amplitude of the arbitrary pulse
during the fith time segment. B6S5 -B0S5 is in signed magni-
tude format with B6 S5 as the sign bit and B0S5 as the least sig-
nificant bit (LSB).
R/W 0
XRT83L30
59
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 31: MICROPROCESSOR REGISTER #13 BIT DESCRIPTION
REGISTER ADDRESS
01101 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S6 - B0S6 Arbitrary Transmit Pulse Shape, Segment 6
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCL K .
This 7 bit number represents the amplitude of the arbitrary pulse
during the sixth time segment. B6S6 -B0S6 is in signed magni-
tude format with B6 S6 as the sign bit and B0S6 as the least sig-
nificant bit (LSB).
R/W 0
TABLE 32: MICROPROCESSOR REGISTER #14 BIT DESCRIPTION
REGISTER ADDRESS
01110 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S7 - B0S7 Arbitrary Transmit Pulse Shape, Segment 7
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCL K .
This 7 bit number represents the amplitude of the arbitrary pulse
during the seventh time segment. B6S7 -B0S7 is in signed mag-
nitude format with B6S7 as the sign bit and B0S7 as the least
significant bit (LSB).
R/W 0
XRT83L30
60
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 33: MICROPROCESSOR REGISTER #15 BIT DESCRIPTION
REGISTER ADDRESS
01111 FUNCTION REGISTER
TYPE RESET
VALUE
BIT # NAME
D7 Reserved R/W 0
D6-D0 B6S8 - B0S8 Arbitrary Transmit Pulse Shape, Segment 8
The shape of the transmitte d pulse can be made user program -
mable by selecting "Arbitrary Pulse" mode, see Table 5. The
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCLK.
This 7 bit number represents the amplitude of the arbitrary pulse
during the eighth time segment. B6S8 -B0S8 is in signed magni-
tude format with B6 S8 as the sign bit and B0S8 as the least sig-
nificant bit (LSB).
R/W 0
XRT83L30
61
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 34: MICROPROCESSOR REGISTER #16 BIT DESCRIPTION
REGISTER ADDRESS
10000 NAME FUNCTION REGISTER
TYPE RESET
VALUE
BIT #
D7 SR/DR Single-rail/Dual-rail Select: Writing a "1" to this bit configures
the XRT83L30 to operate in the Single-rail mode.
Writing a "0" configures the XRT83L30 to operate in Dual-rail
mode.
R/W 0
D6 ATAOS Automatic Transmit All Ones Upon RLOS: Writing a "1" to this
bit enables the automatic transmission of All Ones data to the
line.
Writing a "0" disables this feature.
R/W 0
D5 RCLKE Receive Clock Edge: Writing a "1" to this bit selects receive out-
put data to be updated on the negative edge of RCLK.
Writing a "0" selects data to be updated on the positive edge of
RCLK.
R/W 0
D4 TCLKE Transmit Clock Edge: Writing a "0" to this bit selects transmit
data at TPOS/TDATA and TNEG to be sampled on the falling
edge of TCLK.
Writing a "1" selects the rising edge of the TCLK for sampling.
R/W 0
D3 DATAP DATA Polarity: Writing a "0" to this bit selects transmit input and
receive output data of the XRT83L30 to be active "High".
Writing a "1" selects an active "Low" state.
R/W 0
D2 Reserved R/W 0
D1 Reserved R/W 0
D0 SRESET Software Reset µP Registers: Writing a "1" to this bit longer
than 10µs resets all internal state machines R/W 0
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 35: MICROPROCESSOR REGISTER #17 BIT DESCRIPTION
REGISTER ADDRESS
10001 NAME FUNCTION REGISTER
TYPE RESET
VALUE
BIT #
D7 Reserved R/W 0
D6 CLKSEL2 Clock Select Inputs for Master Clock Synthesizer bit 2: In
Host mode, CLKSEL[2:0] are input signals to a programmable
frequency synthesizer that can be used to generate a master
clock from an external accurate clock source according to the fol-
lowing table:
In Hardware mode the state of these bits are ignored and the
master frequency PLL is controlled by the corresponding Hard-
ware pins.
R/W 0
D5 CLKSEL1 Clock Select inputs for Master Clock Synthesizer bit 1: See
description of bit D6 for function of this bit. R/W 0
D4 CLKSEL0 Clock Select inputs for Master Clock Synthesizer bit 0: See
description of bit D6 for function of this bit. R/W 0
2048
2048
2048
1544
MCLKE1
kHz
8
16
16
56
8
56
64
64
128
256
256
128
2048
2048
1544
1544
MCLKT1
kHz
1544
X
X
X
1544
X
X
X
X
X
X
X
2048
1544
2048
CLKOUT
kHz
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
0
1
1
CLKSEL0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
CLKSEL1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
CLKSEL2
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
1544
2048
X
X
2048
1544
0
1
0
1
MCLKRATE
1
0
1
0
0
1
0
1
1
0
1
0
0
1
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
D3 MCLKRATE Master Clock Rate Select: The state of this bit programs the
Master Clock Synthesizer to generate the T1/J1 or E1 clock. The
Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE = “1”.
R/W 0
D2 RXMUTE Receive Output Mute: Writing a "1" to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a "0" state.
NOTE: RCLK is not muted.
R/W 0
D1 EXLOS Extended LOS: Writing a "1" to this bit extends the number of
zeros at the receive input before RLOS is declared to 4096 bits.
Writing a "0" reverts to the normal mode (175+75 bits for T1 and
32 bits for E1).
R/W 0
D0 ICT In-Circuit-Testing: Writing a "1" to this bit configures all the out-
put pins of the chip in "High" impedance mode for In-Circuit-Test-
ing. Setting ICT bit to “1” is equivalent to connecting the
Hardware ICT pin to ground.
R/W 0
TABLE 36: MICROPROCESSOR REGISTER #18 BIT DESCRIPTION
REGISTER ADDRESS
10010 NAME FUNCTION REGISTER
TYPE RESET
VALUE
BIT #
D7 GAUGE1 Wire Gauge Selector Bit 1
This bit along with bit D6 are used to select wire gauge size as
shown in the table below.
R/W 0
D6 GAUGE0 Wire Gauge Selector Bit 0
See bit D7. R/W 0
D5 TXONCNTL Transmit On Control.
In Host mode, setting this bit to “1” transfers the control of the
Transmit On/Off function to the TXON Hardware control pin.
NOTE: This provides a faster On/Off capability for redunda ncy
application.
R/W 0
D4 TERCNTL Termination Control:
In Host mode, setting this bit to “1” transfers the control of the
RXTSEL to the RXTSEL Hardware cont rol pin.
NOTE: This provides a faster On/Off capability for redunda ncy
application.
R/W 0
TABLE 35: MICROPROCESSOR REGISTER #17 BIT DESCRIPTION
GAUGE1
0
1
1
0
GAUGE0
0
1
0
1
Wire Size
22 and 24 Gauge
26 Gauge
24 Gauge
22 Gauge
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
D3 SL_1 Slicer Level Control bit 1: This bit and bit D2 control the slic-
ing level for the slicer per the following table. R/W 0
D2 SL_0 Slicer Level Control bit 0: See description bit D3. R/W 0
D1 EQG_1 Equalizer Gain Control bit 1: This bit together with bit D0
control the gain of the equalizer as shown in the table below. R/W 0
D0 EQG_0 Equalizer Gain Control bit 0: See description of bit D1. R/W 0
TABLE 36: MICROPROCESSOR REGISTER #18 BIT DESCRIPTION
SL_1 SL_0
0 0
0 1
1 0
1 1
Slicer Mode
Normal
Decrease by 5% from Normal
Increase by 5% from Normal
Normal
EQG_1 EQG_0
0 0
0 1
1 0
1 1
Equalizer Gain
Normal
Reduce Gain by 1 dB
Reduce Gain by 3 dB
Normal
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
ELECTRICAL CHARACTERISTICS
TABLE 37: ABSOLUTE MAXIMUM RATINGS
Storage Temperature...............-65°C to +150°C
Operating Temperature.. ... ........ -40°C to +85°C
Supply Voltage............................-0.5V to +3.8V
Vin................................................-0.5 to +5.5V
TABLE 38: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER SYMBOL MIN TYP MAX UNITS
Power Supply Vo ltage VDD 3.13 3.3 3.46 V
Input High Voltage VIH 2.0 -5.0 V
Input Low Voltage VIL -0.5 -0.8 V
Output High Voltage @ IOH = 2.0mA VOH 2.4 - - V
Output Low Vo ltage @IOL = 2. 0mA VOL - - 0.4 V
Input Leakage Curren t (except Input pins
with Pull-up or Pull- down resi stor). IL- - ±10 µA
Input Capacitance CI-5.0 -pF
Output Load Capacitance CL- - 25 pF
TABLE 39: XRT83L30 POWER CONSUMPTION
VDD=3.3V±5%, TA=25°C, INTERNAL IMPEDANCE, UNLESS OTHERWISE SPECIFIED
MODE SUPPLY
VOLTAGE IMPEDANCE TERMINATION
RESISTOR
TRANSFORMER
RATIO TYP MAX UNIT TEST
CONDITIONS
RECEIVER TRANSMITTER
E1 3.3V 75ΩInternal 1:1 1:2 298 350 mW 100% “1’s”
E1 3.3V 120ΩInternal 1:1 1:2 276 325 mW 100% “1’s”
T1 3.3V 100ΩInternal 1:1 1:2 310 365 mW 100% “1’s”
--- 3.3V --- External --- --- 72 85 mW All transmitters off
XRT83L30
66
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 40: E1 RECEIVER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA= -40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER MIN TYP MAX UNIT TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS De-asserted
10
15
12.5
175
20
255
dB
dB
Cable attenuation @1024KHz
ITU-G.775, ETSI 300 233
Receiver Sensitivity
(Short Haul with cable loss) 11 dB With nominal pulse amplitude of 3.0V
for 120Ω and 2.37V for 75Ω applica-
tion. With -18dB interference signal
added.
Receiver Sensitivity
(Long Haul with cable loss)
Nominal
Extended 0
036
43
dB With nominal pulse amplitude of 3.0V
for 120Ω and 2.37V for 75Ω applica-
tion. With -18dB interference signal
added.
Input Impedance 13 kΩ
Input Jitter Tolerance:
1 Hz
10kHz-100kHz >64
0.4 UIpp
UIpp ITU G.823
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude -20 0.5 kHz
dB ITU G.736
Jitter Attenuator Corner Fre-
quency (-3dB curve) (JABW=0)
(JABW=1) -10
1.5 -Hz
Hz ITU G.736
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
14
20
16
- - dB
dB
dB
ITU-G.703
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 41: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA= -40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER MIN TYP MAX UNIT TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS Clear
100
15
12.5
175
20
-
250
-
-
dB
% ones
Cable attenuation @772kHz
ITU-G.775, ETSI 300 233
Receiver Sensitivity
(Short Haul with cable loss) 12 dB With nominal pulse amplitude of 3.0V
for 100Ω termination
Receiver Sensitivity
(Long Haul with cable loss) 0-36 dB
dB
With nominal pulse amplitude of 3.0V
for 100Ω termination
Input Impedance 13 -kΩ
Jitter Tolerance:
1Hz
10kHz - 100kHz 138
0.4 -
--
-UIpp AT&T Pub 62411
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude -
-9.8 -
0.1 kHz
dB TR-TSY-000499
Jitter Attenuator Corner Fre-
quency
(-3dB curve)
- 3 Hz AT&T Pub 62411
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
-
-
-
20
25
25
-
-
-
dB
dB
dB
TABLE 42: E1 TRANSMIT RETURN LOSS REQUIREMENT
FREQUENCY RETURN LOSS
G.703/CH-PTT ETS 300166
51-102kHz 8dB 6dB
102-2048kHz 14dB 8dB
2048-3072kHz 10dB 8dB
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 43: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA= -40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER MIN TYP MAX UNIT TEST CONDITIONS
AMI Output Pulse Amplitud e:
75Ω Application
120Ω Application 2.185
2.76 2.37
3.0 2.555
3.24 V
V
Tr ansformer wi th 1:2 ratio and 9.1 Ω
resistor in series with each end of pri-
mary.
Output Pulse Width 224 244 264 ns
Output Pulse Width Ratio 0.95 -1.05 - ITU-G.703
Output Pulse Amplitude Ratio 0.95 -1.05 - ITU-G.703
Jitter Added by the Transmitter Out-
put -0.025 0.05 UIpp Broad Band with jitter free TCLK
applied to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
8
14
10
-
-
-
-
-
-
dB
dB
dB
ETSI 300 166, CHPTT
TABLE 44: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDD=3.3V±5%, TA= -40° TO 85°C, UNLESS OTHERWISE SPECIFIED
PARAMETER MIN TYP MAX UNIT TEST CONDITIONS
AMI Output Pulse Amplitud e: 2.5 3.0 3.5 VTansformer with 1:2.45 ratio and mea -
sured at DSX-1
Output Pulse Width 338 350 362 ns ANSI T1.102
Output Pulse Width Imbalance - - 20 -ANSI T1.102
Output Pulse Amplitude Imbalance - - +200 mV ANSI T1.102
Jitter Added by the Transmitter Out-
put -0.025 0.05 UIpp Broad Band with jitter free TCLK
applied to the input.
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
-
-
-
15
15
15
-
-
-
dB
dB
dB
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
FIGURE 26. ITU G.703 PULSE TEMPLATE
TABLE 45: TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance 75Ω Resistive (Coax) 120Ω Resistive (twisted Pair)
Nominal Peak Voltage of a Mark 2.37V 3.0V
Peak voltage of a Space (no Mark) 0 + 0.237 V 0 + 0.3V
Nominal Pulse width 244ns 244ns
Ratio of Positive and Negative Pulse s Im balance 0.95 to 1.05 0.95 to 1.05
10% 10%
10%10%
10% 10%
269 ns
(244 + 25)
194 ns
(244–50)
244 ns
219 ns
(244 – 25)
488 ns
(244 + 244)
0%
50%
20%
V = 100%
Nominal pulse
Note – V corresponds to the nominal peak value.
20%
20%
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FIGURE 27. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
TABLE 46: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE MAXIMUM CURVE
TIME (UI) NORMALIZED AMPLITUDE TIME (UI) NORMALIZED AMPLITUDE
-0.77 -.05V -0.77 .05V
-0.23 -.05V -0.39 .05V
-0.23 0.5V -0.27 .8V
-0.15 0.95V -0.27 1.15V
0.0 0.95V -0.12 1.15V
0.15 0.9V 0.0 1.05V
0.23 0.5V 0.27 1.05V
0.23 -0.45V 0.35 -0.07V
0.46 -0.45V 0.93 0.05V
0.66 -0.2V 1.16 0.05V
0.93 -0.05V
1.16 -0.05V
XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
TABLE 47: AC ELECTRICAL CHARACTERISTICS
(TA=25°C, VDD=3.3V±5%, UNLESS OTHERWISE SPECIFIED)
PARAMETER SYMBOL MIN TYP MAX UNITS
E1 MCLK Clock Frequency -2.048 -MHz
T1 MCLK Clock Frequency -1.544 -MHz
MCLK Clock Duty Cycle 40 -60 %
MCLK Clock Tolerance -±50 -ppm
TCLK Duty Cycle TCDU 30 50 70 %
Transmit Data Setup Time TSU 50 - - ns
Transmit Data Hold Time THO 30 - - ns
TCLK Rise Time(10%/90%) TCLKR - - 40 ns
TCLK Fall Time(90%/10%) TCLKF - - 40 ns
RCLK Duty Cycle RCDU 45 50 55 %
Receive Data Setup Time RSU 150 - - ns
Receive Data Hold Time RHO 150 - - ns
RCLK to Data Delay RDY - - 40 ns
RCLK Rise Time(10%/90%) with
25pF Loading. RCLKR- - 40 ns
RCLK Fall Time(90%/10%) with 25pF
Loading. RCLKF40 ns
FIGURE 28. TRANSMIT CLOCK AND INPUT DATA TIMING
TCLKRTCLKF
TCLK
TPOS/TDATA
or
TNEG
TSU THO
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FIGURE 29. RECEIVE CLOCK AND OUTPUT DATA TIMING
RCLKRRCLKF
RCLK
RPOS
or
RNEG
RDY
RHO
XRT83L30
73
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
PACKAGE DIMENSIONS
64 LEAD THIN QUAD FLAT PACK
(10 X 10 X 1.4 MM TQFP)
REV. 3.00
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.055 0.063 1.40 1.60
A10.002 0.006 0.05 0.15
A20.053 0.057 1.35 1.45
B0.007 0.011 0.17 0.27
C0.004 0.008 0.09 0.20
D0.465 0.480 11.80 12.20
D10.390 0.398 9.90 10.10
e0.020 BSC 0.50 BSC
L0.018 0.030 0.45 0.75
α0°7°0°7°
48 33
32
17
116
49
64
D
D1
DD1
B
e
A2
α
A1
A
Seating Plane
L
C
XRT83L30
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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/S H TRANSCEIV ER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
ORDERING INFORMATION
REVISION HISTORY
Rev. A1.0.0 Advanced version.
Rev. P1.1.0 Preliminary release.
Rev. P1.2.0 Modified microprocessor tables, moved various functions. Added GHCI_n, SL_1, SL_0, EQG_1
EQG_0, GAUGE1 and GAUGE0 to Control Global Register 18. Separ ated Microprocessor descr iption t able by
register number. Moved absolute maximum and DC electrical characteristics before AC electrical
characteristics. Replaced TBD’s in electrical ables. Reformated table of contents.
Rev. P1.2.1 Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the
FIFO size is selected by the jitter attenuator select.
Rev. P1.2.2 Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path
and FIFO size.
Rev. P1.2.3 Added definitions to dual function pins in the pin description section.
Rev P1.2.4 Added JABW, JASEL1 and JASEL0 t able in pin list and Jitter attenuator section. Corrected typos in
features, fi gu re s 7, 8, 9 and 11. Added Jitter atte nu a tor tables in micro pr oc es so r reg ist er tables.
Rev. P1.2.5 Table 18, 23, 24, 25 change GCHIE to GIE, GHCI and GCHIS to Reserved. Corrected package
outline drawing.
Rev. P1.2.6 TERCNTL (pin 46) function removed. Bit 7 of Microprocessor Register #2 was INSBER, is now
reserved. Bit 1 of Micr oprocessor Register #3 was INVQRSS, is now reserved. New description for bits D6 -
D0 in Tables 27 - 34 Microprocessor Registers.
Rev. P1.2.7 Expanded information on Receive Redundancy. 2 tables and 1 figure.
Rev. P1.2.8 Edited section on RLOS
Rev. P1.2.9 Removed TERCNTL from block diagram. Edit EQC[4:0] to be input only on block diagram.
Corrected RXMUTE, TCLK, JABW, MCKLE1, CLKSEL [2:0], RXTSEL, TERSEL[1:0], RXRES[1:0], ATAOS,
NLCD in the pin descriptions section. Replaced the Functional Description section. Edits to Table 18:
Microprocessor Register Bit Map, Table 21: Microprocessor Register #2 Bit Description, Table 35:
Microprocessor Register #16 Bit Description
Rev. P1.3. 0 Ta ble 35: Microprocessor Register #17 Bit Description , edit E1 clock MCLKRATE= “0” and T1/J 1
clock MCLKRATE=”1” .
Rev. 1.0.0 Final Release.
Rev. 1.0.1 Corrected package dimensions in ordering information table page 3.
TABLE 48.
PART # PACKAGE OPERATING TEMPERATURE RANGE
XRT83L30IV 64 Pin TQFP -40oC to +85oC
THERMAL INFORMATION Theta - JA = 38° C/W Theta JC = 7° C/W
75
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits descr ibed herein , conveys no license unde r any p atent or other ri ght, and makes no represent ation th at
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user ’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect it s safety or effectiveness. Product s are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected un de r the circumstances.
Copyright 2006 EXAR Corporation
Datasheet June 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
NOTES
