Advanced v0.2 TM ProASIC3 Flash Family FPGAs Features and Benefits * * * High Capacity * * * Advanced I/O 30 k to 1 Million System Gates Up to 144 kbits of True Dual-Port SRAM Up to 288 User I/Os Reprogrammable Flash Technology * * * * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live-At-Power-Up Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off On-Chip User Nonvolatile Memory * 1 kbit of FlashROM (FROM) Performance * * 150+ MHz Internal System Performance with 3.3 V, 66 MHz 64-bit PCI (except A3P030) Up to 350 MHz External System Performance In-System Programming (ISP) and Security * * Secure ISP Using On-Chip 128-Bit AES Decryption via JTAG (IEEE1532-compliant) (except A3P030) FlashLockTM to Secure FPGA Contents Low Power * * * * * * * * * * 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages - Up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except A3P030), and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL and LVDS (A3P250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable I/Os (A3P030 only) Programmable Output Slew Rate and Drive Strength Weak Pull-Up/Down IEEE1149.1 (JTAG) Boundary-Scan Test Pin-Compatible Packages Across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL (except A3P030) * * * * * * Segmented, Hierarchical Routing and Clock Structure Ultra-Fast Local and Long-Line Network Table 1 * * * * * Six CCC Blocks Total, One with an Integrated PLL Flexible Phase Shift, Multiply/Divide, and Delay Capabilities Wide Input Frequency Range (1.5 MHz to 350 MHz) SRAMs and FIFOs (except A3P030) 1.5 V Core Voltage for Low Power Support for 1.5-V-Only Systems Low-Impedance Flash Switches High-Performance Routing Hierarchy * * Enhanced High-Speed, Very Long-Line Network High-Performance, Low-Skew Global Network Architecture Supports Ultra-High Utilization * Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4, x9, x18 Organizations Available) True Dual-Port SRAM (except x18) 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz Programmable Embedded FIFO Control Logic ProASIC3 Product Family System Gates VersaTiles (D-Flip-Flops) RAM kbits (1,024 bits) 4,608 Bit Blocks FlashROM (FROM) Bits Secure (AES) ISP Integrated PLL in CCCs VersaNet Globals1 I/O Banks Maximum User I/Os Package Pins QFN VQFP TQFP PQFP FBGA A3P030 30 k 768 - - 1k - - 6 A3P060 60 k 1,536 18 4 1k Yes 1 18 A3P125 125 k 3,072 36 8 1k Yes 1 18 A3P250 250 k 6,144 36 8 1k Yes 1 18 A3P400 400 k 9,216 54 12 1k Yes 1 18 A3P600 600 k 13,824 108 24 1k Yes 1 18 A3P1000 1M 24,576 144 32 1k Yes 1 18 2 81 2 96 2 133 4 157 4 194 4 227 4 288 VQ100 TQ144 VQ100 TQ144 PQ208 FG144 VQ100 QN132 VQ100 FG144 PQ208 PQ208 FG144, FG256 FG144, FG256, FG484 PQ208 PQ208 FG144, FG256, FG144, FG484 FG256, FG484 Notes: 1. Six chip (main) and three quadrant global networks are available for A3P060 and above. 2. For higher densities and support of additional features, refer to the ProASIC3E Flash FPGAs datasheet. January 2005 (c) 2005 Actel Corporation i See Actel's website for the latest version of the datasheet. ProASIC3 Flash Family FPGAs I/Os Per Package - 68 - 151 97 157 - - 13 - 34 24 38 - - - - 151 97 178 194 - - - 33 24 38 38 Differential I/O Pairs - 71 100 133 97 - - Single-Ended I/O Differential I/O Pairs - 71 91 - 96 - - A3P1000 Differential I/O Pairs Single-Ended I/O 81 79 - - - - - A3P600 Single-Ended I/O Differential I/O Pairs A3P400 Single-Ended I/O A3P250 Single-Ended I/O A3P125 Single-Ended I/O Package QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484 Notes: A3P060 Single-Ended I/O A3P030 - 154 97 179 227 - - - 35 24 45 56 - - - 154 97 179 288 - - - 35 24 45 68 1. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 2. FG256 and FG484 are footprint-compatible packages. 3. Advanced information subject to change. Ordering Information A3P1000 _ 1 FG 144 I Application (Ambient Temperature Range) Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) PP = Pre-Production ES = Engineering Silicon (Room Temperature Only) Package Lead Count Package Type QN = Quad Flat No Leads (0.5 mm pitch) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) TQ = Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade F = 20% Slower than Standard* Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number A3P030 = A3P060 = A3P125 = A3P250 = A3P400 = A3P600 = A3P1000 = 30,000 System Gates 60,000 System Gates 125,000 System Gates 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates Note: *DC and switching characteristics for -F speed grade targets based only on simulation. The characteristics provided for -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in commercial temperature range. Figure 1 * Ordering Information ii A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Temperature Grade Offerings Package A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 QN132 C, I - - - - - - VQ100 C, I C, I C, I C, I - - - TQ144 - C, I C, I - - - - PQ208 - - C, I C, I C, I C, I C, I FG144 - C, I C, I C, I C, I C, I C, I FG256 - - - C, I C, I C, I C, I FG484 - - - - C, I C, I C, I Note: C = Commercial Temperature Range: 0C to 70C Ambient I = Industrial Temperature Range: -40C to 85C Ambient Speed Grade and Temperature Grade Matrix -F 3 Std. -1 -2 C I - Notes: 1. C = Commercial Temperature Range: 0C to 70C Ambient 2. I = Industrial Temperature Range: -40C to 85C Ambient 3. DC and switching characteristics for -F speed grade targets based only on simulation. The characteristics provided for -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in commercial temperature range. Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html). A d v a n c ed v 0.2 iii ProASIC3 Flash Family FPGAs Table of Contents Introduction and Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Device Architecture Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 Embedded FROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60 Package Pin Assignments 132-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Datasheet Information Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 iv A d va n ce d v 0 . 2 ProASIC3 Flash Family FPGAs Introduction and Overview General Description Security ProASIC3, the third-generation family of Actel Flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS(R) family. The nonvolatile Flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up. ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, user nonvolatile FlashROM (FROM) memory storage as well as clock conditioning circuitry based on an integrated phaselocked loop (PLL). The A3P030 device has no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 288 user I/Os. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low-unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, the Flash-based ProASIC3 devices allow for all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. The nonvolatile, Flash-based ProASIC3 devices require no boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile, Flash programming can offer. ProASIC3 devices utilize a 128-bit Flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FROM data in the ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000, and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decryption engine and a Flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The Flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. ProASIC3, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. A ProASIC3 device provides the most impenetrable security for programmable logic designs. A d v a n c ed v 0.2 1-1 ProASIC3 Flash Family FPGAs Single Chip Low Power Flash-based FPGAs store the configuration information in on-chip Flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, Flash-based ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load the device configuration data. This reduces bill-of-materials costs and printed circuit board (PCB) area, and increases security and system reliability. Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge, and no high-current transition period, both of which occur on many FPGAs. ProASIC3 devices also have low dynamic power consumption to further maximize power savings. Live at Power-Up Actel's Flash-based ProASIC3 devices support Level 0 of the live-at-power-up classification standard, hence helping in system components initialization, executing critical tasks before the processor wakes up, setup and configure memory blocks, clock generation, and bus activity management. The live-at-power-up feature of Flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for Complex Programmable Logic Device (CPLD) and clock generation PLL that are used for this purpose in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's Flash configuration, and unlike SRAMbased FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flashbased ProASIC3 devices simplify total system design, and reduce cost and design risk, while increasing system reliability and improving system initialization time. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 Flashbased FPGAs. Once it is programmed, the Flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced Flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant Flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-3 and Figure 1-2 on page 1-3): * Dedicated FlashROM (FROM) memory * Dedicated SRAM/FIFO memory1 * Extensive clock conditioning circuitry (CCC) and PLLs1 * Advanced I/O structure * FPGA VersaTiles The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function or a D-flip-flop (with or without enable) or latch by programming the appropriate Flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input look-up-table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC families of Flash-based FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of the ProASIC3 devices via an IEEE1532 JTAG interface. 1. The A3P030 device does not support PLL and SRAM. 1 -2 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* User Nonvolatile FlashROM (FROM) Bank 0 Bank 1 VersaTile Charge Pumps Bank 1 Note: *Not supported by A3P030. Figure 1-1 * ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125) Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption User Nonvolatile FlashROM (FROM) Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000) Bank 2 Figure 1-2 * ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P400, A3P600, and A3P1000) A d v a n c ed v 0.2 1-3 ProASIC3 Flash Family FPGAs User Nonvolatile FlashROM (FROM) SRAM and FIFO Actel ProASIC3 devices have 1 kbit of on-chip, useraccessible, nonvolatile FlashROM (FROM). The FROM can be used in diverse system applications such as: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FROM is written using the standard ProASIC3 IEEE1532 JTAG programming interface. The core can be individually programmed (erased and written) and onchip AES decryption can be used selectively to securely load data over public networks (except in the A3P030 device), such as security keys stored in the FROM for a user design. The FROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FROM can ONLY be programmed from the JTAG interface, and cannot be programmed from the internal logic array. The FROM is programmed as 8 banks of 128 bits; however, reading is performed on a random byte-bybyte basis. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three MSBs of the FROM address determine the bank and the four LSBs of the FROM address define the byte. The Actel ProASIC3 development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer version 6.1 or later, have extensive support for the FROM memory. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. The second part allows the inclusion of static data for system version control. Data for the FROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FROM contents. 1 -4 ProASIC3 devices (except in the A3P030 device) have embedded SRAM blocks along the north and south sides of the device. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, or 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a four-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode), using the UJTAG macro (except for the A3P030 device). Refer to the application note, UJTAG in ProASIC3/E Devices, for more details. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for the generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and Clock Conditioning Circuitry (CCC) ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a phase-locked loop (PLL) (Figure 2-10 on page 2-10). The A3P030 does not have a PLL. The six CCC blocks are located in the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access (refer to the "Clock Conditioning Circuits" section on page 2-13 for more information). The inputs of the six CCC blocks are accessible from the FPGA core or from one of several I/O inputs located near the CCC that have dedicated connections to the CCC block. A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs The CCC block has the following key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz * Clock delay adjustment via programmable and fixed delays from -7.56 ns to +11.12 ns * Two programmable delay types; refer to Figure 217 on page 2-17, Table 2-4 on page 2-18, and the "Features Supported on Every I/O" section on page 2-29 for more information. * Clock skew minimization * Clock frequency synthesis (for PLL only) Additional CCC specifications: * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). * Output duty cycle = 50% 1.5% or better (for PLL only) * Low output jitter: worst case < 2.5% * clock period peak-to-peak period jitter (for PLL only) Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks (Figure 2-10 on page 2-10). The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In all, ProASIC3 FPGAs support many different I/O standards, both single-ended and differential. For more information, see Table 2-19 on page 2-42. The I/Os are organized into banks, with two or four banks per device. Refer to Table 2-18 on page 2-42 for details on I/O bank configuration. The configuration of these banks determines the I/O standards supported (see Table 2-18 on page 2-42 for more information). Each I/O module contains several input, output, and enable registers (Figure 2-23 on page 2-30). These registers allow the implementation of the following: - 70 ps at 350 MHz * Single-Data-Rate applications - 90 ps at 100 MHz * - 180 ps at 24 MHz Double-Data-Rate applications - DDR LVDS I/O for point-to-point communications * Maximum acquisition time = 150 s (for PLL only) VersaTiles * Low power consumption of 5 mW * Exceptional tolerance to input period jitter - allowable input jitter is up to 1.5 ns (for PLL only) The ProASIC3 core consists of VersaTiles, which have been enhanced over the ProASICPLUS core tiles. The ProASIC3 VersaTile supports the following: * Four precise phases; maximum misalignment between adjacent phases of 40 ps * (350 MHz / fOUT_CCC) (for PLL only) Global Clocking ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. LUT-3 Equivalent X1 X2 X3 LUT-3 Y * All three-input logic functions - LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. For more information about VersaTiles, refer to the "VersaTile" section on page 2-2. D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Y D-FF Enable CLR Figure 1-3 * VersaTile Configurations A d v a n c ed v 0.2 1-5 ProASIC3 Flash Family FPGAs Related Documents Application Notes In-System Programming (ISP) in ProASIC3/E Using FlashPro3 http://www.actel.com/documents/PA3_E_ISP_AN.pdf Optimal Usage of Global Network Spines in ProASICPLUS Devices http://www.actel.com/documents/PAPLUS_Spines_AN.pdf ProASIC3/E FlashROM (FROM) http://www.actel.com/documents/PA3_E_FROM_AN.pdf ProASIC3/E Security http://www.actel.com/documents/PA3_E_Security_AN.pdf ProASIC3/E SRAM/FIFO Blocks http://www.actel.com/documents/PA3_E_SRAMFIFO_AN.pdf Programming a ProASIC3/E Using a Microprocessor http://www.actel.com/documents/PA3_E_Microprocessor_AN.pdf UJTAG Applications in ProASIC3/E Devices http://www.actel.com/documents/PA3_E_UJTAG_AN.pdf Using DDR for ProASIC3/E Devices http://www.actel.com/documents/PA3_E_DDR_AN.pdf Using Global Resources in Actel ProASIC3/E Devices http://www.actel.com/documents/PA3_E_Global_AN.pdf For additional ProASIC3 application notes, go to http://www.actel.com/techdocs/appnotes/products.aspx. User's Guides ACTgen Core Reference Guide http://www.actel.com/documents/gen_refguide.pdf Designer's User's Guide http://www.actel.com/documents/designerUG.pdf ProASIC3/E Macro Library Guide http://www.actel.com/documents/pa3_libguide.pdf 1 -6 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Device Architecture Introduction Flash Technology Advanced Flash Switch Unlike SRAM FPGAs, the ProASIC3 family uses a live-onpower-up ISP Flash switch as its programming element. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate VersaTile inputs and outputs. In the Flash switch, two transistors share the floating gate, which stores the programming information (Figure 2-1). One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. The latter is used to connect or separate routing nets, or to configure VersaTile logic. It is also used to erase the floating gate. Dedicated highperformance lines are connected as required using the Flash switch for fast, low-skew, global signal distribution throughout the device core. Maximum core utilization is possible for virtually any design. The use of the Flash switch technology also removes the possibility of firm errors, which are increasingly common in SRAM-based FPGAs. Floating Gate Sensing Switch In Switching Word Switch Out Figure 2-1 * ProASIC3 Flash-Based Switch A d v a n c ed v 0.2 2-1 ProASIC3 Flash Family FPGAs Device Overview The ProASIC3 device family consists of five distinct programmable architectural features (Figure 2-2 and Figure 2-3 on page 2-3): * FPGA fabric/core (VersaTiles) * Routing and clock resources (VersaNets) * FlashROM (FROM) memory * Dedicated SRAM/FIFO memory (except A3P030) * Advanced I/O structure VersaTile The proprietary ProASIC3 family architecture provides granularity comparable to gate arrays. The ProASIC3 device core consists of a sea-of-VersaTiles architecture. As illustrated in Figure 2-4 on page 2-4, there are four inputs in a logic VersaTile cell, and each VersaTile can be configured using the appropriate Flash switch connections: Any three-input logic function * Latch with clear or set D-flip-flop with clear or set * Enable D-flip-flop with clear or set (on a fourth input) VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. When the VersaTile is used as an enable D-flip-flop, the SET/CLR is supported by a fourth input. The fourth input is routed to the core cell over the VersaNet (global) network. Core Architecture * * The SET/CLR signal can only be routed to this fourth input over the VersaNet (global) network. However, if in the user design, the SET/CLR signal is not routed over the VersaNet network, a compile warning message will be given and the intended logic function will be implemented by two VersaTiles instead of one. The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when connection is to the efficient long-lines or very-long-lines resources. Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* User Nonvolatile FlashROM (FROM) Bank 0 Bank 1 VersaTile Charge Pumps Bank 1 Note: *Not supported by A3P030. Figure 2-2 * ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125) 2 -2 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption User Nonvolatile FlashROM (FROM) Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000) Bank 2 Figure 2-3 * ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P400, A3P600, A3P1000) A d v a n c ed v 0.2 2-3 ProASIC3 Flash Family FPGAs 0 1 Y pin 1 Data X3 0 1 0 1 F2 YL 0 1 CLK X2 CLR/ Enable X1 CLR XC* Legend: Via (hard connection) Switch (Flash connection) Note: *This input can only be connected to the global clock distribution network. Figure 2-4 * ProASIC3 Core VersaTile 2 -4 A d v a n c e d v 0 .2 Ground ProASIC3 Flash Family FPGAs Array Coordinates Since the I/O coordinate system changes depending on the die/package combination, it is not listed in Table 2-1. The Designer ChipPlanner tool provides array coordinates of all I/O locations. I/O and cell coordinates are used for placement constraints. However, I/O placement is easier by package pin assignment. During many place-and-route operations in the Actel Designer software tool, it is possible to set constraints that require array coordinates. Table 2-1 is provided as a reference. The array coordinates are measured from the lower left (0, 0). They can be used in region constraints for specific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and I/Os. Figure 2-5 illustrates the array coordinates of an A3P600 device. For more information on how to use array coordinates for region/placement constraints, see the Designer User's Guide or online help (available in the software) for ProASIC3 software tools. Table 2-1 provides array coordinates of core cells and memory blocks. Table 2-1 * ProASIC3 Array Coordinates VersaTiles Memory Rows Min. Max. All Bottom Top Min. Max. Device x y x y (x, y) (x, y) (x, y) (x, y) A3P030 - - - - - - - - A3P060 3 2 66 25 None (3, 26) (0, 0) (69, 29) A3P125 3 2 130 25 None (3, 26) (0, 0) (133, 29) A3P250 3 2 130 49 None (3, 50) (0, 0) (133, 53) A3P400 3 2 194 49 None (3, 50) (0, 0) (197, 53) A3P600 3 4 194 75 (3,2) (3, 76) (0, 0) (197, 79) A3P1000 3 4 258 99 (3,2) (3, 100) (0, 0) (261, 103) I/O Tile (0,79) Top Row (7, 79) to (189, 79) Bottom Row (5, 78) to (192, 78) (197, 79) Memory (3, 77) Blocks (3, 76) (194, 77) Memory (194, 76) Blocks VersaTile (Core) (3, 75) (194, 75) VersaTile (Core) (194, 4) VersaTile(Core) VersaTile (Core) (3, 4) (194, 3) Memory (194, 2) Blocks Memory (3, 3) Blocks (3, 2) (197, 1) (0, 0) I/O Tile UJTAG FlashROM Top Row (5, 1) to (168, 1) Bottom Row (7, 0) to (165, 0) (197, 0) Top Row (192, 1) to (169, 1) Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. Figure 2-5 * Array Coordinates for A3P600 A d v a n c ed v 0.2 2-5 ProASIC3 Flash Family FPGAs Routing Architecture Routing Resources The routing structure of ProASIC3 devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very-long-line resources, and the high-performance VersaNet networks. The ultra-fast local resources are dedicated lines that allow the output of each VersaTile to connect directly to every input of the eight surrounding VersaTiles (Figure 2-6). The exception to this is that the SET/CLR input of a VersaTile configured as a D-type flip-flop is driven only by the VersaTile global network. The efficient, long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 VersaTiles), run both vertically and horizontally, and cover the entire ProASIC3 device (Figure 2-7 on page 2-7). Each VersaTile can drive signals onto the efficient long-line resources, which can access every input of every VersaTile. Active buffers are inserted automatically by routing software to limit the loading effects. The high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length +/-12 VersaTiles in the vertical direction and length +/-16 in the horizontal direction from a given core VersaTile (Figure 2-8 on page 2-8). Very long lines in ProASIC3 devices have been enhanced over those in previous ProASIC families. This provides a significant performance boost for long-reach signals. The high-performance VersaNet global networks are low-skew, high-fanout nets that are accessible from external pins or from internal logic (Figure 2-9 on page 2-9). These nets are typically used to distribute clocks, resets, and other high-fanout nets requiring minimum skew. The VersaNet networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all VersaTiles. Long Lines L Inputs L L L Ultra-Fast Local Lines (connects a VersaTile to the adjacent VersaTile, I/O buffer, or memory block) Output L L L L L Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection. Figure 2-6 * Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors 2 -6 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Spans Four VersaTiles Spans Two VersaTiles Spans One VersaTile Logic VersaTile L L L L L L L L L L L L L L L L L L L L L L L L Spans One VersaTile Spans Two VersaTiles Spans Four VersaTiles VersaTile L L L L L L Figure 2-7 * Efficient Long-Line Resources A d v a n c ed v 0.2 2-7 ProASIC3 Flash Family FPGAs High-Speed, Very-Long-Line Resources Pad Ring SRAM I/O Ring Pad Ring I/O Ring 16x12 Block of VersaTiles Pad Ring Figure 2-8 * Very-Long-Line Resources 2 -8 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Clock Resources (VersaNets) ProASIC3 devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has up to six CCCs. The west CCC also contains a phase-locked loop (PLL) core, delay lines, phase shifter (0, 90, 180, 270), and clock multiplier/dividers. Each CCC has all the circuitry needed for the selection and interconnection of inputs to the VersaNet global network. The east and west CCCs each have access to three VersaNet global lines on each side of the chip (six total lines). Advantages of the VersaNet Approach One of the architectural benefits of ProASIC3 is the set of powerful and low-delay VersaNet global networks. ProASIC3 offers six chip (main) global networks that are distributed from the center of the FPGA array (Figure 2-9). In addition, ProASIC3 devices have three regional globals in each of the four chip quadrants. Each core VersaTile has access to nine global network resources: three quadrant and six chip (main) global networks, and a total of 18 globals on the device. Each of these networks contain spines and rows that reach all the VersaTiles in the quadrants (Figure 2-10 on page 2-10). This flexible VersaNet global network architecture allows users to map up to 144 different internal/external clocks in a ProASIC3 device. Details on the VersaNet networks are given in Table 2-2 on page 2-10. The flexible use of the ProASIC3 VersaNet global network allows the designer to address several design requirements. User applications that are clock-resource-intensive can easily route external or gated internal clocks using VersaNet global routing networks. Designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the VersaNet global network. In A3P030 devices, all six VersaNets come from the North edge of the FPGA fabric. The A3P030 does not support the VersaNet global network concept of top and bottom spines due to the limited gate density of this part. Quadrant Global Pads High-Performance VersaNet Global Network I/O Ring Pad Ring Pad Ring Top Spine Main (chip) Global Network Global Pads Chip (main) Global Pads Global Spine Global Ribs I/O RING Bottom Spine Spine-Selection Tree MUX Pad Ring Note: Not applicable to the A3P030 device. Figure 2-9 * Overview of ProASIC3 VersaNet Global Network A d v a n c ed v 0.2 2-9 ProASIC3 Flash Family FPGAs North Quadrant Global Network Quadrant Global Spine CCC CCC 3 3 3 Chip (main) Global Network 6 6 3 6 6 3 3 CCC CCC 6 Global Spine 6 6 3 3 6 3 3 CCC CCC South Quadrant Global Network Note: This does not apply to the A3P030, since the VersaNet global network is sourced only for the north edge of the FPGA fabric. Figure 2-10 * Global Network Architecture Table 2-2 * ProASIC3 Globals/Spines/Rows by Device A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Global VersaNets (Trees)* 6 9 9 9 9 9 9 VersaNet Spines/Tree 4 4 4 8 8 12 16 Total Spines 24 36 36 72 72 108 144 VersaTiles in Each Top or Bottom Spine 384 384 384 768 768 1,152 1,536 Total VersaTiles 768 1,536 3,072 6,144 9,216 13,824 24,576 Note: *There are six chip (main) globals and three globals per quadrant (except in the A3P030 device). VersaNet Global Networks and Spine Access The ProASIC3 architecture contains nine segmented global networks that can access all the VersaTiles, SRAM memory, and I/O tiles on the ProASIC3 device. These VersaNet global networks offer fast, low-skew routing resources for high-fanout nets, including clock signals. In addition, these highly-segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 144 internal/external clocks (in an A3P1000 device) or other high-fanout nets in ProASIC3 devices. Optimal usage of these low-skew networks can result in significant improvement in design performance on ProASIC3 devices. 2 -1 0 The nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global network, which has six spines. There are four quadrant global network regions per device (Figure 2-10). The spines are the vertical branches of the global network tree, shown in Figure 2-11 on page 2-11. Each spine in a vertical column of a chip (main) global network is further divided into two spine segments: one in the top and one in the bottom half of the die. Top and Advanced v0.2 ProASIC3 Flash Family FPGAs bottom spine segments, radiating from the center of a device, are the same height. Each spine covers a certain area of the ProASIC3 device (the "scope" of the spine). Each spine is accessed by the dedicated global network MUX tree architecture, which defines how a particular spine is driven--either by the signal on the global network from a CCC, for example, or another net defined by the user (Figure 2-12 on page 212). Quadrant spines can be driven from user I/Os on the north and south sides of the die. The ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design. Quadrant Global Pads T1 T2 Details of the chip (main) global network spine-selection MUX are presented in Figure 2-12 on page 2-12. The spine drivers for each spine are located in the middle of the die. Quadrant spines are driven from a north or south rib. Access to the top and bottom ribs is from the corner CCC or from the I/O on the north and south sides of the device. For details on using spines in ProASIC3 devices, see the Actel application note Optimal Usage of Global Network Spines in ProASICPLUS Devices. T3 High-Performance Global Network I/O Ring Pad Ring Pad Ring Top Spine Global Pads Chip (main) Global Pads Global Spine I/O RING Bottom Spine Global Ribs Spine-Selection MUX Tree Pad Ring B1 B2 B3 Logic Tiles Figure 2-11 * Spines in a Global Clock Tree Network A d v a n c ed v 0.2 2-11 ProASIC3 Flash Family FPGAs Clock Aggregation Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also through local resources in the north and south ribs, allowing I/Os to directly feed into the clock system. As Figure 2-13 indicates, this access system is contiguous. There is no break in the middle of the chip for the north and south I/O VersaNet access. This is different from the quadrant clocks, located in these ribs, which only reach the middle of the rib. Refer to the Using Global Resources in Actel ProASIC3/E Devices application note. Internal/External Signals Internal/External Signals Tree Node MUX Tree Node MUX Internal/External Signal Tree Node MUX Global Rib Internal/External Signal Global Driver MUX Spine Figure 2-12 * Spine Selection MUX of Global Tree Global Spine Global Rib Global Driver and MUX Tree Node MUX I/O Access Internal Signal Access Global Signal Access Figure 2-13 * Clock Aggregation Tree Architecture 2 -1 2 Advanced v0.2 I/O Tiles ProASIC3 Flash Family FPGAs Clock Conditioning Circuits Overview of Clock Conditioning Circuitry In ProASIC3 devices, the clock conditioning circuits (CCCs) are used to implement frequency division, frequency multiplication, phase shifting, and delay operations. The CCCs are available in six chip locations - each of the four chip corners and in the middle of the east and west chip sides. Each CCC can implement up to three independent global buffers (with or without programmable delay), or a PLL function (programmable frequency division/ multiplication, phase shift, and delays) with up to three global outputs. Unused global outputs of a PLL can be used to implement independent global buffers, up to a maximum of three global outputs for a given CCC. A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, and CLKC-GLC) of a given CCC. A PLL macro uses the CLKA CCC input to drive its reference clock. It uses the GLA and optionally the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global outputs cannot be reused if the YB (or YC) outputs are used (Figure 2-14 on page 2-14). Each global buffer, as well as the PLL reference clock, can be driven from one of the following: * Three dedicated single-ended hardwired connection I/Os using a * Two dedicated differential I/Os using a hardwired connection * The FPGA core The CCC block is fully configurable, either via Flash configuration bits set in the programming bitstream or through an asynchronous interface. This asynchronous interface is dynamically accessible from inside the ProASIC3 device to permit parameter changes (such as divide ratios) during device operation. To increase the versatility and flexibility of the clock conditioning system, the CCC configuration is determined either by the user during the design process, with configuration data being stored in Flash memory as part of the device programming procedure, or by writing data into a dedicated shift register during normal device operation. This latter mode allows the user to dynamically reconfigure the CCC without the need for core programming. The shift register is accessed through a simple serial interface. Refer to the UJTAG Applications in ProASIC3/E Devices application note and the "CCC Electrical Specifications" section on page 2-18 for more information. Global Buffers with No Programmable Delays The CLKBUF and CLKBUF_LVPECL/LVDS macros are composite macros that include an I/O macro driving a global buffer, which uses a hardwired connection. The CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are pass-through clock sources and do not use the PLL or provide any programmable delay functionality. The CLKINT macro provides a global buffer function driven by the FPGA core. Many specific CLKBUF macros support the wide variety of single-ended and differential I/O standards supported by ProASIC3 devices. The available CLKBUF macros are described in the ProASIC3/E Macro Library Guide. Global Buffer with Programmable Delay The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay. The CLKDLY macro takes the selected clock input and adds a userdefined delay element. This has the effect of a frequency-dependent output clock phase shift from the input clock. The CLKDLY macro can be driven by an INBUF macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. The CLKDLY macro can be driven directly from the FPGA core. The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. The visual CLKDLY configuration in the ACTgen part of the Libero IDE and Designer tools allows the user to select the desired amount of delay, and configures the delay elements appropriately. ACTgen also allows the user to select where the input clock is coming from. ACTgen will automatically instantiate the special macro, PLLINT, when needed. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards supported by the ProASIC3 family. The available INBUF macros are described in the ProASIC3/E Macro Library Guide. A d v a n c ed v 0.2 2-13 ProASIC3 Flash Family FPGAs Clock Source Clock Conditioning Input LVDS/LVPECL Macro PADN Output PLL Macro CLKA EXTFB POWERDOWN Y GLA GLA LOCK GLB YB GLC YC PADP or GLA and (GLB or YB) or OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV[4:0] OBMUX[2:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] INBUF* Macro PAD Y GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) CLKDLY Macro CLK GLA or GL GLB or DLYGL[4:0] GLC CLKBUF_LVDS/LVPECL Macro CLKBUF Macro CLKINT Macro PADN PADP Y PAD Y A Y Notes: 1. See the Actel website for future application notes concerning the dynamic PLL.The PLL is only supported on the west center CCC. The A3P030 has no PLL support. Refer to "PLL Function" section on page 2-15 for signal descriptions. 2. Refer to the ProASIC3/E Macro Library Guide for more information. Figure 2-14 * ProASIC3 CCC Options 2 -1 4 Advanced v0.2 ProASIC3 Flash Family FPGAs PLL Function1 The PLL functionality of the clock conditioning block is supported by the PLL macro. Note that the PLL macro reference clock uses the CLKA input of the CCC block, which is only accessible from the global A[0:2] package pins. Refer to Figure 2-15 on page 2-16 for more information. The PLL macro supports three inputs and up to six outputs (Figure 2-17 on page 2-17). Inputs: * CLKA: selected clock input * EXTFB: allows an external signal to be compared to a reference clock in the PLL core's phase detector * Powerdown (active Low): disables PLLs. The default state is Powerdown On (active Low). Outputs: * Lock: indicates that PLL output has locked on the input reference signal * GLA, GLB, GLC: outputs to respective global networks * YB, YC: allows output from the CCC to be routed back to the FPGA core As previously described, the PLL allows up to five flexible and independently configurable clock outputs. Figure 2-14 on page 2-14 illustrates the various clock output options and delay elements. As illustrated, the PLL will support three distinct output frequencies from a given input clock. Two of these (GLB and GLC) can be routed to the B and C global network access, respectively, and/or routed to the device core (YB and YC). Also in the feedback loop, there is a delay element that can be used to advance the clock relative to the reference clock. There are five delay elements to support phase control on all five outputs (GLA, GLB, GLC, YB, and YC). Note: Care must be taken if the output delay element is used in conjunction with an output divide. As there are a finite number of dividers and delay elements, exact output frequency and output phase may not always be derived from the input clock frequency. The PLL macro reference clock can be driven by an INBUF macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. The PLL macro reference clock can be driven directly from the FPGA core. The PLL macro reference clock can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. The visual PLL configuration in ACTgen, associated with the Libero IDE and Designer tools, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. ACTgen also allows the user to select the various delays and phase shift values necessary to adjust the phases between the reference clock (CLKA) and the derived clocks (GLA, GLB, GLC, YB and YC). ACTgen also allows the user to select where the input clock is coming from. ACTgen automatically instantiates the special macro, PLLINT, when needed. 1. The A3P030 device does not support PLL. A d v a n c ed v 0.2 2-15 ProASIC3 Flash Family FPGAs Each shaded box represents an input buffer called out by the appropriate INBUF or INBUF_LVDS/LVPECL. To Core Sample Pin Names 1 GAA0/IO0NDB0V0 1 GAA1/IO00PDB0V0 + Source for CCC (CLKA or CLKB or CLKC) 1 GAA2/IO13PDB7V1 Routed Clock 2 (from FPGA Core) + GAA[0:2]: GA represents global in the northwest corner Notes: 1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric. Refer to the "User I/O Naming Convention" on page 2-44 for more information. 2. Instantiate the routed clock source input as follows: a) Connect the output of a logic element to the clock input of PLL, CLKDLY, or CLKINT macro. b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location. 3. LVDS-based clock sources are only available on A3P250 through A3P1000 family members. A3P060 and A3P125 support singleended clock sources only. The A3P030 device does not support this feature. Figure 2-15 * Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT CLKBUF PAD A Y CLKINT Y CLKBUF_LVDS/LVPECL PADN PADP Y Note: The A3P030 device does not support this feature. Figure 2-16 * CLKBUF and CLKINT 2 -1 6 Advanced v0.2 ProASIC3 Flash Family FPGAs Table 2-3 * Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros CLKDLY CLKBUF Macros CLKBUF_LVCMOS5 CLK CLKBUF_LVCMOS33* GL CLKBUF_LVCMOS18 CLKBUF_LVCMOS15 DLYGL[4:0] CLKBUF_PCI CLKBUF_LVDS Note: The CLKDLY macro uses programmable delay element type 2. Figure 2-18 * CLKDLY CLKBUF_LVPECL Note: *By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology. For more details refer to the ProASIC3/E Macro Library Guide. CLKA EXTFB POWERDOWN GLA LOCK GLB YB GLC YC OADIV[4:0]* OAMUX[2:0]* DLYGLA[4:0]* OBDIV[4:0]* OBMUX[2:0]* DLYYB[4:0]* DLYGLB[4:0]* OCDIV[4:0]* OCMUX[2:0]* DLYYC[4:0]* DLYGLC[4:0]* FINDIV[6:0]* FBDIV[6:0]* FBDLY[4:0]* FBSEL[1:0]* XDLYSEL* VCOSEL[2:0]* Note: *See the Actel website for future application notes concerning the dynamic PLL. The A3P030 device does not support PLL. Figure 2-17 * CCC/PLL Macro A d v a n c ed v 0.2 2-17 ProASIC3 Flash Family FPGAs CCC Electrical Specifications Timing Characteristics Table 2-4 * ProASIC3 CCC/PLL Specification Parameter Min. Typ. Max. Unit Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz 1, 2 160 Delay Increments in Programmable Delay Blocks ps Number of Programmable Values in Each Programmable Delay Block 32 Input Period Jitter 1.5 ns Long Term Output Pk-Pk Period Jitter at fPLL_OUT = 24 MHz - 180 ps at fPLL_OUT = 100 MHz - 90 ps at fPLL_OUT = 350 MHz - 70 ps 150 s Acquisition Time Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 0.6 5.56 ns Delay Range in Block: Programmable Delay 2 1, 2 0.025 5.56 ns Delay Range in Block: Fixed Delay 1, 2 2.2 Notes: 1. This delay is a function of voltage and temperature. See Table 3-6 on page 3-4 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. The A3P030 device does not support PLL. 2 -1 8 Advanced v0.2 ns ProASIC3 Flash Family FPGAs Physical Implementation of CCC2 CCC Programming The CCC circuit is composed of the following (Figure 2-19): The clock conditioning circuit block is fully configurable, either via static Flash configuration bits in the array, set by the user in the programming bitstream, or through an asynchronous dedicated shift register dynamically accessible from inside the ProASIC3 device. The dedicated shift register permits parameter changes such as PLL divide ratios and delays during device operation. This latter mode allows the user to dynamically reconfigure the PLL without the need for core programming. The register file is accessed through a simple serial interface. Refer to the UJTAG Applications in ProASIC3/E Devices application note for more information. * PLL core * Three phase selectors * Six programmable delays and one fixed delay that advance/delay phase * Five programmable frequency dividers that provide frequency multiplication/division (not shown in Figure 2-19, because they are automatically configured based on the user's required frequencies) * One dynamic shift register that provides CCC dynamic reconfiguration capability CLKA Four-Phase Output PLL Core Phase Select Fixed Delay Programmable Delay Type 2 GLA Programmable Delay Type 1 EXTFB Phase Select Programmable Delay Type 2 GLB Programmable Delay Type 1 YB Programmable Delay Type 2 Clock divider and clock multiplier blocks are not shown in this figure or in ACTgen. They are automatically configured based on the user's required frequencies. GLC Phase Select Programmable Delay Type 1 YC Note: Refer to the "Clock Conditioning Circuits" section on page 2-13 and Table 2-4 on page 2-18 for signal descriptions. Figure 2-19 * PLL Block 2. The A3P030 device does not support PLL. A d v a n c ed v 0.2 2-19 ProASIC3 Flash Family FPGAs Nonvolatile Memory (NVM) Overview of User Nonvolatile FlashROM (FROM) ProASIC3 devices have 1 kbit of on-chip nonvolatile Flash memory that can be read from the FPGA core fabric. The FROM is arranged in 8 banks of 128 bits during programming. The 128 bits in each bank are addressable as 16 bytes during the read back of the FROM from the FPGA core (Figure 2-20). Programming involves an automatic, on-chip bank erase prior to reprogramming the bank. The FROM supports asynchronous read with a nominal 10 ns access time. The FROM can be read on byte boundaries. The top 3 bits of the FROM address from the FPGA core define the bank that is being accessed. The bottom 4 bits of the FROM address from the FPGA core define which of the 16 bytes in the bank is being accessed. The FROM can only be programmed via the IEEE1532 JTAG port. It cannot be programmed directly from the FPGA core. When programming, each of the 8 128-bit banks can be selectively reprogrammed. The FROM can only be reprogrammed on a bank boundary. Byte Number in Bank 0 1 2 3 4 4 LSB of ADDR (READ) 5 6 7 8 Bank Number 3 MSB of ADDR (READ) 0 1 2 3 4 5 6 7 Figure 2-20 * FROM Architecture 2 -2 0 Advanced v0.2 9 10 11 12 13 14 15 ProASIC3 Flash Family FPGAs SRAM and FIFO3 ProASIC3 devices have embedded SRAM blocks along the north side of the device. In addition, A3P600 and A3P100 have an embedded SRAM block on the south side of the device. To meet the needs of high performance designs, the memory blocks operate strictly in synchronous mode for both read and write operations. The read and write clocks are completely independent, and each may operate at any desired frequency less than or equal to 350 MHz. * 4kx1, 2kx2, 1kx4, 512x9 (dual-port RAM - two read, two write or one read, one write) * 512x9, 256x18 (two-port RAM - one read and one write) * Sync write, sync pipelined, and nonpipelined read The ProASIC3 memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (Full, Empty, AFULL, AEMPTY). Block diagrams of the memory modules are illustrated in Figure 2-21 on page 2-22. During RAM operation, addresses are sourced by the user logic and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Refer to Figure 2-22 on page 2-23 for more information about the implementation of the embedded FIFO controller. The ProASIC3 architecture enables the read side and write side of RAMs to be organized independently, allowing for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9. Both the write width and read width for the RAM blocks can be specified independently with the WW (write width) and RW (read width) pins. The different DxW configurations are: 256x18, 512x9, 1kx4, 2kx2, and 4kx1. Refer to the allowable RW and WW values supported for each of the RAM macro types in Table 2-5 on page 2-24. When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. The RAM blocks employ little-endian byte order for read and write operations. 3. The A3P030 device does not support SRAM and FIFO. A d v a n c ed v 0.2 2-21 ProASIC3 Flash Family FPGAs RAM512X18 RAM4K9 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB0 DOUTB0 DINB8 DINB7 RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL0 AFVAL11 AFVAL10 REN RCLK DOUTB8 DOUTB7 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 PIPE ADDRB11 ADDRB10 FIFO4K18 WADDR8 WADDR7 WADDR0 WD17 WD16 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WD0 WW1 WW0 WEN WBLK WCLK RPIPE WEN WCLK RESET RESET Note: The A3P030 device does not support SRAM and FIFO. Figure 2-21 * Supported Basic RAM Macros 2 -2 2 Advanced v0.2 RESET ProASIC3 Flash Family FPGAs WBLK WEN RPIPE FREN FWEN RD RW[2:0] WW[2:0] RD [17:0] WD [17:0] RCLK WCLK RAM RADD [J:0] WADD [J:0] REN WEN WD RCLK WCLK CNT 16 E FSTOP = FULL AFVAL AFULL V AEMPTY RBLK REN CNT 16 E SUB 16 AEVAL V= = EMPTY ESTOP Reset Note: The A3P030 device does not support SRAM and FIFO. Figure 2-22 * ProASIC3 RAM Block with Embedded FIFO Controller A d v a n c ed v 0.2 2-23 ProASIC3 Flash Family FPGAs Signal Descriptions for RAM4K94 The following signals are used to configure the RAM4K9 memory element: WIDTHA and WIDTHB These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 2-5). Table 2-5 * Allowable Aspect Ratio Settings for WIDTHA[1:0] ADDRA and ADDRB These are used as read or write addresses and are 12 bits wide. When a depth of less than 4 k is specified, the unused high-order bits must be grounded (Table 2-6). Table 2-6 * Address Pins Used for Various Supported Bus Widths DxW ADDRA/ADDRB UNUSED 4kx1 - WIDTHB1, WIDTHB0 DxW 2kx2 ADDRA[11], ADDRB[11] 00 00 4kx1 1kx4 ADDRA[11:10], ADDRB[11:10] 01 01 2kx2 512x9 10 10 1kx4 11 11 512x9 WIDTHA1, WIDTHA0 BLKA and BLKB These signals are active low and will enable the respective ports when asserted. When a BLKx signal is deasserted, that port's outputs hold the previous value. WENA and WENB These signals switch the RAM between read and write modes for the respective ports. A Low on these signals indicates a write operation, and a High indicates a read. CLKA and CLKB These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. ADDRA[11:9], ADDRB[11:9] DINA and DINB These are the input data signals, and these are nine bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused high-order signals must be grounded (Table 2-7). Table 2-7 * Data Pins Used for Various Supported Bus Widths DxW DINA/DINB UNUSED 4kx1 DINA[8:1], DINB[8:1] 2kx2 DINA[8:2], DINB[8:2] 1kx4 DINA[8:4], DINB[8:4] 512x9 - PIPEA and PIPEB These signals are used to specify pipelined read on the output. A Low on PIPEA and/or PIPEB indicates a nonpipelined read and the data appears on the corresponding output in the same clock cycle. A High indicates a pipelined read and data appears on the corresponding output in the next clock cycle. DOUTA and DOUTB These are the output data signals, and these are nine bits wide. Not all nine bits are valid in all configurations. As with DINA and DINB, high-order bits become unusable. The output data on unused pins is undefined. WMODEA and WMODEB These signals are used to configure the behavior of the output when RAM is in the write mode. A Low on these signals makes the output retain data from the previous read. A High indicates pass-through behavior where the data being written will appear immediately on the output. This signal gets overridden when RAM is being read. RAM512X18 has slightly different behavior than the RAM4K9, as it has dedicated read and write ports. RESET This active low signal resets the output to zero when asserted. It does not reset the content of the memory. Signal Descriptions for RAM512X184 WW and RW These signals enable the RAM to be configured in one of the two allowable aspect ratios (Table 2-8). Table 2-8 * Aspect Ratio Settings for WW[1:0] WW1, WW0 RW1, RW0 DxW 01 01 512x9 10 10 256x18 00, 11 Reserved 00, 11 4. The A3P030 device does not support SRAM and FIFO. 2 -2 4 Advanced v0.2 ProASIC3 Flash Family FPGAs WD and RD These are the input data and output signals, and they are 18 bits wide. When a 512x9 aspect ratio is used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, then RD[17:9] are undefined. WADDR and RADDR These are read and write addresses, and they are nine bits wide. When the 256x18 aspect ratio is used for write or read, WADDR[8] or RADDR[8] is unused and must be grounded. WCLK and RCLK These signals are the write and read clocks, respectively. They are both active high. WEN and REN These signals are the write and read enables, respectively. They are both active low by default. These signals can be configured as active high. RESET This active low signal resets the output to zero when asserted. It does not reset the contents of the memory. PIPE This signal is used to specify pipelined read on the output. A Low on PIPE indicates a nonpipelined read and the data appears on the output in the same clock cycle. A High indicates a pipelined read and data appears on the output in the next clock cycle. Clocking The dual-port SRAM blocks are only clocked on the rising edge. ACTgen allows falling-edge triggered clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge and/or by separate clocks by port. ProASIC3 devices support inversion (bubble pushing) throughout the FPGA architecture, including the clock input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the HDL code will be automatically accounted for during design compile without incurring additional delay in the clock path. The two-port SRAM can be clocked on the rising edge or falling edge of the WCLK and RCLK. If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automatically used within the ProASIC3 development tools, without performance penalty. Modes of Operation There are two read modes and one write mode: * Read Nonpipelined (synchronous - one clock edge): In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the read port clock active edge and data appears at RD after the RAM access time. Setting PIPE to Off enables this mode. * Read Pipelined (synchronous - two clock edges): The pipelined mode incurs an additional clock delay from the address to the data but enables operation at a much higher frequency. The read address is registered on the read port active clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting the PIPE to ON enables this mode. * Write (synchronous - one clock edge): On the write clock active edge, the write data is written into the SRAM at the write address when WEN is high. The setup times of the write address, write enables, and write data are minimal with respect to the write clock. Write and read transfers are described with timing requirements in the "DDR Module Specifications" section on page 3-37. RAM Initialization Each SRAM block can be individually initialized on power-up by means of the JTAG port using the UJTAG mechanism (refer to the "JTAG 1532" section on page 248 and the ProASIC3/E SRAM/FIFO Blocks application note). The shift register for a target block can be selected and loaded with the proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation. Signal Descriptions for FIFO4K185 The following signals are used to configure the FIFO4K18 memory element: WW and RW These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 2-9). Table 2-9 * Aspect Ratio Settings for WW[2:0] WW2, WW1, WW0 RW2, RW1, RW0 DxW 000 000 4kx1 001 001 2kx2 010 010 1kx4 011 011 512x9 100 100 256x18 101, 110, 111 Reserved 101, 110, 111 5. The A3P030 device does not support SRAM and FIFO. A d v a n c ed v 0.2 2-25 ProASIC3 Flash Family FPGAs WBLK and RBLK These signals are active low and will enable the respective ports when low. When the RBLK signal is high, that port's outputs hold the previous value. WEN and REN Read and write enables. WEN is active low and REN is active high by default. These signals can be configured as active high or low. WCLK and RCLK These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. RPIPE This signal is used to specify pipelined read on the output. A Low on RPIPE indicates a nonpipelined read and the data appears on the output in the same clock cycle. A High indicates a pipelined read and data appears on the output in the next clock cycle. RESET This active low signal resets the output to zero when asserted. It resets the FIFO counters. It also sets all the RD pins low, the Full and AFULL pins low, and the Empty and AEMPTY pins high (Table 2-10). WD This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data width less than 18 is specified, unused higher-order signals must be grounded (Table 2-10). RD This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD bus, highorder bits become unusable if the data width is less than 18. The output data on unused pins is undefined (Table 2-10). Table 2-10 * Input Data Signal Usage for Different Aspect Ratios DxW WD/RD Unused 4kx1 WD[17:1], RD[17:1] 2kx2 WD[17:2], RD[17:2] 1kx4 WD[17:4], RD[17:4] 512x9 WD[17:9], RD[17:9] 256x18 - ESTOP, FSTOP ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the Empty flag goes high). A High on this signal inhibits the counting. 2 -2 6 FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the Full flag goes high). A High on this signal inhibits the counting. For more information on these signals, refer to the "ESTOP and FSTOP Usage" section. FULL, EMPTY When the FIFO is full and no more data can be written, the Full flag asserts high. The Full flag is synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to prevent overflows. Since the write address is compared to a resynchronized (and thus timedelayed) version of the read address, the Full flag will remain asserted until two WCLK active edges after a read operation eliminates the full condition. When the FIFO is empty and no more data can be read, the Empty flag asserts high. The Empty flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition and to prevent underflows. Since the read address is compared to a resynchronized (and thus time delayed) version of the write address, the Empty flag will remain asserted until two RCLK active edges, after a write operation, removes the empty condition. For more information on these signals, refer to the "FIFO Flags Usage Considerations" section on page 2-27. AFULL, AEMPTY These are programmable flags and will be asserted on the threshold specified by AFVAL and AEVAL, respectively. When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output will go high. Likewise, when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go high. AFVAL, AEVAL The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values, respectively. They are 12-bit signals. For more information on these signals, refer to the "FIFO Flags Usage Considerations" section on page 2-27. ESTOP and FSTOP Usage The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e., the EMPTY flag goes high). Likewise, the FSTOP pin is used to stop the write counter from counting any further once the FIFO is full (i.e., the Full flag goes high). The FIFO counters in the ProASIC3 device start the count from 0, reach the maximum depth for the configuration (e.g., 511 for a 512x9 configuration), and then restart from 0. An example application for the ESTOP, where the read counter keeps counting, would be writing to the FIFO once and reading the same content over and over, without doing a write again. Advanced v0.2 ProASIC3 Flash Family FPGAs FIFO Flags Usage Considerations The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values, respectively. They are 12-bit signals. In order to handle different read and write aspect ratios, the values specified by the AEVAL and AFVAL pins are to be interpreted as the address of the last word stored in the FIFO. The FIFO actually contains separate write address (WADDR) and read address (RADDR) counters. These counters calculate the 12-bit memory address that is a function of WW and RW, respectively. WADDR is incremented every time a write operation is performed, and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To handle different read and write aspect ratios, the AFVAL and AEVAL are expressed in terms of total data bits instead of total data words. When users specify the AFVAL and AEVAL in terms of read or write words, the ACTgen tool translates them into bit addresses and configures these signals. ACTgen configures the Almost-Full flag, AFULL, to assert when the write address exceeds the read address by a predefined value. Assume the user has a 2kx8 FIFO, a value of 1,500 for AFVAL means that the AFULL flag will be asserted when a write causes the difference between the write address and the read address to be 1,500. The AEMPTY flag is asserted when the difference between the write address and the read address is less than a predefined value. In the example above, a value of 200 for AEVAL means that the AEMPTY flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. Note that the FIFO can be configured with different read and write widths; in this case the AFVAL setting is based on the number of write data entries and the AEVAL setting is based on the number of read data entries. In the case of 512x9 and 256x18 aspect ratios, since only 4,096 bits can be addressed by 12 bits of the AFVAL/ AEVAL, the number of words must be multiplied by 8 and 16, instead of 9 and 18. The ACTgen tool automatically uses the proper values. To avoid half words being written or read, which could happen if different read and write aspect ratios are specified, the FIFO will assert Full or Empty as soon as at least a minimum of one word cannot be written or read. For example, if a two-bit word is written and a four-bit word is being read, FIFO will remain in the empty state when the first word is written. This occurs even if the FIFO is not completely empty, because at this time a single word cannot be read. The same is applicable in the full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one word is read. The FULL flag will remain asserted because a complete word cannot be written at this point. Refer to the ProASIC3/E SRAM/FIFO Blocks application note for more information. Advanced I/Os Introduction ProASIC3 devices feature a flexible I/O structure, supporting a range of mixed-voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) through a bank-selectable voltage. Table 2-11, Table 2-12, and Table 2-18 on page 2-42 show the voltages and the compatible I/O standards. I/Os provide programmable slew rates, drive strengths, weak pull-up, and weak pull-down circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V tolerant. See the "5 V Input Tolerance" section on page 2-35 for possible implementations of 5 V tolerance. All I/Os are in a known state during power-up, and any power-up sequence is allowed without current impact. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)" section on page 3-3 for more information. I/O Tile The ProASIC3 I/O tile provides a flexible, programmable structure for implementing a large number of I/O standards. In addition, the registers available in selected I/O banks can be used to support high-performance register inputs and outputs, with register enable if desired (Figure 2-23 on page 2-30). The registers can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure (see the "Double Data Rate (DDR) Support" section on page 2-31 for more information). As depicted from Figure 2-23 on page 2-30, all I/O registers share one CLR port. The output register and output enable register share one CLK port. Refer to the "I/O Registers" section on page 2-30 for more information. A d v a n c ed v 0.2 2-27 ProASIC3 Flash Family FPGAs I/O Banks and I/O Standards Compatibility I/Os are grouped into I/O voltage banks. There are four I/O banks on the A3P250 through A3P1000. The A3P030, A3P060, and A3P125 have two I/O banks. Each I/O voltage bank has dedicated input/output supply and ground voltages (VMV/GNDQ for input buffers and VCCI/ GND for output buffers). Because of these dedicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Table 2-12 shows the required voltage compatibility values for each of these voltages. For more information about I/O and global assignments to I/O banks, refer to the specific pin table of the device in the "Package Pin Assignments" section on page 4-1 and the "User I/O Naming Convention" section on page 2-44. I/O standards are compatible if their VCCI and VMV values are identical. VMV and GNDQ are "quiet" input power supply pins and are not used on A3P030. Table 2-11 * ProASIC3 Supported I/O Standards A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5V, LVCMOS 2.5 /5.0 V 3.3 V PCI / 3.3 V PCI-X - - - - Single-Ended Differential LVPECL and LVDS Table 2-12 * VCCI Voltages and Compatible Standards VCCI and VMV (typ.) Compatible Standards 3.3 V LVTTL/LVCMOS 3.3, PCI 3.3, LVPECL 2.5 V LVCMOS 2.5, LVCMOS 2.5/5.0, LVDS 1.8 V LVCMOS 1.8 1.5 V LVCMOS 1.5 2 -2 8 Advanced v0.2 ProASIC3 Flash Family FPGAs Features Supported on Every I/O Table 2-13 lists all features supported by Transmitter/Receiver for single-ended and differential I/Os. Table 2-13 * I/O Features Feature Single-Ended Transmitter Features Description * Hot insertion in every mode except PCI or 5-V-input-tolerant (these modes use clamp diodes and do not allow hot insertion) (A3P030 only) * Activation of hot insertion (disabling the clamp diode) is selectable by I/Os (A3P030 only) * Weak pull-up and pull-down * Two slew rates * Skew between output buffer enable/disable time: 2 ns delay (delay on rising edge) and 0 ns delay on falling edge (see "Selectable Skew between Output Buffer Enable/Disable Time" on page 2-39 for more information) * * Three drive strengths 5 V tolerant receiver ("5 V Input Tolerance" section on page 2- 35) Single-Ended Receiver Features Differential Receiver Features (A3P250 through A3P1000) CMOS-Style LVDS or LVPECL Transmitter LVDS/LVPECL Differential Receiver Features * LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs ("5 V Output Tolerance" section on page 2-38) * High performance (Table 2-14) * Electro-Statics Discharge (ESD) protection * High performance (Table 2-14) * Separate ground and power planes, GNDQ/VMV, for input buffers only to avoid output-induced noise in the input circuitry * ESD protection * High performance (Table 2-14) * Separate ground and power plane, GNDQ, and VMV pins for input buffers only to avoid output-induced noise in the input circuitry * Two I/Os and external resistors are used to provide a CMOS-style LVDS or LVPECL transmitter solution. * Weak pull-up and pull-down * Fast slew rate * ESD protection * High performance (Table 2-14) * Separate input buffer ground and power planes to avoid outputinduced noise in the input circuitry Table 2-14 * Maximum I/O Frequency for Single-Ended and Differential I/Os (maximum drive strength and high slew selected) Specification Performance Up To LVTTL/LVCMOS 3.3 V 200 MHz LVCMOS 2.5 V 250 MHz LVCMOS 1.8 V 200 MHz LVCMOS 1.5 V 130 MHz PCI 200 MHz PCI-X 200 MHz LVDS 350 MHz LVPECL 350 MHz A d v a n c ed v 0.2 2-29 ProASIC3 Flash Family FPGAs I/O Registers Each I/O module contains several input, output, and enable registers. Refer to Figure 2-23 for a simplified representation of the I/O block. The number of input registers is selected by a set of switches (not shown in Figure 2-23) in between registers to implement single or differential data transmission to and from the FPGA core. The Designer software sets these switches for the user. A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. 1 Input Reg IO/Q0 2 Input Reg Y Pull-Up/Down Resistor Control CLR/PRE To FPGA Core IO/Q1 ICE 3 Input Reg PAD CLR/PRE IO/ICLK Signal Drive Strength and Slew-Rate Control A IO/D 0 4 Output OCE Reg From FPGA Core E= Enable Pin CLR/PRE CLR/PRE IO/D1/ICE ICE 5 Output Reg IO/OCLK IO/OE CLR/PRE OCE 6 Output Enable Reg IO/CLR or IO/PRE/OCE CLR/PRE Note: ProASIC3 I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-31). Figure 2-23 * I/O Block Logical Representation 2 -3 0 Advanced v0.2 ProASIC3 Flash Family FPGAs Double Data Rate (DDR) Support Output Support for DDR The basic DDR output structure is shown in Figure 2-25 on page 2-32. New data is presented to the output every half clock cycle. Note: DDR macros and I/O registers do not require additional routing. The combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the edge of the chip. The routing delay from the I/O registers to the I/O buffers is already taken into account in the DDR macro. Refer to the Actel application note, Using DDR for ProASIC3/E Devices for more information. ProASIC3 devices support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very highspeed systems. In addition, high-speed implemented using LVDS. DDR interfaces can be Input Support for DDR The basic structure to support a DDR input is shown in Figure 2-24. Three input registers are used to capture incoming data, which is presented to the core on each rising edge of the I/O register clock. Each I/O tile on ProASIC3 devices supports DDR inputs. Input DDR INBUF Data A X D X Out_QF (To Core) X Out_QR (To Core) FF1 E B X CLK CLKBUF FF2 C X CLR INBUF DDR_IN Figure 2-24 * DDR Input Register Support in ProASIC3 Devices A d v a n c ed v 0.2 2-31 ProASIC3 Flash Family FPGAs Data_F (From Core) A X FF1 Out B CLK 0 X CLKBUF C D Data_R (From Core) E X 1 X FF2 B CLR INBUF C X X DDR_OUT Figure 2-25 * DDR Output Support for ProASIC3 Devices 2 -3 2 Advanced v0.2 X OUTBUF ProASIC3 Flash Family FPGAs Hot-Swap Support For boards and cards with three levels of staging, it is assumed that card power supplies have time to reach their final value before the I/Os are connected. Pay attention to the sizing of power supply decoupling capacitors on the card to ensure that the power supplies are not overloaded with capacitance. Hot swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered-up system. The levels of hot-swap support and examples of related applications are described in Table 215. The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required. The only ProASIC3 device supporting hot-swap is the A3P030, which supports hot-swapping when the clamp diode is disabled. Cards with three levels of staging should have the following sequence: * Grounds * Powers I/Os and other pins Table 2-15 * Levels of Hot-Swap Support Power Hot Applied Swapping to Level Description Device Bus State Card Ground Connection Device Circuitry Connected to Bus Pins Example of Application with Cards that Contain ProASIC3 Devices - - - System and card is Compliant powered down, and then the card gets plugged into the system. Then, the power supplies are turned on. - In PCI hot-plug Compliant specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. Compliance of ProASIC3 Devices 1 Cold swap No 2 Hot swap while reset Yes Held state 3 Hot swap while bus idle Yes Held idle (no Same as Level 2 ongoing I/O processes during insertion/removal Board bus shared with card bus is "frozen", and there is no toggling activity on the bus, and it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. Compliant with cards with three levels of staging 4 Hot swap on an active bus Yes Bus may have Same as Level 2 Same as Level There is activity on the active I/O processes 3 system bus, and it is ongoing, but critical that the logic device being states set on the bus inserted or signal do not get removed must be disturbed during card idle insertion/removal. Compliant with cards with three levels of staging in reset Must be made and maintained for 1 ms before, during, and after insertion/ removal A d v a n c ed v 0.2 Must remain glitch-free during power up or power down 2-33 ProASIC3 Flash Family FPGAs Electro-Static Discharge (ESD) Protection ProASIC3 devices are tested per JEDEC Standard JESD22-A114-B. ProASIC3 devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage transients. Each I/O has two clamp diodes. One diode has its positive (P) side connected to pad, and its negative (N) side connected to VCCI. The second diode has its P side connected to GND, and its N side connected to pad. During operation, these diodes are normally biased in the off state, except when transient voltage is significantly above VCCI or below GND levels. In A3P030, the first diode is always off while on other ProASIC3 devices, the clamp diode is always on and cannot be switched off. By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 2-16 for more information about the I/O standards and the clamp diode. The second diode is always connected to the pad, regardless of the I/O configuration selected. Table 2-16 * ProASIC3I/O Hot-Swap and 5 V Input Tolerance Capabilities Clamp Diode1 I/O Assignment 3.3 V LVTTL/LVCMOS 3.3 V PCI, 3.3 V PCI-X A3P030 Other ProASIC3 Devices No Yes N/A Yes 5 V Input Tolerance2 A3P030 Other ProASIC3 Devices A3P030 Other ProASIC3 Devices Yes No Yes2 Yes2 Enabled/Disabled No N/A Yes2 Enabled/Disabled Yes3 Enabled/Disabled N/A Input Buffer Output Buffer No Yes Yes No Yes2 LVCMOS 2.5 V / 5.0 V 3 No Yes Yes No Yes2 Yes3 Enabled/Disabled LVCMOS 1.8 V No Yes Yes No No No Enabled/Disabled No Yes Yes No No No Enabled/Disabled N/A Yes N/A No N/A No Enabled/Disabled LVCMOS 2.5 V 3 Hot Insertion LVCMOS 1.5 V 4 Differential, LVDS/ LVPECL Notes: 1. 2. 3. 4. The clamp diode is always off for the A3P030 device and always active for other ProASIC3 devices. Can be implemented with an external IDT bus switch, resistor divider, or zener with resistor. Can be implemented with an external resistor and an internal clamp diode. LVCMOS 2.5 V and LVCMOS 2.5 V / 5.0 V I/O standards are identical in the ProASIC3 family. For the A3P030 device, these standards have no clamp diode; therefore, they both behave like a LVCMOS 2.5 V standard. For other ProASIC3 devices, these standards have a clamp diode; therefore, they both behave like LVCMOS 2.5 V / 5.0 V input standard. 5. Bidirectional LVDS or LVPECL buffers are not supported. I/Os can either be configured as input buffers or output buffers. 2 -3 4 Advanced v0.2 ProASIC3 Flash Family FPGAs 5 V Input Tolerance Rtx_out_high = Rtx_out_low = 10 I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V and LVCMOS 2.5 V configurations are used (see Table 2-17 on page 2-38 for more details). There are four recommended solutions (see Figure 2-26 to Figure 2-29 on page 2-38 for details of board and macro setups) to achieve 5 V receiver tolerance. All the solutions meet a common requirement of limiting the voltage at the I/O input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any voltage above 3.6 V may cause long term gate oxide failures. R1 = 36 (+/-5%), P(r1)min = 0.069 Solution 1 The board-level needs to ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-3 on page 3-2. This is a long term reliability requirement. This scheme will also work for a 3.3 V PCI / PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the two external resistors as explained below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Examples of possible resistor values (based on a simplified simulation model with no line effects, and 10 transmitter output resistance, where Rtx_out_high = (VCCI - VOH)/ IOH, Rtx_out_low = VOL / IOL). Example 1: (high speed, high current) R2 = 82 (+/-5%), P(r2)min = 0.158 Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 +10) = 45.04 mA tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Example 2: (low-medium speed, medium current) Rtx_out_high = Rtx_out_low = 10 R1 = 220 (+/-5%), P(r1)min = 0.018 R2 = 390 (+/-5%), P(r2)min = 0.032 Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 +10) = 9.17 mA tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V* when the transmitter sends a logic '1'. This range of Vin_dc(rx) has to be ensured for any combination of transmitter supply (5 V +/- 0.5 V), transmitter output resistance, and board resistor tolerances. Temporary overshoots are allowed according to Table 3-3 on page 3-2. Solution 1 ProASIC3 I/O Input 3.3 V 5.5 V Rext1 Rext2 Requires two board resistors, LVCMOS 3.3 V I/Os. Figure 2-26 * Solution 1 A d v a n c ed v 0.2 2-35 ProASIC3 Flash Family FPGAs Solution 2 The board-level design needs to ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-3 on page 3-2. This is a long-term reliability requirement. This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and zener, as shown in Figure 2-27. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Solution 2 ProASIC3 I/O Input 3.3 V 5.5 V Rext1 Zener 3.3 V Requires one board resistor, one Zener 3.3 V diode, LVCMOS 3.3 V I/Os. Figure 2-27 * Solution 2 2 -3 6 Advanced v0.2 ProASIC3 Flash Family FPGAs Solution 3 The board-level design needs to ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-3 on page 3-2. This is a long-term reliability requirement. This scheme will also work for 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in Figure 2-28. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Solution 3 ProASIC3 I/O Input 3.3 V Bus Switch IDTQS32X23 5.5 V 5.5 V Requires a bus switch on the board, LVTTL/LVCMOS 3.3 V I/Os. Figure 2-28 * Solution 3 A d v a n c ed v 0.2 2-37 ProASIC3 Flash Family FPGAs Solution 4 Solution 4 ProASIC3 I/O Input 2.5 V On-Chip Clamp Diode 5.5 V 2.5 V Rext Requires one board resistor. Available for all I/O standards excluding 3.3 V I/O standards. (Not supported for A3P030 device.) Figure 2-29 * Solution 4 Table 2-17 * Comparison Table for 5 V Compliant Receiver Scheme Solution Board Components 1 Two resistors 2 Resistor and Zener 3.3 V 3 Bus switch 4 Speed 2 Resistor R = 250 at TJ = 70C R = 500 at TJ = 85C R = 1000 at TJ = 100C Current Limitations Low to High1 Limited by transmitter's drive strength Medium Limited by transmitter's drive strength High N/A Low Diode current 12 mA at TJ = 70C 6 mA at TJ = 85C 3 mA at TJ = 100C Notes: 1. Speed and current consumption increase as the board resistance values decrease. 2. Resistor values ensure I/O diode long term reliability. 5 V Output Tolerance ProASIC3 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad voltage beyond the 3.6 V absolute maximum value, and consequently cause damage to the I/O. 2 -3 8 When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, ProASIC3 I/Os can directly drive signals into 5 V TTL receivers. In fact, VOL = 0.4 V and VOH = 2.4 V voltages on both 3.3 V LVTTL and 3.3 V LVCMOS modes exceed the VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level '1' and level '0' will be recognized correctly by 5 V TTL receivers. Advanced v0.2 ProASIC3 Flash Family FPGAs Selectable Skew between Output Buffer Enable/Disable Time The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion (disable) time. Output Enable ENABLE (IN) (from FPGA core) MUX ENABLE (OUT) Skew Circuit I/O Output Buffers Skew Select Figure 2-30 * Block Diagram of Output Enable Path ENABLE (IN) ENABLE (OUT) Less than 0.1 ns Less than 0.1 ns Figure 2-31 * Timing Diagram (Option1: Bypasses Skew Circuit) ENABLE (IN) ENABLE (OUT) 1.2 ns (typ) Less than 0.1 ns Figure 2-32 * Timing Diagram (Option 2: With Skew Circuit Selected) A d v a n c ed v 0.2 2-39 ProASIC3 Flash Family FPGAs On a system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter Transmitter ENABLE/ DISABLE Transmitter 1: ProASIC3 I/O Skew or Bypass Skew Routing EN(r1) Delay (t1) current shorts. Figure 2-33 presents an example of the skew circuit implementation in a bidirectional communication system. Figure 2-34 shows how a bus contention is created, and Figure 2-35 on page 2-41 shows how it can be avoided with the skew circuit. EN(b1) Transmitter 2: Generic I/O EN(b2) Routing Delay (t2) ENABLE(t2) ENABLE(t1) Bidirectional Data Bus Figure 2-33 * Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using ProASIC3 Devices EN (b1) EN (b2) ENABLE (r1) ENABLE (t1) Transmitter 1: OFF Transmitter 1: ON ENABLE (t2) Transmitter 2: ON Transmitter 2: OFF Bus Contention Figure 2-34 * Timing Diagram (Bypasses Skew Circuit) 2 -4 0 Advanced v0.2 Transmitter 1: OFF ProASIC3 Flash Family FPGAs EN (b1) EN (b2) ENABLE (t1) Transmitter 1: OFF Transmitter 1: ON Transmitter 1: OFF ENABLE (t2) Transmitter 2: ON Transmitter 2: OFF Result: No Bus Contention Figure 2-35 * Timing Diagram (with Skew Circuit Selected) A d v a n c ed v 0.2 2-41 ProASIC3 Flash Family FPGAs I/O Software Support Single-ended I/O standards in ProASIC3 support up to five different drive strengths. In the ProASIC3 development software, default settings have been defined for the various I/O standards that are supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are applicable for all I/O standards. Table 2-18 lists the valid I/O attributes that can be manipulated by the user for each I/O standard. Table 2-19 lists the default values for the above selectable I/O attributes as well as those that are preset for that I/O standard. See Table 2-21 on page 2-43 for SLEW and OUT_DRIVE settings. Table 2-18 * I/O Attributes vs. I/O Standard Applications SLEW (output only) OUT_DRIVE (output only) SKEW (all macros with OE) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 2.5/5.0 V LVCMOS 1.8 V LVCMOS 1.5 V I/O Standards LVDS LVPECL PCI (3.3 V) PCI-X (3.3 V) Table 2-19 * I/O Default Attributes RES_PULL OUT_LOAD (output only) COMBINE_REGISTER Off None 35 pF - LVCMOS 2.5 V Off None 35 pF - LVCMOS 2.5/5.0 V Off None 35 pF - LVCMOS 1.8 V Off None 35 pF - LVCMOS 1.5 V Off None 35 pF - PCI (3.3 V) Off None 10 pF - PCI-X (3.3 V) Off None 10 pF - LVDS Off None 0 pF - LVPECL Off None 0 pF - I/O Standards LVTTL/LVCMOS 3.3 V 2 -4 2 SLEW (output only) OUT_DRIVE (output only) SKEW) (tribuf and bibuf only) See Table 2-21 See Table 2-21 on page 2-43 on page 2-43 Advanced v0.2 ProASIC3 Flash Family FPGAs Weak Pull-Up and Weak Pull-Down Resistors ProASIC3 devices support optional weak pull-up and pull-down resistors per I/O pin. When the I/O is pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled-down it is connected to GND. Refer to Table 3-20 on page 3-16 for more information. Slew Rate Control and Drive Strength ProASIC3 devices support output slew rate control: high and low. The A3P030 device does not support slew rate control. The high slew rate option is recommended to minimize the propagation delay. This high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of noise but adds some delays in the system. A low slew rate is recommended when bus transients are expected. Drive strength should also be selected according to the design requirements and noise immunity of the system. The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V and LVCMOS 1.5 V. All other I/O standards have a high output slew rate by default. For A3P030, refer to Table 2-20; for other ProASIC3 devices, refer to Table 2-21 for more information about the slew rate and drive strength specification. Table 2-20 * A3P030 I/O Standards--OUT_DRIVE Settings OUT_DRIVE (mA) I/O Standards 2 4 8 LVTTL/LVCMOS33 LVCMOS25 LVCMOS25_50 LVCMOS18 - LVCMOS15 - Table 2-21 * ProASIC3 Device I/O Standards--SLEW and OUT_DRIVE Settings OUT_DRIVE (mA) I/O Standards 2 4 6 8 12 16 LVTTL/LVCMOS33 High Low LVCMOS25 - High Low LVCMOS25_50 - High Low LVCMOS18 - - High Low LVCMOS15 - - - - High Low A d v a n c ed v 0.2 Slew 2-43 ProASIC3 Flash Family FPGAs User I/O Naming Convention Due to the comprehensive and flexible nature of the ProASIC3 device user I/Os, a naming scheme is used to show the details of the I/O (Figure 2-36 and Figure 2-37 on page 2-45). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os. I/O Nomenclature = Gmn/IOuxwBy Gmn is only used for I/Os that also have CCC access - i.e., global pins. G = Global m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west middle). n = Global input MUX and pin number of the associated Global location m, either A0, A1,A2, B0, B1, B2, C0, C1, or C2. Figure 2-15 on page 2-16 shows the three input pins per each clock source MUX at the CCC location m. u = I/O pair number in the bank, starting at 00 from the northwest I/O bank in a clockwise direction. x = P (Positive) or N (Negative) for differential pairs, or S (Single-Ended) for the I/O that support single-ended and voltage-referenced I/O standards only w = D (Differential Pair) or P (Pair) or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair. GND VCC GND VCCIB1 VCOMPLF VCCPLF CCC "A" Vcc VCCIB0 GND Vcc VCCIB0 GND = Bank number [0..3]. Bank number starting at 0 from the northwest I/O bank in a clockwise direction. VCCIB0 GND = Bank y VMV0 GNDQ B CCC "B" Bank 0 GND GNDQ VMV0 VCC Bank 0 GND VCCIB0 Bank 1 A3P030 A3P060 A3P125 CCC/PLL "F" CCC "C" GND VCC VCCIB1 GND VMV1 GNDQ GND GND VCC Bank 0 VCCIB0 GND Bank 1 CCC "E" TCK TDI TMS Advanced v0.2 VMV2 GNDQ GND VCCIB1 VCC GND VCCIB2 VCC GND VCCIB1 Note: The A3P030 device does not support PLL (VCOMPLF and VCCPLF pins). Figure 2-36 * Naming Conventions of ProASIC3 Devices with Two I/O Banks 2 -4 4 CCC "D" Bank 1 VJTAG TRST TDO VPUMP GND GND Vcc GND VCCIB3 VCOMPLF VCCPLF GND VCC VCCIB3 GND VMV3 CCC "A" VCC VCCIB0 GND VCC VCCIB0 GND VCCIB0 GND VMV0 GNDQ ProASIC3 Flash Family FPGAs CCC "B" Bank 0 Bank 3 Bank 1 A3P250 A3P400 A3P600 A3P1000 CCC/PLL "F" VCC GND VCCIB1 CCC "C" Bank 3 Bank 1 GNDQ GND CCC "E" GND GNDQ VMV1 CCC "D" Bank 2 GND VCC VCCIB1 GND VJTAG TRST TDO VPUMP GND TCK TDI TMS VMV2 GNDQ GND VCCIB2 VCC GND VCCIB2 VCC GND VCCIB2 Figure 2-37 * Naming Conventions of ProASIC3 Devices with Four I/O Banks A d v a n c ed v 0.2 2-45 ProASIC3 Flash Family FPGAs Pin Descriptions VCOMPLF Ground to analog PLL. Unused VCOMPL pins should be connected to GND. Supply Pins GND VJTAG Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (Quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package, and improves input signal integrity. GNDQ needs to always be connected on the board to GND. VCC PLL Ground6 Core Supply Voltage JTAG Supply Voltage ProASIC3 devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies power supply and printed circuit board design. VPUMP Programming Supply Voltage ProASIC3 devices support single-voltage ISP programming of the configuration Flash and FROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and 3.6 V. Supply voltage to the FPGA core, nominal 1.5 V. VCCIBx Global Pins I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are eight I/O banks on ProASIC3 devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. X is the bank number. Within the package, the VMV plane is decoupled from the simultaneous switching noise originated from the output buffer VCCI domain. This minimizes the noise transfer within the package, and improves input signal integrity. Each bank must have at least one VMV connection. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e. VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLF GL GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as I/Os, since they have identical capabilities. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on page 2-13. Refer to the "User I/O Naming Convention" section on page 2-44 for a description of naming of global pins. JTAG Pins TCK Supply voltage to analog PLL. If unused, VCCPLF should be tied to GND. TDI Test data Input Serial input for JTAG boundary-scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. Test Data Output Serial output for JTAG boundary-scan, ISP, and UJTAG usage. The TDO pin does not have an internal weak pullup resistor. 6. The A3P030 device does not support this feature. 2 -4 6 Test Clock Test clock input for the JTAG boundary-scan, ISP, and UJTAG usage. Per the (JTAG) IEEE1532 specification, it is recommended that TCK be tied to GND or VJTAG when not used. This prevents a possible totem-pole current on the input buffer stage. The TCK pin does not have an internal weak pull-up resistor. TDO PLL Supply Voltage6 Globals Advanced v0.2 ProASIC3 Flash Family FPGAs TMS Test Mode Select The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK,TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Special Function Pins No connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Don't connect This pin should not be connected to any signals on the printed circuit board (PCB). These pins should be left unconnected. Software Tools * ChipPlanner - a graphical floorplanner viewer and editor * SmartPower - tool which enables the designer to quickly estimate the power consumption of a design * PinEditor - a graphical application for editing pin assignments and I/O attributes * I/O Attribute Editor - tool which displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel back-annotation flow is compatible with all the major simulators. Another tool included in the Designer software is the ACTgen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence(R). The Designer software is available for both the Windows(R) and UNIX operating systems. Programming Overview of Tools Flow The ProASIC3 family of FPGAs is fully supported by both Actel Libero IDE and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE flow diagram located on the Actel website). Libero IDE includes Synplify(R) AE from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), PALACETM Physical Synthesis from Magma Design AutomationTM, and Designer software from Actel. Actel Designer software is a place-and-route tool and provides a comprehensive suite of back-end support tools for FPGA development. The Designer software includes the following: * NetlistViewer - a design netlist schematic viewer Boundary Scan Reset Pin The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. In the operating mode, a 100 external pulldown resistor should be placed between TRST and GND to ensure that the chip does not switch into a different mode. NC * Timer - a world-class integrated static timing analyzer and constraints editor that supports timing-driven place-and-route Programming can be performed using various programming tools, such as Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel). The user can generate *.stp programming files from the Designer software and can use these files to program a device. ProASIC3 devices can be programmed in system. For more information on ISP of ProASIC3 devices, refer to the In-System Programming (ISP) in ProASIC3/E Using FlashPro3 and Programming a ProASIC3/E Using a Microprocessor application notes. Security ProASIC3 devices have a built-in 128-bit AES decryption core (except the A3P030 device). The decryption core facilitates secure, in-system programming of the FPGA core array fabric and the FROM. The FROM and the FPGA core fabric can be programmed independently from each other, allowing the FROM to be updated without the need for change to the FPGA core fabric. The AES master key is stored in on-chip nonvolatile memory (Flash). The AES master key can be preloaded into parts in a secure programming environment (such as the Actel in-house programming center) and then "blank" parts can be A d v a n c ed v 0.2 2-47 ProASIC3 Flash Family FPGAs shipped to an untrusted programming or manufacturing center for final personalization with an AES encrypted bitstream. Late stage product changes or personalization can be implemented easily and securely by simply sending a STAPL file with AES encrypted data. Secure remote field updates over public networks (such as the Internet) are possible by sending and programming a STAPL file with AES encrypted data. 128-Bit AES Decryption7 The 128-bit AES standard (FIPS-192) block cipher is the NIST (National Institute of Standards and Technology) replacement for the DES (Data Encryption Standard FIPS46-2). AES has been designed to protect sensitive government information well into the 21st century. It will replace the aging DES, which NIST adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect sensitive, unclassified information. The 128-bit AES standard has 3.4x1038 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text using exhaustive techniques. Keys are stored (securely) in ProASIC3 devices in nonvolatile Flash memory. All programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. All programming verification is performed on-chip, ensuring that the contents of ProASIC3 devices remain secure. AES decryption can also be used on the 1,024-bit FROM to allow for secure remote updates of the FROM contents. This allows for easy, secure support for subscription model products. See the application note, ProASIC3/E Security, for more details. ISP ProASIC3 devices support IEEE1532 ISP via JTAG and require a single VPUMP voltage of 3.3 V during programming. In addition, programming via a Microcontroller (MCU) in a target system can be achieved. See the application note In-System Programming (ISP) in ProASIC3/E Using FlashPro3 for more details. JTAG 1532 Programming ProASIC3 devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a ProASIC3 device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping the global IO_EN signal deactivated, which also has the effect of disabling the input buffers. Consequently, the SAMPLE instruction will have no effect while the ProASIC3 device is in this unprogrammed state. This is different behavior from that observed in the ProASICPLUS device family. This lack of effect is necessitated by the fact that SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be a noninvasive instruction, hence the lack of effect when the ProASIC3 device is in this unprogrammed state. Refer to the standard or the InSystem Programming (ISP) in ProASIC3/E Using FlashPro3 application note for more details. Boundary Scan ProASIC3 devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary-scan testing. The basic ProASIC3 boundary-scan logic circuit is composed of the TAP (test access port) controller, test data registers, and instruction register (Figure 2-38 on page 2-49). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-22 on page 2-49). Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI, and TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20 k pull-up resistor be added to TDO and TCK pins. The TAP controller is a 4-bit state machine (16 states) that operates as shown in Figure 2-38 on page 2-49. The 1s and 0s represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASIC3 devices have to be programmed at least once for complete boundary-scan functionality to be available. If boundary-scan functionality is required prior to partial programming, refer to online technical support on the Actel website and search for ProASIC3 BSDL. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin 7. The A3P030 device does not support AES decryption. 2 -4 8 Advanced v0.2 ProASIC3 Flash Family FPGAs may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. ProASIC3 devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number, and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. I/O I/O I/O I/O I/O TDI Test Data Registers Instruction Register TAP Controller Device Logic TDO I/O TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O I/O I/O Figure 2-38 * Boundary-Scan Chain in ProASIC3 Table 2-22 * Boundary-Scan Opcodes Hex Opcode EXTEST 00 HIGHZ 07 USERCODE 0E SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF A d v a n c ed v 0.2 2-49 ProASIC3 Flash Family FPGAs DC and Switching Characteristics General Specifications DC and switching characteristics for -F speed grade targets based only on simulation. The characteristics provided for -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in commercial temperature range. Operating Conditions Stresses beyond those listed in the Table 3-1 may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating ranges specified in Table 3-2 on page 3-2. Table 3-1 * Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage -0.3 to 1.65 V VJTAG JTAG DC voltage -0.3 to 3.75 V VPUMP Programming voltage -0.3 to 3.75 V VCCPLL Analog power supply (PLL) -0.3 to 1.65 V VCCI DC I/O output buffer supply voltage -0.3 to 3.75 V VMV DC I/O input buffer supply voltage -0.3 to 3.75 V VI I/O input voltage -0.3 V to 3.6 V (when I/O hot insertion mode is enabled) V -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) Notes: 1. Device performance is not guaranteed if storage temperature exceeds 110C. 2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-3 on page 3-2. A d v a n c ed v 0.2 3-1 ProASIC3 Flash Family FPGAs Table 3-2 * Recommended Operating Conditions Symbol Parameter Ta Ambient temperature VCC 1.5 V DC core supply voltage VJTAG JTAG DC voltage VPUMP Programming voltage Programming Mode Operation3 Commercial Industrial Units 0 to +70 -40 to +85 C 1.425 to 1.575 1.425 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.0 to 3.6 3.0 to 3.6 V 0 to 3.6 0 to 3.6 V 1.4 to 1.6 1.4 to 1.6 V VCCPLL Analog power supply (PLL) VCCI and VMV 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V 2.375 to 2.625 2.375 to 2.625 V 3.0 to 3.6 3.0 to 3.6 V LVDS differential I/O LVPECL differential I/O Notes: 1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 3-13 on page 3-14. VMV and VCCI should be at the same voltage within a given I/O bank. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. VPUMP can be left floating during operation (not programming mode). Table 3-3 * Overshoot and Undershoot Limits (as measured on quiet I/Os)1 VCCI and VMV Average VCCI-GND Overshoot or Undershoot Duration as Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V 2.7 V or less 3V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85C. 2. The duration is allowed at one cycle out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at one out of two cycles, then the maximum overshoot/undershoot has to be reduced by 0.15 V. Table 3-4 * Flash Programming, Storage, and Operating Limits Product Grade Programming Cycles Program Retention Commercial 500 Industrial 500 Storage Temperature Min. Max. Maximum Operating Junction Temperature TJ (C) 20 years 0 110 110 20 years -40 110 110 Note: This is a stress rating only. Functional operation at any other condition other than those indicated is not implied. 3 -2 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power-up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 3-1. VCC Trip Point: Ramping up: 0.6 V < trip_point_up <1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: * During programming, I/Os become tristated and weakly pulled up to VCCI. * JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. 1. VCC and VCCI are above the minimum specified trip points (Figure 3-1) Internal Power-Up Activation Sequence 2. VCCI > VCC - 0.75 V (Typ) 1. Core 3. Chip is in the operating mode 2. Input buffers VCCI Trip Point: Ramping up: 0.6 V < trip_point_up <1.2 V 3. Output buffers: after 200 ns delay from input buffer activation. Ramping down: 0.5 V < trip_point_down < 1.1 V VCC =VCCI + VT Where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specifcation. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH /VOL , etc. VCC = 1.425 V Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 3-1 * I/O State as a Function of VCCI and VCC Voltage Levels A d v a n c ed v 0.2 3-3 ProASIC3 Flash Family FPGAs Thermal Characteristics T = Temperature gradient between junction (silicon) and ambient T = ja * P Introduction ja = Junction-to-ambient of the package. ja numbers are located in Table 3-5. The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 110C. EQ 3-2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and still air. EQ 3-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + Ta EQ 3-1 Where Ta = Ambient Temperature 150C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 3.90 W 20.5C/W ja (C/W) EQ 3-2 Table 3-5 * Package Thermal Resistivities ja Pin Count jc Still Air Quad Flat No Lead (QFN) 132 13.2 28.9 24.6 23.1 C/W Very Thin Quad Flat Pack (VQFP) 100 10.0 35.3 29.4 27.1 C/W Thin Quad Flat Pack (TQFP) 144 11.0 33.5 28.0 25.7 C/W Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W Plastic Quad Flat Package (PQFP) with embedded heat spreader 208 3.8 16.2 13.3 11.9 C/W Fine Pitch Ball Grid Array (FBGA) 144 3.8 26.9 22.9 21.5 C/W 256 3.8 26.6 22.8 21.5 C/W 484 3.2 20.5 17.0 15.9 C/W Package Type 200 ft./min. 500 ft./min. Units Temperature and Voltage Derating Factors Table 3-6 * Temperature and Voltage Derating Factors for Timing Delays (Normalized to TJ = 70C, VCC = 1.425 V) Junction Temperature (C) Array Voltage VCC (V) -40C 0C 25C 70C 85C 110C 1.425 0.88 0.93 0.95 1.00 1.02 1.05 1.500 0.83 0.87 0.89 0.94 0.96 0.98 1.575 0.79 0.84 0.86 0.91 0.92 0.94 3 -4 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Calculating Power Dissipation Quiescent Supply Current Table 3-7 * Quiescent Supply Current Characteristics Static IDD1 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 70 mA Notes: 1. IDD Includes VCC, VPUMP, VCCI, and VMV currents in industrial temperature ranges (junction temperature from -40C to 85C). Values do not include I/O static contribution, which is shown in Table 3-8 and Table 3-9. 2. -F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage. Power Per I/O Pin Table 3-8 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings VMV (V) Static Power PDC2 (mW)1 Dynamic Power PAC9 (W/MHz)2 3.3 V LVTTL / 3.3 V LVCMOS 3.3 - 16.69 2.5 V LVCMOS 2.5 - 5.12 1.8 V LVCMOS 1.8 - 2.13 1.5 V LVCMOS (JESD8-11) 1.5 - 1.45 Single-Ended 3.3 V PCI 3.3 - 18.11 3.3 V PCI-X 3.3 - 18.11 LVDS 2.5 2.26 1.20 LVPECL 3.3 5.72 1.87 Differential Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. Table 3-9 * Summary of I/O Output Buffer Power (Per Pin) - Default I/O Software Settings1 CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 - 468.67 2.5 V LVCMOS 35 2.5 - 267.48 138.32 Single-Ended 1.8 V LVCMOS 35 1.8 - 1.5 V LVCMOS (JESD8-11) 35 1.5 - 96.13 3.3 V PCI 10 3.3 - 201.02 3.3 V PCI-X 10 3.3 - 201.02 LVDS - 2.5 7.74 88.92 LVPECL - 3.3 19.54 166.52 Differential Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. A d v a n c ed v 0.2 3-5 ProASIC3 Flash Family FPGAs Power Consumption of Various Internal Resources Table 3-10 * Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices Parameter Definition Device Specific Dynamic Power (W/MHz) A3P250 PAC1 Clock contribution of a Global Rib 100 PAC2 Clock contribution of a Global Spine 10 PAC3 Clock contribution of a VersaTile row 1.00 PAC4 Clock contribution of a VersaTile used as a sequential module 0.00 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard dependent) See Table 3-7 on page 3-5. PAC10 Contribution of an I/O output pin. (standard dependent) See Table 3-8 on page 3-5 PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 First contribution of a PLL 4.00 PAC14 Second Contribution of a PLL 2.00 Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator or SmartPower tool in Libero IDE software. 3 -6 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Power Calculation Methodology The section below describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * The number of PLLs as well as the number and the frequency of each output clock generated * The number of combinatorial and sequential cells used in the design * The internal clock frequencies * The number and the standard of I/O pins used in the design * The number of RAM blocks used in the design * Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 3-11 on page 3-9 * Enable rates of output buffers--guidelines are provided for typical applications in Table 3-12 on page 3-9 * Read rate and write rate to the memory--guidelines are provided for typical applications in Table 3-12 on page 3-9. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3) * FCLK NSPINE is the number of global spines used in the user design--guideline are provided in Table 3-11 on page 3-9. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 3-11 on page 3-9. FCLK is the global clock signal frequency. If the number of spines and rows is not known, use the simplified formula below: PCLOCK = (PAC1 + NS-CELL*PAC4 ) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. FCLK is the global clock signal frequency. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5+ 1* PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 3-11 on page 3-9. FCLK is the global clock signal frequency. A d v a n c ed v 0.2 3-7 ProASIC3 Flash Family FPGAs Combinational Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 * PAC7*FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 3-11 on page 3-9. FCLK is the global clock signal frequency. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 * PAC8 * FCLK NS-CELL is the number VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 3-11 on page 3-9. FCLK is the global clock signal frequency. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 3-11 on page 3-9. FCLK is the global clock signal frequency. I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 3-11 on page 3-9. 1 is the I/O buffer enable rate--guidelines are provided in Table 3-12 on page 3-9. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 the RAM enable rate for write operations--guidelines are provided in Table 3-12 on page 3-9. PLL/CCC Contribution--PPLL PPLL = PAC13 * FCLKIN + PAC14 *FCLKOUT FCLKIN is the input clock frequency. FCLKOUT is the output clock frequency.1 1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 *FCLKOUT product) to the total PLL contribution. 3 -8 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs Guidelines - Bit 2 Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * The average toggle rate of a shift-register is 100% because all flip-flop outputs toggle at half of the clock frequency. * The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50% - ... - Bit 7 (MSB) = 0.78125% - The average toggle rate is = (100% + 50% + 25% + 12.5% +...0.78125%) / 8. = 25% Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 3-11 * Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 3-12 * Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% A d v a n c ed v 0.2 3-9 ProASIC3 Flash Family FPGAs User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y Y t PD = 0.54 ns LVPECL t PD =0.47 ns tDP = 1.34 ns Combinational Cell I/O Module (Non-Registered) Buffer Y t DP = 2.64 ns t PD = 0.85 ns Combinational Cell I/O Module (Non-Registered) Y Buffer I/O Module (Registered) LVTTL Output drive strength = 12 mA High slew rate LVTTL Output drive strength = 8 mA t DP = 3.66 ns High slew rate t PY = 1.05 ns t PD = 0.49 ns LVPECL D Q Combinational Cell Y t ICLKQ = 0.63 ns t ISUD = 0.43 ns I/O Module (Non-Registered) LVCMOS 1.5v Output drive strength = 4 mA t DP = 3.97 ns High slew rate t PD = 0.46 ns Input LVTTL Clock Register Cell t PY = 0.76 ns D Combinational Cell Y Q I/O Module (Non-Registered) t PY = 1.20 ns D Q D Input LVTTL Clock t PY = 0.76 ns Q LVTTL 3.3 V t DP = 2.64 ns Output drive strength = 12 mA High slew rate t PD = 0.46 ns t CLKQ = 0.53 ns t SUD = 0.40 ns LVDS I/O Module (Registered) Register Cell t CLKQ = 0.53 ns t SUD = 0.40 ns t OCLKQ = 0.63 ns t OSUD = 0.43 ns Input LVTTL Clock t PY = 0.76 ns Figure 3-2 * Timing Model Operating Conditions: -2 Speed, Commercial Temperature Range (TJ = 70C), Worst Case VCC =1.425 V 3 -1 0 Advanced v0.2 ProASIC3 Flash Family FPGAs t PY t PYS tDIN D PAD Q DIN Y CLK To array I/O interface tPY = MAX(t PY (R), tPY (F)) tPYS = MAX(t PYS (R), tPYS (F)) tDIN= MAX(t DIN(R), tDIN (F)) VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (R) tPY (F) tPYS (R) tPYS (F) VCC 50% DIN GND 50% tDOUT tDOUT (F) (R) Figure 3-3 * Input Buffer Timing Model and Delays (example) A d v a n c ed v 0.2 3-11 ProASIC3 Flash Family FPGAs t DOUT t DP D Q D PAD DOUT Std Load CLK From Array t DP = MAX(t DP(R), t DP (F)) t DOUT = MAX(t DOUT (R), t DOUT (F)) I/O interface t DOUT t DOUT VCC (R) D 50% (F) 50% 0V VCC 50% DOUT 50% 0V VOH Vtrip Vtrip VOL PAD t DP (R) Figure 3-4 * Output Buffer Model and Delays (example) 3 -1 2 Advanced v0.2 t DP (F) ProASIC3 Flash Family FPGAs t EOUT D Q t ZL,tZH,tHZ ,tLZ, tZLS, tZHS CLK E EOUT D Q PAD DOUT CLK D t EOUT = MAX(t EOUT (R), t EOUT (F)) I/O interface VCC D Vcc 50% t EOUT (F) 50% t EOUT (R) E EOUT Vcc 50% 50% tZL PAD tHZ Vtrip 50% tZH 50% tLZ VCCI 90% VCCI Vtrip VOL 10% VCCI VCC D VCC E 50% EOUT PAD tEOUT (R) 50% tEOUT (F) Vcc 50% 50% tZLS VOH Vtrip V 50% tZHS Vtrip OL Figure 3-5 * Tristate Output Buffer Timing Model and Delays (example) A d v a n c ed v 0.2 3-13 ProASIC3 Flash Family FPGAs Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 3-13 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions VIL VIH VOL VOH IOL IOH Max, V Max, V Min, V mA mA 2 3.6 0.4 2.4 12 12 0.7 1.7 3.6 0.7 1.7 12 12 -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 8 8 -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 Drive Strength Slew Rate Min, V Max, V Min, V 3.3 V LVTTL / 3.3 V LVCMOS 12 mA High -0.3 0.8 2.5 V LVCMOS 12 mA High -0.3 1.8 V LVCMOS 8 mA High 1.5 V LVCMOS 4 mA High I/O Standard 3.3 V PCI Per PCI specifications 3.3 V PCI-X Per PCI-X specifications Note: Currents are measured at 85C junction temperature. Table 3-14 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 IIL IIH IIL IIH DC I/O Standards A A A A 3.3 V LVTTL /3.3V LVCMOS 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 Notes: 1. Commercial range (0C < TJ < 70C) 2. Industrial range (-40C < TJ < 85C) Summary of I/O Timing Characteristics - Default I/O Software Settings Table 3-15 * Summary of AC Measuring Points Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 0.285 * VCCI (RR) 3.3 V PCI 0.615 * VCCI (FF) 0.285 * VCCI (RR) 3.3 V PCI-X 0.615 * VCCI (FF) 3 -1 4 Advanced v0.2 ProASIC3 Flash Family FPGAs Table 3-16 * I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer--high to Z tZH Enable to Pad delay through the Output Buffer--Z to high tLZ Enable to Pad delay through the Output Buffer--low to Z tZL Enable to Pad delay through the Output Buffer--Z to low tZHS Enable to Pad delay through the Output Buffer with delayed enable--Z to high tZLS Enable to Pad delay through the Output Buffer with delayed enable--Z to low - 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns 1.8 V LVCMOS 8 mA High 35pF - 0.45 3.32 0.03 0.91 0.32 3.12 3.32 2.63 2.52 4.79 4.99 ns 1.5 V LVCMOS 4 mA High 35pF - 0.45 3.97 0.03 1.07 0.32 3.62 3.97 2.79 2.54 5.29 5.64 ns 2 Units 35pF tZHS High tZLS 12 mA tHZ 2.5 V LVCMOS tLZ ns tZH 0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.67 4.36 3.78 tZL - tEO UT 35 pF tPY External Resistor High tDIN Capacitive Load (pF) 12 mA tDP Slew Rate 3.3 V LVTTL / 3.3 V LVCMOS I/O Standard tDOUT Drive Strength (mA) Table 3-17 * Summary of I/O Timing Characteristics--Software Default Settings Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Per PCI spec High 10pF 25 0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.67 2.04 1.46 ns Per PCI-X spec High 10pF 25 2 0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.67 2.04 1.46 ns LVDS 24 mA High - - 0.45 1.36 0.03 1.20 - - - - - - - ns LVPECL 24 mA High - - 0.45 1.34 0.03 1.05 - - - - - - - ns 3.3 V PCI 3.3 V PCI-X Notes: 1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-10 on page 3-26 for connectivity. This resistor is not required during normal operation. A d v a n c ed v 0.2 3-15 ProASIC3 Flash Family FPGAs Detailed I/O DC Characteristics Table 3-18 * Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input Capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input Capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Table 3-19 * I/O Output Buffer Maximum Resistances1 RPULL-DOWN Standard Drive Strength () ()3 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 25 75 4 mA 100 200 8 mA 50 100 12 mA 25 50 2 mA 200 225 4 mA 100 112 8 mA 50 56 2 mA 200 224 4 mA 100 112 Per PCI/PCI-X specification 25 75 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X RPULL-UP 2 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IO H sp e c Table 3-20 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Min. Max. Min. Max. 3.3 V 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) 3 -1 6 Advanced v0.2 ProASIC3 Flash Family FPGAs Table 3-21 * I/O Short Currents IOSH/IOSL 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LCMOS Drive Strength IOSH (mA)* IOSL (mA)* 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 103 109 4 mA 16 18 8 mA 32 37 12 mA 65 74 2 mA 9 11 4 mA 17 22 8 mA 35 44 2 mA 13 16 4 mA 25 33 Note: *TJ = 100C The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 3-22 * Short Current Event Duration before Failure Temperature Time Before Failure -40C > 20 years 0C > 20 years 25C > 20 years 70C 5 years 85C 2 years 100C 6 months 110C 3 months Table 3-23 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (Min.) Input Rise/fall Time (Max.) Reliability LVTTL/LVCMOS No requirement 10 ns (or more *) 20 years (110C) LVDS/LVPECL No requirement 10 ns (or more *) 10 years (100C) Note: *This limitation is related only to the noise induced into input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. A d v a n c ed v 0.2 3-17 ProASIC3 Flash Family FPGAs Single Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor-Transistor Logic (LVTTL) is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 3-24 * Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL/ 3.3 V LVCMOS Drive Strength VIL Min, V VIH VOL VOH Max, V Min, V Max, V Max, V Min,V IOL IOH mA mA IOSL IOSH Max, mA1 Max, mA1 IIL IIH A2 A2 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Data Path 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ Figure 3-6 * AC Loading Table 3-25 * AC Waveforms, Measuring Points and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 35 Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. 3 -1 8 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-26 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Drive Strength (mA) 4 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 12.32 0.05 1.22 0.51 12.55 10.69 3.18 2.95 15.23 13.37 ns Std. 0.60 10.26 0.04 1.02 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns -1 0.51 8.72 0.04 0.86 0.36 8.88 7.57 2.25 2.09 10.79 9.47 ns -2 0.45 7.66 0.03 0.76 0.32 7.80 6.64 1.98 1.83 9.47 8.31 ns -F 0.72 8.74 0.05 1.22 0.51 8.90 7.55 3.58 3.65 11.59 10.23 ns Std. 0.60 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.64 8.52 ns -1 0.51 6.19 0.04 0.86 0.36 6.30 5.34 2.54 2.59 8.20 7.25 ns -2 0.45 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns -F 0.72 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns Std. 0.60 5.58 0.04 1.02 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns -1 0.51 4.75 0.04 0.86 0.36 4.83 4.14 2.73 2.90 6.74 6.04 ns -2 0.45 4.17 0.03 0.76 0.32 4.24 3.64 2.39 2.55 5.91 5.31 ns -F 0.72 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns Std. 0.60 5.58 0.04 1.02 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns -1 0.51 4.75 0.04 0.86 0.36 4.83 4.14 2.73 2.90 6.74 6.04 ns -2 0.45 4.17 0.03 0.76 0.32 4.24 3.64 2.39 2.55 5.91 5.31 ns tZHS Units Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-27 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Drive Strength (mA) 4 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ -F 0.72 9.20 0.05 1.22 0.51 9.37 7.91 3.18 3.14 12.05 10.60 tZLS ns Std. 0.60 7.66 0.04 1.02 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns -1 0.51 6.51 0.04 0.86 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns -2 0.45 5.72 0.03 0.76 0.32 5.82 4.92 1.98 1.95 7.49 6.59 ns -F 0.72 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns Std. 0.60 4.91 0.04 1.02 0.43 5.00 4.07 2.98 3.20 7.23 6.30 ns -1 0.51 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns -2 0.45 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns -F 0.72 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns Std. 0.60 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns -1 0.51 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns -2 0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.67 4.36 3.78 ns -F 0.72 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns Std. 0.60 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns -1 0.51 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns -2 0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.67 4.36 3.78 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-19 ProASIC3 Flash Family FPGAs 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V applications. It uses a 5-V-tolerant input buffer and push-pull output buffer. Table 3-28 * Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH Min, V Max, V Min, V Max, V Max, V Min, V IOL IOH mA mA IOSL IOSH Max, mA1 Max, mA1 IIL IIH A2 A2 4 mA -0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 8 mA -0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 mA -0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Data Path 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ Figure 3-7 * AC Loading Table 3-29 * AC Waveforms, Measuring Points and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 35 Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. 3 -2 0 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-30 * 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V Drive Strength (mA) 4 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 13.69 0.05 1.57 0.51 13.47 13.69 3.22 2.65 16.16 16.38 ns Std. 0.60 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns -1 0.51 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns -2 0.45 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns -F 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns -1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns -2 0.45 5.94 0.03 0.98 0.32 6.05 5.83 2.28 2.16 7.72 7.50 ns -F 0.72 7.42 0.05 1.57 0.51 7.56 7.11 3.97 3.99 10.25 9.79 ns Std. 0.60 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns -1 0.51 5.26 0.04 1.11 0.36 5.35 5.03 2.81 2.83 7.25 6.94 ns -2 0.45 4.61 0.03 0.98 0.32 4.70 4.42 2.47 2.48 6.37 6.09 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-31 * 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V Drive Strength (mA) 4 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 10.41 0.05 1.57 0.51 9.41 10.41 3.21 2.77 12.09 13.09 ns Std. 0.60 8.66 0.04 1.31 0.43 7.83 8.66 2.68 2.30 10.07 10.90 ns -1 0.51 7.37 0.04 1.11 0.36 6.66 7.37 2.28 1.96 8.56 9.27 ns -2 0.45 6.47 0.03 0.98 0.32 5.85 6.47 2.00 1.72 7.52 8.14 ns -F 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.73 8.89 ns Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns -1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns -2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns -F 0.72 4.28 0.05 1.57 0.51 4.36 4.12 3.97 4.13 7.04 6.81 ns Std. 0.60 3.56 0.04 1.31 0.43 3.62 3.43 3.30 3.44 5.86 5.67 ns -1 0.51 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns -2 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-21 ProASIC3 Flash Family FPGAs 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8 V applications. It uses 1.8 V input buffer and push-pull output buffer. Table 3-32 * Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL VIH VOL Max, V Max, V VOH IOL IOH IOSL IOSH Min, V mA mA Max, mA1 Max, mA1 IIL IIH Drive Strength Min, V Max, V Min, V 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 2 2 11 9 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 4 4 22 17 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 8 8 44 35 10 10 A2 A2 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Data Path 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ Figure 3-8 * AC Loading Table 3-33 * AC Waveforms, Measuring Points and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 35 Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. 3 -2 2 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-34 * 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V Drive Strength (mA) 2 mA 4 mA 6 mA 8mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 14.25 0.05 1.46 0.51 10.97 14.25 3.33 1.99 13.66 16.94 ns Std. 0.60 11.86 0.04 1.22 0.43 9.13 11.86 2.77 1.66 11.37 14.10 ns -1 0.51 10.09 0.04 1.03 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns -2 0.45 8.86 0.03 0.91 0.32 6.82 8.86 2.07 1.24 8.49 10.53 ns -F 0.72 8.31 0.05 1.46 0.51 7.04 8.31 3.87 3.41 9.73 10.99 ns Std. 0.60 6.91 0.04 1.22 0.43 5.86 6.91 3.22 2.84 8.10 9.15 ns -1 0.51 5.88 0.04 1.03 0.36 4.99 5.88 2.74 2.41 6.89 7.78 ns -2 0.45 5.16 0.03 0.91 0.32 4.38 5.16 2.40 2.12 6.05 6.83 ns -F 0.72 5.34 0.05 1.46 0.51 5.02 5.34 4.24 4.06 7.71 8.03 ns Std. 0.60 4.45 0.04 1.22 0.43 4.18 4.45 3.53 3.38 6.42 6.68 ns -1 0.51 3.78 0.04 1.03 0.36 3.56 3.78 3.00 2.88 5.46 5.68 ns -2 0.45 3.32 0.03 0.91 0.32 3.12 3.32 2.63 2.52 4.79 4.99 ns -F 0.72 14.25 0.05 1.46 0.51 10.97 14.25 3.33 1.99 13.66 16.94 ns Std. 0.60 11.86 0.04 1.22 0.43 9.13 11.86 2.77 1.66 11.37 14.10 ns -1 0.51 10.09 0.04 1.03 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns -2 0.45 8.86 0.03 0.91 0.32 6.82 8.86 2.07 1.24 8.49 10.53 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-35 * 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V Drive Strength (mA) 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns Std. 0.60 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns -1 0.51 13.21 0.04 1.03 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns -2 0.45 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns -F 0.72 12.58 0.05 1.46 0.51 12.51 12.58 3.88 3.28 15.19 15.27 ns Std. 0.60 10.47 0.04 1.22 0.43 10.41 10.47 3.23 2.73 12.64 12.71 ns -1 0.51 8.91 0.04 1.03 0.36 8.86 8.91 2.75 2.33 10.76 10.81 ns -2 0.45 7.82 0.03 0.91 0.32 7.77 7.82 2.41 2.04 9.44 9.49 ns -F 0.72 9.67 0.05 1.46 0.51 9.85 9.42 4.25 3.93 12.53 12.11 ns Std. 0.60 8.05 0.04 1.22 0.43 8.20 7.84 3.54 3.27 10.43 10.08 ns -1 0.51 6.85 0.04 1.03 0.36 6.97 6.67 3.01 2.78 8.88 8.57 ns -2 0.45 6.01 0.03 0.91 0.32 6.12 5.86 2.64 2.44 7.79 7.53 ns -F 0.72 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns Std. 0.60 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns -1 0.51 13.21 0.04 1.03 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns -2 0.45 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-23 ProASIC3 Flash Family FPGAs 1.5 V LVCMOS (JESD8-11) Low-voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5V applications. It uses 1.5 V input buffer and push-pull output buffer. Table 3-36 * Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL Drive Strength Min, V VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 A2 A2 2 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 16 13 10 10 4 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 33 25 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Data Path 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ Figure 3-9 * AC Loading Table 3-37 * AC Waveforms, Measuring Points and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 35 Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. 3 -2 4 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-38 * 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V Drive Strength (mA) 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 15.36 0.05 1.73 0.51 15.39 15.36 4.08 3.18 18.07 18.04 ns Std. 0.60 12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.04 15.02 ns -1 0.51 10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78 ns -2 0.45 9.55 0.03 1.07 0.32 9.56 9.55 2.54 1.97 11.23 11.21 ns -F 0.72 12.02 0.05 1.73 0.51 12.25 11.47 4.50 3.93 14.93 14.15 ns Std. 0.60 10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns -1 0.51 8.51 0.04 1.22 0.36 8.67 8.12 3.19 2.78 10.57 10.02 ns -2 0.45 7.47 0.03 1.07 0.32 7.61 7.13 2.80 2.44 9.28 8.80 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-39 * 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V Drive Strength (mA) 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 10.04 0.05 1.73 0.51 8.20 10.04 4.07 3.32 10.88 12.73 ns Std. 0.60 8.36 0.04 1.44 0.43 6.82 8.36 3.39 2.77 9.06 10.60 ns -1 0.51 7.11 0.04 1.22 0.36 5.80 7.11 2.88 2.35 7.71 9.02 ns -2 0.45 6.24 0.03 1.07 0.32 5.09 6.24 2.53 2.06 6.76 7.91 ns -F 0.72 6.38 0.05 1.73 0.51 5.83 6.38 4.49 4.09 8.51 9.07 ns Std. 0.60 5.31 0.04 1.44 0.43 4.85 5.31 3.74 3.40 7.09 7.55 ns -1 0.51 4.52 0.04 1.22 0.36 4.12 4.52 3.18 2.89 6.03 6.42 ns -2 0.45 3.97 0.03 1.07 0.32 3.62 3.97 2.79 2.54 5.29 5.64 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-25 ProASIC3 Flash Family FPGAs 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 3-40 * Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X Drive Strength VIL VIH VOL VOH Min, V Max, V Min, V Max, V Max, V Min, V Per PCI specification IOL IOH mA mA IOSL IOSH IIL IIH Max, mA1 Max, mA1 A2 A2 Per PCI curves 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the data path; Actel loadings for enable path characterization are described in Figure 3-10. R = 25 Test Point Data Path R to VCCI for tDP (F) R to GND for tDP (R) R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ Figure 3-10 * AC Loading AC loading are defined per PCI/PCI-X specifications for the data path; Actel loading for tristate is described in Table 3-41. Table 3-41 * AC Waveforms, Measuring Points and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) CLOAD (pF) 3.3 0.285 * VCCI for tDP(R) 10 0 0.615 * VCCI for tDP(F) Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. Timing Characteristics Table 3-42 * 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 3.22 0.05 1.04 0.51 3.28 2.34 3.86 4.3 3.28 2.34 ns Std. 0.60 2.68 0.04 0.86 0.43 2.73 1.95 3.21 3.58 2.73 1.95 ns -1 0.51 2.28 0.04 0.73 0.36 2.32 1.66 2.73 3.05 2.32 1.66 ns -2 0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.67 2.04 1.46 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -2 6 Advanced v0.2 ProASIC3 Flash Family FPGAs Differential I/O Characteristics Physical Implementation LVDS Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit is carried through two signal lines, so two pins are needed. It also requires external resistor termination. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with these standards. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 3-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation, because the output standard specifications are different. Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 ZO = 50 165 ZO = 50 FPGA INBUF_LVDS + - 100 140 N P N Figure 3-11 * LVDS Circuit Diagram and Board-Level Implementation Table 3-43 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units 2.375 2.5 2.625 V VCCI Supply Voltage VOL Output Low Voltage 0.9 1.075 1.25 V VOH Output High Voltage 1.25 1.425 1.6 V VI Input Voltage 2.925 V VODIFF Differential Output Voltage VOCM 0 250 350 450 mV Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 mV Notes: 1. 5% 2. Differential input voltage = 350 mV. Table 3-44 * AC Waveforms, Measuring Points and Capacitive Loads Input Low (V) 1.075 Input High (V) Measuring Point* (V) 1.325 Cross point Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. A d v a n c ed v 0.2 3-27 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-45 * LVDS Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V tDOUT tDP tDIN tPY Units -F 0.72 2.2 0.05 1.92 ns Std. 0.60 1.83 0.04 1.60 ns -1 0.51 1.55 0.04 1.36 ns -2 0.45 1.36 0.03 1.20 ns Speed Grade Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -2 8 Advanced v0.2 ProASIC3 Flash Family FPGAs LVPECL The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 3-12. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation, because the output standard specifications are different. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 P ZO = 50 N + - 100 187 W FPGA INBUF_LVPECL ZO = 50 100 N Figure 3-12 * LVPECL Circuit Diagram and Board-Level Implementation Table 3-46 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Max. Min. Max. Min. Max. Units VCCI Supply Voltage VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V VIL, VIH Input Low, Input High voltages 0 3.3 0 3.6 0 3.9 V VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V VOCM Output Common Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V VICM Input Common Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V VIDIFF Input Differential Voltage 300 3.0 3.3 3.6 300 V 300 mV Table 3-47 * AC Waveforms, Measuring Points and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.94 Cross point 1.64 Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. Timing Characteristics Table 3-48 * LVPECL Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY Units -F 0.72 2.16 0.05 1.69 ns Std. 0.60 1.80 0.04 1.40 ns -1 0.51 1.53 0.04 1.19 ns -2 0.45 1.34 0.03 1.05 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-29 ProASIC3 Flash Family FPGAs I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L X Pad Out X D DOUT Data_out Enable INBUF CLK CLKBUF X B E Y X F Core Array X G X X E X E PRE D Q DFN1E1P1 EOUT H X X A I X J X K X CLKBUF INBUF INBUF CLK Enable D_Enable Data Input I/O Register with: Active High Enable Active High Preset Postive Edge Triggered PRE D Q DFN1E1P1 E Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive Edge Triggered Figure 3-13 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset 3 -3 0 TRIBUF PRE X D Q C DFN1E1P1 INBUF Data Advanced v0.2 ProASIC3 Flash Family FPGAs Table 3-49 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (From, To)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup time for the Output Data Register F, H tOHD Data Hold time for the Output Data Register F, H tOSUE Enable Setup time for the Output Data Register G, H tOHE Enable Hold time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset removal time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup time for the Output Enable Register J, H tOEHD Data Hold time for the Output Enable Register J, H tOESUE Enable Setup time for the Output Enable Register K, H tOEHE Enable Hold time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup time for the Input Data Register C, A tIHD Data Hold time for the Input Data Register C, A tISUE Enable Setup time for the Input Data Register B, A tIHE Enable Hold time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery time for the Input Data Register D, A L, DOUT H, EOUT I, EOUT Note: *See Figure 3-13 on page 3-30 for more information. A d v a n c ed v 0.2 3-31 ProASIC3 Flash Family FPGAs Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear X CC Data_out FF X D Q DFN1E1C1 X TRIBUF INBUF Data Core Array GG INBUF CLR CLKBUF CLK INBUF Enable X BB EOUT X E X E CLR CLR X X X AA LL HH JJ X DD D Q DFN1E1C1 KK X E CLR Data Input I/O Register with Active high enable Active high clear Positive edge triggered INBUF INBUF CLKBUF Enable D_Enable CLK X Data Output Register and Enable Output Register with Active high enable Active high clear Positive edge triggered Figure 3-14 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear 3 -3 2 Advanced v0.2 Pad Out DOUT Y D Q X EE DFN1E1C1 ProASIC3 Flash Family FPGAs Table 3-50 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (From, To)* tOCLK Q Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup time for the Output Data Register FF, HH tOHD Data Hold time for the Output Data Register FF, HH tOSUE Enable Setup time for the Output Data Register GG, HH tOHE Enable Hold time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup time for the Output Enable Register JJ, HH tOEHD Data Hold time for the Output Enable Register JJ, HH tOESUE Enable Setup time for the Output Enable Register KK, HH tOEHE Enable Hold time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup time for the Input Data Register CC, AA tIHD Data Hold time for the Input Data Register CC, AA tISUE Enable Setup time for the Input Data Register BB, AA tIHE Enable Hold time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery time for the Input Data Register DD, AA LL, DOUT HH, EOUT Note: *See Figure 3-14 on page 3-32 for more information. A d v a n c ed v 0.2 3-33 ProASIC3 Flash Family FPGAs Input Register tICKMPWH tICKMPWL 50% 50% CLK Enable 50% 1 50% 50% 50% tIHD tISUD Data 50% 50% 50% 0 tIWPRE 50% tIRECPRE tIREMPRE 50% 50% tIHE 50% tISUE Preset tIWCLR 50% Clear tIRECCLR tIREMCLR 50% 50% tIPRE2Q 50% Out_1 50% tICLR2Q 50% tICLKQ Figure 3-15 * Input Register Timing Diagram Timing Characteristics Table 3-51 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tICLKQ Clock-to-Q of the Input Data Register 0.63 0.71 0.84 1.01 ns tISUD Data Setup time for the Input Data Register 0.43 0.49 0.57 0.69 ns tIHD Data Hold time for the Input Data Register 0.00 0.00 0.00 0.00 ns tISUE Enable Setup time for the Input Data Register 0.43 0.49 0.57 0.69 ns tIHE Enable Hold time for the Input Data Register 0.00 0.00 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.57 0.65 0.76 1.01 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.51 0.60 0.72 ns tIREMCLR Asynchronous Clear Removal time for the Input Data Register 0.00 0.00 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery time for the Input Data Register 0.10 0.10 0.10 0.10 ns tIREMPRE Asynchronous Preset Removal time for the Input Data Register 0.00 0.00 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery time for the Input Data Register 0.10 0.10 0.10 0.10 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.25 0.28 0.33 0.40 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.25 0.28 0.33 0.40 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.36 0.41 0.48 0.58 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.41 0.46 0.54 0.65 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -3 4 Advanced v0.2 ProASIC3 Flash Family FPGAs Output Register tOCKMPWH tOCKMPWL 50% 50% CLK 50% 50% 50% 50% 50% tOSUD tOHD 1 Data_out Enable 50% 50% 0 50% tOWPRE tOHE t OREMPRE 50% 50% tOSUE Preset tORECPRE 50% tOWCLR 50% Clear tOREMCLR tORECCLR 50% 50% tOPRE2Q 50% DOUT 50% t OCLR2Q 50% tOCLKQ Figure 3-16 * Output Register Timing Diagram Timing Characteristics Table 3-52 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tOCLKQ Clock-to-Q of the Output Data Register 0.63 0.71 0.84 1.01 ns tOSUD Data Setup time for the Output Data Register 0.43 0.49 0.57 0.69 ns tOHD Data Hold time for the Output Data Register 0.00 0.00 0.00 0.00 ns tOSUE Enable Setup time for the Output Data Register 0.43 0.49 0.57 0.69 ns tOHE Enable Hold time for the Output Data Register 0.00 0.00 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.57 0.65 0.76 1.01 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.45 0.51 0.60 0.72 ns tOREMCLR Asynchronous Clear Removal time for the Output Data Register 0.00 0.00 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery time for the Output Data Register 0.24 0.27 0.32 0.38 ns tOREMPRE Asynchronous Preset Removal time for the Output Data Register 0.00 0.00 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery time for the Output Data Register 0.24 0.27 0.32 0.38 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.26 0.29 0.34 0.41 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.26 0.29 0.34 0.41 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.38 0.43 0.51 0.61 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.43 0.49 0.57 0.69 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-35 ProASIC3 Flash Family FPGAs Output Enable Register tOECKMPWH tOECKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOESUD tOEHD 1 D_Enable Enable 50% 0 50% 50% tOESUEtOEHE Preset tOEWPRE 50% tOEREMPRE tOERECPRE 50% 50% tOEWCLR 50% Clear 50% 50% tOEPRE2Q tOECLR2Q 50% 50% 50% EOUT tOEREMCLR tOERECCLR tOECLKQ Figure 3-17 * Output Enable Register Timing Diagram Timing Characteristics Table 3-53 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units 0.63 0.71 0.84 1.01 ns tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup time for the Output Enable Register 0.43 0.49 0.57 0.69 ns tOEHD Data Hold time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOESUE Enable Setup time for the Output Enable Register 0.43 0.49 0.57 0.69 ns tOEHE Enable Hold time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.57 0.65 0.76 1.01 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.45 0.51 0.60 0.72 ns tOEREMCLR Asynchronous Clear Removal time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery time for the Output Enable Register 0.24 0.27 0.32 0.38 ns tOEREMPRE Asynchronous Preset Removal time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery time for the Output Enable Register 0.24 0.27 0.32 0.38 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.26 0.29 0.34 0.41 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.26 0.29 0.34 0.41 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.38 0.43 0.51 0.61 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.43 0.49 0.57 0.69 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -3 6 Advanced v0.2 ProASIC3 Flash Family FPGAs DDR Module Specifications Input DDR Module Input DDR INBUF A X Data D X Out_QF (To core) X Out_QR (To Core) FF1 B X CLK E CLKBUF FF2 C X CLR INBUF DDR_IN Figure 3-18 * Input DDR Timing Model Table 3-54 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (From, To) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup time of DDR input A, B tDDRIHD Data Hold time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B A d v a n c ed v 0.2 3-37 ProASIC3 Flash Family FPGAs CLK t DDRISUD Data 1 2 3 4 5 tDDRIHD 6 7 8 9 t DDRIRECCLR CLR t DDRIREMCLR t DDRICLKQ1 t DDRICLR2Q1 Out_QF 2 6 4 t DDRICLKQ2 t DDRICLR2Q2 Out_QR 3 7 5 Table 3-55 * Input DDR Timing Diagram Timing Characteristics Table 3-56 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.63 0.71 0.84 1.01 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.63 0.71 0.84 0.91 ns tDDRISUD Data Setup for Input DDR 0.43 0.49 0.57 0.86 ns tDDRIHD Data Hold for Input DDR 0.00 0.00 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear to out Out_QR for Input DDR 0.57 0.65 0.76 0.91 ns tDDRICLR2Q2 Asynchronous Clear to out Out_QF for Input DDR 0.57 0.65 0.76 0.91 ns tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.10 0.10 0.10 0.10 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR ns FDDRIMAX Maximum Frequency for Input DDR MHz Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -3 8 Advanced v0.2 ProASIC3 Flash Family FPGAs Output DDR Module A Data_F (From Core) X FF1 B CLK CLKBUF C D Data_R (From Core) Out 0 X E X X 1 X OUTBUF FF2 BX CLR INBUF CX DDR_OUT Figure 3-19 * Output DDR Timing Model Table 3-57 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (From, To) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDR ORE CCLR Clear Recovery C, B tDDR OSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B A d v a n c ed v 0.2 3-39 ProASIC3 Flash Family FPGAs CLK t DDROSUD2 Data_F 1 2 tDDROSUD1 Data_R 6 t DDROHD2 4 3 5 t DDROHD1 7 8 9 10 11 t DDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 2 7 8 3 9 4 10 Figure 3-20 * Output DDR Timing Diagram Timing Characteristics Table 3-58 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.63 0.71 0.84 1.01 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.43 0.49 0.57 0.69 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.43 0.49 0.57 0.69 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear to out for Output DDR 0.57 0.65 0.76 0.91 ns tDDROREMCLR Asynchronous Clear Removal time for Output DDR 0.00 0.00 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery time for Output DDR 0.10 0.10 0.10 0.10 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR ns tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR ns tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR ns FDDOMAX Maximum Frequency for the Output DDR MHz Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -4 0 Advanced v0.2 ProASIC3 Flash Family FPGAs VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the ProASIC3/E Macro Library Guide. A A A OR2 NOR2 Y A AND2 A Y NAND2 B Y B A B C A XOR2 Y A A B C Y B B B Y INV NAND3 Y A MAJ3 B XOR3 0 Y MUX2 B Y 1 C S Figure 3-21 * Sample of Combinatorial Cells A d v a n c ed v 0.2 3-41 ProASIC3 Flash Family FPGAs t PD A NAND2 OR Any Combinatorial Logic B Y t PD = MAX(t PD(RR), tPD(RF) ), t PD(FF) , tPD(FR) ) where edges are applicable for the particular combinatorial cell VCCA 50% 50% A, B, C GND VCCA 50% 50% OUT GND VCCA t PD (FF) t PD (RR) t PD (FR) OUT 50% t PD (RF) GND Figure 3-22 * Timing Model and Waveforms 3 -4 2 Advanced v0.2 50% ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-59 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Combinatorial Cell Equation Parameter -2 -1 Std. -F Units Y = !A tPD 0.40 0.45 0.53 0.64 ns Y=A.B tPD 0.46 0.52 0.62 0.74 ns Y = !(A . B) tPD 0.46 0.52 0.62 0.74 ns Y=A+B tPD 0.47 0.54 0.63 0.76 ns NOR2 Y = !(A + B) tPD 0.47 0.54 0.63 0.76 ns XOR2 Y=AB tPD 0.72 0.82 0.96 1.15 ns MAJ3 Y = MAJ (A , B, C) tPD 0.67 0.76 0.90 1.08 ns XOR3 Y=ABC tPD 0.85 0.97 1.14 1.37 ns MUX2 Y = A !S + B S tPD 0.49 0.56 0.65 0.79 ns AND3 Y=A.B.C tPD 0.54 0.62 0.73 0.87 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells including flip-flops and latches. Each have a data input and optional Enable, Clear, or Preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the ProASIC3/E Macro Library Guide. Data D Q Out Data Out D En DFN1 Q DFN1E1 CLK CLK PRE Data D Q Out Data En DFN1C1 D Q Out DFI1E1P1 CLK CLK CLR Figure 3-23 * Sample of Sequential Cells A d v a n c ed v 0.2 3-43 ProASIC3 Flash Family FPGAs tCKMPWH tCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tHD tSUD 50% Data 50% 0 EN tWPRE 50% tHE PRE 50% t SUE tRECPRE tREMPRE 50% 50% tRECCLR tWCLR 50% CLR tREMCLR 50% 50% tPRE2Q 50% Out 50% tCLR2Q 50% tCLKQ Figure 3-24 * Timing Model and Waveforms Timing Characteristics Table 3-60 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units 0.54 0.61 0.72 0.86 ns tCLKQ Clock-to-Q of the Core Register tSUD Data Setup time for the Core Register 0.40 0.46 0.54 0.65 ns tHD Data Hold time for the Core Register 0.00 0.00 0.00 0.00 ns tSUE Enable Setup time for the Core Register 0.43 0.49 0.57 0.69 ns tHE Enable Hold time for the Core Register 0.00 0.00 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns tREMCLR Asynchronous Clear Removal time for the Core Register 0.00 0.00 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery time for the Core Register 0.24 0.27 0.32 0.38 ns tREMPRE Asynchronous Preset Removal time for the Core Register 0.00 0.00 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery time for the Core Register 0.24 0.27 0.32 0.38 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.26 0.29 0.34 0.41 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.26 0.29 0.34 0.41 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.38 0.43 0.51 0.61 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.43 0.49 0.57 0.69 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -4 4 Advanced v0.2 ProASIC3 Flash Family FPGAs Global Resource Characteristics A3P250 Clock Tree Topology Clock delays are device-specific. Figure 3-25 is an example of a global tree used for clock routing. The global tree presented in Figure 3-25 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flipflops in the device. Central Global RIb CCC VersaTile Rows Global Spine Figure 3-25 * Example of Global Tree Use in an A3P250 Device for Clock Routing A d v a n c ed v 0.2 3-45 ProASIC3 Flash Family FPGAs Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard dependent and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to "Clock Conditioning Circuits" section on page 2-13. Table 3-61 to Table 3-67 on page 3-49 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 3-61 * A3P030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description Min. 1 -1 2 Max. Min. 1 Std. 2 Max. Min. 1 -F 2 Max. Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock ns tRCKH Input High Delay for Global Clock ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-62 * A3P060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description Min. 1 -1 Std. -F Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.05 1.18 1.02 1.34 1.20 1.58 1.44 1.91 ns tRCKH Input High Delay for Global Clock 1.07 1.19 1.02 1.36 1.21 1.60 1.45 1.91 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.14 0.34 0.40 0.47 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -4 6 Advanced v0.2 ProASIC3 Flash Family FPGAs Table 3-63 * A3P125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description Min. 1 -1 2 Max. Min. 1 Std. 2 Max. Min. 1 -F 2 Max. Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.10 1.23 1.08 1.40 1.26 1.64 1.52 1.99 ns tRCKH Input High Delay for Global Clock 1.12 1.24 1.07 1.41 1.26 1.66 1.52 1.98 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.14 0.34 0.40 0.47 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-64 * A3P250 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425V -2 Parameter Description Min. 1 -1 Std. -F Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.10 1.22 1.07 1.40 1.26 1.64 1.52 1.99 ns tRCKH Input High Delay for Global Clock 1.11 1.24 1.07 1.41 1.26 1.65 1.52 1.98 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.14 0.34 0.39 0.47 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-47 ProASIC3 Flash Family FPGAs Table 3-65 * A3P400 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description Min. 1 -1 2 Max. Min. 1 Std. 2 Max. Min. 1 -F 2 Max. Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.15 1.27 1.13 1.45 1.33 1.70 1.59 2.06 ns tRCKH Input High Delay for Global Clock 1.16 1.28 1.12 1.46 1.32 1.72 1.59 2.05 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.13 0.34 0.40 0.47 ns Mhz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-66 * A3P600 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description Min. 1 -1 Std. -F Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.15 1.27 1.13 1.45 1.33 1.70 1.59 2.06 ns tRCKH Input High Delay for Global Clock 1.16 1.28 1.12 1.46 1.32 1.72 1.59 2.05 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.13 0.34 0.40 0.47 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -4 8 Advanced v0.2 ProASIC3 Flash Family FPGAs Table 3-67 * A3P1000 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description Min. 1 -1 2 Max. Min. 1 Std. 2 Max. Min. 1 -F 2 Max. Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.19 1.32 1.18 1.50 1.39 1.76 1.67 2.13 ns tRCKH Input High Delay for Global Clock 1.20 1.32 1.18 1.51 1.38 1.77 1.66 2.12 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.13 0.33 0.39 0.47 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-49 ProASIC3 Flash Family FPGAs Embedded SRAM and FIFO Characteristics SRAM RAM4K9 RAM512X18 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 3-26 * RAM Models 3 -5 0 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tCKQ1 DO Dn D0 D1 D2 tDOH1 Figure 3-27 * RAM Read for Flow-Through Output tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 t BKS tBKH BLK_B tENH t ENS WEN_B tCKQ2 DO Dn D0 D1 tDOH2 Figure 3-28 * RAM Read for Pipelined Output A d v a n c ed v 0.2 3-51 ProASIC3 Flash Family FPGAs tCYC tCKH t CKL CLK tAS tAH A0 ADD A1 A2 t BKS t BKH BLK_B tENS t ENH WEN_B t DI DS DI0 t DH DI1 Dn DO Figure 3-29 * RAM Write, Output Retained (WMODE = 0) 3 -5 2 Advanced v0.2 D2 ProASIC3 Flash Family FPGAs tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS t BKH BLK_B tENS WEN_B tDS DI0 DI DO (flow-through) DO (Pipelined) tDH DI1 Dn DI2 DI1 DI0 DI0 Dn DI1 Figure 3-30 * RAM Write, Output as Write Data (WMODE = 1) A d v a n c ed v 0.2 3-53 ProASIC3 Flash Family FPGAs CLK1 tAS tAH A0 ADD1 tDS A3 D2 D3 tDH D0 DI1 A2 t WRO CLK2 tAS A0 ADD2 tAH A1 A4 tCKQ1 DO2 (flow-through) Dn D0 D1 tCKQ2 DO2 (Pipelined) Dn D0 Figure 3-31 * One Port Write/Other Port Read Same tCYC t CKH t CKL CLK RESET_B t RSTBQ DO Dm Dn Figure 3-32 * RAM Reset 3 -5 4 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-68 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tAS Address Setup time 0.30 0.34 0.40 0.48 ns tAH Address Hold time 0.00 0.00 0.00 0.00 ns tENS REN_B,WEN_B Setup time 0.20 0.22 0.26 0.32 ns tENH REN_B, WEN_B Hold time 0.03 0.03 0.04 0.05 ns tBKS BLK_B Setup time 0.00 0.00 0.00 0.00 ns tBKH BLK_B Hold time 0.06 0.07 0.08 0.10 ns tDS Input data (DI) Setup time 0.24 0.27 0.32 0.38 ns tDH Input data (DI) Hold time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 1.73 1.97 2.32 2.79 ns Clock High to New Data Valid on DO (flow-through, WMODE =1) 2.28 2.60 3.05 3.67 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.85 0.97 1.14 1.37 ns tRSTBQ RESET_B Low to Data Out Low on DO (flow through) 0.98 1.12 1.31 1.57 ns RESET_B Low to Data Out Low on DO (pipelined) 0.98 1.12 1.31 1.57 ns tREMRSTB RESET_B Removal 0.00 0.00 0.00 0.00 ns tRECRSTB RESET_B Recovery 0.10 0.10 0.10 0.10 ns tMPWRSTB RESET_B Minimum Pulse Width 0.22 0.25 0.29 0.35 ns tCYC Clock Cycle time 2.10 2.38 2.80 3.36 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-69 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units ns tAS Address Setup time 0.30 0.34 0.40 0.48 tAH Address Hold time 0.00 0.00 0.00 0.00 ns tENS REN_B,WEN_B Setup time 0.14 0.16 0.19 0.23 ns tENH REB_B, WEN_B Hold time 0.02 0.03 0.03 0.04 ns tDS Input data (DI) Setup time 0.22 0.25 0.30 0.36 ns tDH Input data (DI) Hold time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE =0) 2.08 2.37 2.79 3.35 ns tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.85 0.97 1.14 1.37 ns tRSTBQ RESET_B Low to Data Out Low on DO (flow through) 0.98 1.12 1.31 1.57 ns RESET_B Low to Data Out Low on DO (pipelined) 0.98 1.12 1.31 1.57 ns tREMRSTB RESET_B Removal 0.00 0.00 0.00 0.00 ns tRECRSTB RESET_B Recovery 0.10 0.10 0.10 0.10 ns tMPWRSTB RESET_B Minimum Pulse Width 0.22 0.25 0.29 0.35 ns tCYC Clock Cycle time 2.10 2.38 2.80 3.36 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. A d v a n c ed v 0.2 3-55 ProASIC3 Flash Family FPGAs FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 3-33 * FIFO Model 3 -5 6 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Waveforms RCLK/ WCLK tMPWRSTB tRSTCK RESET_B tRSTFG EF tRSTAF AEF tRSTFG FF tRSTAF AFF WA/RA (Address Counter) MATCH (A0) Figure 3-34 * FIFO Reset tCYC RCLK tRCKEF EF tCKAF AEF WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 3-35 * FIFO Reset, Empty Flag, and Almost-Empty Flag A d v a n c ed v 0.2 3-57 ProASIC3 Flash Family FPGAs tCYC WCLK t WCKFF FF t CKAF AFF WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 3-36 * FIFO FULL and AFULL Flag WCLK WA/RA (Address Counter) RCLK MATCH (EMPTY) NO MATCH 1st rising edge after 1st write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd rising edge after 1st write t RCKEF EF t CKAF AEF Figure 3-37 * EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA (Address Counter) MATCH (FULL) NO MATCH 1st rising edge after 1st read WCLK NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1 1st rising edge after 2nd read t WCKF FF t CKAF AFF Figure 3-38 * FULL and ALFULL Deassertion 3 -5 8 Advanced v0.2 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-70 * FIFO Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tENS REN_B,WEN_B Setup time 0.14 0.16 0.19 0.23 ns tENH REN_B, WEN_B Hold time 0.06 0.07 0.08 0.10 ns tBKS BLK_B Setup time 0.25 0.29 0.34 0.40 ns tBKH BLK_B Hold time 0.00 0.00 0.00 0.00 ns tDS Input data (DI) Setup time 0.22 0.25 0.30 0.36 ns tDH Input data (DI) Hold time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on DO (flow-through) 2.28 2.60 3.05 3.67 ns tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.85 0.97 1.14 1.37 ns tRCKEF RCLK High to Empty flag Valid 1.69 1.92 2.26 2.71 ns tWCKFF WCLK High to Full flag Valid 1.61 1.83 2.15 2.58 ns tCKAF Clock High to Almost Empty/Full Flag Valid 3.62 4.12 4.85 5.82 ns tRSTFG RESET_B Low to Empty/Full flag valid 1.71 1.94 2.28 2.74 ns tRSTAF RESET_B Low to Almost-Empty/Full Flag Valid 3.58 4.08 4.80 5.77 ns tRSTBQ RESET_B Low to Data out Low on DO (flow through) 0.98 1.12 1.31 1.57 ns RESET_B Low to Data out Low on DO (pipelined) 0.98 1.12 1.31 1.57 ns tREMRSTB RESET_B Removal 0.00 0.00 0.00 0.00 ns tRECRSTB RESET_B Recovery 0.10 0.10 0.10 0.10 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns tCYC Clock Cycle time 2.06 2.33 2.75 3.29 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Embedded FROM Characteristics tA ADDR DO tA A0 A1 D0 D1 Figure 3-39 * Timing Diagram A d v a n c ed v 0.2 3-59 ProASIC3 Flash Family FPGAs Timing Characteristics Table 3-71 * Embedded FROM Access Time Parameter tA Description Data Access Time -2 -1 Std. Units 10 10 10 ns JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected, refer to the I/O Timing characteristics for more details. Timing Characteristics Table 3-72 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, worst-case VCC = 1.425 V Parameter Description -2 -1 Std. Units tDISU Test Data Input Setup Time ns tDIHD Test Data Input Hold Time ns tTMSSU Test Mode Select Setup Time ns tTMDHD Test Mode Select Hold Time ns tTCK2Q Clock to Q (Data Out) ns tRSTB2Q Reset to Q (Data Out) ns FTCKMAX TCK maximum frequency tTRSTREM ResetB Removal time ns tTRSTREC ResetB Recovery time ns tTRSTMPW ResetB minimum pulse ns 20/40 20/40 20/40 Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 3 -6 0 Advanced v0.2 MHz ProASIC3 Flash Family FPGAs Package Pin Assignments 132-Pin QFN A48 B44 C40 A37 B34 C31 Pin A1 Mark A1 B1 C1 C30 C21 B23 A25 C10 B11 A12 Optional Corner Pad (4x) A36 B33 C11 B12 A13 C20 B22 A24 Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. A d v a n c ed v 0.2 4-1 ProASIC3 Flash Family FPGAs 100-Pin VQFP 100 1 100-Pin VQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 4 -2 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs 100-Pin VQFP* 100-Pin VQFP* 100-Pin VQFP* Pin Number A3P060 Function Pin Number A3P060 Function Pin Number A3P060 Function 1 GND 37 VCC 73 GBA2/IO25RSB0 2 GAA2/IO51RSB1 38 GND 74 VMV0 3 IO52RSB1 39 VCCIB1 75 GNDQ 4 GAB2/IO53RSB1 40 IO60RSB1 76 GBA1/IO24RSB0 5 IO95RSB1 41 IO59RSB1 77 GBA0/IO23RSB0 6 GAC2/IO94RSB1 42 IO58RSB1 78 GBB1/IO22RSB0 7 IO93RSB1 43 GDC2/IO57RSB1 79 GBB0/IO21RSB0 8 IO92RSB1 44 GDB2/IO56RSB1 80 GBC1/IO20RSB0 9 GND 45 GDA2/IO55RSB1 81 GBC0/IO19RSB0 10 GFB1/IO87RSB1 46 IO54RSB1 82 IO18RSB0 11 GFB0/IO86RSB1 47 TCK 83 IO17RSB0 12 VCOMPLF 48 TDI 84 IO15RSB0 13 GFA0/IO85RSB1 49 TMS 85 IO13RSB0 14 VCCPLF 50 NC 86 IO11RSB0 15 GFA1/IO84RSB1 51 GND 87 VCCIB0 16 GFA2/IO83RSB1 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB1 54 TDO 90 IO10RSB0 19 GEC1/IO77RSB1 55 TRST 91 IO09RSB0 20 GEB1/IO75RSB1 56 VJTAG 92 IO08RSB0 21 GEB0/IO74RSB1 57 GDA1/IO49RSB0 93 GAC1/IO07RSB0 22 GEA1/IO73RSB1 58 GDC0/IO46RSB0 94 GAC0/IO06RSB0 23 GEA0/IO72RSB1 59 GDC1/IO45RSB0 95 GAB1/IO05RSB0 24 VMV1 60 IO44RSB0 96 GAB0/IO04RSB0 25 GNDQ 61 GCB2/IO42RSB0 97 GAA1/IO03RSB0 26 GEA2/IO71RSB1 62 GCA0/IO40RSB0 98 GAA0/IO02RSB0 27 GEB2/IO70RSB1 63 GCA1/IO39RSB0 99 IO01RSB0 28 GEC2/IO69RSB1 64 GCC0/IO36RSB0 100 IO00RSB0 29 IO68RSB1 65 GCC1/IO35RSB0 30 IO67RSB1 66 VCCIB0 31 IO66RSB1 67 GND 32 IO65RSB1 68 VCC 33 IO64RSB1 69 IO31RSB0 34 IO63RSB1 70 GBC2/IO29RSB0 35 IO62RSB1 71 GBB2/IO27RSB0 36 IO61RSB1 72 IO26RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-3 ProASIC3 Flash Family FPGAs 100-Pin VQFP* 100-Pin VQFP* 100-Pin VQFP* Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 1 GND 39 VCCIB1 77 GBA0/IO39RSB0 2 GAA2/IO67RSB1 40 IO87RSB1 78 GBB1/IO38RSB0 3 IO68RSB1 41 IO84RSB1 79 GBB0/IO37RSB0 4 GAB2/IO69RSB1 42 IO81RSB1 80 GBC1/IO36RSB0 5 IO132RSB1 43 IO75RSB1 81 GBC0/IO35RSB0 6 GAC2/IO131RSB1 44 GDC2/IO72RSB1 82 IO32RSB0 7 IO130RSB1 45 GDB2/IO71RSB1 83 IO28RSB0 8 IO129RSB1 46 GDA2/IO70RSB1 84 IO25RSB0 9 GND 47 TCK 85 IO22RSB0 10 GFB1/IO124RSB1 48 TDI 86 IO19RSB0 11 GFB0/IO123RSB1 49 TMS 87 VCCIB0 12 VCOMPLF 50 VMV1 88 GND 13 GFA0/IO122RSB1 51 GND 89 VCC 14 VCCPLF 52 VPUMP 90 IO15RSB0 15 GFA1/IO121RSB1 53 NC 91 IO13RSB0 16 GFA2/IO120RSB1 54 TDO 92 IO11RSB0 17 VCC 55 TRST 93 IO09RSB0 18 VCCIB1 56 VJTAG 94 IO07RSB0 19 GEC0/IO111RSB1 57 GDA1/IO65RSB0 95 GAC1/IO05RSB0 20 GEB1/IO110RSB1 58 GDC0/IO62RSB0 96 GAC0/IO04RSB0 21 GEB0/IO109RSB1 59 GDC1/IO61RSB0 97 GAB1/IO03RSB0 22 GEA1/IO108RSB1 60 GCC2/IO59RSB0 98 GAB0/IO02RSB0 23 GEA0/IO107RSB1 61 GCB2/IO58RSB0 99 GAA1/IO01RSB0 24 VMV1 62 GCA0/IO56RSB0 100 GAA0/IO00RSB0 25 GNDQ 63 GCA1/IO55RSB0 26 GEA2/IO106RSB1 64 GCC0/IO52RSB0 27 GEB2/IO105RSB1 65 GCC1/IO51RSB0 28 GEC2/IO104RSB1 66 VCCIB0 29 IO102RSB1 67 GND 30 IO100RSB1 68 VCC 31 IO99RSB1 69 IO47RSB0 32 IO97RSB1 70 GBC2/IO45RSB0 33 IO96RSB1 71 GBB2/IO43RSB0 34 IO95RSB1 72 IO42RSB0 35 IO94RSB1 73 GBA2/IO41RSB0 36 IO93RSB1 74 VMV0 37 VCC 75 GNDQ 38 GND 76 GBA1/IO40RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -4 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs 100-Pin VQFP* 100-Pin VQFP* 100-Pin VQFP* Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function 1 GND 37 VCC 73 GBA2/IO41PDB1 2 GAA2/IO118PDB3 38 GND 74 VMV1 3 IO118NDB3 39 VCCIB2 75 GNDQ 4 GAB2/IO117PDB3 40 IO77RSB2 76 GBA1/IO40RSB0 5 IO117NDB3 41 IO74RSB2 77 GBA0/IO39RSB0 6 GAC2/IO116PDB3 42 IO71RSB2 78 GBB1/IO38RSB0 7 IO116NDB3 43 GDC2/IO63RSB2 79 GBB0/IO37RSB0 8 IO112PSB3 44 GDB2/IO62RSB2 80 GBC1/IO36RSB0 9 GND 45 GDA2/IO61RSB2 81 GBC0/IO35RSB0 10 GFB1/IO109PDB3 46 GNDQ 82 IO29RSB0 11 GFB0/IO109NDB3 47 TCK 83 IO27RSB0 12 VCOMPLF 48 TDI 84 IO25RSB0 13 GFA0/IO108NPB3 49 TMS 85 IO23RSB0 14 VCCPLF 50 VMV2 86 IO21RSB0 15 GFA1/IO108PPB3 51 GND 87 VCCIB0 16 GFA2/IO107PSB3 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB3 54 TDO 90 IO15RSB0 19 GFC2/IO105PSB3 55 TRST 91 IO13RSB0 20 GEC1/IO100PDB3 56 VJTAG 92 IO11RSB0 21 GEC0/IO100NDB3 57 GDA1/IO60PSB1 93 GAC1/IO05RSB0 22 GEA1/IO98PDB3 58 GDC0/IO58NDB1 94 GAC0/IO04RSB0 23 GEA0/IO98NDB3 59 GDC1/IO58PDB1 95 GAB1/IO03RSB0 24 VMV3 60 IO52NDB1 96 GAB0/IO02RSB0 25 GNDQ 61 GCB2/IO52PDB1 97 GAA1/IO01RSB0 26 GEA2/IO97RSB2 62 GCA1/IO50PDB1 98 GAA0/IO00RSB0 27 GEB2/IO96RSB2 63 GCA0/IO50NDB1 99 GNDQ 28 GEC2/IO95RSB2 64 GCC0/IO48NDB1 100 VMV0 29 IO93RSB2 65 GCC1/IO48PDB1 30 IO92RSB2 66 VCCIB1 31 IO91RSB2 67 GND 32 IO90RSB2 68 VCC 33 IO88RSB2 69 IO43NDB1 34 IO86RSB2 70 GBC2/IO43PDB1 35 IO85RSB2 71 GBB2/IO42PSB1 36 IO84RSB2 72 IO41NDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-5 ProASIC3 Flash Family FPGAs 144-Pin TQFP 144 1 144-Pin TQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 4 -6 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs 144-Pin TQFP* 144-Pin TQFP* 144-Pin TQFP* Pin Number A3P060 Function Pin Number A3P060 Function Pin Number A3P060 Function 1 GAA2/IO51RSB1 37 NC 73 VPUMP 2 IO52RSB1 38 GEA2/IO71RSB1 74 NC 3 GAB2/IO53RSB1 39 GEB2/IO70RSB1 75 TDO 4 IO95RSB1 40 GEC2/IO69RSB1 76 TRST 5 GAC2/IO94RSB1 41 IO68RSB1 77 VJTAG 6 IO93RSB1 42 IO67RSB1 78 GDA0/IO50RSB0 7 IO92RSB1 43 IO66RSB1 79 GDB0/IO48RSB0 8 IO91RSB1 44 IO65RSB1 80 GDB1/IO47RSB0 9 VCC 45 VCC 81 VCCIB0 10 GND 46 GND 82 GND 11 VCCIB1 47 VCCIB1 83 IO44RSB0 12 IO90RSB1 48 NC 84 GCC2/IO43RSB0 13 GFC1/IO89RSB1 49 IO64RSB1 85 GCB2/IO42RSB0 14 GFC0/IO88RSB1 50 NC 86 GCA2/IO41RSB0 15 GFB1/IO87RSB1 51 IO63RSB1 87 GCA0/IO40RSB0 16 GFB0/IO86RSB1 52 NC 88 GCA1/IO39RSB0 17 VCOMPLF 53 IO62RSB1 89 GCB0/IO38RSB0 18 GFA0/IO85RSB1 54 NC 90 GCB1/IO37RSB0 19 VCCPLF 55 IO61RSB1 91 GCC0/IO36RSB0 20 GFA1/IO84RSB1 56 NC 92 GCC1/IO35RSB0 21 GFA2/IO83RSB1 57 NC 93 IO34RSB0 22 GFB2/IO82RSB1 58 IO60RSB1 94 IO33RSB0 23 GFC2/IO81RSB1 59 IO59RSB1 95 NC 24 IO80RSB1 60 IO58RSB1 96 NC 25 IO79RSB1 61 GDC2/IO57RSB1 97 NC 26 IO78RSB1 62 NC 98 VCCIB0 27 GND 63 GND 99 GND 28 VCCIB1 64 NC 100 VCC 29 GEC1/IO77RSB1 65 GDB2/IO56RSB1 101 IO30RSB0 30 GEC0/IO76RSB1 66 GDA2/IO55RSB1 102 GBC2/IO29RSB0 31 GEB1/IO75RSB1 67 IO54RSB1 103 IO28RSB0 32 GEB0/IO74RSB1 68 GNDQ 104 GBB2/IO27RSB0 33 GEA1/IO73RSB1 69 TCK 105 IO26RSB0 34 GEA0/IO72RSB1 70 TDI 106 GBA2/IO25RSB0 35 VMV1 71 TMS 107 VMV0 36 GNDQ 72 VMV1 108 GNDQ Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-7 ProASIC3 Flash Family FPGAs 144-Pin TQFP* Pin Number A3P060 Function 109 NC 110 NC 111 GBA1/IO24RSB0 112 GBA0/IO23RSB0 113 GBB1/IO22RSB0 114 GBB0/IO21RSB0 115 GBC1/IO20RSB0 116 GBC0/IO19RSB0 117 VCCIB0 118 GND 119 VCC 120 IO18RSB0 121 IO17RSB0 122 IO16RSB0 123 IO15RSB0 124 IO14RSB0 125 IO13RSB0 126 IO12RSB0 127 IO11RSB0 128 NC 129 IO10RSB0 130 IO09RSB0 131 IO08RSB0 132 GAC1/IO07RSB0 133 GAC0/IO06RSB0 134 NC 135 GND 136 NC 137 GAB1/IO05RSB0 138 GAB0/IO04RSB0 139 GAA1/IO03RSB0 140 GAA0/IO02RSB0 141 IO01RSB0 142 IO00RSB0 143 GNDQ 144 VMV0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -8 A d v a n c e d v 0 .2 ProASIC3 Flash Family FPGAs 144_Pin TQFP* 144_Pin TQFP* 144_Pin TQFP* Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 1 GAA2/IO67RSB1 37 NC 73 VPUMP 2 IO68RSB1 38 GEA2/IO106RSB1 74 NC 3 GAB2/IO69RSB1 39 GEB2/IO105RSB1 75 TDO 4 IO132RSB1 40 GEC2/IO104RSB1 76 TRST 5 GAC2/IO131RSB1 41 IO103RSB1 77 VJTAG 6 IO130RSB1 42 IO102RSB1 78 GDA0/IO66RSB0 7 IO129RSB1 43 IO101RSB1 79 GDB0/IO64RSB0 8 IO128RSB1 44 IO100RSB1 80 GDB1/IO63RSB0 9 VCC 45 VCC 81 VCCIB0 10 GND 46 GND 82 GND 11 VCCIB1 47 VCCIB1 83 IO60RSB0 12 IO127RSB1 48 IO99RSB1 84 GCC2/IO59RSB0 13 GFC1/IO126RSB1 49 IO97RSB1 85 GCB2/IO58RSB0 14 GFC0/IO125RSB1 50 IO95RSB1 86 GCA2/IO57RSB0 15 GFB1/IO124RSB1 51 IO93RSB1 87 GCA0/IO56RSB0 16 GFB0/IO123RSB1 52 IO92RSB1 88 GCA1/IO55RSB0 17 VCOMPLF 53 IO90RSB1 89 GCB0/IO54RSB0 18 GFA0/IO122RSB1 54 IO88RSB1 90 GCB1/IO53RSB0 19 VCCPLF 55 IO86RSB1 91 GCC0/IO52RSB0 20 GFA1/IO121RSB1 56 IO84RSB1 92 GCC1/IO51RSB0 21 GFA2/IO120RSB1 57 IO83RSB1 93 IO50RSB0 22 GFB2/IO119RSB1 58 IO82RSB1 94 IO49RSB0 23 GFC2/IO118RSB1 59 IO81RSB1 95 NC 24 IO117RSB1 60 IO80RSB1 96 NC 25 IO116RSB1 61 IO79RSB1 97 NC 26 IO115RSB1 62 VCC 98 VCCIB0 27 GND 63 GND 99 GND 28 VCCIB1 64 VCCIB1 100 VCC 29 GEC1/IO112RSB1 65 GDC2/IO72RSB1 101 IO47RSB0 30 GEC0/IO111RSB1 66 GDB2/IO71RSB1 102 GBC2/IO45RSB0 31 GEB1/IO110RSB1 67 GDA2/IO70RSB1 103 IO44RSB0 32 GEB0/IO109RSB1 68 GNDQ 104 GBB2/IO43RSB0 33 GEA1/IO108RSB1 69 TCK 105 IO42RSB0 34 GEA0/IO107RSB1 70 TDI 106 GBA2/IO41RSB0 35 VMV1 71 TMS 107 VMV0 36 GNDQ 72 VMV1 108 GNDQ Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-9 ProASIC3 Flash Family FPGAs 144_Pin TQFP* Pin Number A3P125 Function 109 GBA1/IO40RSB0 110 GBA0/IO39RSB0 111 GBB1/IO38RSB0 112 GBB0/IO37RSB0 113 GBC1/IO36RSB0 114 GBC0/IO35RSB0 115 IO34RSB0 116 IO33RSB0 117 VCCIB0 118 GND 119 VCC 120 IO29RSB0 121 IO28RSB0 122 IO27RSB0 123 IO25RSB0 124 IO23RSB0 125 IO21RSB0 126 IO19RSB0 127 IO17RSB0 128 IO16RSB0 129 IO14RSB0 130 IO12RSB0 131 IO10RSB0 132 IO08RSB0 133 IO06RSB0 134 VCCIB0 135 GND 136 VCC 137 GAC1/IO05RSB0 138 GAC0/IO04RSB0 139 GAB1/IO03RSB0 140 GAB0/IO02RSB0 141 GAA1/IO01RSB0 142 GAA0/IO00RSB0 143 GNDQ 144 VMV0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -1 0 Advanced v0.2 ProASIC3 Flash Family FPGAs 208-Pin PQFP 1 208 208-Pin PQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. A d v a n c ed v 0.2 4-11 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 1 GND 39 NC 77 IO88RSB1 2 GAA2/IO67RSB1 40 VCCIB1 78 IO87RSB1 3 IO68RSB1 41 GND 79 IO86RSB1 4 GAB2/IO69RSB1 42 IO114RSB1 80 IO85RSB1 5 IO132RSB1 43 IO113RSB1 81 GND 6 GAC2/IO131RSB1 44 GEC1/IO112RSB1 82 IO84RSB1 7 NC 45 GEC0/IO111RSB1 83 IO83RSB1 8 NC 46 GEB1/IO110RSB1 84 IO82RSB1 9 IO130RSB1 47 GEB0/IO109RSB1 85 IO81RSB1 10 IO129RSB1 48 GEA1/IO108RSB1 86 IO80RSB1 11 NC 49 GEA0/IO107RSB1 87 IO79RSB1 12 IO128RSB1 50 VMV1 88 VCC 13 NC 51 GNDQ 89 VCCIB1 14 NC 52 GND 90 IO78RSB1 15 NC 53 NC 91 IO77RSB1 16 VCC 54 NC 92 IO76RSB1 17 GND 55 GEA2/IO106RSB1 93 IO75RSB1 18 VCCIB1 56 GEB2/IO105RSB1 94 IO74RSB1 19 IO127RSB1 57 GEC2/IO104RSB1 95 IO73RSB1 20 NC 58 IO103RSB1 96 GDC2/IO72RSB1 21 GFC1/IO126RSB1 59 IO102RSB1 97 GND 22 GFC0/IO125RSB1 60 IO101RSB1 98 GDB2/IO71RSB1 23 GFB1/IO124RSB1 61 IO100RSB1 99 GDA2/IO70RSB1 24 GFB0/IO123RSB1 62 VCCIB1 100 GNDQ 25 VCOMPLF 63 IO99RSB1 101 TCK 26 GFA0/IO122RSB1 64 IO98RSB1 102 TDI 27 VCCPLF 65 GND 103 TMS 28 GFA1/IO121RSB1 66 IO97RSB1 104 VMV1 29 GND 67 IO96RSB1 105 GND 30 GFA2/IO120RSB1 68 IO95RSB1 106 VPUMP 31 NC 69 IO94RSB1 107 NC 32 GFB2/IO119RSB1 70 IO93RSB1 108 TDO 33 NC 71 VCC 109 TRST 34 GFC2/IO118RSB1 72 VCCIB1 110 VJTAG 35 IO117RSB1 73 IO92RSB1 111 GDA0/IO66RSB0 36 NC 74 IO91RSB1 112 GDA1/IO65RSB0 37 IO116RSB1 75 IO90RSB1 113 GDB0/IO64RSB0 38 IO115RSB1 76 IO89RSB1 114 GDB1/IO63RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -1 2 Advanced v0.2 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 115 GDC0/IO62RSB0 153 GBA2/IO41RSB0 191 IO13RSB0 116 GDC1/IO61RSB0 154 VMV0 192 IO12RSB0 117 NC 155 GNDQ 193 IO11RSB0 118 NC 156 GND 194 IO10RSB0 119 NC 157 NC 195 GND 120 NC 158 GBA1/IO40RSB0 196 IO09RSB0 121 NC 159 GBA0/IO39RSB0 197 IO08RSB0 122 GND 160 GBB1/IO38RSB0 198 IO07RSB0 123 VCCIB0 161 GBB0/IO37RSB0 199 IO06RSB0 124 NC 162 GND 200 VCCIB0 125 NC 163 GBC1/IO36RSB0 201 GAC1/IO05RSB0 126 VCC 164 GBC0/IO35RSB0 202 GAC0/IO04RSB0 127 IO60RSB0 165 IO34RSB0 203 GAB1/IO03RSB0 128 GCC2/IO59RSB0 166 IO33RSB0 204 GAB0/IO02RSB0 129 GCB2/IO58RSB0 167 IO32RSB0 205 GAA1/IO01RSB0 130 GND 168 IO31RSB0 206 GAA0/IO00RSB0 131 GCA2/IO57RSB0 169 IO30RSB0 207 GNDQ 132 GCA0/IO56RSB0 170 VCCIB0 208 VMV0 133 GCA1/IO55RSB0 171 VCC 134 GCB0/IO54RSB0 172 IO29RSB0 135 GCB1/IO53RSB0 173 IO28RSB0 136 GCC0/IO52RSB0 174 IO27RSB0 137 GCC1/IO51RSB0 175 IO26RSB0 138 IO50RSB0 176 IO25RSB0 139 IO49RSB0 177 IO24RSB0 140 VCCIB0 178 GND 141 GND 179 IO23RSB0 142 VCC 180 IO22RSB0 143 IO48RSB0 181 IO21RSB0 144 IO47RSB0 182 IO20RSB0 145 IO46RSB0 183 IO19RSB0 146 NC 184 IO18RSB0 147 NC 185 IO17RSB0 148 NC 186 VCCIB0 149 GBC2/IO45RSB0 187 VCC 150 IO44RSB0 188 IO16RSB0 151 GBB2/IO43RSB0 189 IO15RSB0 152 IO42RSB0 190 IO14RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-13 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function 1 GND 39 IO103PSB3 77 IO79RSB2 2 GAA2/IO118PDB3 40 VCCIB3 78 IO78RSB2 3 IO118NDB3 41 GND 79 IO77RSB2 4 GAB2/IO117PDB3 42 IO101PDB3 80 IO76RSB2 5 IO117NDB3 43 IO101NDB3 81 GND 6 GAC2/IO116PDB3 44 GEC1/IO100PDB3 82 IO75RSB2 7 IO116NDB3 45 GEC0/IO100NDB3 83 IO74RSB2 8 IO115PDB3 46 GEB1/IO99PDB3 84 IO73RSB2 9 IO115NDB3 47 GEB0/IO99NDB3 85 IO72RSB2 10 IO114PDB3 48 GEA1/IO98PDB3 86 IO71RSB2 11 IO114NDB3 49 GEA0/IO98NDB3 87 IO70RSB2 12 IO113PDB3 50 VMV3 88 VCC 13 IO113NDB3 51 GNDQ 89 VCCIB2 14 IO112PDB3 52 GND 90 IO69RSB2 15 IO112NDB3 53 NC 91 IO68RSB2 16 VCC 54 NC 92 IO67RSB2 17 GND 55 GEA2/IO97RSB2 93 IO66RSB2 18 VCCIB3 56 GEB2/IO96RSB2 94 IO65RSB2 19 IO111PDB3 57 GEC2/IO95RSB2 95 IO64RSB2 20 IO111NDB3 58 IO94RSB2 96 GDC2/IO63RSB2 21 GFC1/IO110PDB3 59 IO93RSB2 97 GND 22 GFC0/IO110NDB3 60 IO92RSB2 98 GDB2/IO62RSB2 23 GFB1/IO109PDB3 61 IO91RSB2 99 GDA2/IO61RSB2 24 GFB0/IO109NDB3 62 VCCIB2 100 GNDQ 25 VCOMPLF 63 IO90RSB2 101 TCK 26 GFA0/IO108NPB3 64 IO89RSB2 102 TDI 27 VCCPLF 65 GND 103 TMS 28 GFA1/IO108PPB3 66 IO88RSB2 104 VMV2 29 GND 67 IO87RSB2 105 GND 30 GFA2/IO107PDB3 68 IO86RSB2 106 VPUMP 31 IO107NDB3 69 IO85RSB2 107 NC 32 GFB2/IO106PDB3 70 IO84RSB2 108 TDO 33 IO106NDB3 71 VCC 109 TRST 34 GFC2/IO105PDB3 72 VCCIB2 110 VJTAG 35 IO105NDB3 73 IO83RSB2 111 GDA0/IO60NDB1 36 NC 74 IO82RSB2 112 GDA1/IO60PDB1 37 IO104PDB3 75 IO81RSB2 113 GDB0/IO59NDB1 38 IO104NDB3 76 IO80RSB2 114 GDB1/IO59PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -1 4 Advanced v0.2 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function 115 GDC0/IO58NDB1 153 GBA2/IO41PDB1 191 IO13RSB0 116 GDC1/IO58PDB1 154 VMV1 192 IO12RSB0 117 IO57NDB1 155 GNDQ 193 IO11RSB0 118 IO57PDB1 156 GND 194 IO10RSB0 119 IO56NDB1 157 NC 195 GND 120 IO56PDB1 158 GBA1/IO40RSB0 196 IO09RSB0 121 IO55RSB1 159 GBA0/IO39RSB0 197 IO08RSB0 122 GND 160 GBB1/IO38RSB0 198 IO07RSB0 123 VCCIB1 161 GBB0/IO37RSB0 199 IO06RSB0 124 NC 162 GND 200 VCCIB0 125 NC 163 GBC1/IO36RSB0 201 GAC1/IO05RSB0 126 VCC 164 GBC0/IO35RSB0 202 GAC0/IO04RSB0 127 IO53NDB1 165 IO34RSB0 203 GAB1/IO03RSB0 128 GCC2/IO53PDB1 166 IO33RSB0 204 GAB0/IO02RSB0 129 GCB2/IO52PSB1 167 IO32RSB0 205 GAA1/IO01RSB0 130 GND 168 IO31RSB0 206 GAA0/IO00RSB0 131 GCA2/IO51PSB1 169 IO30RSB0 207 GNDQ 132 GCA1/IO50PDB1 170 VCCIB0 208 VMV0 133 GCA0/IO50NDB1 171 VCC 134 GCB0/IO49NDB1 172 IO29RSB0 135 GCB1/IO49PDB1 173 IO28RSB0 136 GCC0/IO48NDB1 174 IO27RSB0 137 GCC1/IO48PDB1 175 IO26RSB0 138 IO47NDB1 176 IO25RSB0 139 IO47PDB1 177 IO24RSB0 140 VCCIB1 178 GND 141 GND 179 IO23RSB0 142 VCC 180 IO22RSB0 143 IO46RSB1 181 IO21RSB0 144 IO45NDB1 182 IO20RSB0 145 IO45PDB1 183 IO19RSB0 146 IO44NDB1 184 IO18RSB0 147 IO44PDB1 185 IO17RSB0 148 IO43NDB1 186 VCCIB0 149 GBC2/IO43PDB1 187 VCC 150 IO42NDB1 188 IO16RSB0 151 GBB2/IO42PDB1 189 IO15RSB0 152 IO41NDB1 190 IO14RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-15 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function 1 GND 39 IO140PSB3 77 IO108RSB2 2 GAA2/IO155PDB3 40 VCCIB3 78 IO107RSB2 3 IO155NDB3 41 GND 79 IO106RSB2 4 GAB2/IO154PDB3 42 IO138PDB3 80 IO103RSB2 5 IO154NDB3 43 IO138NDB3 81 GND 6 GAC2/IO153PDB3 44 GEC1/IO137PDB3 82 IO102RSB2 7 IO153NDB3 45 GEC0/IO137NDB3 83 IO101RSB2 8 IO152PDB3 46 GEB1/IO136PDB3 84 IO100RSB2 9 IO152NDB3 47 GEB0/IO136NDB3 85 IO99RSB2 10 IO151PDB3 48 GEA1/IO135PDB3 86 IO98RSB2 11 IO151NDB3 49 GEA0/IO135NDB3 87 IO97RSB2 12 IO150PDB3 50 VMV3 88 VCC 13 IO150NDB3 51 GNDQ 89 VCCIB2 14 IO149PDB3 52 GND 90 IO94RSB2 15 IO149NDB3 53 NC 91 IO92RSB2 16 VCC 54 NC 92 IO90RSB2 17 GND 55 GEA2/IO134RSB2 93 IO88RSB2 18 VCCIB3 56 GEB2/IO133RSB2 94 IO86RSB2 19 IO148PDB3 57 GEC2/IO132RSB2 95 IO84RSB2 20 IO148NDB3 58 IO131RSB2 96 GDC2/IO82RSB2 21 GFC1/IO147PDB3 59 IO130RSB2 97 GND 22 GFC0/IO147NDB3 60 IO129RSB2 98 GDB2/IO81RSB2 23 GFB1/IO146PDB3 61 IO128RSB2 99 GDA2/IO80RSB2 24 GFB0/IO146NDB3 62 VCCIB2 100 GNDQ 25 VCOMPLF 63 IO126RSB2 101 TCK 26 GFA0/IO145NPB3 64 IO124RSB2 102 TDI 27 VCCPLF 65 GND 103 TMS 28 GFA1/IO145PPB3 66 IO122RSB2 104 VMV2 29 GND 67 IO120RSB2 105 GND 30 GFA2/IO144PDB3 68 IO118RSB2 106 VPUMP 31 IO144NDB3 69 IO116RSB2 107 NC 32 GFB2/IO143PDB3 70 IO114RSB2 108 TDO 33 IO143NDB3 71 VCC 109 TRST 34 GFC2/IO142PDB3 72 VCCIB2 110 VJTAG 35 IO142NDB3 73 IO112RSB2 111 GDA0/IO79NDB1 36 NC 74 IO111RSB2 112 GDA1/IO79PDB1 37 IO141PDB3 75 IO110RSB2 113 GDB0/IO78NDB1 38 IO141NDB3 76 IO109RSB2 114 GDB1/IO78PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -1 6 Advanced v0.2 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function 115 GDC0/IO77NDB1 153 GBA2/IO60PDB1 191 IO13RSB0 116 GDC1/IO77PDB1 154 VMV1 192 IO12RSB0 117 IO76NDB1 155 GNDQ 193 IO11RSB0 118 IO76PDB1 156 GND 194 IO10RSB0 119 IO75NDB1 157 NC 195 GND 120 IO75PDB1 158 GBA1/IO59RSB0 196 IO09RSB0 121 IO74RSB1 159 GBA0/IO58RSB0 197 IO08RSB0 122 GND 160 GBB1/IO57RSB0 198 IO07RSB0 123 VCCIB1 161 GBB0/IO56RSB0 199 IO06RSB0 124 NC 162 GND 200 VCCIB0 125 NC 163 GBC1/IO55RSB0 201 GAC1/IO05RSB0 126 VCC 164 GBC0/IO54RSB0 202 GAC0/IO04RSB0 127 IO73PSB1 165 IO52RSB0 203 GAB1/IO03RSB0 128 GCC2/IO72PSB1 166 IO50RSB0 204 GAB0/IO02RSB0 129 GCB2/IO71PSB1 167 IO48RSB0 205 GAA1/IO01RSB0 130 GND 168 IO46RSB0 206 GAA0/IO00RSB0 131 GCA2/IO70PSB1 169 IO44RSB0 207 GNDQ 132 GCA1/IO69PDB1 170 VCCIB0 208 VMV0 133 GCA0/IO69NDB1 171 VCC 134 GCB0/IO68NDB1 172 IO37RSB0 135 GCB1/IO68PDB1 173 IO36RSB0 136 GCC0/IO67NDB1 174 IO35RSB0 137 GCC1/IO67PDB1 175 IO34RSB0 138 IO66NDB1 176 IO33RSB0 139 IO66PDB1 177 IO32RSB0 140 VCCIB1 178 GND 141 GND 179 IO31RSB0 142 VCC 180 IO30RSB0 143 IO65RSB1 181 IO29RSB0 144 IO64NDB1 182 IO28RSB0 145 IO64PDB1 183 IO27RSB0 146 IO63NDB1 184 IO25RSB0 147 IO63PDB1 185 IO23RSB0 148 IO62NDB1 186 VCCIB0 149 GBC2/IO62PDB1 187 VCC 150 IO61NDB1 188 IO19RSB0 151 GBB2/IO61PDB1 189 IO17RSB0 152 IO60NDB1 190 IO15RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-17 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function 1 GND 39 IO146PSB3 77 IO114RSB2 2 GAA2/IO170PDB3 40 VCCIB3 78 IO113RSB2 3 IO170NDB3 41 GND 79 IO112RSB2 4 GAB2/IO169PDB3 42 IO145PDB3 80 IO110RSB2 5 IO169NDB3 43 IO145NDB3 81 GND 6 GAC2/IO168PDB3 44 GEC1/IO144PDB3 82 IO109RSB2 7 IO168NDB3 45 GEC0/IO144NDB3 83 IO108RSB2 8 IO167PDB3 46 GEB1/IO143PDB3 84 IO107RSB2 9 IO167NDB3 47 GEB0/IO143NDB3 85 IO106RSB2 10 IO166PDB3 48 GEA1/IO142PDB3 86 IO105RSB2 11 IO166NDB3 49 GEA0/IO142NDB3 87 IO104RSB2 12 IO165PDB3 50 VMV3 88 VCC 13 IO165NDB3 51 GNDQ 89 VCCIB2 14 IO164PDB3 52 GND 90 IO102RSB2 15 IO164NDB3 53 NC 91 IO100RSB2 16 VCC 54 GEA2/IO141RSB2 92 IO98RSB2 17 GND 55 GEB2/IO140RSB2 93 IO96RSB2 18 VCCIB3 56 GEC2/IO139RSB2 94 IO94RSB2 19 IO163PDB3 57 IO138RSB2 95 IO90RSB2 20 IO163NDB3 58 IO137RSB2 96 GDC2/IO89RSB2 21 GFC1/IO161PDB3 59 IO136RSB2 97 GND 22 GFC0/IO161NDB3 60 IO135RSB2 98 GDB2/IO88RSB2 23 GFB1/IO160PDB3 61 IO134RSB2 99 GDA2/IO87RSB2 24 GFB0/IO160NDB3 62 VCCIB2 100 GNDQ 25 VCOMPLF 63 IO133RSB2 101 TCK 26 GFA0/IO159NPB3 64 IO131RSB2 102 TDI 27 VCCPLF 65 GND 103 TMS 28 GFA1/IO159PPB3 66 IO129RSB2 104 VMV2 29 GND 67 IO127RSB2 105 GND 30 GFA2/IO158PDB3 68 IO125RSB2 106 VPUMP 31 IO158NDB3 69 IO123RSB2 107 GNDQ 32 GFB2/IO157PDB3 70 IO121RSB2 108 TDO 33 IO157NDB3 71 VCC 109 TRST 34 GFC2/IO156PDB3 72 VCCIB2 110 VJTAG 35 IO156NDB3 73 IO118RSB2 111 GDA0/IO86NDB1 36 VCC 74 IO117RSB2 112 GDA1/IO86PDB1 37 IO147PDB3 75 IO116RSB2 113 GDB0/IO85NDB1 38 IO147NDB3 76 IO115RSB2 114 GDB1/IO85PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -1 8 Advanced v0.2 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function 115 GDC0/IO84NDB1 153 GBA2/IO60PDB1 191 IO17RSB0 116 GDC1/IO84PDB1 154 VMV1 192 IO16RSB0 117 IO82NDB1 155 GNDQ 193 IO14RSB0 118 IO82PDB1 156 GND 194 IO12RSB0 119 IO80NDB1 157 NC 195 GND 120 IO80PDB1 158 GBA1/IO59RSB0 196 IO10RSB0 121 IO79PSB1 159 GBA0/IO58RSB0 197 IO09RSB0 122 GND 160 GBB1/IO57RSB0 198 IO08RSB0 123 VCCIB1 161 GBB0/IO56RSB0 199 IO07RSB0 124 IO75NDB1 162 GND 200 VCCIB0 125 IO75PDB1 163 GBC1/IO55RSB0 201 GAC1/IO05RSB0 126 NC 164 GBC0/IO54RSB0 202 GAC0/IO04RSB0 127 IO73NDB1 165 IO52RSB0 203 GAB1/IO03RSB0 128 GCC2/IO73PDB1 166 IO50RSB0 204 GAB0/IO02RSB0 129 GCB2/IO72PSB1 167 IO48RSB0 205 GAA1/IO01RSB0 130 GND 168 IO46RSB0 206 GAA0/IO00RSB0 131 GCA2/IO71PSB1 169 IO44RSB0 207 GNDQ 132 GCA1/IO70PDB1 170 VCCIB0 208 VMV0 133 GCA0/IO70NDB1 171 VCC 134 GCB0/IO69NDB1 172 IO36RSB0 135 GCB1/IO69PDB1 173 IO35RSB0 136 GCC0/IO68NDB1 174 IO34RSB0 137 GCC1/IO68PDB1 175 IO33RSB0 138 IO66NDB1 176 IO32RSB0 139 IO66PDB1 177 IO31RSB0 140 VCCIB1 178 GND 141 GND 179 IO29RSB0 142 VCC 180 IO28RSB0 143 IO65PSB1 181 IO27RSB0 144 IO64NDB1 182 IO26RSB0 145 IO64PDB1 183 IO25RSB0 146 IO63NDB1 184 IO24RSB0 147 IO63PDB1 185 IO23RSB0 148 IO62NDB1 186 VCCIB0 149 GBC2/IO62PDB1 187 VCC 150 IO61NDB1 188 IO20RSB0 151 GBB2/IO61PDB1 189 IO19RSB0 152 IO60NDB1 190 IO18RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-19 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function 1 GND 39 IO189PSB3 77 IO151RSB2 2 GAA2/IO219PDB3 40 VCCIB3 78 IO149RSB2 3 IO219NDB3 41 GND 79 IO147RSB2 4 GAB2/IO218PDB3 42 IO188PDB3 80 IO145RSB2 5 IO218NDB3 43 IO188NDB3 81 GND 6 GAC2/IO217PDB3 44 GEC1/IO187PDB3 82 IO140RSB2 7 IO217NDB3 45 GEC0/IO187NDB3 83 IO138RSB2 8 IO216PDB3 46 GEB1/IO186PDB3 84 IO136RSB2 9 IO216NDB3 47 GEB0/IO186NDB3 85 IO134RSB2 10 IO215PDB3 48 GEA1/IO185PDB3 86 IO132RSB2 11 IO215NDB3 49 GEA0/IO185NDB3 87 IO130RSB2 12 IO214PDB3 50 VMV3 88 VCC 13 IO214NDB3 51 GNDQ 89 VCCIB2 14 IO213PDB3 52 GND 90 IO125RSB2 15 IO213NDB3 53 NC 91 IO123RSB2 16 VCC 54 GEA2/IO184RSB2 92 IO121RSB2 17 GND 55 GEB2/IO183RSB2 93 IO119RSB2 18 VCCIB3 56 GEC2/IO182RSB2 94 IO117RSB2 19 IO211PDB3 57 IO181RSB2 95 IO115RSB2 20 IO211NDB3 58 IO180RSB2 96 GDC2/IO113RSB2 21 GFC1/IO206PDB3 59 IO179RSB2 97 GND 22 GFC0/IO206NDB3 60 IO178RSB2 98 GDB2/IO112RSB2 23 GFB1/IO205PDB3 61 IO177RSB2 99 GDA2/IO111RSB2 24 GFB0/IO205NDB3 62 VCCIB2 100 GNDQ 25 VCOMPLF 63 IO175RSB2 101 TCK 26 GFA0/IO204NPB3 64 IO173RSB2 102 TDI 27 VCCPLF 65 GND 103 TMS 28 GFA1/IO204PPB3 66 IO171RSB2 104 VMV2 29 GND 67 IO169RSB2 105 GND 30 GFA2/IO203PDB3 68 IO167RSB2 106 VPUMP 31 IO203NDB3 69 IO165RSB2 107 GNDQ 32 GFB2/IO202PDB3 70 IO163RSB2 108 TDO 33 IO202NDB3 71 VCC 109 TRST 34 GFC2/IO201PDB3 72 VCCIB2 110 VJTAG 35 IO201NDB3 73 IO159RSB2 111 GDA0/IO110NDB1 36 VCC 74 IO157RSB2 112 GDA1/IO110PDB1 37 IO191PDB3 75 IO155RSB2 113 GDB0/IO109NDB1 38 IO191NDB3 76 IO153RSB2 114 GDB1/IO109PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -2 0 Advanced v0.2 ProASIC3 Flash Family FPGAs 208-Pin PQFP* 208-Pin PQFP* 208-Pin PQFP* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function 115 GDC0/IO108NDB1 153 GBA2/IO78PDB1 191 IO16RSB0 116 GDC1/IO108PDB1 154 VMV1 192 IO15RSB0 117 IO106NDB1 155 GNDQ 193 IO14RSB0 118 IO106PDB1 156 GND 194 IO13RSB0 119 IO104NDB1 157 NC 195 GND 120 IO104PDB1 158 GBA1/IO77RSB0 196 IO12RSB0 121 IO102PSB1 159 GBA0/IO76RSB0 197 IO11RSB0 122 GND 160 GBB1/IO75RSB0 198 IO10RSB0 123 VCCIB1 161 GBB0/IO74RSB0 199 IO09RSB0 124 IO97NDB1 162 GND 200 VCCIB0 125 IO97PDB1 163 GBC1/IO73RSB0 201 GAC1/IO05RSB0 126 NC 164 GBC0/IO72RSB0 202 GAC0/IO04RSB0 127 IO93NDB1 165 IO70RSB0 203 GAB1/IO03RSB0 128 GCC2/IO93PDB1 166 IO67RSB0 204 GAB0/IO02RSB0 129 GCB2/IO92PSB1 167 IO63RSB0 205 GAA1/IO01RSB0 130 GND 168 IO60RSB0 206 GAA0/IO00RSB0 131 GCA2/IO91PSB1 169 IO57RSB0 207 GNDQ 132 GCA1/IO90PDB1 170 VCCIB0 208 VMV0 133 GCA0/IO90NDB1 171 VCC 134 GCB0/IO89NDB1 172 IO54RSB0 135 GCB1/IO89PDB1 173 IO51RSB0 136 GCC0/IO88NDB1 174 IO48RSB0 137 GCC1/IO88PDB1 175 IO45RSB0 138 IO85NDB1 176 IO42RSB0 139 IO85PDB1 177 IO40RSB0 140 VCCIB1 178 GND 141 GND 179 IO38RSB0 142 VCC 180 IO35RSB0 143 IO83PSB1 181 IO33RSB0 144 IO82NDB1 182 IO31RSB0 145 IO82PDB1 183 IO29RSB0 146 IO81NDB1 184 IO27RSB0 147 IO81PDB1 185 IO25RSB0 148 IO80NDB1 186 VCCIB0 149 GBC2/IO80PDB1 187 VCC 150 IO79NDB1 188 IO22RSB0 151 GBB2/IO79PDB1 189 IO20RSB0 152 IO78NDB1 190 IO18RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-21 ProASIC3 Flash Family FPGAs 144-Pin FBGA A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 4 -2 2 Advanced v0.2 ProASIC3 Flash Family FPGAs 144-Pin FBGA* 144-Pin FBGA* 144-Pin FBGA* Pin Number A3P060 Function Pin Number A3P060 Function Pin Number A3P060 Function A1 GNDQ D1 IO91RSB1 G1 GFA1/IO84RSB1 A2 VMV0 D2 IO92RSB1 G2 GND A3 GAB0/IO04RSB0 D3 IO93RSB1 G3 VCCPLF A4 GAB1/IO05RSB0 D4 GAA2/IO51RSB1 G4 GFA0/IO85RSB1 A5 IO08RSB0 D5 GAC0/IO06RSB0 G5 GND A6 GND D6 GAC1/IO07RSB0 G6 GND A7 IO11RSB0 D7 GBC0/IO19RSB0 G7 GND A8 VCC D8 GBC1/IO20RSB0 G8 GDC1/IO45RSB0 A9 IO16RSB0 D9 GBB2/IO27RSB0 G9 IO32RSB0 A10 GBA0/IO23RSB0 D10 IO18RSB0 G10 GCC2/IO43RSB0 A11 GBA1/IO24RSB0 D11 IO28RSB0 G11 IO31RSB0 A12 GNDQ D12 GCB1/IO37RSB0 G12 GCB2/IO42RSB0 B1 GAB2/IO53RSB1 E1 VCC H1 VCC B2 GND E2 GFC0/IO88RSB1 H2 GFB2/IO82RSB1 B3 GAA0/IO02RSB0 E3 GFC1/IO89RSB1 H3 GFC2/IO81RSB1 B4 GAA1/IO03RSB0 E4 VCCIB1 H4 GEC1/IO77RSB1 B5 IO00RSB0 E5 IO52RSB1 H5 VCC B6 IO10RSB0 E6 VCCIB0 H6 IO34RSB0 B7 IO12RSB0 E7 VCCIB0 H7 IO44RSB0 B8 IO14RSB0 E8 GCC1/IO35RSB0 H8 GDB2/IO56RSB1 B9 GBB0/IO21RSB0 E9 VCCIB0 H9 GDC0/IO46RSB0 B10 GBB1/IO22RSB0 E10 VCC H10 VCCIB0 B11 GND E11 GCA0/IO40RSB0 H11 IO33RSB0 B12 VMV0 E12 IO30RSB0 H12 VCC C1 IO95RSB1 F1 GFB0/IO86RSB1 J1 GEB1/IO75RSB1 C2 GFA2/IO83RSB1 F2 VCOMPLF J2 IO78RSB1 C3 GAC2/IO94RSB1 F3 GFB1/IO87RSB1 J3 VCCIB1 C4 VCC F4 IO90RSB1 J4 GEC0/IO76RSB1 C5 IO01RSB0 F5 GND J5 IO79RSB1 C6 IO09RSB0 F6 GND J6 IO80RSB1 C7 IO13RSB0 F7 GND J7 VCC C8 IO15RSB0 F8 GCC0/IO36RSB0 J8 TCK C9 IO17RSB0 F9 GCB0/IO38RSB0 J9 GDA2/IO55RSB1 C10 GBA2/IO25RSB0 F10 GND J10 TDO C11 IO26RSB0 F11 GCA1/IO39RSB0 J11 GDA1/IO49RSB0 C12 GBC2/IO29RSB0 F12 GCA2/IO41RSB0 J12 GDB1/IO47RSB0 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-23 ProASIC3 Flash Family FPGAs 144-Pin FBGA* Pin Number A3P060 Function K1 GEB0/IO74RSB1 K2 GEA1/IO73RSB1 K3 GEA0/IO72RSB1 K4 GEA2/IO71RSB1 K5 IO65RSB1 K6 IO64RSB1 K7 GND K8 IO54RSB1 K9 GDC2/IO57RSB1 K10 GND K11 GDA0/IO50RSB0 K12 GDB0/IO48RSB0 L1 GND L2 VMV1 L3 GEB2/IO70RSB1 L4 IO67RSB1 L5 VCCIB1 L6 IO62RSB1 L7 IO59RSB1 L8 IO58RSB1 L9 TMS L10 VJTAG L11 VMV1 L12 TRST M1 GNDQ M2 GEC2/IO69RSB1 M3 IO68RSB1 M4 IO66RSB1 M5 IO63RSB1 M6 IO61RSB1 M7 IO60RSB1 M8 NC M9 TDI M10 VCCIB1 M11 VPUMP M12 GNDQ Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -2 4 Advanced v0.2 ProASIC3 Flash Family FPGAs 144-Pin FBGA* 144-Pin FBGA* 144-Pin FBGA* Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function A1 GNDQ D1 IO112NDB3 G1 GFA1/IO108PPB3 A2 VMV0 D2 IO112PDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO116NDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO118PPB3 G4 GFA0/IO108NPB3 A5 IO16RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO29RSB0 D7 GBC0/IO35RSB0 G7 GND A8 VCC D8 GBC1/IO36RSB0 G8 GDC1/IO58PPB1 A9 IO33RSB0 D9 GBB2/IO42PDB1 G9 IO53NDB1 A10 GBA0/IO39RSB0 D10 IO42NDB1 G10 GCC2/IO53PDB1 A11 GBA1/IO40RSB0 D11 IO43NPB1 G11 IO52NDB1 A12 GNDQ D12 GCB1/IO49PPB1 G12 GCB2/IO52PDB1 B1 GAB2/IO117PDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO110NDB3 H2 GFB2/IO106PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO110PDB3 H3 GFC2/IO105PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO100PDB3 B5 IO14RSB0 E5 IO118NPB3 H5 VCC B6 IO19RSB0 E6 VCCIB0 H6 IO79RSB2 B7 IO22RSB0 E7 VCCIB0 H7 IO65RSB2 B8 IO30RSB0 E8 GCC1/IO48PDB1 H8 GDB2/IO62RSB2 B9 GBB0/IO37RSB0 E9 VCCIB1 H9 GDC0/IO58NPB1 B10 GBB1/IO38RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO50NDB1 H11 IO54PSB1 B12 VMV1 E12 IO51NDB1 H12 VCC C1 IO117NDB3 F1 GFB0/IO109NPB3 J1 GEB1/IO99PDB3 C2 GFA2/IO107PPB3 F2 VCOMPLF J2 IO106NDB3 C3 GAC2/IO116PDB3 F3 GFB1/IO109PPB3 J3 VCCIB3 C4 VCC F4 IO107NPB3 J4 GEC0/IO100NDB3 C5 IO12RSB0 F5 GND J5 IO88RSB2 C6 IO17RSB0 F6 GND J6 IO81RSB2 C7 IO24RSB0 F7 GND J7 VCC C8 IO31RSB0 F8 GCC0/IO48NDB1 J8 TCK C9 IO34RSB0 F9 GCB0/IO49NPB1 J9 GDA2/IO61RSB2 C10 GBA2/IO41PDB1 F10 GND J10 TDO C11 IO41NDB1 F11 GCA1/IO50PDB1 J11 GDA1/IO60PDB1 C12 GBC2/IO43PPB1 F12 GCA2/IO51PDB1 J12 GDB1/IO59PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-25 ProASIC3 Flash Family FPGAs 144-Pin FBGA* Pin Number A3P250 Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60NDB1 K12 GDB0/IO59NDB1 L1 GND L2 VMV3 L3 GEB2/IO96RSB2 L4 IO91RSB2 L5 VCCIB2 L6 IO82RSB2 L7 IO80RSB2 L8 IO72RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO95RSB2 M3 IO92RSB2 M4 IO89RSB2 M5 IO87RSB2 M6 IO85RSB2 M7 IO78RSB2 M8 IO76RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -2 6 Advanced v0.2 ProASIC3 Flash Family FPGAs 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. A d v a n c ed v 0.2 4-27 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function A1 GND C6 GAC1/IO05RSB0 E11 VCCIB0 A2 GAA0/IO00RSB0 C7 IO13RSB0 E12 VMV1 A3 GAA1/IO01RSB0 C8 IO17RSB0 E13 GBC2/IO43PDB1 A4 GAB0/IO02RSB0 C9 IO22RSB0 E14 IO46RSB1 A5 IO07RSB0 C10 IO27RSB0 E15 NC A6 IO10RSB0 C11 IO31RSB0 E16 IO45PDB1 A7 IO11RSB0 C12 GBC0/IO35RSB0 F1 IO113NDB3 A8 IO15RSB0 C13 IO34RSB0 F2 IO112PPB3 A9 IO20RSB0 C14 NC F3 NC A10 IO25RSB0 C15 IO42NPB1 F4 IO115NDB3 A11 IO29RSB0 C16 IO44PDB1 F5 VCCIB3 A12 IO33RSB0 D1 IO114NDB3 F6 GND A13 GBB1/IO38RSB0 D2 IO114PDB3 F7 VCC A14 GBA0/IO39RSB0 D3 GAC2/IO116PDB3 F8 VCC A15 GBA1/IO40RSB0 D4 NC F9 VCC A16 GND D5 GNDQ F10 VCC B1 GAB2/IO117PDB3 D6 IO08RSB0 F11 GND B2 GAA2/IO118PDB3 D7 IO14RSB0 F12 VCCIB1 B3 NC D8 IO18RSB0 F13 IO43NDB1 B4 GAB1/IO03RSB0 D9 IO23RSB0 F14 NC B5 IO06RSB0 D10 IO28RSB0 F15 IO47PPB1 B6 IO09RSB0 D11 IO32RSB0 F16 IO45NDB1 B7 IO12RSB0 D12 GNDQ G1 IO111NDB3 B8 IO16RSB0 D13 NC G2 IO111PDB3 B9 IO21RSB0 D14 GBB2/IO42PPB1 G3 IO112NPB3 B10 IO26RSB0 D15 NC G4 GFC1/IO110PPB3 B11 IO30RSB0 D16 IO44NDB1 G5 VCCIB3 B12 GBC1/IO36RSB0 E1 IO113PDB3 G6 VCC B13 GBB0/IO37RSB0 E2 NC G7 GND B14 NC E3 IO116NDB3 G8 GND B15 GBA2/IO41PDB1 E4 IO115PDB3 G9 GND B16 IO41NDB1 E5 VMV0 G10 GND C1 IO117NDB3 E6 VCCIB0 G11 VCC C2 IO118NDB3 E7 VCCIB0 G12 VCCIB1 C3 NC E8 IO19RSB0 G13 GCC1/IO48PPB1 C4 NC E9 IO24RSB0 G14 IO47NPB1 C5 GAC0/IO04RSB0 E10 VCCIB0 G15 IO54PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -2 8 Advanced v0.2 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function G16 IO54NDB1 K5 VCCIB3 M10 VCCIB2 H1 GFB0/IO109NPB3 K6 VCC M11 VCCIB2 H2 GFA0/IO108NDB3 K7 GND M12 VMV2 H3 GFB1/IO109PPB3 K8 GND M13 NC H4 VCOMPLF K9 GND M14 GDB1/IO59PPB1 H5 GFC0/IO110NPB3 K10 GND M15 GDC1/IO58PDB1 H6 VCC K11 VCC M16 IO56NDB1 H7 GND K12 VCCIB1 N1 IO103NDB3 H8 GND K13 IO52NPB1 N2 IO101PPB3 H9 GND K14 IO55RSB1 N3 GEC1/IO100PPB3 H10 GND K15 IO53NPB1 N4 NC H11 VCC K16 IO51NDB1 N5 GNDQ H12 GCC0/IO48NPB1 L1 IO105NDB3 N6 GEA2/IO97RSB2 H13 GCB1/IO49PPB1 L2 IO104NPB3 N7 IO86RSB2 H14 GCA0/IO50NPB1 L3 NC N8 IO82RSB2 H15 NC L4 IO102RSB3 N9 IO75RSB2 H16 GCB0/IO49NPB1 L5 VCCIB3 N10 IO69RSB2 J1 GFA2/IO107PPB3 L6 GND N11 IO64RSB2 J2 GFA1/IO108PDB3 L7 VCC N12 GNDQ J3 VCCPLF L8 VCC N13 NC J4 IO106NDB3 L9 VCC N14 VJTAG J5 GFB2/IO106PDB3 L10 VCC N15 GDC0/IO58NDB1 J6 VCC L11 GND N16 GDA1/IO60PDB1 J7 GND L12 VCCIB1 P1 GEB1/IO99PDB3 J8 GND L13 GDB0/IO59NPB1 P2 GEB0/IO99NDB3 J9 GND L14 IO57NDB1 P3 NC J10 GND L15 IO57PDB1 P4 NC J11 VCC L16 IO56PDB1 P5 IO92RSB2 J12 GCB2/IO52PPB1 M1 IO103PDB3 P6 IO89RSB2 J13 GCA1/IO50PPB1 M2 NC P7 IO85RSB2 J14 GCC2/IO53PPB1 M3 IO101NPB3 P8 IO81RSB2 J15 NC M4 GEC0/IO100NPB3 P9 IO76RSB2 J16 GCA2/IO51PDB1 M5 VMV3 P10 IO71RSB2 K1 GFC2/IO105PDB3 M6 VCCIB2 P11 IO66RSB2 K2 IO107NPB3 M7 VCCIB2 P12 NC K3 IO104PPB3 M8 NC P13 TCK K4 NC M9 IO74RSB2 P14 VPUMP Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-29 ProASIC3 Flash Family FPGAs 256-Pin FBGA* Pin Number A3P250 Function P15 TRST P16 GDA0/IO60NDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 R3 NC R4 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 R8 IO80RSB2 R9 IO77RSB2 R10 IO72RSB2 R11 IO68RSB2 R12 IO65RSB2 R13 GDB2/IO62RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO94RSB2 T3 GEB2/IO96RSB2 T4 IO93RSB2 T5 IO90RSB2 T6 IO87RSB2 T7 IO83RSB2 T8 IO79RSB2 T9 IO78RSB2 T10 IO73RSB2 T11 IO70RSB2 T12 GDC2/IO63RSB2 T13 IO67RSB2 T14 GDA2/IO61RSB2 T15 TMS T16 GND Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -3 0 Advanced v0.2 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function A1 GND C6 GAC1/IO05RSB0 E11 VCCIB0 A2 GAA0/IO00RSB0 C7 IO20RSB0 E12 VMV1 A3 GAA1/IO01RSB0 C8 IO25RSB0 E13 GBC2/IO62PDB1 A4 GAB0/IO02RSB0 C9 IO32RSB0 E14 IO61NDB1 A5 IO14RSB0 C10 IO38RSB0 E15 IO63PDB1 A6 IO18RSB0 C11 IO44RSB0 E16 IO64PDB1 A7 IO22RSB0 C12 GBC0/IO54RSB0 F1 IO151NDB3 A8 IO27RSB0 C13 IO51RSB0 F2 IO150PPB3 A9 IO30RSB0 C14 IO52RSB0 F3 NC A10 IO39RSB0 C15 IO53RSB0 F4 IO148PPB3 A11 IO41RSB0 C16 IO60NPB1 F5 VCCIB3 A12 IO46RSB0 D1 IO152NPB3 F6 GND A13 GBB1/IO57RSB0 D2 IO155NPB3 F7 VCC A14 GBA0/IO58RSB0 D3 GAC2/IO153PDB3 F8 VCC A15 GBA1/IO59RSB0 D4 IO09RSB0 F9 VCC A16 GND D5 GNDQ F10 VCC B1 GAB2/IO154PDB3 D6 IO15RSB0 F11 GND B2 GAA2/IO155PPB3 D7 IO19RSB0 F12 VCCIB1 B3 IO10RSB0 D8 IO24RSB0 F13 IO62NDB1 B4 GAB1/IO03RSB0 D9 IO33RSB0 F14 NC B5 IO12RSB0 D10 IO40RSB0 F15 IO65RSB1 B6 IO16RSB0 D11 IO43RSB0 F16 IO73NDB1 B7 IO21RSB0 D12 GNDQ G1 IO150NPB3 B8 IO26RSB0 D13 IO49RSB0 G2 IO149PDB3 B9 IO31RSB0 D14 GBB2/IO61PDB1 G3 IO149NDB3 B10 IO37RSB0 D15 IO63NDB1 G4 GFC1/IO147PPB3 B11 IO42RSB0 D16 IO64NDB1 G5 VCCIB3 B12 GBC1/IO55RSB0 E1 IO151PDB3 G6 VCC B13 GBB0/IO56RSB0 E2 IO152PPB3 G7 GND B14 IO48RSB0 E3 IO153NDB3 G8 GND B15 GBA2/IO60PPB1 E4 IO11RSB0 G9 GND B16 IO50RSB0 E5 VMV0 G10 GND C1 IO154NDB3 E6 VCCIB0 G11 VCC C2 IO08RSB0 E7 VCCIB0 G12 VCCIB1 C3 IO07RSB0 E8 IO28RSB0 G13 GCC1/IO67PPB1 C4 IO06RSB0 E9 IO35RSB0 G14 IO66NDB1 C5 GAC0/IO04RSB0 E10 VCCIB0 G15 IO66PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-31 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function G16 IO73PDB1 K5 VCCIB3 M10 VCCIB2 H1 GFB0/IO146NPB3 K6 VCC M11 VCCIB2 H2 GFA0/IO145NDB3 K7 GND M12 VMV2 H3 GFB1/IO146PPB3 K8 GND M13 IO85RSB2 H4 VCOMPLF K9 GND M14 GDB1/IO78PPB1 H5 GFC0/IO147NPB3 K10 GND M15 GDC1/IO77PDB1 H6 VCC K11 VCC M16 IO76NDB1 H7 GND K12 VCCIB1 N1 IO141PDB3 H8 GND K13 IO71NPB1 N2 IO131RSB2 H9 GND K14 IO72NDB1 N3 GEC1/IO137PPB3 H10 GND K15 IO74RSB1 N4 IO128RSB2 H11 VCC K16 IO70NDB1 N5 GNDQ H12 GCC0/IO67NPB1 L1 IO142NDB3 N6 GEA2/IO134RSB2 H13 GCB1/IO68PPB1 L2 IO140NDB3 N7 IO113RSB2 H14 GCA0/IO69NPB1 L3 IO139RSB3 N8 IO109RSB2 H15 NC L4 IO138NDB3 N9 IO100RSB2 H16 GCB0/IO68NPB1 L5 VCCIB3 N10 IO95RSB2 J1 GFA2/IO144PPB3 L6 GND N11 IO90RSB2 J2 GFA1/IO145PDB3 L7 VCC N12 GNDQ J3 VCCPLF L8 VCC N13 IO83RSB2 J4 IO148NPB3 L9 VCC N14 VJTAG J5 GFB2/IO143PPB3 L10 VCC N15 GDC0/IO77NDB1 J6 VCC L11 GND N16 GDA1/IO79PDB1 J7 GND L12 VCCIB0 P1 GEB1/IO136PDB3 J8 GND L13 GDB0/IO78NPB1 P2 GEB0/IO136NDB3 J9 GND L14 IO75NDB1 P3 IO130RSB2 J10 GND L15 IO75PDB1 P4 IO129RSB2 J11 VCC L16 IO76PDB1 P5 IO126RSB2 J12 GCB2/IO71PPB1 M1 IO141NDB3 P6 IO121RSB2 J13 GCA1/IO69PPB1 M2 IO140PDB3 P7 IO115RSB2 J14 GCC2/IO72PDB1 M3 IO127RSB2 P8 IO108RSB2 J15 NC M4 GEC0/IO137NPB3 P9 IO101RSB2 J16 GCA2/IO70PDB1 M5 VMV3 P10 IO94RSB2 K1 GFC2/IO142PDB3 M6 VCCIB2 P11 IO88RSB2 K2 IO144NPB3 M7 VCCIB2 P12 IO84RSB2 K3 IO143NPB3 M8 IO106RSB2 P13 TCK K4 IO138PDB3 M9 IO99RSB2 P14 VPUMP Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -3 2 Advanced v0.2 ProASIC3 Flash Family FPGAs 256-Pin FBGA* Pin Number A3P400 Function P15 TRST P16 GDA0/IO79NDB1 R1 GEA1/IO135PDB3 R2 GEA0/IO135NDB3 R3 IO125RSB2 R4 GEC2/IO132RSB2 R5 IO122RSB2 R6 IO118RSB2 R7 IO112RSB2 R8 IO107RSB2 R9 IO102RSB2 R10 IO96RSB2 R11 IO91RSB2 R12 IO87RSB2 R13 GDB2/IO81RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO124RSB2 T3 GEB2/IO133RSB2 T4 IO123RSB2 T5 IO120RSB2 T6 IO116RSB2 T7 IO111RSB2 T8 IO105RSB2 T9 IO103RSB2 T10 IO97RSB2 T11 IO93RSB2 T12 GDC2/IO82RSB2 T13 IO86RSB2 T14 GDA2/IO80RSB2 T15 TMS T16 GND Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-33 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function A1 GND C6 GAC1/IO05RSB0 E11 VCCIB0 A2 GAA0/IO00RSB0 C7 IO17RSB0 E12 VMV1 A3 GAA1/IO01RSB0 C8 IO25RSB0 E13 GBC2/IO62PDB1 A4 GAB0/IO02RSB0 C9 IO33RSB0 E14 IO63NPB1 A5 IO12RSB0 C10 IO38RSB0 E15 IO64PPB1 A6 IO14RSB0 C11 IO42RSB0 E16 IO65NDB1 A7 IO19RSB0 C12 GBC0/IO54RSB0 F1 IO154PSB3 A8 IO26RSB0 C13 IO52RSB0 F2 IO162PPB3 A9 IO31RSB0 C14 IO51RSB0 F3 IO164PDB3 A10 IO37RSB0 C15 IO50RSB0 F4 IO164NDB3 A11 IO41RSB0 C16 IO61NPB1 F5 VCCIB3 A12 IO47RSB0 D1 IO166NDB3 F6 GND A13 GBB1/IO57RSB0 D2 IO166PDB3 F7 VCC A14 GBA0/IO58RSB0 D3 GAC2/IO168PDB3 F8 VCC A15 GBA1/IO59RSB0 D4 IO168NDB3 F9 VCC A16 GND D5 GNDQ F10 VCC B1 GAB2/IO169PDB3 D6 IO13RSB0 F11 GND B2 GAA2/IO170PDB3 D7 IO16RSB0 F12 VCCIB1 B3 GNDQ D8 IO22RSB0 F13 IO62NDB1 B4 GAB1/IO03RSB0 D9 IO36RSB0 F14 IO64NPB1 B5 IO10RSB0 D10 IO39RSB0 F15 IO66PPB1 B6 IO15RSB0 D11 IO46RSB0 F16 IO67PPB1 B7 IO18RSB0 D12 GNDQ G1 IO155NDB3 B8 IO24RSB0 D13 IO53RSB0 G2 IO155PDB3 B9 IO32RSB0 D14 GBB2/IO61PPB1 G3 IO162NPB3 B10 IO40RSB0 D15 IO63PPB1 G4 GFC1/IO161PPB3 B11 IO43RSB0 D16 IO65PDB1 G5 VCCIB3 B12 GBC1/IO55RSB0 E1 IO165NDB3 G6 VCC B13 GBB0/IO56RSB0 E2 IO165PDB3 G7 GND B14 IO49RSB0 E3 IO167PDB3 G8 GND B15 GBA2/IO60PDB1 E4 IO167NDB3 G9 GND B16 IO60NDB1 E5 VMV0 G10 GND C1 IO169NDB3 E6 VCCIB0 G11 VCC C2 IO170NDB3 E7 VCCIB0 G12 VCCIB1 C3 VMV3 E8 IO29RSB0 G13 GCC1/IO68PPB1 C4 IO06RSB0 E9 IO30RSB0 G14 IO66NPB1 C5 GAC0/IO04RSB0 E10 VCCIB0 G15 IO67NPB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -3 4 Advanced v0.2 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function G16 IO71NPB1 K5 VCCIB3 M10 VCCIB2 H1 GFB0/IO160NPB3 K6 VCC M11 VCCIB2 H2 GFA0/IO159NDB3 K7 GND M12 VMV2 H3 GFB1/IO160PPB3 K8 GND M13 IO81NDB1 H4 VCOMPLF K9 GND M14 GDB1/IO85PPB1 H5 GFC0/IO161NPB3 K10 GND M15 GDC1/IO84PDB1 H6 VCC K11 VCC M16 IO80NDB1 H7 GND K12 VCCIB1 N1 IO145PDB3 H8 GND K13 IO72NPB1 N2 IO145NDB3 H9 GND K14 IO82PDB1 N3 GEC1/IO144PPB3 H10 GND K15 IO79PDB1 N4 IO137RSB2 H11 VCC K16 IO77NPB1 N5 GNDQ H12 GCC0/IO68NPB1 L1 IO149PDB3 N6 GEA2/IO141RSB2 H13 GCB1/IO69PPB1 L2 IO156NPB3 N7 IO120RSB2 H14 GCA0/IO70NPB1 L3 IO147PDB3 N8 IO113RSB2 H15 IO73NPB1 L4 IO147NDB3 N9 IO106RSB2 H16 GCB0/IO69NPB1 L5 VCCIB3 N10 IO99RSB2 J1 GFA2/IO158PPB3 L6 GND N11 IO94RSB2 J2 GFA1/IO159PDB3 L7 VCC N12 GNDQ J3 VCCPLF L8 VCC N13 IO81PDB1 J4 IO157NDB3 L9 VCC N14 VJTAG J5 GFB2/IO157PDB3 L10 VCC N15 GDC0/IO84NDB1 J6 VCC L11 GND N16 GDA1/IO86PDB1 J7 GND L12 VCCIB1 P1 GEB1/IO143PDB3 J8 GND L13 GDB0/IO85NPB1 P2 GEB0/IO143NDB3 J9 GND L14 IO82NDB1 P3 IO138RSB2 J10 GND L15 IO79NDB1 P4 IO135RSB2 J11 VCC L16 IO80PDB1 P5 IO134RSB2 J12 GCB2/IO72PPB1 M1 IO149NDB3 P6 IO128RSB2 J13 GCA1/IO70PPB1 M2 IO146PDB3 P7 IO121RSB2 J14 GCC2/IO73PPB1 M3 IO146NDB3 P8 IO115RSB2 J15 IO77PPB1 M4 GEC0/IO144NPB3 P9 IO108RSB2 J16 GCA2/IO71PPB1 M5 VMV3 P10 IO100RSB2 K1 GFC2/IO156PPB3 M6 VCCIB2 P11 IO95RSB2 K2 IO158NPB3 M7 VCCIB2 P12 VMV1 K3 IO151PDB3 M8 IO111RSB2 P13 TCK K4 IO151NDB3 M9 IO110RSB2 P14 VPUMP Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-35 ProASIC3 Flash Family FPGAs 256-Pin FBGA* Pin Number A3P600 Function P15 TRST P16 GDA0/IO86NDB1 R1 GEA1/IO142PDB3 R2 GEA0/IO142NDB3 R3 IO136RSB2 R4 GEC2/IO139RSB2 R5 IO130RSB2 R6 IO125RSB2 R7 IO119RSB2 R8 IO114RSB2 R9 IO107RSB2 R10 IO101RSB2 R11 IO96RSB2 R12 IO90RSB2 R13 GDB2/IO88RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO133RSB2 T3 GEB2/IO140RSB2 T4 IO132RSB2 T5 IO127RSB2 T6 IO123RSB2 T7 IO117RSB2 T8 IO112RSB2 T9 IO109RSB2 T10 IO102RSB2 T11 IO97RSB2 T12 GDC2/IO89RSB2 T13 IO91RSB2 T14 GDA2/IO87RSB2 T15 TMS T16 GND Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -3 6 Advanced v0.2 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function A1 GND C6 GAC1/IO05RSB0 E11 VCCIB0 A2 GAA0/IO00RSB0 C7 IO27RSB0 E12 VMV1 A3 GAA1/IO01RSB0 C8 IO33RSB0 E13 GBC2/IO80PDB1 A4 GAB0/IO02RSB0 C9 IO43RSB0 E14 IO79NDB1 A5 IO17RSB0 C10 IO51RSB0 E15 IO83PDB1 A6 IO22RSB0 C11 IO58RSB0 E16 IO83NDB1 A7 IO28RSB0 C12 GBC0/IO72RSB0 F1 IO210NDB3 A8 IO34RSB0 C13 IO70RSB0 F2 IO211NDB3 A9 IO44RSB0 C14 IO71RSB0 F3 IO211PDB3 A10 IO50RSB0 C15 IO81PDB1 F4 IO216NDB3 A11 IO56RSB0 C16 IO81NDB1 F5 VCCIB3 A12 IO62RSB0 D1 IO215NDB3 F6 GND A13 GBB1/IO75RSB0 D2 IO215PDB3 F7 VCC A14 GBA0/IO76RSB0 D3 GAC2/IO217PDB3 F8 VCC A15 GBA1/IO77RSB0 D4 IO217NDB3 F9 VCC A16 GND D5 GNDQ F10 VCC B1 GAB2/IO218PDB3 D6 IO21RSB0 F11 GND B2 GAA2/IO219PDB3 D7 IO25RSB0 F12 VCCIB1 B3 GNDQ D8 IO31RSB0 F13 IO85PDB1 B4 GAB1/IO03RSB0 D9 IO46RSB0 F14 IO85NDB1 B5 IO15RSB0 D10 IO53RSB0 F15 IO86PDB1 B6 IO20RSB0 D11 IO59RSB0 F16 IO86NDB1 B7 IO26RSB0 D12 GNDQ G1 IO200PSB3 B8 IO35RSB0 D13 IO80NDB1 G2 IO208NDB3 B9 IO45RSB0 D14 GBB2/IO79PDB1 G3 IO208PDB3 B10 IO52RSB0 D15 IO82PDB1 G4 GFC1/IO206PPB3 B11 IO57RSB0 D16 IO82NDB1 G5 VCCIB3 B12 GBC1/IO73RSB0 E1 IO210PDB3 G6 VCC B13 GBB0/IO74RSB0 E2 IO213NDB3 G7 GND B14 IO69RSB0 E3 IO213PDB3 G8 GND B15 GBA2/IO78PDB1 E4 IO216PDB3 G9 GND B16 IO78NDB1 E5 VMV0 G10 GND C1 IO218NDB3 E6 VCCIB0 G11 VCC C2 IO219NDB3 E7 VCCIB0 G12 VCCIB1 C3 VMV3 E8 IO38RSB0 G13 GCC1/IO88PPB1 C4 IO06RSB0 E9 IO47RSB0 G14 IO87PDB1 C5 GAC0/IO04RSB0 E10 VCCIB0 G15 IO87NDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-37 ProASIC3 Flash Family FPGAs 256-Pin FBGA* 256-Pin FBGA* 256-Pin FBGA* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function G16 IO94PSB1 K5 VCCIB3 M10 VCCIB2 H1 GFB0/IO205NPB3 K6 VCC M11 VCCIB2 H2 GFA0/IO204NDB3 K7 GND M12 VMV2 H3 GFB1/IO205PPB3 K8 GND M13 IO107PDB1 H4 VCOMPLF K9 GND M14 GDB1/IO109PPB1 H5 GFC0/IO206NPB3 K10 GND M15 GDC1/IO108PDB1 H6 VCC K11 VCC M16 IO106PSB1 H7 GND K12 VCCIB1 N1 IO191NDB3 H8 GND K13 IO92NPB1 N2 IO188PPB3 H9 GND K14 IO100NDB1 N3 GEC1/IO187PPB3 H10 GND K15 IO100PDB1 N4 IO188NPB3 H11 VCC K16 IO102PDB1 N5 GNDQ H12 GCC0/IO88NPB1 L1 IO195PDB3 N6 GEA2/IO184RSB2 H13 GCB1/IO89PPB1 L2 IO195NDB3 N7 IO153RSB2 H14 GCA0/IO90NPB1 L3 IO194PDB3 N8 IO146RSB2 H15 IO91NPB1 L4 IO194NDB3 N9 IO134RSB2 H16 GCB0/IO89NPB1 L5 VCCIB3 N10 IO126RSB2 J1 GFA2/IO203PPB3 L6 GND N11 IO121RSB2 J2 GFA1/IO204PDB3 L7 VCC N12 GNDQ J3 VCCPLF L8 VCC N13 IO107NDB1 J4 IO202NDB3 L9 VCC N14 VJTAG J5 GFB2/IO202PDB3 L10 VCC N15 GDC0/IO108NDB1 J6 VCC L11 GND N16 GDA1/IO110PDB1 J7 GND L12 VCCIB1 P1 GEB1/IO186PDB3 J8 GND L13 GDB0/IO109NPB1 P2 GEB0/IO186NDB3 J9 GND L14 IO103NDB1 P3 IO181RSB2 J10 GND L15 IO103PDB1 P4 IO178RSB2 J11 VCC L16 IO102NDB1 P5 IO166RSB2 J12 GCB2/IO92PPB1 M1 IO191PDB3 P6 IO159RSB2 J13 GCA1/IO90PPB1 M2 IO190PDB3 P7 IO154RSB2 J14 GCC2/IO93PDB1 M3 IO190NDB3 P8 IO148RSB2 J15 IO93NDB1 M4 GEC0/IO187NPB3 P9 IO138RSB2 J16 GCA2/IO91PPB1 M5 VMV3 P10 IO131RSB2 K1 GFC2/IO201PSB3 M6 VCCIB2 P11 IO124RSB2 K2 IO203NPB3 M7 VCCIB2 P12 VMV1 K3 IO197PDB3 M8 IO144RSB2 P13 TCK K4 IO197NDB3 M9 IO133RSB2 P14 VPUMP Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -3 8 Advanced v0.2 ProASIC3 Flash Family FPGAs 256-Pin FBGA* Pin Number A3P1000 Function P15 TRST P16 GDA0/IO110NDB1 R1 GEA1/IO185PDB3 R2 GEA0/IO185NDB3 R3 IO177RSB2 R4 GEC2/IO182RSB2 R5 IO167RSB2 R6 IO160RSB2 R7 IO155RSB2 R8 IO150RSB2 R9 IO139RSB2 R10 IO130RSB2 R11 IO127RSB2 R12 IO119RSB2 R13 GDB2/IO112RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO176RSB2 T3 GEB2/IO183RSB2 T4 IO170RSB2 T5 IO164RSB2 T6 IO158RSB2 T7 IO152RSB2 T8 IO145RSB2 T9 IO137RSB2 T10 IO132RSB2 T11 IO125RSB2 T12 GDC2/IO113RSB2 T13 IO117RSB2 T14 GDA2/IO111RSB2 T15 TMS T16 GND Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-39 ProASIC3 Flash Family FPGAs 484-Pin FBGA A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 4 -4 0 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function A1 GND B15 NC D7 GAB0/IO02RSB0 A2 GND B16 NC D8 IO14RSB0 A3 VCCIB0 B17 NC D9 IO18RSB0 A4 NC B18 NC D10 IO22RSB0 A5 NC B19 NC D11 IO27RSB0 A6 IO13RSB0 B20 NC D12 IO30RSB0 A7 IO17RSB0 B21 VCCIB1 D13 IO39RSB0 A8 NC B22 GND D14 IO41RSB0 A9 NC C1 VCCIB3 D15 IO46RSB0 A10 IO23RSB0 C2 NC D16 GBB1/IO57RSB0 A11 IO29RSB0 C3 NC D17 GBA0/IO58RSB0 A12 IO34RSB0 C4 NC D18 GBA1/IO59RSB0 A13 IO36RSB0 C5 GND D19 GND A14 NC C6 NC D20 NC A15 NC C7 NC D21 NC A16 IO45RSB0 C8 VCC D22 NC A17 IO47RSB0 C9 VCC E1 NC A18 NC C10 NC E2 NC A19 NC C11 NC E3 GND A20 VCCIB0 C12 NC E4 GAB2/IO154PDB3 A21 GND C13 NC E5 GAA2/IO155PPB3 A22 GND C14 VCC E6 IO10RSB0 B1 GND C15 VCC E7 GAB1/IO03RSB0 B2 VCCIB3 C16 NC E8 IO12RSB0 B3 NC C17 NC E9 IO16RSB0 B4 NC C18 GND E10 IO21RSB0 B5 NC C19 NC E11 IO26RSB0 B6 NC C20 NC E12 IO31RSB0 B7 NC C21 NC E13 IO37RSB0 B8 NC C22 VCCIB1 E14 IO42RSB0 B9 NC D1 NC E15 GBC1/IO55RSB0 B10 NC D2 NC E16 GBB0/IO56RSB0 B11 NC D3 NC E17 IO48RSB0 B12 NC D4 GND E18 GBA2/IO60PPB1 B13 NC D5 GAA0/IO00RSB0 E19 IO50RSB0 B14 NC D6 GAA1/IO01RSB0 E20 GND Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-41 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function E21 NC G13 IO40RSB0 J5 IO150PPB3 E22 NC G14 IO43RSB0 J6 NC F1 NC G15 GNDQ J7 IO148PPB3 F2 NC G16 IO49RSB0 J8 VCCIB3 F3 NC G17 GBB2/IO61PDB1 J9 GND F4 IO154NDB3 G18 IO63NDB1 J10 VCC F5 IO08RSB0 G19 IO64NDB1 J11 VCC F6 IO07RSB0 G20 NC J12 VCC F7 IO06RSB0 G21 NC J13 VCC F8 GAC0/IO04RSB0 G22 NC J14 GND F9 GAC1/IO05RSB0 H1 NC J15 VCCIB1 F10 IO20RSB0 H2 NC J16 IO62NDB1 F11 IO25RSB0 H3 VCC J17 NC F12 IO32RSB0 H4 IO151PDB3 J18 IO65RSB1 F13 IO38RSB0 H5 IO152PPB3 J19 IO73NDB1 F14 IO44RSB0 H6 IO153NDB3 J20 NC F15 GBC0/IO54RSB0 H7 IO11RSB0 J21 NC F16 IO51RSB0 H8 VMV0 J22 NC F17 IO52RSB0 H9 VCCIB0 K1 NC F18 IO53RSB0 H10 VCCIB0 K2 NC F19 IO60NPB1 H11 IO28RSB0 K3 NC F20 NC H12 IO35RSB0 K4 IO150NPB3 F21 NC H13 VCCIB0 K5 IO149PDB3 F22 NC H14 VCCIB0 K6 IO149NDB3 G1 NC H15 VMV1 K7 GFC1/IO147PPB3 G2 NC H16 GBC2/IO62PDB1 K8 VCCIB3 G3 NC H17 IO61NDB1 K9 VCC G4 IO152NPB3 H18 IO63PDB1 K10 GND G5 IO155NPB3 H19 IO64PDB1 K11 GND G6 GAC2/IO153PDB3 H20 VCC K12 GND G7 IO09RSB0 H21 NC K13 GND G8 GNDQ H22 NC K14 VCC G9 IO15RSB0 J1 NC K15 VCCIB1 G10 IO19RSB0 J2 NC K16 GCC1/IO67PPB1 G11 IO24RSB0 J3 NC K17 IO66NDB1 G12 IO33RSB0 J4 IO151NDB3 K18 IO66PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -4 2 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function K19 IO73PDB1 M11 GND P3 NC K20 NC M12 GND P4 IO142NDB3 K21 NC M13 GND P5 IO140NDB3 K22 NC M14 VCC P6 IO139RSB3 L1 NC M15 GCB2/IO71PPB1 P7 IO138NDB3 L2 NC M16 GCA1/IO69PPB1 P8 VCCIB3 L3 NC M17 GCC2/IO72PDB1 P9 GND L4 GFB0/IO146NPB3 M18 NC P10 VCC L5 GFA0/IO145NDB3 M19 GCA2/IO70PDB1 P11 VCC L6 GFB1/IO146PPB3 M20 NC P12 VCC L7 VCOMPLF M21 NC P13 VCC L8 GFC0/IO147NPB3 M22 NC P14 GND L9 VCC N1 NC P15 VCCIB1 L10 GND N2 NC P16 GDB0/IO78NPB1 L11 GND N3 NC P17 IO75NDB1 L12 GND N4 GFC2/IO142PDB3 P18 IO75PDB1 L13 GND N5 IO144NPB3 P19 IO76PDB1 L14 VCC N6 IO143NPB3 P20 NC L15 GCC0/IO67NPB1 N7 IO138PDB3 P21 NC L16 GCB1/IO68PPB1 N8 VCCIB3 P22 NC L17 GCA0/IO69NPB1 N9 VCC R1 NC L18 NC N10 GND R2 NC L19 GCB0/IO68NPB1 N11 GND R3 VCC L20 NC N12 GND R4 IO141NDB3 L21 NC N13 GND R5 IO140PDB3 L22 NC N14 VCC R6 IO127RSB2 M1 NC N15 VCCIB1 R7 GEC0/IO137NPB3 M2 NC N16 IO71NPB1 R8 VMV3 M3 NC N17 IO72NDB1 R9 VCCIB2 M4 GFA2/IO144PPB3 N18 IO74RSB1 R10 VCCIB2 M5 GFA1/IO145PDB3 N19 IO70NDB1 R11 IO106RSB2 M6 VCCPLF N20 NC R12 IO99RSB2 M7 IO148NPB3 N21 NC R13 VCCIB2 M8 GFB2/IO143PPB3 N22 NC R14 VCCIB2 M9 VCC P1 NC R15 VMV2 M10 GND P2 NC R16 IO85RSB2 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-43 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function R17 GDB1/IO78PPB1 U9 IO121RSB2 W1 NC R18 GDC1/IO77PDB1 U10 IO115RSB2 W2 NC R19 IO76NDB1 U11 IO108RSB2 W3 NC R20 VCC U12 IO101RSB2 W4 GND R21 NC U13 IO94RSB2 W5 IO124RSB2 R22 NC U14 IO88RSB2 W6 GEB2/IO133RSB2 T1 NC U15 IO84RSB2 W7 IO123RSB2 T2 NC U16 TCK W8 IO120RSB2 T3 NC U17 VPUMP W9 IO116RSB2 T4 IO141PDB3 U18 TRST W10 IO111RSB2 T5 IO131RSB2 U19 GDA0/IO79NDB1 W11 IO105RSB2 T6 GEC1/IO137PPB3 U20 NC W12 IO103RSB2 T7 IO128RSB2 U21 NC W13 IO97RSB2 T8 GNDQ U22 NC W14 IO93RSB2 T9 GEA2/IO134RSB2 V1 NC W15 GDC2/IO82RSB2 T10 IO113RSB2 V2 NC W16 IO86RSB2 T11 IO109RSB2 V3 GND W17 GDA2/IO80RSB2 T12 IO100RSB2 V4 GEA1/IO135PDB3 W18 TMS T13 IO95RSB2 V5 GEA0/IO135NDB3 W19 GND T14 IO90RSB2 V6 IO125RSB2 W20 NC T15 GNDQ V7 GEC2/IO132RSB2 W21 NC T16 IO83RSB2 V8 IO122RSB2 W22 NC T17 VJTAG V9 IO118RSB2 Y1 VCCIB3 T18 GDC0/IO77NDB1 V10 IO112RSB2 Y2 NC T19 GDA1/IO79PDB1 V11 IO107RSB2 Y3 NC T20 NC V12 IO102RSB2 Y4 NC T21 NC V13 IO96RSB2 Y5 GND T22 NC V14 IO91RSB2 Y6 NC U1 NC V15 IO87RSB2 Y7 NC U2 NC V16 GDB2/IO81RSB2 Y8 VCC U3 NC V17 TDI Y9 VCC U4 GEB1/IO136PDB3 V18 NC Y10 NC U5 GEB0/IO136NDB3 V19 TDO Y11 NC U6 IO130RSB2 V20 GND Y12 NC U7 IO129RSB2 V21 NC Y13 NC U8 IO126RSB2 V22 NC Y14 VCC Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -4 4 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P400 Function Pin Number A3P400 Function Y15 VCC AB7 IO117RSB2 Y16 NC AB8 IO114RSB2 Y17 NC AB9 IO110RSB2 Y18 GND AB10 NC Y19 NC AB11 NC Y20 NC AB12 IO104RSB2 Y21 NC AB13 IO98RSB2 Y22 VCCIB1 AB14 NC AA1 GND AB15 NC AA2 VCCIB3 AB16 IO92RSB2 AA3 NC AB17 IO89RSB2 AA4 NC AB18 NC AA5 NC AB19 NC AA6 NC AB20 VCCIB2 AA7 NC AB21 GND AA8 NC AB22 GND AA9 NC AA10 NC AA11 NC AA12 NC AA13 NC AA14 NC AA15 NC AA16 NC AA17 NC AA18 NC AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 NC AB5 NC AB6 IO119RSB2 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-45 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function A1 GND B15 NC D7 GAB0/IO02RSB0 A2 GND B16 IO44RSB0 D8 IO12RSB0 A3 VCCIB0 B17 IO48RSB0 D9 IO14RSB0 A4 NC B18 NC D10 IO19RSB0 A5 NC B19 NC D11 IO26RSB0 A6 IO08RSB0 B20 NC D12 IO31RSB0 A7 IO09RSB0 B21 VCCIB1 D13 IO37RSB0 A8 NC B22 GND D14 IO41RSB0 A9 NC C1 VCCIB3 D15 IO47RSB0 A10 IO21RSB0 C2 NC D16 GBB1/IO57RSB0 A11 IO23RSB0 C3 NC D17 GBA0/IO58RSB0 A12 IO27RSB0 C4 NC D18 GBA1/IO59RSB0 A13 IO28RSB0 C5 GND D19 GND A14 NC C6 NC D20 NC A15 NC C7 NC D21 NC A16 IO35RSB0 C8 VCC D22 NC A17 IO45RSB0 C9 VCC E1 NC A18 NC C10 NC E2 NC A19 NC C11 NC E3 GND A20 VCCIB0 C12 NC E4 GAB2/IO169PDB3 A21 GND C13 NC E5 GAA2/IO170PDB3 A22 GND C14 VCC E6 GNDQ B1 GND C15 VCC E7 GAB1/IO03RSB0 B2 VCCIB3 C16 NC E8 IO10RSB0 B3 NC C17 NC E9 IO15RSB0 B4 NC C18 GND E10 IO18RSB0 B5 NC C19 NC E11 IO24RSB0 B6 IO07RSB0 C20 NC E12 IO32RSB0 B7 IO11RSB0 C21 NC E13 IO40RSB0 B8 NC C22 VCCIB1 E14 IO43RSB0 B9 NC D1 NC E15 GBC1/IO55RSB0 B10 IO20RSB0 D2 NC E16 GBB0/IO56RSB0 B11 NC D3 NC E17 IO49RSB0 B12 NC D4 GND E18 GBA2/IO60PDB1 B13 IO34RSB0 D5 GAA0/IO00RSB0 E19 IO60NDB1 B14 NC D6 GAA1/IO01RSB0 E20 GND Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -4 6 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function E21 NC G13 IO39RSB0 J5 IO162PPB3 E22 NC G14 IO46RSB0 J6 IO164PDB3 F1 NC G15 GNDQ J7 IO164NDB3 F2 NC G16 IO53RSB0 J8 VCCIB3 F3 NC G17 GBB2/IO61PPB1 J9 GND F4 IO169NDB3 G18 IO63PPB1 J10 VCC F5 IO170NDB3 G19 IO65PDB1 J11 VCC F6 VMV3 G20 NC J12 VCC F7 IO06RSB0 G21 NC J13 VCC F8 GAC0/IO04RSB0 G22 NC J14 GND F9 GAC1/IO05RSB0 H1 NC J15 VCCIB1 F10 IO17RSB0 H2 NC J16 IO62NDB1 F11 IO25RSB0 H3 VCC J17 IO64NPB1 F12 IO33RSB0 H4 IO165NDB3 J18 IO66PPB1 F13 IO38RSB0 H5 IO165PDB3 J19 IO67PPB1 F14 IO42RSB0 H6 IO167PDB3 J20 NC F15 GBC0/IO54RSB0 H7 IO167NDB3 J21 IO74PDB1 F16 IO52RSB0 H8 VMV0 J22 IO74NDB1 F17 IO51RSB0 H9 VCCIB0 K1 IO153NDB3 F18 IO50RSB0 H10 VCCIB0 K2 NC F19 IO61NPB1 H11 IO29RSB0 K3 NC F20 NC H12 IO30RSB0 K4 IO155NDB3 F21 NC H13 VCCIB0 K5 IO155PDB3 F22 NC H14 VCCIB0 K6 IO162NPB3 G1 IO163NDB3 H15 VMV1 K7 GFC1/IO161PPB3 G2 IO163PDB3 H16 GBC2/IO62PDB1 K8 VCCIB3 G3 NC H17 IO63NPB1 K9 VCC G4 IO166NDB3 H18 IO64PPB1 K10 GND G5 IO166PDB3 H19 IO65NDB1 K11 GND G6 GAC2/IO168PDB3 H20 VCC K12 GND G7 IO168NDB3 H21 NC K13 GND G8 GNDQ H22 NC K14 VCC G9 IO13RSB0 J1 IO153PDB3 K15 VCCIB1 G10 IO16RSB0 J2 IO154NDB3 K16 GCC1/IO68PPB1 G11 IO22RSB0 J3 NC K17 IO66NPB1 G12 IO36RSB0 J4 IO154PDB3 K18 IO67NPB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-47 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function K19 IO71NPB1 M11 GND P3 NC K20 NC M12 GND P4 IO149PDB3 K21 NC M13 GND P5 IO156NPB3 K22 IO75PDB1 M14 VCC P6 IO147PDB3 L1 NC M15 GCB2/IO72PPB1 P7 IO147NDB3 L2 IO152PDB3 M16 GCA1/IO70PPB1 P8 VCCIB3 L3 NC M17 GCC2/IO73PPB1 P9 GND L4 GFB0/IO160NPB3 M18 IO77PPB1 P10 VCC L5 GFA0/IO159NDB3 M19 GCA2/IO71PPB1 P11 VCC L6 GFB1/IO160PPB3 M20 NC P12 VCC L7 VCOMPLF M21 IO76PDB1 P13 VCC L8 GFC0/IO161NPB3 M22 NC P14 GND L9 VCC N1 IO150PPB3 P15 VCCIB1 L10 GND N2 NC P16 GDB0/IO85NPB1 L11 GND N3 NC P17 IO82NDB1 L12 GND N4 GFC2/IO156PPB3 P18 IO79NDB1 L13 GND N5 IO158NPB3 P19 IO80PDB1 L14 VCC N6 IO151PDB3 P20 NC L15 GCC0/IO68NPB1 N7 IO151NDB3 P21 NC L16 GCB1/IO69PPB1 N8 VCCIB3 P22 IO78PDB1 L17 GCA0/IO70NPB1 N9 VCC R1 NC L18 IO73NPB1 N10 GND R2 IO148PDB3 L19 GCB0/IO69NPB1 N11 GND R3 VCC L20 NC N12 GND R4 IO149NDB3 L21 NC N13 GND R5 IO146PDB3 L22 IO75NDB1 N14 VCC R6 IO146NDB3 M1 NC N15 VCCIB1 R7 GEC0/IO144NPB3 M2 IO152NDB3 N16 IO72NPB1 R8 VMV3 M3 NC N17 IO82PDB1 R9 VCCIB2 M4 GFA2/IO158PPB3 N18 IO79PDB1 R10 VCCIB2 M5 GFA1/IO159PDB3 N19 IO77NPB1 R11 IO111RSB2 M6 VCCPLF N20 NC R12 IO110RSB2 M7 IO157NDB3 N21 IO76NDB1 R13 VCCIB2 M8 GFB2/IO157PDB3 N22 NC R14 VCCIB2 M9 VCC P1 NC R15 VMV2 M10 GND P2 IO150NPB3 R16 IO81NDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -4 8 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function R17 GDB1/IO85PPB1 U9 IO128RSB2 W1 NC R18 GDC1/IO84PDB1 U10 IO121RSB2 W2 NC R19 IO80NDB1 U11 IO115RSB2 W3 NC R20 VCC U12 IO108RSB2 W4 GND R21 IO83PDB1 U13 IO100RSB2 W5 IO133RSB2 R22 IO78NDB1 U14 IO95RSB2 W6 GEB2/IO140RSB2 T1 NC U15 VMV1 W7 IO132RSB2 T2 IO148NDB3 U16 TCK W8 IO127RSB2 T3 NC U17 VPUMP W9 IO123RSB2 T4 IO145PDB3 U18 TRST W10 IO117RSB2 T5 IO145NDB3 U19 GDA0/IO86NDB1 W11 IO112RSB2 T6 GEC1/IO144PPB3 U20 NC W12 IO109RSB2 T7 IO137RSB2 U21 NC W13 IO102RSB2 T8 GNDQ U22 NC W14 IO97RSB2 T9 GEA2/IO141RSB2 V1 NC W15 GDC2/IO89RSB2 T10 IO120RSB2 V2 NC W16 IO91RSB2 T11 IO113RSB2 V3 GND W17 GDA2/IO87RSB2 T12 IO106RSB2 V4 GEA1/IO142PDB3 W18 TMS T13 IO99RSB2 V5 GEA0/IO142NDB3 W19 GND T14 IO94RSB2 V6 IO136RSB2 W20 NC T15 GNDQ V7 GEC2/IO139RSB2 W21 NC T16 IO81PDB1 V8 IO130RSB2 W22 NC T17 VJTAG V9 IO125RSB2 Y1 VCCIB3 T18 GDC0/IO84NDB1 V10 IO119RSB2 Y2 NC T19 GDA1/IO86PDB1 V11 IO114RSB2 Y3 NC T20 NC V12 IO107RSB2 Y4 NC T21 IO83NDB1 V13 IO101RSB2 Y5 GND T22 NC V14 IO96RSB2 Y6 NC U1 NC V15 IO90RSB2 Y7 NC U2 NC V16 GDB2/IO88RSB2 Y8 VCC U3 NC V17 TDI Y9 VCC U4 GEB1/IO143PDB3 V18 GNDQ Y10 NC U5 GEB0/IO143NDB3 V19 TDO Y11 NC U6 IO138RSB2 V20 GND Y12 NC U7 IO135RSB2 V21 NC Y13 NC U8 IO134RSB2 V22 NC Y14 VCC Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-49 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P600 Function Pin Number A3P600 Function Y15 VCC AB7 IO124RSB2 Y16 NC AB8 IO122RSB2 Y17 NC AB9 IO118RSB2 Y18 GND AB10 NC Y19 NC AB11 NC Y20 NC AB12 IO105RSB2 Y21 NC AB13 IO104RSB2 Y22 VCCIB1 AB14 NC AA1 GND AB15 NC AA2 VCCIB3 AB16 IO98RSB2 AA3 NC AB17 IO92RSB2 AA4 NC AB18 NC AA5 NC AB19 NC AA6 IO131RSB2 AB20 VCCIB2 AA7 IO126RSB2 AB21 GND AA8 NC AB22 GND AA9 NC AA10 IO116RSB2 AA11 NC AA12 NC AA13 IO103RSB2 AA14 NC AA15 NC AA16 IO93RSB2 AA17 NC AA18 NC AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 NC AB5 NC AB6 IO129RSB2 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -5 0 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function A1 GND AA15 NC B7 IO14RSB0 A2 GND AA16 IO118RSB2 B8 IO18RSB0 A3 VCCIB0 AA17 IO115RSB2 B9 IO23RSB0 A4 IO08RSB0 AA18 NC B10 IO30RSB0 A5 IO10RSB0 AA19 NC B11 IO37RSB0 A6 IO12RSB0 AA20 NC B12 IO41RSB0 A7 IO16RSB0 AA21 VCCIB1 B13 IO49RSB0 A8 IO19RSB0 AA22 GND B14 IO55RSB0 A9 IO24RSB0 AB1 GND B15 IO61RSB0 A10 IO32RSB0 AB2 GND B16 IO64RSB0 A11 IO39RSB0 AB3 VCCIB2 B17 IO66RSB0 A12 IO40RSB0 AB4 IO175RSB2 B18 IO68RSB0 A13 IO48RSB0 AB5 IO172RSB2 B19 NC A14 IO54RSB0 AB6 IO168RSB2 B20 NC A15 IO60RSB0 AB7 IO163RSB2 B21 VCCIB1 A16 IO63RSB0 AB8 IO161RSB2 B22 GND A17 IO65RSB0 AB9 IO156RSB2 C1 VCCIB3 A18 IO67RSB0 AB10 IO147RSB2 C2 NC A19 NC AB11 IO141RSB2 C3 NC A20 VCCIB0 AB12 IO140RSB2 C4 NC A21 GND AB13 IO128RSB2 C5 GND A22 GND AB14 IO123RSB2 C6 NC AA1 GND AB15 IO122RSB2 C7 IO13RSB0 AA2 VCCIB3 AB16 IO120RSB2 C8 VCC AA3 NC AB17 IO116RSB2 C9 VCC AA4 IO179RSB2 AB18 IO114RSB2 C10 IO29RSB0 AA5 IO174RSB2 AB19 NC C11 IO36RSB0 AA6 IO171RSB2 AB20 VCCIB2 C12 IO42RSB0 AA7 IO165RSB2 AB21 GND C13 NC AA8 IO162RSB2 AB22 GND C14 VCC AA9 IO157RSB2 B1 GND C15 VCC AA10 IO149RSB2 B2 VCCIB3 C16 NC AA11 IO142RSB2 B3 NC C17 NC AA12 IO135RSB2 B4 IO07RSB0 C18 GND AA13 IO129RSB2 B5 IO09RSB0 C19 NC AA14 NC B6 IO11RSB0 C20 NC Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-51 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function C21 NC E13 IO52RSB0 G5 IO215PDB3 C22 VCCIB1 E14 IO57RSB0 G6 GAC2/IO217PDB3 D1 NC E15 GBC1/IO73RSB0 G7 IO217NDB3 D2 NC E16 GBB0/IO74RSB0 G8 GNDQ D3 NC E17 IO69RSB0 G9 IO21RSB0 D4 GND E18 GBA2/IO78PDB1 G10 IO25RSB0 D5 GAA0/IO00RSB0 E19 IO78NDB1 G11 IO31RSB0 D6 GAA1/IO01RSB0 E20 GND G12 IO46RSB0 D7 GAB0/IO02RSB0 E21 NC G13 IO53RSB0 D8 IO17RSB0 E22 NC G14 IO59RSB0 D9 IO22RSB0 F1 NC G15 GNDQ D10 IO28RSB0 F2 IO214NDB3 G16 IO80NDB1 D11 IO34RSB0 F3 IO214PDB3 G17 GBB2/IO79PDB1 D12 IO44RSB0 F4 IO218NDB3 G18 IO82PDB1 D13 IO50RSB0 F5 IO219NDB3 G19 IO82NDB1 D14 IO56RSB0 F6 VMV3 G20 IO84PDB1 D15 IO62RSB0 F7 IO06RSB0 G21 IO84NDB1 D16 GBB1/IO75RSB0 F8 GAC0/IO04RSB0 G22 NC D17 GBA0/IO76RSB0 F9 GAC1/IO05RSB0 H1 NC D18 GBA1/IO77RSB0 F10 IO27RSB0 H2 NC D19 GND F11 IO33RSB0 H3 VCC D20 NC F12 IO43RSB0 H4 IO210PDB3 D21 NC F13 IO51RSB0 H5 IO213NDB3 D22 NC F14 IO58RSB0 H6 IO213PDB3 E1 NC F15 GBC0/IO72RSB0 H7 IO216PDB3 E2 NC F16 IO70RSB0 H8 VMV0 E3 GND F17 IO71RSB0 H9 VCCIB0 E4 GAB2/IO218PDB3 F18 IO81PDB1 H10 VCCIB0 E5 GAA2/IO219PDB3 F19 IO81NDB1 H11 IO38RSB0 E6 GNDQ F20 NC H12 IO47RSB0 E7 GAB1/IO03RSB0 F21 NC H13 VCCIB0 E8 IO15RSB0 F22 NC H14 VCCIB0 E9 IO20RSB0 G1 IO212NDB3 H15 VMV1 E10 IO26RSB0 G2 IO212PDB3 H16 GBC2/IO80PDB1 E11 IO35RSB0 G3 NC H17 IO79NDB1 E12 IO45RSB0 G4 IO215NDB3 H18 IO83PDB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -5 2 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function H19 IO83NDB1 K11 GND M3 IO201NPB3 H20 VCC K12 GND M4 GFA2/IO203PPB3 H21 NC K13 GND M5 GFA1/IO204PDB3 H22 NC K14 VCC M6 VCCPLF J1 IO209NDB3 K15 VCCIB1 M7 IO202NDB3 J2 IO209PDB3 K16 GCC1/IO88PPB1 M8 GFB2/IO202PDB3 J3 NC K17 IO87PDB1 M9 VCC J4 IO210NDB3 K18 IO87NDB1 M10 GND J5 IO211NDB3 K19 IO94PDB1 M11 GND J6 IO211PDB3 K20 IO94NDB1 M12 GND J7 IO216NDB3 K21 NC M13 GND J8 VCCIB3 K22 IO97PDB1 M14 VCC J9 GND L1 NC M15 GCB2/IO92PPB1 J10 VCC L2 IO199PDB3 M16 GCA1/IO90PPB1 J11 VCC L3 IO200NPB3 M17 GCC2/IO93PDB1 J12 VCC L4 GFB0/IO205NPB3 M18 IO93NDB1 J13 VCC L5 GFA0/IO204NDB3 M19 GCA2/IO91PPB1 J14 GND L6 GFB1/IO205PPB3 M20 IO98PDB1 J15 VCCIB1 L7 VCOMPLF M21 IO98NDB1 J16 IO85PDB1 L8 GFC0/IO206NPB3 M22 NC J17 IO85NDB1 L9 VCC N1 IO198PDB3 J18 IO86PDB1 L10 GND N2 IO198NDB3 J19 IO86NDB1 L11 GND N3 NC J20 NC L12 GND N4 GFC2/IO201PPB3 J21 IO95PDB1 L13 GND N5 IO203NPB3 J22 IO95NDB1 L14 VCC N6 IO197PDB3 K1 IO207NDB3 L15 GCC0/IO88NPB1 N7 IO197NDB3 K2 IO207PDB3 L16 GCB1/IO89PPB1 N8 VCCIB3 K3 NC L17 GCA0/IO90NPB1 N9 VCC K4 IO200PPB3 L18 IO91NPB1 N10 GND K5 IO208NDB3 L19 GCB0/IO89NPB1 N11 GND K6 IO208PDB3 L20 IO96PDB1 N12 GND K7 GFC1/IO206PPB3 L21 IO96NDB1 N13 GND K8 VCCIB3 L22 IO97NDB1 N14 VCC K9 VCC M1 NC N15 VCCIB1 K10 GND M2 IO199NDB3 N16 IO92NPB1 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-53 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function N17 IO100NDB1 R9 VCCIB2 U1 IO192NPB3 N18 IO100PDB1 R10 VCCIB2 U2 IO189PDB3 N19 IO102PDB1 R11 IO144RSB2 U3 IO189NDB3 N20 NC R12 IO133RSB2 U4 GEB1/IO186PDB3 N21 IO101PDB1 R13 VCCIB2 U5 GEB0/IO186NDB3 N22 IO99PDB1 R14 VCCIB2 U6 IO181RSB2 P1 NC R15 VMV2 U7 IO178RSB2 P2 IO196PDB3 R16 IO107PDB1 U8 IO166RSB2 P3 IO196NDB3 R17 GDB1/IO109PPB1 U9 IO159RSB2 P4 IO195PDB3 R18 GDC1/IO108PDB1 U10 IO154RSB2 P5 IO195NDB3 R19 IO106PPB1 U11 IO148RSB2 P6 IO194PDB3 R20 VCC U12 IO138RSB2 P7 IO194NDB3 R21 IO104NDB1 U13 IO131RSB2 P8 VCCIB3 R22 IO104PDB1 U14 IO124RSB2 P9 GND T1 IO193NPB3 U15 VMV1 P10 VCC T2 IO192PPB3 U16 TCK P11 VCC T3 NC U17 VPUMP P12 VCC T4 IO191NDB3 U18 TRST P13 VCC T5 IO188PPB3 U19 GDA0/IO110NDB1 P14 GND T6 GEC1/IO187PPB3 U20 NC P15 VCCIB1 T7 IO188NPB3 U21 NC P16 GDB0/IO109NPB1 T8 GNDQ U22 IO105NDB1 P17 IO103NDB1 T9 GEA2/IO184RSB2 V1 NC P18 IO103PDB1 T10 IO153RSB2 V2 NC P19 IO102NDB1 T11 IO146RSB2 V3 GND P20 NC T12 IO134RSB2 V4 GEA1/IO185PDB3 P21 IO101NDB1 T13 IO126RSB2 V5 GEA0/IO185NDB3 P22 IO99NDB1 T14 IO121RSB2 V6 IO177RSB2 R1 NC T15 GNDQ V7 GEC2/IO182RSB2 R2 IO193PPB3 T16 IO107NDB1 V8 IO167RSB2 R3 VCC T17 VJTAG V9 IO160RSB2 R4 IO191PDB3 T18 GDC0/IO108NDB1 V10 IO155RSB2 R5 IO190PDB3 T19 GDA1/IO110PDB1 V11 IO150RSB2 R6 IO190NDB3 T20 NC V12 IO139RSB2 R7 GEC0/IO187NPB3 T21 IO106NPB1 V13 IO130RSB2 R8 VMV3 T22 IO105PDB1 V14 IO127RSB2 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. 4 -5 4 Advanced v0.2 ProASIC3 Flash Family FPGAs 484-Pin FBGA* 484-Pin FBGA* Pin Number A3P1000 Function Pin Number A3P1000 Function V15 IO119RSB2 Y7 IO169RSB2 V16 GDB2/IO112RSB2 Y8 VCC V17 TDI Y9 VCC V18 GNDQ Y10 IO151RSB2 V19 TDO Y11 IO143RSB2 V20 GND Y12 IO136RSB2 V21 NC Y13 NC V22 NC Y14 VCC W1 NC Y15 VCC W2 NC Y16 NC W3 NC Y17 NC W4 GND Y18 GND W5 IO176RSB2 Y19 NC W6 GEB2/IO183RSB2 Y20 NC W7 IO170RSB2 Y21 NC W8 IO164RSB2 Y22 VCCIB1 W9 IO158RSB2 W10 IO152RSB2 W11 IO145RSB2 W12 IO137RSB2 W13 IO132RSB2 W14 IO125RSB2 W15 GDC2/IO113RSB2 W16 IO117RSB2 W17 GDA2/IO111RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 NC Y3 NC Y4 IO180RSB2 Y5 GND Y6 IO173RSB2 Note: *Refer to the "User I/O Naming Convention" section on page 2-44. A d v a n c ed v 0.2 4-55 ProASIC3 Flash Family FPGAs Datasheet Information Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Web-only." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. Unmarked (production) This datasheet version contains information that is considered to be final. International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR) The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export can include a release or disclosure to a foreign national inside or outside the United States. A d v a n c ed v 0.2 5-1 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan www.jp.actel.com Actel Hong Kong www.actel.com.cn 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 51700012-1/1.05