KSZ8851-16MLL/MLLI/MLLU
Single-Port Ethernet MAC Controller
with 8-Bit or 16-Bit Non-PCI Interface
Revision 2.3
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • US A • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 12
, 2015
Revision 2.3
General Description
The KSZ8851M-series is a single-port controller chip with
a non-PCI CPU interface and is available in 8-bit and 16-
bit bus des igns. T his datas heet des cribes the 48-pin LQFP
KSZ8851-16MLL for applications requiring high-
performance from a single-port Ethernet controller with an
8-bit or 16-bit generic processor interface. The KSZ8851-
16MLL offers the most cost-effective solution for adding
high-throughput Ethernet connectivity to traditional
embedded systems.
The KSZ88 51-16MLL is a single c hip, mixed analog/digital
device offering wake-on-LAN technology for effectively
addressing fast Ethernet applications. It consists of a fast
Ethernet MAC controller, an 8-bit or 16-bit generic host
processor interface, and incorporates a unique, dynamic
memory pointer with 4-byte buffer boundary and a fully
utilizable 18KB for both TX (allocated 6KB) and RX
(allocated 12KB) direc t ions in the host buffer interface.
The KSZ8851-16MLL is designed to be fully compliant with
the appropriate IEEE 802.3 standards. An industrial
temperature-grade version of the KSZ8851-16MLLI and a
qualified AEC-Q100 automotive version of the KSZ8851-
16MLLU are also available (see the Ordering Information
section).
LinkMD®
Physical signal transmission and reception are enhanced
through the use of analog circuitry. This makes the design
more efficient and allows lower-power consumption. The
KSZ8851-16MLL is designed using a low-power CMOS
process that features a single 3.3V power supply with
options for 1.8V, 2.5V, or 3.3V VDD I/O. The device
includes an extensive feature set that offers management
information base (MIB) counters and CPU control/data
interfaces with single shared data bus timing.
The KSZ8851-16MLL includes a unique cable diagnostics
feature c alled Link MD®. This f eature determ ines the length
of the cabling plant and als o ascertains if there is an open
or short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8851-16MLL
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Datasheets and support documentation are available on
Micrel’s webs ite at: www.micrel.com.
Functional Diagram
Figure 1. KSZ8851-16MLL/MLLI Functional Diagram
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 2 Revision 2.3
Features
• Integrated MAC and PHY Ethernet Controller fully
compliant with IEEE 802.3/802.3µ standards
• Designed for high performance and high throughput
applications
• Supports 10BASE-T/100BASE-TX
• Supports IEEE 802.3x full-duplex flow control and half-
duplex backpressure collision flow control
• Supports DMA-sla ve burs t data read and write transf er s
• Supports IP Header (IPv4)/TCP/UDP/ICMP checksum
generation and checking
• Supports IPv6 TCP/UDP/ICMP checksum generation
and checking
• Automatic 32-bit CRC generation and checking
• Simple SRAM-like host interface easily connects to most
common embedded MCUs.
• Supports multiple data frames for receive without
address bus and b yte-enable signals
• Supports both Big- and Little-Endian processors
• Larger internal memory with 12KB for RX FIFO and 6KB
for TX FIFO. Programmable low, high and overrun
watermark for flow control in RX FIFO
• Shared data bus for Data, Address and Byte Enable
• Efficient architecture design with configurable host
interrupt schemes to minimize host CPU overhead and
utilization
• Powerful and flexible address filtering scheme
• Optional to use external serial EEPROM configuration
for MAC address
• Single 25MHz reference clock for both PHY and MAC
• HBM ESD Rating 6kV
Power Modes, Power Supplies, and Packaging
• Single 3.3V power supply with options for 1.8V, 2.5V
and 3.3V VDD I/O
• Built-in integrated 3.3V or 2.5V to 1.8V low noise
regulator (LDO) for core and analog blocks
• Enhanced power management feature with energy
detect mode and soft power-down mode to ensure low-
power dissipation during device idle periods
• Comprehensive LED indicator support for link, activity
and 10/100 speed (2 LEDs) - User programmable
• Low-power CMOS design
• Commercial Temperature Range: 0°C to +70°C
• Industrial Temperature Range: –40°C to +85°C
• Flexible package options available in 48-pin
• (7mm × 7mm) LQFP KSZ8851-16MLL or 128-p in PQ FP
KSZ8851-16/32MQL
Additional Features
In addition to offering all the features of a Layer 2
controller, the KSZ8851-16MLL of f ers :
• Flexib le 8-bit and 16-bit generic host pr oces s or
interfaces with same access time and single bus timing
to any I/O registers and RX/TX FIFO buffers
• Supports to add two-byte before frame header in order
for IP frame content with double word boundary
• Micrel Link MD® cable diagnostic capabilities to
determine cable length, diagnose faulty cables, and
determine distance to fault
• Wake-on-LAN functionality
− Incorporates Magic Packet™, wake-up frame,
network link state, and detection of energy signal
technology
• HP Auto MDI-X™ crossover with disable/enable option
• Ability to transmit and receive frames up to 2000 bytes
Network Features
• 10BASE-T and 100BASE-TX physical layer support
• Auto-negotiation: 10/1 00 M bps f ull and half duplex
• Adaptive eq uali zer
• Baseline wander correction
Applications
• Video/Audio Distribution Systems
• High-end Cable, Sa tel li te, a nd IP set-top boxes
• Video over IP and IPTV
• Voice over IP (VoIP) and Analog Telephone Adapters
(ATA)
• Industrial Contr o l in Late ncy Crit ical Appl icat ions
• Home Base Station with Ethernet Connection
• Industrial Contr o l Sensor D ev ices (T em per ature,
Pressure, Levels, and Valves)
• Security, Motion Control and Surveillance Cameras
• In-vehicle Diagnostics (OBD) and sof t ware do wnl oad
Markets
• Fast Ethernet
• Embedded Eth er net
• Industrial Eth er net
• Embedded System s
• Automoti ve Ether net
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 3 Revision 2.3
Ordering Information
Part Number Temperature Range Package Lead Finish
KSZ8851-16MLL 0°C to 70°C 48-Pin LQFP Pb-Free
KSZ8851-16MLLI –40°C to +85°C 48-Pin LQFP Pb-Free
KSZ8851-16MLLU
(Automotive AEC-Q100 qualified) –40°C to +85°C 48-Pin LQFP Pb-Free
KSZ8851-16MLL-Eval Evaluation Board for the KSZ8851-16MLL
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 4 Revision 2.3
Revision History
Revision Date Summary of Changes
1.0 06/30/2008 First released Information.
1.1 2/13/2009 Improved EDS Rating up to 6KV, revised Ordering Information and Updated Table content
and description.
2.0 8/31/2009
Change revision ID from “0” to “1” in CIDER (0xc0) register. U pdate pin s 8, 14 and 29
description for 1.8V VDD_IO supply. To add the command write (CMD=1) address index
register in order for software to read back the CMD register value. To enable software read
or write external EEPROM.
2.1
04/30/2012
In 16-bit bus mode, the SD1 bit must set to “1” when CMD = 1 during DMA access. Remove
auto-enqueue function, add the reset circuit. Update the description for the register PMECR
Bits [1,0]. Add KSZ 8851MLLU Automotive part. Add the description for the register TXCR bit
7. Update read/write timing diagram for Asynchronous Cycle. Add power sequence
descriptions in the reset timing section.
2.2
03/04/2014
Remove auto-enqueue function for transmit, Update the description for section of
Asynchronous Interface. Update read/write timing diagram and table, add notes for timing
table ,CIDER and RXFCTR registers. Update the defination for Register P1CR bit [9],
P1MBCR bit [4] and RX/TX pair. Update the description in Half-Duplex Backpressure
section. Change TTL to CMOS and updates min/max I/O voltage in different VDDIO.
2.3 03/12/2015 Update the thermal data f or Ja and Jc.
Update the package picture and contents index.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 5 Revision 2.3
Contents
List of Figures .......................................................................................................................................................................... 8
List of Tables ........................................................................................................................................................................... 9
Pin Configuration ................................................................................................................................................................... 10
Pin Description ...................................................................................................................................................................... 11
Pin for Strap-In Options ......................................................................................................................................................... 14
Functional Description ........................................................................................................................................................... 15
Fuctional Overview ................................................................................................................................................................ 15
Power Manag ement ..................................................................................................................................................... 15
Normal Operation Mode ............................................................................................................................................... 15
Energy Detect Mode ..................................................................................................................................................... 15
Soft Power-Down Mode ................................................................................................................................................ 16
Power-Saving Mode ..................................................................................................................................................... 16
Wake-on-LAN ............................................................................................................................................................... 16
Detection of Energy ...................................................................................................................................................... 16
Detection of Linkup ....................................................................................................................................................... 16
Wake-up Packet ........................................................................................................................................................... 16
Magic Packet™ ............................................................................................................................................................ 17
Physical Layer Transceiver (PHY) 18
100BASE-TX Transmit ................................................................................................................................................. 18
100BASE-TX Receive .................................................................................................................................................. 18
PLL Clock Synthesizer (Recovery) ............................................................................................................................... 18
Scrambler/De-scrambler (100BASE-TX only) .............................................................................................................. 18
10BASE-T Transmit ...................................................................................................................................................... 18
10BASE-T Receive ....................................................................................................................................................... 18
MDI/MDI-X Auto Crossover .......................................................................................................................................... 19
Straight Cab le ............................................................................................................................................................... 19
Crossover Cable ........................................................................................................................................................... 20
Auto Negotiation ........................................................................................................................................................... 20
LinkMD® Cab le Di agn os tic s .......................................................................................................................................... 22
Access .......................................................................................................................................................................... 22
Usage ........................................................................................................................................................................... 22
Media Access Control (MAC) Operation 23
Inter Packet Gap (IPG) ................................................................................................................................................. 23
Back-Off Algorithm ....................................................................................................................................................... 23
Late Collision ................................................................................................................................................................ 23
Flow Control.................................................................................................................................................................. 23
Half-Duplex Backpressure ............................................................................................................................................ 23
Address Filtering Function ............................................................................................................................................ 23
Clock Generator ........................................................................................................................................................... 24
Bus Interface Unit (BIU) 25
Supported Transfers ..................................................................................................................................................... 25
Physical Data Bus Size ................................................................................................................................................ 25
Little and Big Endia n Supp or t ....................................................................................................................................... 25
Asynchronous Interface ................................................................................................................................................ 26
BIU Summ at ion ............................................................................................................................................................ 26
Queue Management Unit (QMU) .......................................................................................................................................... 27
Transmit Queue (TXQ) Frame Format .......................................................................................................................... 27
Frame Transmitting Path Operation in TXQ ................................................................................................................. 28
Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLL ............................................................ 29
Frame Queue (RXQ) Frame Format ............................................................................................................................. 30
Frame Receiving Path Operation in RXQ .................................................................................................................... 30
Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor ............................................................. 31
EEPROM Interface ................................................................................................................................................................ 32
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 6 Revision 2.3
Loopback Support ................................................................................................................................................................. 32
Near-End (Remote) Loopback...................................................................................................................................... 32
Far-End (Local) Loopback ............................................................................................................................................ 32
CPU Interface I/O Registers 34
I/O Registers ................................................................................................................................................................. 34
Internal I/O Registers Space Mapping ......................................................................................................................... 34
Register Map: MAC, PHY, and QMU .................................................................................................................................... 40
Bit Type Definition ......................................................................................................................................................... 40
Chip Configuration Register (0x08 – 0x09): CCR ......................................................................................................... 40
Host MAC Address Registers: MARL, MARM, and MARH .......................................................................................... 41
Host MAC Address Register Low (0x10 – 0x 11) : MAR L .............................................................................................. 41
Host MAC Address Register Middle (0x12 – 0x13): MARM ......................................................................................... 41
Host MAC Address Register High (0x14 – 0x15): MARH ............................................................................................. 41
On-Chip Bus Control Register (0x20 – 0x21): OBCR ................................................................................................... 42
EEPROM Control Register (0x22 – 0x23): EEPCR ...................................................................................................... 42
Memory BIST Info Register (0x24 – 0x25): MBIR......................................................................................................... 43
Global Reset Register (0x26 – 0x27): GRR .................................................................................................................. 43
Wakeup Frame Control Register (0x2A – 0 x 2B) : WFCR .............................................................................................. 44
Wakeup Frame 0 CRC0 Register (0x30 – 0x 31) : WF0CRC0 ....................................................................................... 44
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC 1 ....................................................................................... 44
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ............................................................................... 45
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ............................................................................... 45
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ............................................................................... 45
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3 .............................................................................. 45
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC 0 ....................................................................................... 45
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC 1 ....................................................................................... 46
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ............................................................................... 46
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ............................................................................... 46
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ............................................................................... 46
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3 .............................................................................. 46
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ....................................................................................... 46
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC 1 ....................................................................................... 47
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ............................................................................... 47
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 ............................................................................... 47
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 ............................................................................... 47
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3 .............................................................................. 47
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC 0 ....................................................................................... 47
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC 1 ....................................................................................... 48
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 ............................................................................... 48
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 ............................................................................... 48
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 ............................................................................... 48
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3 .............................................................................. 48
Transmit Control Register (0x70 – 0x71): TXCR .......................................................................................................... 49
Transmit Status Register (0x72 – 0x73): TXSR ............................................................................................................ 50
Receive Control Register 1 (0x74 – 0x75): RXCR1 ...................................................................................................... 50
Receive Control Register 2 (0x76 – 0x77): RXCR2 ...................................................................................................... 51
TXQ Memory Information Register (0x78 – 0x79): TXMIR ........................................................................................... 52
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR .............................................................................. 52
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR .................................................................... 53
TXQ Command Register (0x80 – 0x81): TXQCR ......................................................................................................... 53
RXQ Command Register (0x82 – 0x 83) : RX Q CR ........................................................................................................ 54
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR ........................................................................................... 55
RX Frame Data Pointer Register (0x86 – 0x 8 7): R XF DPR .......................................................................................... 55
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ................................................................................ 56
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR ........................................................................... 56
Interrupt Enable Register (0x90 – 0x91): IER ............................................................................................................... 56
Interrupt Status Register (0x92 – 0x93): ISR ................................................................................................................ 57
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 7 Revision 2.3
RX Frame Count and Threshold Register (0x9C – 0x9D): RXFCTR ........................................................................... 58
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR ................................................................................. 59
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0 .................................................................................. 59
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1 .................................................................................. 59
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHT R 2 .................................................................................. 59
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHT R 3 .................................................................................. 60
Flow Control Low Watermark Register (0xB0 – 0xB1): FC LWR .................................................................................. 60
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR ................................................................................ 60
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR........................................................................... 60
Chip ID and Enable Register (0xC0 – 0xC1): CIDER .................................................................................................. 61
Chip Global Control Register (0xC6 – 0xC7): CGCR ................................................................................................... 61
Indirect Access Control Register (0xC8 – 0xC9): IACR ............................................................................................... 62
Indirect Acc ess Data Low Register (0xD0 – 0xD1): IADLR ......................................................................................... 62
Indirect Acc ess Data High R egist er (0xD2 – 0xD3): IADHR ........................................................................................ 62
Power Management Event Control Register (0xD4 – 0xD5): PMECR......................................................................... 63
Go-Sleep and Wake-Up Time Register (0xD6 – 0xD7): GSWUTR ............................................................................. 64
PHY Reset Register (0xD8 – 0xD9) : PH YRR .............................................................................................................. 64
PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR......................................................................... 65
PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7) : P1M B SR .......................................................................... 66
PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR ............................................................................................... 66
PHY 1 PHY ID High Register (0xEA – 0x E B) : PHY1IH R ............................................................................................. 67
PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR ............................................................... 67
PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0x EF) : P1ANL PR ....................................................... 68
Port 1 PHY Special Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD ...................................................................... 68
Port 1 Control Register (0xF6 – 0xF7): P1C R .............................................................................................................. 69
Port 1 Status Register (0xF8 – 0x F 9) : P1 SR ............................................................................................................... 70
MIB (Management Information Base) Counters 72
Additional MIB Information ........................................................................................................................................... 74
Absolute Maximum Ratings .................................................................................................................................................. 75
Operating Ratings ................................................................................................................................................................. 75
Electrical Characteristics ....................................................................................................................................................... 75
Timing Specifications ............................................................................................................................................................ 77
Asynchronous Read and Write Timing (Processor Read and Write) ........................................................................... 77
Auto-Negotiation Timing ........................................................................................................................................................ 78
Reset Timing ......................................................................................................................................................................... 79
EEPROM Timing ................................................................................................................................................................... 80
Reset Circuit Diagram ........................................................................................................................................................... 81
Selection of Isolation Transformers....................................................................................................................................... 82
Selection of Reference Crystal.............................................................................................................................................. 82
Package Information and Recommended Landing Pattern .................................................................................................. 83
Acronyms and Glossary ........................................................................................................................................................ 84
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 8 Revision 2.3
List of Figures
Figure 1. KSZ8851-16MLL/MLLI Functional Diagram .......................................................................................................... 1
Figure 2. 48-Pin LQF P ........................................................................................................................................................ 10
Figure 3. Typical Straight Cable Connection ...................................................................................................................... 19
Figure 4. Typical Crossover Cable Connection .................................................................................................................. 20
Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................. 21
Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections ................................................................................... 26
Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................. 29
Figure 8. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram .................................................................. 31
Figure 9. PHY Port 1 Near-End (Remote) and Host Far-End (Local) Loopback Paths ...................................................... 33
Figure 10. As ynchr ono us C ycle ............................................................................................................................................ 77
Figure 11. Auto-Negotiation Timing ...................................................................................................................................... 78
Figure 12. Reset T im ing ........................................................................................................................................................ 79
Figure 13. EEPROM Read Cycle Timing Diagram ............................................................................................................... 80
Figure 14. Recom mended Res et Cir cuit ............................................................................................................................... 81
Figure 15. Recom mended Cir cuit for Interfacing with CPU/FPGA Reset ............................................................................. 81
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 9 Revision 2.3
List of Tables
Table 1. Internal Function Blocks Statuses .......................................................................................................................... 15
Table 2. MDI/MDI-X Pin Definitions .................................................................................................................................... 19
Table 3. Address Filtering Scheme ..................................................................................................................................... 24
Table 4. Bus Interface Unit Signal Grouping ....................................................................................................................... 25
Table 5. Frame Format for Transmit Queue ....................................................................................................................... 27
Table 6. Transmit Control Word Bit Fields .......................................................................................................................... 27
Table 7. Transmit Byte Count Format ................................................................................................................................. 28
Table 8. Registers Setting for Transmit Function Block ...................................................................................................... 28
Table 9. Frame Format for Receive Queue ........................................................................................................................ 30
Table 10. Registers Settings for Receive Function Block ..................................................................................................... 30
Table 11. KSZ8851-16MLL EEPROM Format ...................................................................................................................... 32
Table 12. Format of MIB Counters ........................................................................................................................................ 72
Table 13. Port 1 MIB Counters Indirect Memory Offsets ...................................................................................................... 73
Table 14. Asynchronous Cycle Timing Parameters .............................................................................................................. 77
Table 15. Auto-Negotiation Timing Parameters .................................................................................................................... 78
Table 16. Reset Timing Parameters ..................................................................................................................................... 79
Table 17. EEPROM Timing Parameters ............................................................................................................................... 80
Table 18. Transformer Selection Criteria .............................................................................................................................. 82
Table 19. Qualified Single-Port Magnetics ............................................................................................................................ 82
Table 20. Typical Reference Crystal Characteristics ............................................................................................................ 82
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 10 Revision 2.3
Pin Configuration
Figure 2. 48-Pin LQFP
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 11 Revision 2.3
Pin Description
Pin Number Pin Name Type
(1)
Pin Function
1 P1LED1 IPU/O
Programmable LED output to indicate port activity/status.
LED is ON when output is LOW; LED is OFF when output is HIGH.
Port 1 LED indicators* d efin ed as follows:
Chip Global Control Register: CGCR bit [9]
0 (Default) 1
P1LED1 100BT ACT
P1LED0 LINK/ACT LINK
* Link = LED On; Activity = LED Blink; Link/Act = LED On/Blink;
Speed = LED On (100BASE-T); LED Off (10BASE-T)
Config Mode: The P1LED1 pull-up/pull-down value is latched as 16-/8-bit mode during
power-up/reset. See the Pin for Strap-In Options section for d etail s
2 P1LED0 OPU
3 PME OPU
Power Management Event (default ac tive low): It is asserted (low or high depends on
polarity set in PMECR register) when one of the wake-on-LAN events is detected by
KSZ8851-16MLL. The KSZ8851-16MLL is requesting the system to wake up from low
power mode.
4 INTRN OPU Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin
need an external 4.7K pull-up resistor.
5 RDN IPU Read Strobe Not
Asynchronous read strobe, active low to indicate read cycle.
6 WRN IPU Write Strobe Not
Asynchronous write strobe, active low to indicate write cycle.
7 DGND GND Digital ground
8 VDD_CO1.8 P
1.8V regulator output . This 1.8V output pin provides power to pins 14 (VDD_A1.8) and 29
(VDD_D1.8) for core VDD supply.
If VDD_IO is set for 1.8V then this pin should be left floating, pins 14 (VDD_A1.8) and 29
(VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 27, 38 and 46
(VDD_IO) with appropriate filtering.
9 EED_IO IPD/O In/Out Data from/to externa l EEPROM.
Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during
power-up/reset. See the Pin for Strap-In Options section for d etail s
Notes:
1. P = Power supply
GND = Ground
I/O = Bi-directional
I = Input
O = Output.
IPD = Input with internal pull-down (58K ±30%).
IPU = Input with internal pull-up (58K ±30%).
OPD = Output with internal pull-down (58K ±30%).
OP U = Output with int ernal pull-up (58K ±30%).
IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.
IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.
I/O (PD) = Input/Output with internal pull-down (58K ±30%).
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 12 Revision 2.3
Pin Description (Continued)
Pin Number Pin Name Type Pin Function
10 EESK IPD/O
EEPROM Serial Clock
A 4µs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip
bus speed @ 125MHz) serial output clock cycle to load configuration data from the serial
EEPROM.
Config Mode: The pull-up/pull-down value is latched as big-/little-Endian mode during
power-up/reset. See the Pin for Strap-In Options section for detail s
11 CMD IPD
Command Type
This command input decides the SD[15:0] shared data bus access information.
When command input is low, the access of shared data bus is for data access in 16-bit
mode shared data bus SD[15:0] or in 8-bit mode shared data bus SD[7:0].
When command input is high, the access of shared data bus is for address A[7:2] access
at shared data bus SD[7:2], byte enable BE[3:0] at SD[15:12] and the SD[11:8] is “Do Not
Care” in 16-bit mode. It is for address A[7:0] access at SD[7:0] in 8-bit mode.
12 CSN IPU Chip Select Not
Chip select for the shared data bus access enable, active Low.
13 AGND GND Analog ground
14 VDD_A1.8 P
1.8V analog power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46
(VDD_IO) with appropriate filtering.
15 EECS OPD EEPROM Chip Sele ct
This signal is used to select an external EEPROM device.
16 RXP1 I/O Port 1 physical receive signal (+ differential).
17 RXM1 I/O Port 1 physical receive signal (– differential).
18 AGND GND Analog ground.
19 TXP1 I/O Port 1 physical transmit signal (+ differential).
20 TXM1 I/O Port 1 physical transmit signal (– differential).
21 VDD_A3.3 P 3.3V analog VDD input power supply with well dec oupling capacitors.
22 ISET O Set physical transmits output current.
Pull-down this pin with a 3.01K 1% res istor to ground.
23 RSTN IPU Reset Not
Hardware reset pin (active Low). This reset input is required minimum of 10ms low after
stable supply voltage 3.3V.
24 X1 I 25MHz crystal or oscillator clock connection.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant
oscillator and X2 is a no connect.
Note: Clock requirement is ±50ppm for either crystal or oscillator.
25 X2 O
26 DGND GND Digital ground
27 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
28 DGND GND Digital ground
29 VDD_D1.8 P 1.8V digital power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is
1.8V, this pin must be supplied power from the same source as pins 27, 38, and 46
(VDD_IO) with appropriate filtering.
30 SD15 I/O (PD) Shared Data Bus bit 15. Data D15 access when CMD=0. Byte Enable 3 at double-word
boundary access (BE3, 4th byte enable and active high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 13 Revision 2.3
Pin Description (Continued)
Pin Number Pin Name Type Pin Function
31 SD14 I/O (PD) Shared Data Bus bit 14. Data D14 access when CMD=0. Byte Enable 2 at double-word
boundary access (BE2, 3rd byte enable and active high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
32 SD13 I/O (PD) Shared Data Bus bit 13. Data D13 access when CMD=0. Byte Enable 1 at double-word
boundary access (BE1, 2nd byte enable and acti ve high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
33 SD12 I/O (PD) Shared Data Bus bit 12. Data D12 access when CMD=0. Byte Enable 0 at double-word
boundary access (BE0, 1st byte enable and ac tive high) in 16-bit mode when CMD=1.
This pin must be tied to GND in 8-bit bus mode.
34 SD11 I/O (PD)
Shared Data Bus bit 11. Data D11 access when CMD=0. Do Not Care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
35 SD10 I/O (PD) Shared Data Bus bit 10. Data D10 access when CMD=0. Do Not Care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
36 SD9 I/O (PD) Shared Data Bus bit 9. Data D9 access when CMD=0. Do Not Care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
37 DGND GND Digital ground
38 VDD_IO P 3.3V, 2.5V, or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
39 SD8 I/O (PD) Shared Data Bus bit 8. Data D8 access when CMD=0. Do Not Care when CMD=1. This
pin must be tied to GND in 8-bit bus mode.
40 SD7 I/O (PD) Shared Data Bus bit 7. Data D7 access when CMD=0. Address A7 access when CMD=1.
41 SD6 I/O (PD) Shared Data Bus bit 6. Data D6 access when CMD=0. Address A6 access when CMD=1.
42 SD5 I/O (PD) Shared Data Bus bit 5. Data D5 access when CMD=0. Address A5 access when CMD=1.
43 SD4 I/O (PD) Shared Data Bus bit 4. Data D4 access when CMD=0. Address A4 access when CMD=1.
44 SD3 I/O (PD) Shared Data Bus bit 3. Data D3 access when CMD=0. Address A3 access when CMD=1.
45 SD2 I/O (PD) Shared Data Bus bit 2. Data D2 access when CMD=0. Address A2 access when CMD=1.
46 VDD_IO P 3.3V, 2.5V, or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
47 SD1 I/O (PD) Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode, this is address A1
access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.
48 SD0 I/O (PD) Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode, this is address A0
access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 14 Revision 2.3
Pin for Strap-In Options
Pin Number Pin Name Type
(2)
Pin Function
1 P1LED1 IPU/O
8- or 16-bit bus mode select during power-up/reset:
NC or Pull -up (default ) = 16-bit bus
Pull-down = 8-bit bus
This pin value is also latched into register CCR, bit 6/7.
9 EED_IO IPD/O
EEPROM select during power-up/reset:
Pull-up = EEPROM present
NC or Pull -down (default ) = EEPROM not present
This pin value is latched into register CCR, bit 9.
10 EESK IPD/O
Endian mode select during pow er -up/reset:
Pull-up = Big Endian
NC or Pull -down (default) = Little Endi an
This pin value is latched into register CCR, bit 10.
When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR
register can be used to program either Little (bit11=0 default) Endian mode or Big (bit11=1)
Endian mode.
Note:
2. IPU/ O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.
IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 15 Revision 2.3
Functional Description
The KSZ8851-16MLL is a single-chip fast Ethernet M AC/PH Y controller consisting of a 10/100 physical layer transceiver
(PHY), a MAC, and a Bus Interface Unit (BIU) that controls the KSZ8851-16MLL via an 8-bit or 16-bit host bus interface.
The KSZ8851-16MLL is fully compliant with IEEE802.3u standards.
Fuctional Overview
Power Management
The KSZ88 51-16MLL suppor ts enhanced po wer managem ent feature in low po wer state with ener gy detection to ensure
low-power dissipation during device idle periods. T here are four operation m odes under the power m anagement function
which is controlled by two bits in PMECR (0xD4) register as shown below:
PMECR[1 :0] = 00 Norm al O perati on Mod e
PMECR[1:0] = 01 Energy Detect Mode
PMECR[1:0] = 10 Soft Power-down mode
PMECR[1:0] = 11 Power-saving mode
Table 1. Internal Function Blocks Statuses
KSZ8851-16MLL
Function Blocks
Power Management Operation Modes
Normal M ode Power-saving mode Energy Detect Mode Soft Power-Down Mode
Internal PLL Clock Enabled Enabled Disabled Disabled
Tx/Rx PHY Enabled Rx unused block disabled Energy detect at Rx Disabled
MAC Enabled Enabled Disabled Disabled
Host Interface Enabled Enabled Disabled Disabled
Normal Operation Mode
This is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). When
KSZ8851-16MLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host
interface is ready for CPU read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal
operation mode to any one of the other three power management operation modes.
Energy De tect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8851-16MLL is not connected to an active link partner. For example, if cable is not present or it is connected to a
powered do wn partner , the KSZ8 851-16MLL can auto matically enter to the low po wer state in energy detec t mode. O nce
activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLL can
automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8851-16MLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver.
The energy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851-16MLL is in this mode, it
will m onitor the cabl e energy. If ther e is no ener gy on the cable for a time longer than pr e-configure d value at bi t[7:0] Go-
Sleep tim e in GSW UTR register, KSZ8851-16MLL will go into a low po wer state. W hen KSZ8851-16ML L is in low power
state, it wi ll keep monitorin g the cable energ y. Once the energ y is det ected from the c able and is contin uously presented
for a time longer t han pr e-configure d val ue a t b it[1 5: 8] Wake-Up time in GSWUT R register, the KSZ8851-16 MLL will e nte r
either the normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal operation mode if
both auto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.
The KSZ88 51-16 MLL wil l a lso as s ert PM E out put p in if the c orr esponding ena bl e bit[ 8] is s et in PM ECR ( 0x D 4) regis ter or
generate in terr upt to s ig na l an energy detect eve nt oc c urr ed if the c orr espondin g e nab le bit [2] is set in IER ( 0x90) regis ter.
Once the po wer management un it detects the PME o utput asserted or int errupt active, it will power up the hos t CPU and
issue a wakeup command which is a read cycle to read the Globe Reset Register (GRR at 0x26) to wake up the
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 16 Revision 2.3
KSZ8851-16MLL from the low power state to the normal power state in case the auto-wakeup enable bit[7] is disabled.
When KSZ8851-16MLL is at normal power state, it is able to transmit or receive packet from the cable.
Soft Power-Down Mode
The soft power-down mode is entered by setting bit[1:0]=10 in PMECR register. When KSZ8851-16MLL is in this mode,
all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change, and the host
interface is only used to wake-up this device from current soft power-down mode to normal operation mode.
In order to go back the normal operation mode from this soft power-down mode, the only way to leave this mode is
through a host wake-up command which the CPU issues to read the Globe Reset Register (GRR at 0x26).
Power-Saving Mode
The power-saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting
bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. W hen KSZ8851M is in this mode, all PLL clocks are
enabled, MAC is on, all internal registers value will not change, and host interfa ce is ready for CPU r ead or write. In this
mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains
transm itting and on ly turns off the unused r eceiver b lock . Once activi ty resum es due to plugg ing a cab le or att empting b y
the far end to establish link, the KSZ8851M can automatically enabled the PHY power up to normal power state from
power-saving mode.
During this po wer-sav ing mode, the host C PU can pro gram the bit[1:0] in PMEC R register an d set bit[10] =0 in P1SCL MD
register to transit the current power-saving mode to any one of the other three power management operation modes.
Wake-on-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the
network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote
adminis trator, or s im ply network traf fic direc tly targeted to the local s ystem . In all of these instanc es, the net work device is
pre-programmed by the policy owner or other software with information on how to identify wake frames from other network
traffic. The KSZ8851-16MLL controller can be programmed to notify the host of the wake-up frame detection with the
assertion of the interrupt signal (INTRN) or assertion of the power management event signal (PME).
A wake-up event is a request for hardware and/or software external to the network device to put the system into a
powered state (working).
A wake -up signal is caused by:
1. Detection of energy signal over a pre-configured value (bit 2 in ISR register)
2. Detection of a linkup in the network link state (bit 3 in ISR register)
3. Receipt of a Magic Packet (bit 4 in ISR register)
4. Receipt of a network wake-up frame (bit 5 in ISR register)
There ar e also other types of wak e-up e ve nts tha t ar e not liste d here as manuf ac tur ers m a y choose to im plement thes e in
their own wa ys.
Detecti o n o f Energy
The energy is detected from the cable and is continuously presented for a time longer than pre-configured value,
especially when this energy change may impact the level at which the system should re-enter to the normal power state.
Detecti o n o f L inkup
Link status wake events are useful to indicate a linkup in the network’s connectivity status.
Wake-up Packet
Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a wake-up frame.
The KSZ8851-16MLL supports up to four users defined wake-up frames as below:
• Wake-up f ram e 0 is def ine d in wak eup fram e register s (0x30 – 0x3 B) and is en abled b y bit 0 in wak eup fra m e contr ol
register (0x2A).
• Wake-up f ram e 1 is def ine d in w akeup f ram e register s ( 0x40 – 0x4 B) and is en abled b y bit 1 in wak eup fra m e contr ol
register (0x2A).
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 17 Revision 2.3
• Wake-up f ram e 2 is def ine d in w akeup f ram e register s ( 0x50 – 0x5 B) and is en abled b y bit 2 in wak eup fra m e contr ol
register (0x2A).
• Wake-up f ram e 3 is def ine d in w akeup f ram e register s ( 0x60 – 0x6 B) and is en abled b y bit 3 in wak eup fra m e contr ol
register (0x2A).
Magic Packet™
Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by
sending a specific packet of information, called a Magic Packet frame, to a node on the network. W hen a PC capable of
receiving th e specif ic f r am e goes to sleep, it e na bles th e Ma gic Packet RX mode i n th e L AN c o ntr o ller, an d when the LAN
controller receives a Magic Packet frame, it will alert the system to wake up.
Magic Packet is a standard feature integrated into the KSZ8851-16MLL. The controller implements multiple advanced
power-down modes including Magic Packet to conserve power and operate more efficiently.
Once the KSZ8851-16MLL has been put into Magic Packet Enable mode (WFCR[7]=1), it scans all incoming frames
addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address
(SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address
and CRC.
The specific sequence consists of 16 duplications of the IEEE addr ess of this node, with no breaks or interruptions. This
sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The
synchron ization stream allows the sc anning state m achine to be m uch simpler. T he synchroniza tion stream is defined as
6 bytes of FFh. The device will also acc ept a broadcas t fram e, as long as the 16 dupl icati ons of the IEEE addres s match
the address of the machine to be awakened.
Example:
If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be
scanning for the data sequence (assuming an Ethernet frame):
DESTINATION SOURCE – MISC - FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -
11 22 33 4 4 55 66 - 1 1 2 2 33 4 4 5 5 6 6 - 1 1 2 2 3 3 4 4 55 6 6 - 1 1 2 2 3 3 4 4 5 5 6 6 - 11 22 33 44 55 66 - 11 22 33 4 4 5 5 66 -
11 22 33 4 4 55 66 - 1 1 2 2 33 4 4 5 5 6 6 - 1 1 2 2 3 3 4 4 55 6 6 - 1 1 2 2 3 3 4 4 5 5 6 6 - 11 22 33 44 55 66 - 11 22 33 4 4 5 5 6 6 -
11 22 33 44 55 66 - MISC - CRC.
There ar e no furt her restric tions on a Magic P ack et frame. F or instance, the sequ ence could be in a TCP/IP pack et or an
IPX pack et. The fram e may b e bridged or r outed across the network without af fecting its a bility to wak e-up a node at th e
frame’s destination.
If the LAN contr oll er scans a fr ame and does not find t he specif ic seque nce sho wn abo ve, it dis cards the f ram e and tak es
no further action. If the KSZ8851-16MLL controller detects the data sequence, however, it then alerts the PC’s power
management circuitry (assert the PME pin) to wake up the system.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 18 Revision 2.3
Physical Layer Transceiver (PHY)
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The cir cuitry starts with a p arallel-to-serial convers ion, which c onverts the MII dat a from the MAC into a 1 25MHz seria l bit
stream . The data and control st ream is then converte d into 4B/5B codi ng, followed b y a s crambler. T he serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 3.01KΩ (1%)
resistor for the 1:1 transformer ratio sets the output current.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, o vers ho ot, a nd t i ming j itter. The wave-shap ed 10 BA SE-T output dri v er is also i nc orpor a ted into the 100 BA SE-TX
driver.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The rec eiving side s tarts with the equal ization filter to c ompens ate for inter-s ym bol interferenc e (ISI) over the twisted p air
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
compar isons of i ncoming s ignal str ength ag ainst som e known c able char acteristic s, and th en tunes itself f or optim ization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, th e equ alized signal goes thr ough a DC r estorat ion an d data con versi on bloc k . The DC res tor ation c ircuit is use d to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recover y circuit e x trac ts the 125MH z cloc k from the edges of the N RZI sign al. T his rec overed c lock is then use d
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.
PLL Clock Synthesizer (Recovery)
The interna l PLL cloc k synthesi zer can gener ate eith er 125MH z, 62.5M Hz, 41.6 6MH z, or 25MH z clock s b y setting the on-
chip bus c ontrol register ( 0x20) f or KSZ88 51-16MLL s ystem timing. T hese intern al clock s are gen erated f rom an ex ternal
25MHz crystal or oscillator.
Scrambler/De-scrambler (100BASE-TX only)
The purpos e of the scram bler is to s pread th e power s pectrum of the s ignal to reduce e lectrom agnetic inter ference ( EMI)
and baselin e wander.
Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler
generates a 2047-bit non-repetitive s equence. T hen the receiver d e-scrambles the i ncoming data stre am using the sam e
sequence as at the transmitter.
10BASE-T Transmit
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
The y are interna ll y wave-shaped and pre-emphasi zed into ou t puts w ith typical 2. 4 V amplitude. The harmonic c ontents are
at least 27dB below the fundamental frequency when driven by an all-ones Manches ter-encoded signal.
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and
a phase-locked loop (PLL) perform the decoding function.
The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with
levels les s than 400m V or with short puls e widths to pr event noise at the RX P1 or RXM1 in put from f alsely triggering t he
decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8851-16MLL
decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 19 Revision 2.3
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8851-16MLL supports HP-Auto MDI/MDI-X
and IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MD I/ MDI-X is the default.
The auto-s ense f unc tio n de tec ts rem ot e trans mit and rec ei ve pair s and c or rec tly ass igns the tr ans mit and receive pa irs f or
the KSZ8851-16MLL device. This feature is extremely useful when end users are unaware of cable types in addition to
saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port
control registers. The IEEE 802.3u standard MDI and MDI-X definitions are as below:
Table 2. MDI/MDI-X Pin Definitions
MDI MDI-X
RJ45 Pins Signals RJ45 Pins Signals
1 TD+ 1 RD+
2 TD- 2 RD-
3 RD+ 3 TD+
6 RD- 6 TD-
Strai g h t Cable
A straight c able conn ects an MDI dev ice to a n MDI-X dev ice or an MDI-X device to an MDI de vice. T he foll owing diagram
shows a typical straight cable connection between a network interface card (NIC) and a switch, or hub (MDI-X).
Figure 3. Typical Straight Cable Connection
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 20 Revision 2.3
Crossover Cab le
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The
following diagram shows a typical crossover cable connection between two chips or hubs (two MDI-X devices).
Figure 4. Typical Crossover Cable Connection
Auto Negotiation
The KSZ8851-16MLL conf orms to the auto negotiation protocol as described b y the 802.3 committee to allow the port to
operate at either 10Base-T or 100Base-TX.
Auto negot iation a llows u nshielded twisted pair (UT P) link partners to select th e best c omm on mode of op eration. In auto
negotiatio n, the li nk partners adver tise c apabilit ies acr oss the link to each oth er. If auto negot iation is not su pport ed or the
link partner to the KSZ8851-16MLL is forced to bypass auto negotiation, the mode is set by observing the signal at the
receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the
receiver is listening for advertisements or a fixed signal protocol.The auto negotiation link setup is shown in Figure 5.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 21 Revision 2.3
Figure 5. Auto Negotiation and Parallel Operation
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 22 Revision 2.3
LinkMD® Cable Diagnostics
The KSZ8851-16MLL LinkMD® uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling
problems such as open circuits, short circuits, and impedance mismatches.
LinkMD wor k s by sending a puls e of k nown am plitude and duratio n down the MD I and MDI -X pairs and then anal yzes the
shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a
maximum distance of 200m and an accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable
digital format in register P1SCLMD[8:0].
Note: cable diagnostics are only valid for copper connections – fiber-optic operation is not supported.
Access
LinkMD is initiated by accessing register P1SCLMD, the PHY special control/status and LinkMD register (0xF4).
Usage
LinkMD can be run at any time by ensuring that Auto-MDIX has been disabled. To disable Auto-MDIX, write a ‘1’ to
P1CR[10] to enable manual control over the pair used to transmit the LinkMD pulse. The self-clearing cable diagnostic
test enable bit, P1SCLMD [12], is set to ‘1’ to start the test on this pair.
When bit P1SCLMD[12] returns to ‘0’, the test is complete. The test result is returned in bits P1SCLMD[14:13] and the
distance is returned in bits P1SCLMD[8:0]. The cable diagnostic test results are as follows:
00 = Valid test, normal condition
01 = Valid test, open circuit in cable
10 = Valid test, short circuit in cable
11 = Invalid test, LinkMD failed
If P1SCLMD[14:13]=11, this indicates an invalid test, and occurs when the KSZ8851-16MLL is unable to shut down the
link partner. In this instance, the test is not run, as it is not possible for the KSZ8851-16MLL to determ ine if the detected
signal is a reflection of the signal generated or a signal from another source.
Cable distance can be approximated by the following formula:
P1SCLMD[8:0] x 0.4m for port 1 cable distance
This c onstant m ay be calibrated f or diff erent cabling c onditions , includin g cables with a veloc ity of propag ation that v aries
significantly from the norm.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 23 Revision 2.3
Media Access Control (MAC) Operation
The KSZ8851-16MLL strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive
packets. If the current pack et is experiencing collisions, the minimum 96-bit tim e for IPG is measured from carrier sense
(CRS) to the next transmit packet.
Back-Off Algorithm
The KSZ8851-16MLL implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode.
After 16 collisions, the packet is dropped.
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
Flow Control
The KSZ8851-16MLL supports standard 802.3x flow control frames on both transmit and receive sides.
On the receiv e side, if the KSZ8 851-16M LL r ec ei ves a paus e contr o l f r am e, the KSZ8851-16M LL will n ot trans mit the nex t
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the
current tim er expires, the tim er will be updat ed with the new valu e in the second pause fr am e. During this period (whil e it
is flow controlled), only flow control packets from the KSZ8851-16MLL are transmitted.
On the tr ansmit s ide, th e K SZ8851-16MLL has int el ligent and eff icient wa ys t o d e ter mine when t o invoke f lo w c ontro l. The
flow control is based on availability of the system resources.
There are three programmable low watermark register FCLWR (0xB0), high watermark register FCHWR (0xB2) and
overrun watermark register FCOWR (0xB4) for flow control in RXQ FIFO. The KSZ8851-16MLL will send PAUSE frame
when the RXQ buffer hit the high watermark level (default 3.072KB available) and stop PAUSE frame when the RXQ
buff er hit the low watermar k level (defau lt 5.12KB availabl e). The KSZ8851-1 6MLL will drop pack et when the RXQ buffer
hit the overrun watermark level (default 256 Bytes available).
The KSZ88 51-16MLL iss ues a f low control fr ame (X off, or transm itter of f), containing t he maxim um pause ti m e defined in
IEEE standard 802.3x. Once the resource is freed up, the KSZ8851-16MLL sends out the another flow control frame
(Xon, or transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis
feature is provided to prevent the flow control mechanism from being constantly activated and deactivated.
Half-Duplex Backpressure
A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as in full-duplex mode. If backpressure is required, the KSZ8851-16MLL sends preambles to
defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851-16MLL
discontinues the carrier sense backpressure and then raises it again quickly. This short silent time (no carrier sense)
prevents oth er stations from sending out packets thus keeping other stations in a carrier sense def erred state. The short
silent tim e is about 4µs and repeat every 1.64ms in the backpressure jam patter for 10Base-T. If the port has pack ets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are
transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until
chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is
generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet
reception.
Address Filtering Function
The KSZ8851-16MLL supports 11 different address filtering schemes as shown in Table 3. The Ethernet destination
address (DA) field inside the packet is the first 6-byte field which uses to compare with either the host MAC address
registers (0x 10 – 0x1 5) or t he M AC addr ess h as h ta bl e registers ( 0xA0 – 0x A 7) f or addr es s f ilt er ing operat io n. T he first bit
(bit 40) of the des tination a ddress (DA) in the Ethernet pack et decides whether this is a ph ys ical addr ess if bit 40 is “ 0” or
a multicast address if bit 40 is “1”.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 24 Revision 2.3
Table 3. Address Filtering Scheme(3,4)
Item Address
Filtering Mode
Receive Control Register (0x74 – 0x75): RXCR1
Description
RX All
(Bit 4) RX Inverse
(Bit 1)
RX Physical
Address
(Bit 11)
RX Multicast
Address
(Bit 8)
1 Perfect 0 0 1 1
All Rx frames are passed only if the DA exactly
matches the MAC address in MARL, MARM and MARH
registers.
2 Inverse perfect 0 1 1 1
All Rx frames are passed if the DA is not matching the
MAC address in MARL, MARM and MARH registers.
3 Hash only 0 0 0 0
All Rx frames with either multicast or physical
destination address are filtering against the MAC
address hash table.
4 Inverse hash only 0 1 0 0
All Rx frames with either multicast or physical
destination address are filtering not against the MAC
address hash table.
All Rx frames which are filtering out at item 3 (Hash
only) only are passed in this mode.
5 Hash perfect
(Default) 0 0 1 0
All Rx frames are passed with Physical address (DA)
matching the MAC address and
to enable receive
multicast frames that pass the hash table
when
Multicast address is matching the MAC address hash
table.
6 Inverse hash
perfect 0 1 1 0
All Rx
frames which are filtering out at item 5 (Hash
perfect) only are passed in this mode.
7 Promiscuous 1 1 0 0
All Rx frames are passed without any conditions.
8 Hash only with
Multicast addre ss
passed 1 0 0 0
All Rx frames are passed with Physical address
(DA)
matching the MAC address hash table and with
Multicast address without any conditions.
9 Perfect with
Multicast addre ss
passed 1 0 1 1
All Rx frames are passed with Physical address (DA)
matching the MAC address and with Multicast address
without any
conditions.
10 Hash only with
Physical address
passed 1 0 1 0
All Rx frames are passed with Multicast address
matching the MAC address hash table and with
Physical address without any conditions.
11 Perfect with
Physical address
passed 1 0 0 1
All Rx
frames are passed with Multicast address
matching the MAC address and with Physical address
without any conditions.
Notes:
3. Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set to 1 in RXCR1 register.
4. The KSZ8851-16MLL will discard frame with the same SA as the MAC address if bit[0] is set in RXCR2 register.
Clock Generator
The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator
(as described in the Pin Description section).
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 25 Revision 2.3
Bus Interface Unit (BIU)
The BIU host interface is a generic shared data bus interface, designed to communicate with embedded processors. No
glue logic is required when it talks to various standard asynchronous buses and processors.
Supporte d Transfers
In terms of transfer type, the BIU can support asynchronous transfer or SRAM-like slave mode. To support the data
transfers, the BIU provides a group of signals:
Shared Data bus SD[15:0] for Address, Data and Byte Enable, Command (CMD), Chip Select Enable (CSN), Read
(RDN), Write (WRN) and Interrupt (INTRN).
Physical Data Bus Size
The BIU s upports a n 8-bi t o r 16-bit h ost s tand ar d da ta bus . Dep ending on t he s i ze of the ph ysic al d ata bus, th e KSZ 885 1-
16MLL can support 8-bit or 16-bit data transfers.
For example,
For a 16-bit data bus mode, the KSZ8851-16MLL allows an 8-bit and 16-bit data transfer.
For an 8-bit data bus mode, the KSZ 885 1-16MLL only allows an 8-bit data transfer.
The KSZ8 85 1-16M LL s upp or ts int er na l data byte-swa p. T his means that t h e system/host data bus HD [7: 0] just c onn ec t to
SD[7:0] f or an 8-bit data bu s interf ace. F or a 16-bit data bus , the s ystem/hos t data bus HD[15: 8] and HD[7: 0] onl y need to
connect to SD[15:8] and SD[7:0] respectively.
Table 4 describes the BIU signal grouping.
Table 4. Bus Interface Unit Signal Grouping
Signal Type Function
SD[15:0] I/O Shared Data Bus
Data D[15:0] → SD[15:0] access when CMD=0. Address A[7:2] → SD[7:2] and Byte Enable
BE[3:0] → SD[15:12] access when CMD=1 in 16-b it mode . A ddres s A[7: 0] → SD[ 7:0] only access
when CMD=1 in 8-bit mode (Shared data bus SD[15:8] must be tied to low in 8-bit bus mode) .
CMD Input Command Type
This command input decides the SD[15:0] shared data bus access cycle information.
CSN Input Chip Selec t Enable
Chip Enable asserted (low) indicates that the shared data bus access is enabled.
INTRN Output Interrupt
This pin is asserted to l ow when interrupt occurred.
RDN Input Asynchronous Read
This pin is asserted to l ow during read cycle.
WRN Input Asynchronous Write
This pin is asserted to l ow during write cycle.
Little and Big Endian Support
The KSZ8851-16MLL supports either Little- or Big-Endian microprocessor. The external strap pin 10 (EESK) is used to
select between two m odes. The KSZ8851-16MLL operates in Little Endian when this pin is pulled-down or in Big Endian
when this pin is pulled-up.
When this pin 10 is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to
program either Little (bit11=0) Endian mode or Big (bit11=1) Endian mode.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 26 Revision 2.3
Asynchronous Interface
For asynchronous transfers, the asynchronous interface uses RDN (read) and WRN (write) signal strobes for data
latching. T he h os t uti li zes t he r isin g ed ge of RD N t o la tc h REA D dat a wh en t he h os t read d ata from KSZ885 1-16M LL. The
KSZ8851-16MLL utilizes the internal pulse to latch WRITE data based on the RXFDPR register bit 12 setting.
All asynchronous transfers are either single-data or burst-data transfers. Byte or word data bus access (transfers) is
supported. The BIU, however, provides flexible asynchronous interfacing to communicate with various applications and
architectures. No additional address latch is required. The BIU qualifies both CSN (Chip Select) pin and WRN (Write
Enable) pin to write the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address A[7:0] value (in 8-bit mode) into
KSZ8851-16MLL when CMD (Com mand type) pin is high. T he BIU qua lifies both CSN (Chip Se lect) pin and RDN (Read
Enable) or WRN (Write Enable) pin to read or write the SD[15:0] data value from or to KSZ8851-16MLL when CMD
(Command type) pin is low.
In order for software to read back the previous CMD register write value when CMD is “1”, the BIU qualifies both CSN
(Chip Select) pin and RDN (Read Enable) pin to read the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address
A[7:0] value (in 8-bit mode) back from KSZ8851-16MLL when CMD (Command type) pin is high.
BIU Summation
Figure 6 shows the connection for different data bus sizes. Also refer to reference schematics in hardware design
package.
All of control and status registers in the KSZ8851-16MLL are accessed indirectly depending on CMD (Command type)
pin. The command sequence to access the specified control or status register is to write the register’s address (when
CMD=1) then read or write this register data (when CMD=0). If both RDN and WRN signals in the s ystem are only used
for KSZ8851-16MLL, the CSN pin can be forced to active low to simplify the system design. The CMD pin can be
connected to host address line HA0 for 8-bit bus mode or HA1 for 16-bit bus mode.
Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections
Note: In 16-bit bus mode, t he SD1 bit must be set to “1” when CMD = 1 during DMA access.
CMD
SD[7:0]
8-bit D at a Bus
HD[7:0]
CMD
16-bit D at a Bus
HA1
HD[7:0]
HD[15:8]
KSZ8851 -16MLL
GND
/RD
/WR WRN
RDN
/CS CSN
IRQ INTRN
/RD
/WR WRN
RDN
/CS CSN
IRQ INTRN
KSZ8851 -16MLL
HA0
SD[15:8] SD[7:0]
SD[15:8]
P1LED1P1LED 1
1K ohm
NC
-
-
A2
A3
A4
A5
A6
A7
-
-
-
-
BE0
BE1
BE2
BE3
CMD=1
ÒHighÓ
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CMD=0
ÒLowÓ
16-Bit Bus Mode
P i n 1 (P 1LED1) = NC or
P ul l Up during RE S ET
A0
A1
A2
A3
A4
A5
A6
A7
GND
GND
GND
GND
GND
GND
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
GND
GND
GND
GND
GND
GND
GND
GND
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CMD=1
ÒHighÓ
CMD=0
ÒLowÓ
Shared
Data Bus
8-Bit Bus Mode
P i n 1 (P 1LED1) = 1K Pull
Down during RE SE T
-
-
A2
A3
A4
A5
A6
A7
-
-
-
-
BE0
BE1
BE2
BE3
CMD=1
ÒHighÓ
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CMD=0
ÒLowÓ
16-Bit Bus Mode
P i n 1 (P 1LED1) = NC or
P ul l Up during RE S ET
A0
A1
A2
A3
A4
A5
A6
A7
GND
GND
GND
GND
GND
GND
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
GND
GND
GND
GND
GND
GND
GND
GND
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CMD=1
ÒHighÓ
CMD=0
ÒLowÓ
Shared
Data Bus
8-Bit Bus Mode
P i n 1 (P 1LED1) = 1K Pull
Down during RE SE T
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 27 Revision 2.3
Queue Management Unit (QMU)
The Queue Man agem ent Unit (Q MU) m anages pac k et traffic between t he MAC /PH Y interfac e and the s ystem hos t. It has
built-in pack et mem ory for recei ve and transm it func tions called T XQ (Tr ansmit Queue) a nd RXQ ( Receive Q ueue). Each
queue cont ains 12KB for RXQ and 6KB f or TXQ of mem ory with back -to-back, non-bloc king fram e transfer perform ance.
It provides a gr o up of c ontrol re gister s f or system c ont r ol, f rame s tatus regis t ers f or c urr ent pac k et trans mit/rec ei ve sta tus,
and interrupts to inform the host of the real time TX/RX status.
Transmit Queue (TXQ) Frame For mat
The f rame form at for the trans mit queue is shown i n T able 5. The f irst word c ontains t he contr ol inform ation for the f rame
to transmit. The second word is used to specify the total number of bytes of the frame. The packet data follows. The
pack et data area hol ds the fram e itself. It m ay or ma y not include the CRC ch ecksum depending u pon whet her hard ware
CRC checksum generation is enabled in TXCR (bit 1) register.
Multiple frames can be pipelined in the receive queue as long as there is enough queu e memory, thus avoiding overrun.
For each transmitted frame, the transmit status information for the frame is located in the TXSR (0x72) register.
Table 5. Frame Format for Transmit Queue
Packet Memory Address Offset Bit 15
2
nd
Byte
Bit 0
1
st
Byte
0 Control Word
(High byte and low byte need to swap in Big Endian mode)
2 Byte Count
(High byte and low byte need to s wap in Big Endian mode)
4 - up Transmit Packet Data
(Maximum size is 2000 bytes)
Because packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of the
pack et that is c ur rently bein g trans f er red on the MAC i nter f ac e, whic h may or ma y not be the las t qu eue d pack et in the T X
queue.
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be word
aligned. Each co ntr ol word corresponds to one TX packet. Table 6 gives the transmit control word bit fields.
Table 6. Transmit Control Word Bit Fields
Bit Description
15 TXIC Transmit Interrupt on Completion
When this bit is set, the KS Z8851-16MLL sets the transmit interrupt after the present frame has been transmitted.
14-6 Reserved.
5-0 TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status information in the transmit
status register.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 28 Revision 2.3
The transmit byte count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 7.
Table 7. Transmit Byte Count Format
Bit Description
15-11 Reserved.
10-0
TXBC Transmit Byte Count
Hardware uses the byte count information to conserve the TX buffer memory for better utilization of the packet
memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this field. Writing a 0 value
to this field is not permitted.
The data area cont ai ns six b ytes of Des ti nat io n Address ( DA) follo wed by six bytes of Sour ce Addr ess ( S A), f oll o wed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851-16MLL do es not i ns er t its own SA. The 802. 3 Fr am e Length word ( Fr a me Type in Etherne t) is not inter pret ed b y
the KSZ8851-16MLL. It is treated transparently as data both for transmit operations.
Frame Transmitting Path Operation in TXQ
This section describes the typical register settings for transmitting packets from host processor to KSZ8851-1 6MLL with
generic bus interface. User can use the default value for most of the transmit registers. Table 8 describes all registers
which need to be set and used for transmitting single frames.
Table 8. Registers Setting for Transmit Function Bloc k
Register Name
[bit](offset) Description
TXCR[3:0](0x70)
TXCR[8:5](0x70)
Set transmit control func tion as below:
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enabl e transmitting block operatio n.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
TXMIR[12:0](0x78) The amount of free transmit memory available is represented in units of byte. The TXQ memory (6 KByte)
is used for both frame payload and control word.
TXQCR[0](0x80)
For single frame to transmit, set this bit 0 = 1(manual enqueue). the KSZ8851-16MLL wi ll enable current
TX frame prepared in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before setting up another new TX frame.
TXQCR[1](0x80)
When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR register) to CPU when
TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR
(0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before set to 1 again
RXQCR[3](0x82) Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data frame)
TXFDPR[14](0x84) Set bit 14 to enable TXQ transmit frame data pointer register increments automatically on accesses to the
data register.
IER[14][6](0x90) Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
ISR[15:0](0x92) Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
TXNTFSR[15:0](0x9E) The host CPU is used to program the total amount of TXQ buffer space which is required for next total
transmit fram es size in doubl e-word count.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 29 Revision 2.3
Driver R o u tine for Transmit Packet from Host Processor to KSZ8851-16MLL
The transmit routin e is cal le d b y the u pper la yer to tra n smit a contig uous b lock of data thr oug h th e Et her ne t cont rol ler. It is
user’s choice to decide how the transmit routine is implemented. If the Ethernet controller encounters an error while
transm itting the frame, it’s the user’s choice to decide whether the driver should attempt to retransmit the same frame or
discard the data. Figure 7 shows the step-by-step for single transmit packets from host processor to KSZ8851-16MLL.
Figure 7. Host TX Single Frame in Manual Enqueue Flo w Diagram
Host receives an Ethernet pkt from
upper layer and prepares transmit pkt
data (data, data_length, frame ID).
The transmit queue frame format is
shown in Table 5
Check if KSZ8851M TXQ
Memory size is available for this
transmit pkt?
(Read TXMIR Reg)
Write an “1” to RXQCR[3] reg to enable
TXQ write access, then Host starts
write transmit data (control word, byte
count and pkt data) to TXQ memory.
This is moving transmit data from Host
to KSZ8851M TXQ memory until whole
pkt is finished
Write an “0” to RXQCR[3] reg to end
TXQ write access
Write an “1” to TXQCR[0] reg to issue a
transmit command (manual-enqueue)
to the TXQ. The TXQ will transmit this
pkt data to the PHY port
Option to Read ISR[14] reg, it indicates
that the TXQ has completed to transmit
at least one pkt to the PHY port, then
Write “1” to clear this bit
Yes
No
Write the total amount of TXQ buffer
space which is required for next
transmit frame size in double-word
count in TXNTFSR[15:0] register
Set bit 1=1 in TXQCR register to
enable the TXQ memory available
monitor
Wait for interrupt
and check if the bit 6=1
(memory space available)
in ISR register
?
Yes No
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 30 Revision 2.3
Frame Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 9. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
Table 9. Frame Format for Receive Queue
Packet Memory Address Offset Bit 15
2nd Byte Bit 0
1st Byte
0 Status Word
(High byte and low byte need to swap in Big Endian mode. Also see description in
RXFHSR regist er.)
2 Byte Count
(High byte and low byte need to swap in Big Endian mode. Also see description in
RXFHSR regist er.)
4 - up Receive Pac ket Data
(Maximum size is 2000 bytes)
Frame Receiving Path Operation in RXQ
This section describes the typical register settings for receiving packets from KSZ8851-16MLL to host processor with
generic bus interface. User can use the default value for most of the receive registers. Table 10 describes all registers
which need to be set and used for receiving single or multiple frames.
Table 10. Registers Settings for Receive Function Block
Register Name[bit](offset)
Description
RXCR1(0x74)
RXCR2(0x76)
Set receive control function as below:
Set RXCR1[10] to enable receiving flow control. Set RXCR1[0] to enable receiving block operation.
Set receive checksum check for ICMP, UDP, TCP and IP packet.
Set receive address filtering scheme as shown in the Table 3.
RXFHSR[15:0](0x7C) This register (read only) indicates the current rec ei ved frame header status information.
RXFHBCR[11:0](0x7E) This register (read only) indicates the current received frame header byte count information.
RXQCR[12:3](0x82)
Set RXQ control function as below:
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame). Set bit 4 to automatically enable RXQ frame buffer dequeue. Set bit 5 to enab le RX frame count
threshold and read bit 10 for status. Set bit 6 to enable RX data byte count threshold and read bit 11 for
status. Set bit 7 to enable RX frame duration timer threshold and read bit 12 for status. Set bit 9 enable
RX IP header two-byte offset.
RXFDPR[14](0x86) Set bit 14 to enable RXQ address register increments automatically on accesses to the data register.
RXDTTR[15:0](0x8C) To program received frame duration timer value. When Rx frame duration in RXQ exceeds this
threshold in 1uS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851-16MLL will
generate RX interrupt in ISR[13] and indicate the status in RXQCR[12].
RXDBCTR[15:0](0x8E) To program received data byte count value. When the number of received bytes in RXQ exceeds this
threshold in byte count and bit 6 of RXQC R register is set to 1, the KSZ8851-16MLL will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[11].
IER[13](0x90) Set bit 13 to enable receive interrupt in Interrupt Enable Register.
ISR[15:0](0x92) Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
RXFCTR[15:8](0x9C) Rx frame count read only. To indicate the total received frame in RXQ frame buffer when receive
interrupt (bit 13 in ISR) occurred.
RXFCTR[7:0](0x9C) To program received frame count value. When the number of received frames in RXQ exceeds or
equals to this threshold value and bit 5 of RXQCR register is set to 1, the KSZ8851-16MLL will
generate RX interrupt in ISR[13] and indicate the status in RXQCR[10].
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 31 Revision 2.3
Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor
The software driver receives data packet frames from the KSZ8851-16MLL device either as a result of polling or an
interrupt based serv ice. When an interrupt is r eceived, the OS invok es the interr upt service rout ine that is i n the interru pt
vector table.
If your s ystem has OS support, to m inimize interrupt lockout time, the interrupt service rout ine sho uld handle at interrupt
level only those tasks that require m inimum execution time, such as error checking or device status change. The routine
should queue all the time-consuming work to transfer the packet from the KSZ8851-16 MLL RXQ into system m em ory at
task level. The following Figure 8 shows the step-by-step for receive packets from KSZ8851-1 6ML L to host pr oces s or.
Note: Each D MA read operation f rom the hos t CPU to r ead RXQ f rame buffer , the fir st read data (b yte in 8-bit bus mode,
word in 16-bit bus mode and double word in 32-bit bus mode) is dummy data and must be discarded by host CPU.
Afterward, host C PU must read each frame data to align with double word boundary at end. For example, the host CPU
has to read up to 68 bytes if received frame is 65 bytes.
Figure 8. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram
To program R x fram e c ount t hres hold in
RXFCTR, R x dat a byt e c ount t hres hold in
RXDBCTR or Rx frame duration timer
t hres hold in R XD TTR.
Enable all t hres holds bit s in R XQC R[5:7].
Set bit 4 in R XQC R t o enable R XQ fram e
buffer aut o-dequeue
Enable R x int errupt in I ER[13]
Is Rx interrupt status bit set in
ISR[13] when int errupt as s ert ed?
R x int errupt s ourc e c an be read from
bits in RXQCR[10:12]. Mas k out furt her
R x int errupt by s et bit 13 to 0 in I ER
and c lear R x int errupt s t at us by writ e 1
t o bit 13 in I SR.
Read total Rx frame count in RXFCTR
and read R x fram e header s t at us in
RXFHSR and byte count in RXFHBCR.
Write 0x000 to RXFDPR[10:0] t o c l ear
R X fram e point er
W rit e an Ò1Ó to RXQCR[3] reg t o enable
R XQ read ac c es s, the Host CPU starts
read fram e dat a from R XQ buffer.
W rit e an Ò0Ó to RXQCR[3] reg t o end
R XQ read ac c es s
Yes
Is all Rx frames read?No
Yes
No
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 32 Revision 2.3
In order to read received frames from RXQ without error, the software driver must use following steps:
When receive interrupt occ urred and software driver writes “1” to clear the RX interrupt in ISR register; the KSZ8851 will
update Receive Frame Counter (RXFCTR) Register for this interrupt.
When software driver reads back Receive Frame Count (RXFCTR) Register; the KSZ8851 will update both Receive
Frame Header Status and Byte Count Registers (RXFHSR/RXFHBCR).
When software driver reads back both Receive Frame Header Status and Byte Count Registers (RXFHSR/RXFHBCR);
the KSZ8851 will update next receive frame header status and byte count registers (RXFHSR/RXFHBCR).
EEPROM Interface
It is optiona l in the K SZ 88 5 1-16M LL to us e a n ex terna l EEP RO M. T he EED _IO ( pin 9) m us t be pulled high to us e ex terna l
EEPROM oth erw ise this pin pull ed lo w or float ing without EEPRO M.
An external s eria l EE PROM with a stan dar d micr owire bus interf ac e is used for non-volati le s torag e of inf ormation s uch as
the host MAC address. The KSZ8851-16MLL can detect if the EEPROM is a 1KB (93C46) or 4KB (93C66) EEPROM
device (the 93C46 and the 93C66 are typical EEPROM devices). The EEPROM must be organized as 16-bit mode.
If the EED_IO pin is pulled high, then the KSZ8851-16MLL performs an automatic read of the external EEPROM words
0H to 3H af ter the de-ass ertion of Reset. T he EEPROM valu es are placed i n certain host -accessibl e registers . EEPROM
read/write functions can also be performed by software read/writes to the EEPCR (0x22) registers.
The KSZ8851-16MLL EEPROM format is given in Table 11.
Table 11. KSZ8851-16MLL EEPROM Format
WORD 15 8 7 0
0H Reserved
1H Host MAC Address Byte 2 Host MAC Address Byte 1
2H Host MAC Address Byte 4 Host MAC Address Byte 3
3H Host MAC Address Byte 6 Host MAC Address Byte 5
4H – 6H Reserved
7H – 3FH Not used for KSZ8851-16MLL (av ailab le f or user to use)
Loopback Support
The KSZ8851-16MLL provides two loopback modes, one is near-end (rem ote) loopback to support for remote diagnostic
of failure at line side, and the other is far-end (local) loopback to support for local diagnostic of failure at host side. In
loopback mode, the speed at the PHY port will be set to 100BASE-TX full-duplex mode.
Near-End (Remote ) L o o pback
Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8851-16MLL. The loopback path starts at the PHY
port’s receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit
outputs (TXP1/TXM1).
Bit [9] of r egist er P1 SCL M D ( 0x F4) is us ed to ena bl e near -en d lo op bac k. The po r ts 1 near -en d lo opb ack path is i llust ra ted
in Figure 9.
Far-End (Local) L o o p b ack
Far-end (Local) loopback is conducted at Host of the KSZ8851-16MLL. The loopback path starts at the host port’s
transmit inputs (Tx data), wraps around at the PHY port’s PMD/PMA, and ends at the host port’s receive outputs (Rx data)
Bit [14] of register P1MBCR (0xE4) is used to enable far-end loopback at host side. The host far-end loopback path is
illustrated in Fi gure 9.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 33 Revision 2.3
Figure 9. PHY Port 1 Near-End (Remote) and Host Far-End (Local) Loopback Paths
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 34 Revision 2.3
CPU Interface I/O Registers
The KSZ885 1-16MLL pro vides an SRAM-lik e asynchronous bus int erface for the CPU to acc ess its internal I/O r egisters.
I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for
configuring operational settings, reading or writing control, status information, and transferring packets. The KSZ8851-
16MLL can be program med to interf ace with either Big-Endian or Little-End ian pr oc es s or.
I/O Registers
The f ollowing I /O s pac e mapping ta bles ap ply to 8- or 16-bit bus int er f ac es . Depe ndi ng up on th e bus mode selecte d, eac h
I/O access can be performed the following operations:
In 8-bit bus mode, there are 256 address locations which is based on SD[7:0] for address when CMD=1. The SD[7:0] is
for data when CMD=0.
In 16-bit bus mode, there are 64 address locations which is based on SD[7:2] ([1:0] is “Do Not Care”) for address and
SD[15:12] for Byte Enable BE[3:0] (either one byte or two bytes) when CMD=1. The SD[15:0] is for data when CMD=0.
Interna l I/O Registers Space Mapping
I/O Register Offset Location Register
Name Default Value Description
16-Bit 8-Bit
0x00 - 0x01 0x00
0x01 Reserved Do Not Care None
0x02 - 0x03 0x02
0x03
0x04 - 0x05 0x04
0x05 Reserved Do Not Care None
0x06 - 0x07 0x06
0x07
0x08 - 0x09 0x08
0x09 CCR Read Only Chip Configuration Register [7:0]
Chip Configuration Register [15:8]
0x0A - 0x0B 0x0A
0x0B Reserved Do Not Care None
0x0C - 0x0D 0x0C
0x0D Reserved Do Not Care None
0x0E - 0x0F 0x0E
0x0F
0x10 - 0x11 0x10
0x11 MARL - MAC Address Register Low [7:0]
MAC Address Register Low [15:8]
0x12 - 0x13 0x12
0x13 MARM - MAC Address Register Middle [7:0]
MAC Address Register Middle [15:8]
0x14 - 0x15 0x14
0x15 MARH - MAC Address Register High [7:0]
MAC Address Register High [15:8]
0x16 - 0x17 0x16
0x17 Reserved Do Not Care None
0x18 - 0x19 0x18
0x19 Reserved Do Not Care None
0x1A - 0x1B 0x1A
0x1B
0x1C - 0x1D 0x1C
0x1D Reserved Do Not Care None
0x1E - 0x1F 0x1E
0x1F
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 35 Revision 2.3
Internal I/O Registers Space Mapping (Co n tinued)
I/O Register Offset Location Register
Name Default Value Description
16-Bit 8-Bit
0x20 - 0x21 0x20
0x21 OBCR 0x0000 On-Chip Bus Control Register [7:0]
On-Chip Bus Control Register [15:8]
0x22 - 0x23 0x22
0x23 EEPCR 0x0000 EEPROM Control Register [7:0]
EEPROM Control Register [15:8]
0x24 - 0x25 0x24
0x25 MBIR 0x1010 Memory BIST Info Register [7:0]
Memory BIST Info Register [15:8]
0x26 - 0x27 0x26
0x27 GRR 0x0000 Global Reset Register [7:0]
Global Reset Register [15:8]
0x28 - 0x29 0x28
0x29 Reserved Do Not Care None
0x2A - 0x2B 0x2A
0x2B WFCR 0x0000 Wakeup Frame Control Register [7:0]
Wakeup Frame Control Register [15:8]
0x2C - 0x2D 0x2C
0x2D Reserved Do Not Care
0x2E - 0x2F 0x2E
0x2F
0x30 - 0x31 0x30
0x31 WF0CRC0 0x0000 Wakeup Frame 0 CRC0 Register [7:0]
Wakeup Frame 0 CRC0 Register [15:8]
0x32 - 0x33 0x32
0x33 WF0CRC1 0x0000 Wakeup Frame 0 CRC1 Register [7:0]
Wakeup Frame 0 CRC1 Register [15:8]
0x34 - 0x35 0x34
0x35 WF0BM0 0x0000 Wakeup Frame 0 Byte Mask 0 Register [7:0]
Wakeup Frame 0 Byte Mask 0 Register [15:8]
0x36 - 0x37 0x36
0x37 WF0BM1 0x0000 W akeup Frame 0 Byte Mask 1 Register [7:0]
Wakeup Frame 0 Byte Mask 1 Register [15:8]
0x38 - 0x39 0x38
0x39 WF0BM2 0x0000 Wakeup Frame 0 Byte Mask 2 Register [7:0]
Wakeup Frame 0 Byte Mask 2 Register [15:8]
0x3A - 0x3B 0x3A
0x3B WF0BM3 0x0000 Wakeup Frame 0 Byte Mask 3 Register [7:0]
Wakeup Frame 0 Byte Mask 3 Register [15:8]
0x3C - 0x3D 0x3C
0x3D Reserved Do Not Care None
0x3E - 0x3F 0x3E
0x3F
0x40 - 0x41 0x40
0x41 WF1CRC0 0x0000 Wakeup Frame 1 CRC0 Register [7:0]
Wakeup Frame 1 CRC0 Register [15:8]
0x42 - 0x43 0x42
0x43 WF1CRC1 0x0000 Wakeup Frame 1 CRC1 Register [7:0]
Wakeup Frame 1 CRC1 Register [15:8]
0x44 - 0x45 0x44
0x45 WF1BM0 0x0000 W akeup Frame 1 Byte Mask 0 Register [7:0]
Wakeup Frame 1 Byte Mask 0 Register [15:8]
0x46 - 0x47 0x46
0x47 WF1BM1 0x0000 W akeup Frame 1 Byte Mask 1 Register [7:0]
Wakeup Frame 1 Byte Mask 1 Register [15:8]
0x48 - 0x49 0x48
0x49 WF1BM2 0x0000 W akeup Frame 1 Byte Mask 2 Register [7:0]
Wakeup Frame 1 Byte Mask 2 Register [15:8]
0x4A - 0x4B 0x4A
0x4B WF1BM3 0x0000 Wakeup Frame 1 Byte Mask 3 Register [7:0]
Wakeup Frame 1 Byte Mask 3 Register [15:8]
0x4C - 0x4D 0x4C
0x4D Reserved Do Not Care None
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 36 Revision 2.3
Interna l I/O Registers Space Mapping (Co n tinued)
I/O Register Offset Location Register
Name Default Value Description
16-Bit 8-Bit
0x4E - 0x4F 0x4E
0x4F
0x50 - 0x51 0x50
0x51 WF2CRC0 0x0000 Wakeup Frame 2 CRC0 Register [7:0]
Wakeup Frame 2 CRC0 Register [15:8]
0x52 - 0x53 0x52
0x53 WF2CRC1 0x0000 Wakeup Frame 2 CRC1 Register [7:0]
Wakeup Frame 2 CRC1 Register [15:8]
0x54 - 0x55 0x54
0x55 WF2BM0 0x0000 Wakeu p Frame 2 Byte Mask 0 Register [7:0]
Wakeup Frame 2 Byte Mask 0 Register [15:8]
0x56 - 0x57 0x56
0x57 WF2BM1 0x0000 Wakeu p Frame 2 Byte Mask 1 Register [7:0]
Wakeup Frame 2 Byte Mask 1 Register [15:8]
0x58 - 0x59 0x58
0x59 WF2BM2 0x0000 Wakeu p Frame 2 Byte Mask 2 Register [7:0]
Wakeup Frame 2 Byte Mask 2 Register [15:8]
0x5A - 0x5B 0x5A
0x5B WF2BM3 0x0000 Wakeup Frame 2 Byte Mask 3 Register [7:0]
Wakeup Frame 2 Byte Mask 3 Register [15:8]
0x5C - 0x5D 0x5C
0x5D Reserved Do Not Care None
0x5E - 0x5F 0x5E
0x5F
0x60 - 0x61 0x60
0x61 WF3CRC0 0x0000 Wakeup Frame 3 CRC0 Register [7:0]
Wakeup Frame 3 CRC0 Register [15:8]
0x62 - 0x63 0x62
0x63 WF3CRC1 0x0000 Wakeup Frame 3 CRC1 Register [7:0]
Wakeup Frame 3 CRC1 Register [15:8]
0x64 - 0x65 0x64
0x65 WF3BM0 0x0000 Wakeup Frame 3 Byte Mask 0 Register [7:0]
Wakeup Frame 3 Byte Mask 0 Register [15:8]
0x66 - 0x67 0x66
0x67 WF3BM1 0x0000 Wakeu p Frame 3 Byte Mask 1 Register [7:0]
Wakeup Frame 3 Byte Mask 1 Register [15:8]
0x68 - 0x69 0x68
0x69 WF3BM2 0x0000 Wakeu p Frame 3 Byte Mask 2 Register [7:0]
Wakeup Frame 3 Byte Mask 2 Register [15:8]
0x6A - 0x6B 0x6A
0x6B WF3BM3 0x0000 Wakeup Frame 3 Byte Mask 3 Register [7:0]
Wakeup Frame 3 Byte Mask 3 Register [15:8]
0x6C - 0x6D 0x6C
0x6D Reserved Do Not Care None
0x6E - 0x6F 0x6E
0x6F
0x70 - 0x71 0x70
0x71 TXCR 0x0000 Transmit Control Register [7:0]
Transmit Control Register [15:8]
0x72 - 0x73 0x72
0x73 TXSR 0x0000 Transmit Status Register [7:0]
Transmit Status Register [15:8]
0x74 - 0x75 0x74
0x75 RXCR1 0x0800 Receive Control Register 1 [7:0]
Receive Control Register 1 [15:8]
0x76 - 0x77 0x76
0x77 RXCR2 0x0004 Receive Control Register 2 [7:0]
Receive Control Register 2 [15:8]
0x78 - 0x79 0x78
0x79 TXMIR 0x0000 TX Q Me mory Information Register [7:0]
TXQ Memory Information Register [15:8]
0x7A - 0x7B 0x7A
0x7B Reserved Do Not Care None
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 37 Revision 2.3
Interna l I/O Registers Space Mapping (Co n tinued)
I/O Register Offset Location Register
Name Default Value Description
16-Bit 8-Bit
0x7C - 0x7D 0x7C
0x7D RXFHSR 0x0000 Receive Frame Header Status Register [7:0]
Receive Frame Header Status Register [15:8]
0x7E - 0x7F 0x7E
0x7F RXFHBCR 0x0000 Receive Frame Header Byte Count Register [7:0]
Receive Frame Header Byte Count Register [15:8]
0x80 - 0x81 0x80
0x81 TXQCR 0x0000 TXQ Command Register [7:0]
TXQ Command Register [15:8]
0x82 - 0x83 0x82
0x83 RXQCR 0x0000 RXQ Command Register [7:0]
RXQ Comma nd Register [15:8]
0x84 - 0x85 0x84
0x85 TXFDPR 0x0000 TX Frame Data Pointer Register [7:0]
TX Frame Data Pointer Register [15:8]
0x86 - 0x87 0x86
0x87 RXFDPR 0x0000 RX Frame Data Pointer Register [7:0]
RX Frame Data Pointer Register [15:8]
0x88 - 0x89 0x88
0x89 Reserved Do Not Care None
0x8A - 0x8B 0x8A
0x8B
0x8C - 0x8D 0x8C
0x8D RXDTTR 0x0000 RX Duration Timer Threshold Register [7:0]
RX Duration Timer Threshold Register [15:8]
0x8E - 0x8F 0x8E
0x8F RXDBCTR 0x0000 RX Data Byte Count Threshold Register [7:0]
RX Data Byte Count Threshold Register [15:8]
0x90 - 0x91 0x90
0x91 IER 0x0000 Interrupt Enable Register [7:0]
Interrupt Enable Register [15:8]
0x92 - 0x93 0x92
0x93 ISR 0x0300 Interrupt Status Regis ter [7:0]
Interrupt Status Register [15:8]
0x94 - 0x95 0x94
0x95 Reserved Do Not Care None
0x96 - 0x97 0x96
0x97
0x98 - 0x99 0x98
0x99 Reserved Do Not Care None
0x9A - 0x9B 0x9A
0x9B
0x9C - 0x9D 0x9C
0x9D RXFCTR 0x0000 RX Frame Count & Threshold Register [7:0]
RX Frame Count & Threshold Register [15:8]
0x9E - 0x9F 0x9E
0x9F TXNTFSR 0x0000 TX Next Total Frames Size Register [7:0]
TX Next Total Frames Size Register [15:8]
0xA0 - 0xA1 0xA0
0xA1 MAHTR0 0x0000 MAC Address Hash Table Register 0 [7:0]
MAC Address Hash Table Register 0 [15:8]
0xA2 - 0xA3 0xA2
0xA3 MAHTR1 0x0000 MAC Address Hash Table Register 1 [7:0]
MAC Address Hash Table Register 1 [15:8]
0xA4 - 0xA5 0xA4
0xA5 MAHTR2 0x0000 MAC Address Hash Table Register 2 [7:0]
MAC Address Hash Table Register 2 [15:8]
0xA6 - 0xA7 0xA6
0xA7 MAHTR3 0x0000 MAC Address Hash Table Register 3 [7:0]
MAC Address Hash Table Register 3 [15:8]
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 38 Revision 2.3
Interna l I/O Registers Space Mapping (Co n tinued)
I/O Register Offset Location Register
Name Default Value Description
16-Bit 8-Bit
0xA8 - 0xA9 0xA8
0xA9 Reserved Do Not Care None
0xAA - 0xAB 0xAA
0xAB
0xAC - 0xAD 0xAC
0xAD Reserved Do Not Care None
0xAE - 0xAF 0xAE
0xAF
0xB0 - 0xB1 0xB0
0xB1 FCLWR 0x0500 Flow Control Low Watermark Register [7:0]
Flow Control Low Watermark Register [15:8]
0xB2 - 0xB3 0xB2
0xB3 FCHWR 0x0300 Flow Control High Water mark Register [7:0]
Flow Control High Watermark Register [15:8]
0xB4 - 0xB5 0xB4
0xB5 FCOWR 0x0040 Flow Control Overrun Watermark Register [7:0]
Flow Control Overrun Watermark Register [15:8]
0xB6 - 0xB7 0xB6
0xB7 Reserved Do Not Care None
0xB8 - 0xB9 0xB8
0xB9 Reserved Do Not Care None
0xBA - 0xBB 0xBA
0xBB
0xBC - 0xBD 0xBC
0xBD Reserved Do Not Care None
0xBE - 0xBF 0xBE
0xBF
0xC0 - 0xC1 0xC0
0xC1 CIDER 0x887x Chip ID and Enable Register [7:0]
Chip ID and Enable Register [15:8]
0xC2 - 0xC3 0xC2
0xC3 Reserved Do Not Care None
0xC4 - 0xC5 0xC4
0xC5 Reserved Do Not Care None
0xC6 - 0xC7 0xC6
0xC7 CGCR 0x0835 Chip Global Control Register [7:0]
Chip Global Control Register [15:8]
0xC8 - 0xC9 0xC8
0xC9 IACR 0x0000 Indirect Access Control Register [7:0]
Indirect Access Control Register [15:8]
0xCA - 0xCB 0xCA
0xCB Reserved Do Not Care None
0xCC - 0xCD 0xCC
0xCD Reserved Do Not Care None
0xCE - 0xCF 0xCE
0xCF
0xD0 - 0xD1 0xD0
0xD1 IADLR 0x0000 Indirect Access Data Low Register [7:0]
Indirect Access Data Low Register [15:8]
0xD2 - 0xD3 0xD2
0xD3 IADHR 0x0000 Indirect Access Data High Register [7:0]
Indirect Access Data High Register [15:8]
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 39 Revision 2.3
Interna l I/O Registers Space Mapping (Co n tinued)
I/O Register Offset Location Register
Name Default Value Description
16-Bit 8-Bit
0xD4 - 0xD5 0xD4
0xD5 PMECR 0x0080 Power Management Event Control Register [7:0]
Power Management Event Control Register [15:8]
0xD6 - 0xD7 0xD6
0xD7 GSWUTR 0X080C Go-Sleep & Wake-Up Time Register [7:0]
Go-Sleep & Wake-Up Time Register [15:8]
0xD8 - 0xD9 0xD8
0xD9 PHYRR 0x0000 PHY Reset Register [7:0]
PHY Reset Register [15:8]
0xDA - 0xDB 0xDA
0xDB Reserved Do Not Care None
0xDC - 0xDD 0xDC
0xDD Reserved Do Not Care None
0xDE - 0xDF 0xDE
0xDF
0xE0 - 0xE1 0xE0
0xE1 Reserved Do Not Care None
0xE2 - 0xE3 0xE2
0xE3
0xE4 - 0xE5 0xE4
0xE5 P1MBCR 0x3120 PHY 1 MII-Register Basic Control Register [7:0]
PHY 1 MII-Register Basic Control Register [15:8]
0xE6 - 0xE7 0xE6
0xE7 P1MBSR 0x7808 PHY 1 MII-Register Basic Status Register [7:0]
PHY 1 MII-Register Basic Status Register [15:8]
0xE8 - 0xE9 0xE8
0xE9 PHY1ILR 0x1430 PHY 1 PHY ID Low Register [7:0]
PHY 1 PHY ID Low Register [15:8]
0xEA - 0xEB 0xEA
0xEB PHY1IHR 0x0022 PHY 1 PHY ID High Register [7:0]
PHY 1 PHY ID High Register [15:8]
0xEC - 0xED 0xEC
0xED P1ANAR 0x05E1 PHY 1 Auto-Negotiation Advertisement Register [7:0]
PHY 1 Auto-Negotiation Advertisement Register [15:8]
0xEE - 0xEF 0xEE
0xEF P1ANLPR 0x0001 PHY 1 Auto-Negotiation Link Partner Ability Register [7:0]
PHY 1 Auto-Negotiation Link Partner Ability Register [15:8]
0xF0 - 0xF1 0xF0
0xF1 Reserved Do Not Care None
0xF2 - 0xF3 0xF2
0xF3
0xF4 - 0xF5 0xF4
0xF5 P1SCLMD 0x0000 Port 1 PHY Special Control/Status, LinkMD® [7:0]
Port 1 PHY Special Control/Status, LinkMD® [15:8]
0xF6 - 0xF7 0xF6
0xF7 P1CR 0x00FF Port 1 Control Register [7:0]
Port 1 Control Register [15:8]
0xF8 - 0xF9 0xF8
0xF9 P1SR 0x8080 Port 1 Status Regi ster [7:0]
Port 1 Status Register [15:8]
0xFA - 0xFB 0xFA
0xFB Reserved Do Not Care None
0xFC - 0xFD 0xFC
0xFD Reserved Do Not Care None
0xFE - 0xFF 0xFE
0xFF
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 40 Revision 2.3
Register Map: MAC, PHY, and QMU
Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes
unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these
reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definition
RO = Read only.
WO = Write only.
RW = Read/Write.
W1C = Write 1 to clear (writing a “1” to clear this bit).
0x00 – 0x07: Res erv ed
Chip Configuration Register (0x08 – 0x09): CCR
This register indicates the chip configuration mode based on strapping and bonding options.
Bit Default Value R/W Description
15-11 - RO Reserved.
10 - RO Bus Endian mode
The EESK (pin 10) value is latched into this bit druing power-up/reset.
0: Bus in Big Endian mode, 1: Bus in Little Endian mode.
9 - RO EEPROM presence
The EED_IO (pin 9) value is latched into this bit druing power-up/reset.
0: No external EEPROM, 1: Use external EEPROM.
8 0 RO Reserved.
7 - RO 8-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 8-bit bus mode operation, 1: In 8-bit bus mode operation.
6 - RO 16-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 16-bit bus mode operation, 1: In 16-bit bus mode operation.
5 0 RO Reserved.
4 - RO Shared data bus mode for data and address
0: Data and address bus are seperated.
1: Data and address bus are shared.
3 0 RO Reserved.
2 0 RO Reserved.
1 - RO 48-Pin Chip Package
To indicate chip pack age is 48 -pin.
0: No, 1: Yes.
0 0 RO Reserved.
0x0A – 0x0F: Reserved
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 41 Revision 2.3
Host MAC Ad dress Registers: MARL, MARM, and MARH
These Host MAC address registers are loaded starting at word location 0x1 of the EEPROM upon hardware reset. The
software driver can read or write these registers value, but it will not modify the original Host MAC address value in the
EEPROM. These six bytes of Host MAC address in external EEPROM are loaded to these three registers as mapping
below:
MARL[15 :0] = EEPRO M 0x 1(MAC Byte 2 and 1)
MARM[15 :0] = EEPRO M 0 x 2(MAC Byte 4 and 3)
MARH[15: 0] = EEPRO M 0x 3(MAC Byte 6 and 5)
The Host MAC address is used to define the individual destination address that the KSZ8851-16MLL responds to when
receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are
received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the
actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101.
These three registers value for Host MAC address 01:23:45:67:89:AB will be held as below:
MARL[15:0] = 0x89AB
MARM[15:0] = 0x4567
MARH[15:0] = 0x0123
Host MAC Address Register Low (0x10 – 0x11): MARL
The following table shows the register bit fields for Low word of Host MAC address.
Bit Default Value R/W Description
15-0 - RW MARL MAC Address Low
The least significant word of the MAC address.
Host MAC Address Register Middle (0x12 – 0x 13) : MARM
The following table shows the register bit fields for Middle word of Host MAC address.
Bit Default Value R/W Description
15-0 - RW MARM MAC Address Middle
The middle word of the MAC address.
Host MAC Address Register High (0x14 – 0x15): MARH
The following table shows the register bit fields for High word of Host MAC address.
Bit
Default Value
R/W
Description
15-0 - RW MARH MAC Address High
The most significant word of the MAC address.
0x16 – 0x1F: Reserved
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 42 Revision 2.3
On-Chip Bus Con trol Register (0x20 – 0x21): OBCR
This r egister cont rols the on-chip bus clock speed for the KSZ 8851-16MLL . The default of the on-c hip bus c lock s peed is
125MHz. W hen the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best
performance.
Bit Default Value R/W Description
15-7 - RW Reserved.
6 0 RW Output Pin Drive Strength
Bi-directional or output pad drive strength selection.
0: 8 mA; 1: 16 mA
5-3 - RW Reserved.
2 0 RW On-Chip Bus Clock Selection
0: 125MHz (default setting is divided by 1, Bit[1:0]=00)
1: NA (reserved)
1-0 0x0 RW
On-Chip Bus Clock Divider Selection
00: Divided by 1; 01: Divided by 2; 10: Divided by 3; 11: NA (reserved).
For example to contol the bus clock speed as below:
If Bit 2 = 0 and this value is set 00 to select 125MHz.
If Bit 2 = 0 and this value is set 01 to select 62.5MHz.
EEPROM Control Register (0x22 – 0x23): EEPCR
To support an external EEPROM, pulled-up the EED_IO pin to High; otherwise, it is pulled-down to Low. If an external
EEPROM is not used, the software programs the host MAC address. If an EEPROM is used in the design, t he chip host
MAC address is loaded from the EEPROM immediately after reset. The KSZ8851-16MLL allows the software to access
(read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the
EEPROM Sof t ware Acc es s bit is set.
Bit Default Value R/W Description
15-6 - RO Reserved.
5 0 WO EESRWA EEPROM Software Read or Write Access
0: software read enable to access EEPROM when software access enabled (bit4=1)
1: software write enable to access EEPROM when software access enabled (bit4=1).
4 0 RW EESA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable softw are to acces s EEP ROM.
3 - RO EESB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EED_IO pin.
2-0 0x0 RW
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EED_IO pin.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 43 Revision 2.3
Memory BIST Info Register (0x24 – 0x25): MBIR
This register indicates the build-in self-test result for both TX and RX memories after power-up/reset.
Bit Default Value R/W Description
15-13 0x0 RO Reserved.
12 - RO TXMBF TX Memory BIST Test Finish
When set, it indicates the Memory Built In Self Test completion for the TX Memory.
11 - RO TXMBFA TX Memory BIST Test Fail
When set, it indicates the TX Memory Built In Self Test has failed.
10-8 - RO TXMBFC TX Memory BIST Test Fail Count
To indicate the TX Memory Built In Self Test failed count
7-5 - RO Reserved.
4 - RO RXMBF RX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the RX Memory.
3 - RO RXMBFA RX Memory Bist Fa il
When set, it indicates the RX Memory Built In Self Test has failed.
2-0 - RO RXMBFC RX Memory BIST Test Fail Count
To indicate the RX Memory Built In Self Test failed count.
Global Reset Register (0x26 – 0x27): GRR
This register controls the global and QMU reset functions with information programmed by the CPU.
Bit Default Value R/W Description
15-2 0x0000 RO
Reserved.
1 0 RW
QMU Module Soft Reset
1: Software reset is active to clear both TXQ and RXQ memories.
0: Software reset is ina ctiv e.
QMU software reset will flush out all TX/RX packet data inside the TXQ and RXQ memories
and reset all QMU registers to default value.
0 0 RW
Global Soft Reset
1: Software reset is ac tive.
0: Software reset is ina ctiv e.
Global software reset will affect PHY, MAC, QMU, DMA, and the switch core, all registers
value are set to default value.
0x28 – 0x29: Res erv ed
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 44 Revision 2.3
Wakeup Frame Control Register (0x2A – 0x2B): WFCR
This register holds control information programmed by the CPU to control the wakeup frame function.
Bit Default Value R/W Description
15-8 0x00 RO Reserved.
7 0 RW
MPRXE
Magic Packet RX Enable
When set, it enables the magi c pack et patter n dete cti on.
When reset, the magi c pack et pattern detection is disabl ed.
6-4 0x0 RO Reserved.
3 0 RW
WF3E
Wakeup Frame 3 Enable
When set, it enables the wakeup frame 3 pattern detection.
When reset, the wakeup frame 3 pattern detection is disabled.
2 0 RW
WF2E
Wakeup Frame 2 Enable
When set, it enables the wakeup frame 2 pattern detection.
When reset, the wakeup frame 2 pattern detection is disabled.
1 0 RW
WF1E
Wakeup Frame 1 Enable
When set, it enables the wakeup frame 1 pattern detection.
When reset, the wakeup frame 1 pattern de tection is disabled.
0 0 RW
WF0E
Wakeup Frame 0 Enable
When set, it enables the wakeup frame 0 pattern detection.
When reset, the wakeup frame 0 pattern detection is disabled.
0x2C – 0x2F: Reserved
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0
This register contains the expected CRC values of the wakeup frame 0 pattern.
The value of the CRC calc ulated is bas ed on the IEE E 802.3 Ether net stand ard; it is tak en over the b ytes specified in the
wakeup byte mask registers.
Bit Default Value R/W Description
15-0 0x0000 RW WF0CRC0
Wakeup Frame 0 CRC (lower 16 bits)
The expec ted CRC value of a wakeup frame 0 pattern.
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1
This register contains the expected CRC values of the wakeup frame 0 pattern.
The value of the CRC c alculated is based on the I EEE 802.3 Et hernet st andard; it is t aken over th e bytes specif ied in the
wakeup byte mask registers.
Bit Default Value R/W Description
15-0 0x0000 RW WF0CRC1
Wakeup Frame 0 CRC (upper 16 bits).
The expec ted CRC value of a wakeup frame 0 pattern.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 45 Revision 2.3
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0
This register contains the first 16 bytes mask values of the wakeup frame 0 pattern. Setting bit 0 selects the first byte of
the wakeup frame 0, setting bit 15 selects the 16th byte of the wakeup frame 0.
Bit Default Value R/W Description
15-0 0x0000 RW WF0BM0
Wakeup Frame 0 Byte Mask 0
The first 16 bytes mask of a wakeup frame 0 pattern.
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1
This regis ter contains the n ext 16 b ytes mask values of the wakeup f ram e 0 pattern. Setti ng bit 0 s elects the 17th b yte of
the wakeup frame 0. Setting bit 15 selects the 32nd byte of the wakeup frame 0.
Bit Default Value R/W Description
15-0 0x0000 RW WF0BM1
Wakeup Frame 0 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a wakeup frame 0 pattern.
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2
This r egister conta ins the nex t 16 bytes m ask values o f the wak eup fram e 0 pattern. Sett ing bit 0 se lects the 33r d byte of
the wakeup frame 0. Setting bit 15 selects the 48th byte of the wakeup frame 0.
Bit Default Value R/W Description
15-0 0x0000 RW WF0BM2
Wakeup Frame 0 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a wakeup frame 0 pattern.
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3
This r egister contains the last 16 bytes mas k values of the wakeup f rame 0 patt ern. Setting b it 0 selects t he 49th b yte of
the wakeup frame 0. Setting bit 15 selects the 64th byte of the wakeup frame 0.
Bit Default Value R/W Description
15-0 0x0000 RW WF0BM3
Wakeup Frame 0 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a wakeup frame 0 pattern.
0x3C – 0x3F: Reserved
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0
This register contains the expected CRC values of the wakeup frame 1 pattern.
The value of the CRC calc ulated is bas ed on the IEE E 802.3 Ether net stand ard; it is tak en over the b ytes specified in the
wakeup byte mask registers.
Bit Default Value R/W Description
15-0 0x0000 RW WF1CRC0
Wakeup frame 1 CRC (lower 16 bits).
The expec ted CRC value of a wakeup frame 1 pattern.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 46 Revision 2.3
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1
This register contains the expected CRC values of the wakeup frame 1 pattern.
The value of the CRC calc ulated is bas ed on the IEE E 802.3 Ether net stand ard, it is tak en over the b ytes specified in the
wakeup byte mask registers.
Bit Default Value R/W Description
15-0 0x0000 RW WF1CRC1
Wakeup frame 1 CRC (upper 16 bits).
The expec ted CRC value of a wakeup frame 1 pattern.
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0
This register contains the first 16 bytes mask values of the wakeup frame 1 pattern. Setting bit 0 selects the first byte of
the wakeup frame 1, setting bit 15 selects the 16th byte of the wakeup frame 1.
Bit Default Value R/W Description
15-0 0x0000 RW WF1BM0
Wakeup frame 1 Byte Mask 0.
The first 16 bytes mask of a wakeup frame 1 pattern.
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1
This r egister cont ains the n ext 16 b ytes mask values of the wakeup f ram e 1 pattern. Set ting bit 0 s elects the 17th b yte of
the wakeup frame 1. Setting bit 15 selects the 32nd byte of the wakeup frame 1.
Bit Default Value R/W Description
15-0 0x0000 RW WF1BM1
Wakeup frame 1 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a wakeup frame 1 pattern.
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2
This r egister conta ins the nex t 16 bytes m ask values o f the wak eup fram e 1 pattern. Sett ing bit 0 se lects the 33r d byte of
the wakeup frame 1. Setting bit 15 selects the 48th byte of the wakeup frame 1.
Bit Default Value R/W Description
15-0 0x0000 RW WF1BM2
Wakeup frame 1 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a wakeup frame 1 pattern.
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3
This r egister contains the last 16 bytes mas k values of the wakeup fr ame 1 pattern. Setting bit 0 selects t he 49th b yte of
the wakeup frame 1. Setting bit 15 selects the 64th byte of the wakeup frame 1.
Bit Default Value R/W Description
15-0 0x0000 RW WF1BM3
Wakeup frame 1 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a wakeup frame 1 pattern.
0x4C – 0x4F: Reserved
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0
This register contains the expected CRC values of the wakeup frame 2 pattern.
The value of the CRC calc ulated is bas ed on the IEE E 802.3 Ether net stand ard, it is tak en over the b ytes specified in the
wakeup byte mask registers.
Bit Default Value R/W Description
15-0 0x0000 RW WF2CRC0
Wakeup frame 2 CRC (lower 16 bits). The expected CRC value of a wakeup frame 2
pattern.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 47 Revision 2.3
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1
This register contains the expected CRC values of the wakeup frame 2 pattern.
The value of the CRC calc ulated is bas ed on the IEE E 802.3 Ether net stand ard, it is tak en over the b ytes specified in the
wakeup byte mask registers.
Bit Default Value R/W Description
15-0 0x0000 RW WF2CRC1
Wakeup frame 2 CRC (upper 16 bits). The expected CRC value of a wakeup fram e 2
pattern.
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0
This register contains the first 16 bytes mask values of the wakeup frame 2 pattern. Setting bit 0 selects the first byte of
the wakeup frame 2, setting bit 15 selects the 16th byte of the wakeup frame 2.
Bit Default Value R/W Description
15-0 0x0000 RW WF2BM0
Wakeup frame 2 Byte Mask 0. The first 16 bytes mask of a wakeup frame 2 pattern.
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1
This r egister cont ains the n ext 16 b ytes mask values of the wakeup f ram e 2 pattern. Set ting bit 0 s elects the 17th b yte of
the wakeup frame 2. Setting bit 15 selects the 32nd byte of the wakeup frame 2.
Bit Default Value R/W Description
15-0 0x0000 RW WF2BM1
Wakeup frame 2 Byte Mask 1. The next 16 bytes mask covering bytes 17 to 32 of a wakeup
frame 2 pattern.
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2
This r egister conta ins the nex t 16 bytes m ask values o f the wak eup fram e 2 pattern. Sett ing bit 0 se lects the 33r d byte of
the wakeup frame 2. Setting bit 15 selects the 48th byte of the wakeup frame 2.
Bit Default Value R/W Description
15-0 0 RW WF2BM2
Wakeup frame 2 Byte Mask 2. The next 16 bytes mask covering bytes 33 to 48 of a wakeup
frame 2 pattern.
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3
This r egister contains the last 16 bytes mas k values of the wakeup fr ame 2 pattern. Setting bit 0 selects t he 49th b yte of
the wakeup frame 2. Setting bit 15 selects the 64th byte of the wakeup frame 2.
Bit Default Value R/W Description
15-0 0 RW WF2BM3
Wakeup frame 2 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a wakeup
frame 2 pattern.
0x5C – 0x5F: Reserved
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0
This r egister cont ains the e xpec ted CRC val ues of the wak eup fram e 3 pattern. T he value of the CRC c alculated is based
on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wakeup byte mask registers.
Bit
Default Value
R/W
Description
15-0 0 RW WF3CRC0
Wakeup frame 3 CRC (lower 16 bits). The expected CRC value of a wakeup frame 3
pattern.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 48 Revision 2.3
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1
This r egister cont ains the e xpec ted CRC val ues of the wak eup fram e 3 pattern. T he value of the CRC c alculated is based
on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wakeup byte mask registers.
Bit Default Value R/W Description
15-0 0 RW WF3CRC1
Wakeup frame 3 CRC (upper 16 bits). The expected CRC value of a wakeup frame 3
pattern.
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0
This register contains the first 16 bytes mask values of the wakeup frame 3 pattern. Setting bit 0 selects the first byte of
the wakeup frame 3, setting bit 15 selects the 16th byte of the wakeup frame 3.
Bit Default Value R/W Description
15-0 0 RW WF3BM0
Wakeup Frame 3 Byte Mask 0. The first 16 byte mask of a wakeup frame 3 pattern.
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1
This r egister cont ains the nex t 16 bytes mask values of the wakeup fr ame 3 patte rn. Setti ng bit 0 sel ects the 17th b yte of
the wakeup frame 3. Setting bit 15 selects the 32nd byte of the wakeup frame 3.
Bit Default Value R/W Description
15-0 0 RW WF3BM1
Wakeup Frame 3 Byte Mask 1. The next 16 bytes mask covering bytes 17 to 32 of a
wakeup frame 3 pattern.
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2
This r egister conta ins the nex t 16 bytes m ask values o f the wak eup fram e 3 pattern. Sett ing bit 0 se lects the 33rd b yte of
the wakeup frame 3. Setting bit 15 selects the 48th byte of the wakeup frame 3.
Bit Default Value R/W Description
15-0 0 RW WF3BM2
Wakeup Frame 3 Byte Mask 2. The next 16 bytes mask covering bytes 33 to 48 of a
wakeup frame 3 pattern.
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3
This r egister contains the last 16 bytes mas k values of the wakeup fr ame 3 pattern. Setting bit 0 selects t he 49th b yte of
the wakeup frame 3. Setting bit 15 selects the 64th byte of the wakeup frame 3.
Bit Default Value R/W Description
15-0 0 RW WF3BM3
Wakeup Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a
wakeup frame 3 pattern.
0x6C – 0x6F: Reserved
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 49 Revision 2.3
Transmit Control Register (0x70 – 0x71): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bit Default Value R/W Description
15-9 - RO Reserved.
8 0x0 RW TCGICMP Transmit Checksum Generation for ICMP
When this bit is set, The KSZ8851-16MLL is enabled to transmit ICMP frame (only for non-
fragment frame) checksum generation.
7 0x0 RW TCGUDP Transmit Checksum Generation for UDP
When this bit is set, The KSZ8851-16MLL is enabled to transmit UDP frame checksum
generation..
6 0x0 RW TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851-16MLL is enabled to transmit TCP frame checksum
generation.
5 0x0 RW TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851-16MLL is enabled to transmit IP header checksum
generation.
4 0x0 RW
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX frame pointer is reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit to
normal operation.
3 0x0 RW
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851-16MLL is in full-duplex mode, flow control is enabled.
The KSZ8851-16MLL transmits a PAUSE frame when the Receive Buffer capacity reaches
a threshold level that will cause the buffer to overflow.
When this bit is set and the KSZ8851-16MLL is in half-duplex mode, back-pressure flow
control is enabled. When this bit is cleared, no transmit flow control is enabled.
2 0x0 RW
TXPE Transmit Padding Enable
When this bit is set, the KS Z8851-16MLL automatically adds a padding field to a packet
shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC errors for
the transmit pac ket.
1 0x0 RW TXCE Transmit CRC Enable
When this bit is set, the KS Z8851-16MLL automatically adds a 32-bit CRC checksum field to
the end of a transmit frame.
0 0x0 RW
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When
reset, the transmit process is placed in the stopped state after the transmission of the
current fram e is completed.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 50 Revision 2.3
Transmit Status Register (0x72 – 0x73): TXSR
This register keeps the status of the last transmitted frame.
Bit Default Value R/W Description
15-14 0x0 RO Reserved.
13 0x0 RO TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
12 0x0 RO TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
11-6 - RO Reserved.
5-0 - RO TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame with this ID.
Receive Control Register 1 (0x74 – 0x75): RXCR1
This register holds control information programmed by the CPU to control the receive function.
Bit Default Value R/W Description
15 0x0 RW
FRXQ Flush Receive Queue
When this bit is set, The receive queue memory is cleared and RX frame pointer is reset.
Note: Disable the RXE receive enable bit[0] first before set this bit, then clear this bit to
normal operation.
14 0x0 RW RXUDPFCC Receive UDP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct UDP checksum for incoming UDP
frames. Any received UDP frames wi th incorrect checksum will be discarded.
13 0x0 RW RXTCPFCC Receive TCP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct TCP checksum for incoming TCP
frames. Any received TCP frames wi th incorrect checksum will be discarded.
12 0x0 RW RXIPFCC Receive IP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct IP header checksum for incoming IP
frames. Any received IP frames with incorrec t checksum will be discarded.
11 0x1 RW RXPAFMA Receive Physical Address Filtering with MAC Address Enable
When this bit is set, this bit enables the RX function to receive physical address that pass
the MAC address filtering mechanism (see Address Filtering Scheme in Table 3 for detail).
10 0x0 RW
RXFCE Receive Flow Control Enable
When this bit is set and the KSZ8851-16MLL is in full-duplex mode, flow control is enabled,
and the KSZ8851-16MLL will acknowledge a PAUSE frame from the receive interface; i.e.,
the outgoing packets are pending in the transmit buffer until the PAUSE frame control timer
expires. This field has no meaning in half-duplex mode and should be programmed to 0.
When this bit is cleared, flow c ontrol is not enabled.
9 0x0 RW RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue.
When this bit is cleared, all CRC error frames are discarded.
8 0x0 RW RXMAFMA Receive M ulticast Address Filtering with MAC Address Enable
When this bit is set, this bit enables the RX function to receive multicast address that pass
the MAC address filtering mechanism (see Address Filtering Scheme in Table 3 for detail).
7 0x0 RW RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 51 Revision 2.3
Receive Control Register 1 (0x74 – 0x75): RXCR1 (Continued)
Bit Default Value R/W Description
6 0x0 RW RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
5 0x0 RW RXUE Receive Unicast Enable
When this bit is set, the RX module receives unicast frames that match the 48-bit Station
MAC address of the module.
4 0x0 RW RXAE Receive All Enable
When this bit is set, the KS Z8851-16MLL receives all incoming frames, regardless of the
frame’s destination address (see Address Filtering Scheme in Table 3 for detail).
3 0x0 RW Reserved
2 0x0 RW Reserved
1 0x0 RW RXINVF Receive Inverse Filtering
When this bit is set, the KS Z8851-16MLL receives function with address check operation in
inverse filtering mode (see Address Filtering Scheme in Table 3 for detail).
0 0x0 RW
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state.
When this bit is cleared, the receive process is placed in the stop ped stat e upon com plet ing
reception of the current frame.
Receive Control Register 2 (0x76 – 0x77): RXCR2
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value
R/W
Description
15-5 - RO Reserved.
4 0x0 RW
IUFFP IPV4/IPV6/UDP Fragment Frame Pass
When this bit is set, the KS Z8851-16MLL will pass the checksum check at receive side for
IPv4/IPv6 UDP frame with fragment extension header.
When this bit is cleared, the KSZ8851-16MLL will perform checksum operation based on
configuration and doesn’t care whether it’s a fragment frame or not.
3 0x0 RW
RXIUFCEZ Receive IPV4/IPV6/UDP Frame Checksum Equal Zero
When this bit is set, the KS Z8851-16MLL will pass the filtering for IPv4/IPv6 UDP frame with
UDP checksum equal to zero.
When this bit is cleared, the KSZ8851-16MLL will drop IPv4/IPv6 UDP packet with UDP
checksum equal to zero.
2 0x1 RW
UDPLFE UDP Lite Frame Enable
When this bit is set, the KS Z8851-16MLL will check the checksum at r e ceive si de and
generate the checksum at transmit side for UDP Lite frame.
When this bit is cleared, the KSZ8851-16MLL will pass the checksum check at receive side
and skip the checksum generation at transmit side for UDP Lite frame.
1 0x0 RW
RXICMPFCC Receive ICMP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct ICMP checksum for incoming ICMP
frames (only for non-fragment frame). Any received ICMP frames with incorrect checksum
will be discarded.
0 0x0 RW RXSAF Receive Source Address Filtering
When this bit is set, the KS Z8851-16MLL will drop the frame if the source address is same
as MAC address in MARL, MARM, MARH registers.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 52 Revision 2.3
TXQ Memory Information Register (0x78 – 0x79): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bit Default Value R/W Description
15-13 - RO Reserved.
12-0 - RO
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is used
for both fram e payload, control word.
Note: Software must be written to ensure that there is enough memory for the next transmit
frame including control information before transmit data is written to the TXQ.
0X7A – 0x7B: Reserved
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR
This register indicates the received frame header status information, the received frames are reported in RXFCTR
register. T his register cont ains the status inform ation for the frame received and the CPU can read so many tim es same
as the frame count value in the RXFCTR.
Bit Default Value R/W Description
15 - RO
RXFV Receive Frame Valid
When this bit is set, it indicates that the present frame in the receive packet memory is valid.
The status information currently in this location is also vali d.
When clear, it indicates that there is either no pending receive frame or that the current
frame is still in the process of receiv i ng.
14 - RO Reserved
13 - RO RXICMPFCS Receive ICMP Frame Checksum Status
When this bit is set, the KSZ8851 received ICMP frame checksum field is incorrect.
12 - RO RXIPFCS Receive IP Frame Checksum Status
When this bit is set, the KSZ8851 received IP header checksum field is incorrect.
11 - RO RXTCPFCS Receive TCP Frame Checksum Status
When this bit is set, the KSZ8851 rec ei ved TCP frame checksum field is incorrect.
10 - RO RXUDPFCS Receive UDP Frame Checksum Status
When this bit is set, the KSZ8851 received UDP frame checksum field is incorrect.
9-8 - RO
Reserved
7 - RO RXBF Receive Broadcast Frame
When this bit is set, it indicates that this frame has a broadcast address.
6 - RO RXMF Receive Multicast Frame
When this bit is set, it indicates that this frame has a multicast address (including the
broadcast address).
5 - RO RXUF Receive Unicast Frame
When this bit is set, it indicates that this frame has a unicast address.
4 - RO RXMR Receive MII E rror
When set, it indicates that there is an MII symbol error on the received frame.
3 - RO
RXFT Receive Frame Type
When this bit is set, i t indicates that the frame is an Ethernet-type frame (frame length is
greater than 1500 bytes). When clear, it indicates that the frame is an IEEE 802.3 frame.
This bit is not valid for runt frames.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 53 Revision 2.3
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (Continued)
Bit Default Value R/W Description
2 - RO
RXFTL Receive Frame Too Long
When this bit is set, it indicates that the frame length exceeds the maximum size of 2000 bytes.
Frames that are too long are passed to the host only if the pass bad frame bit is set.
Note: Frame too long is only a frame length indication and does not cause any frame truncation.
1 - RO
RXRF Recei ve Ru nt Frame
When this bit is set, it indicates that a fram e was damaged by a collision or had a premature
termination before the collision window passed.
Runt frames are passed to the host only if the pass bad frame bit is set.
0 - RO
RXCE Receive CRC Error
When this bit is set, it indicates that a CRC error has occurred on the current received
frame.
CRC error frames are passed to the host only if the pass bad frame bit is set.
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR
This register indicates the received frame header byte count information, the received frames are reported in RXFCTR
register. This register contains the total number of bytes information for the frame received and the CPU can read so
many times same as the frame count value in the RXFCTR.
Bit Default Value R/W Description
15-12 - RO Reserved.
11-0 - RO RXBC Receive Byte Count
This field indicates the present received frame byte size.
Note: Always read low byte first for 8-bi t mode opearation.
TXQ Command Register (0x80 – 0x81): TXQCR
This r egister is pr ogramm ed by the Host CPU t o issue a transm it comm and to the TX Q. The pr esent transm it f r am e i n t he
TXQ memory is queued for transmit.
Bit Default Value R/W Description
15-2 - RW Reserved
1 0x0 RW
TXQMAM TXQ Memory Available Monitor
When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR
register) to CPU when TXQ memory is available based upon the total amount of TXQ space
requested by CPU at TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before set to 1 again.
0 0x0 RW
METFE Manual Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will enable current TX frame prepared in
the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before setting up another new TX frame.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 54 Revision 2.3
RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
Bit Default Value R/W Description
15-13 - RW Reserved.
12 - RO
RXDTTS RX Duration Timer Threshold Status
When this bit is set, i t indicates that RX
interrupt is due to the time start at first received frame in
RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register (0x8C,
RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
11 - RO
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in RXQ
buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E, RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
10 - RO
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames in
RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C, RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
9 0x0 RW
RXIPHTOE RX IP Header Two-B yte Offset Enable
When this bit is written as 1, the KSZ8851-16MLL will enable to add two bytes before frame
header in order for IP header inside the frame contents to be aligned with double word
boundary to speed up software operation.
8 - RW
Reserved.
7 0x0 RW
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when
the time start at first received frame in RXQ buffer exceeds the threshold set in RX Duration
Timer Threshold Register (0x8C, RXDTT).
6 0x0 RW
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when
the number of received bytes in RXQ buffer exceeds the threshold set in RX Data Byte Count
Threshold Register (0x8E, RXDBCT).
5 0x0 RW
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when
the number of received frames in RXQ buffer exceeds the threshold set in RX Frame Count
Threshold Register (0x9C, RXFCT).
4 0x0 RW
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will automatically enable RXQ frame buffer
dequeue. The read pointer in RXQ frame buffer will be automatically adjusted to next received
frame location after current fram e is completely read by the host.
3 0x0 WO
SDA Start DMA Access
When this bit is written as 1, the KSZ8851-16MLL allows a DMA operation from the host CPU
to access either read RXQ frame buffer or write TXQ frame buffer with CSN and RDN or WRN
signals whi le the CMD pin is low. All registers access are disabled except this register during
this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to access the rest of regi s ters.
In order to get out of DMA mode the SD1 bit must set to “1” when CMD = 1.
2-1 - RW Reserved.
0 0x0 RW
RRXEF Release RX Error Frame
When this bit is written as 1, the current RX error frame buffer is released.
Note: This bit is self-clearing after the frame memory is rel eased. The software shoul d wait for
the bit to be cleared before processing new RX frame.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 55 Revision 2.3
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR
The value of t his r e gister d eter mines the addr ess t o b e ac c es sed w ith in the TX Q f r am e buff er . When the A U T O inc rem ent
is set, It will automatically increment the pointer value on write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
Bit Default Value R/W Description
15 - RO Reserved.
14 0x0 RW
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments automatically on
accesses to the data register. The increment is by one for every byte access, by two for
every word access, and by four for every doubleword access.
When this bit is reset, the TX frame data pointer is manually controlled by user to access the
TX frame location.
13-11 - RO Reserved.
10-0 0x000 RO
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX Frame Data has been
enqueued through the TXQ command register.
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR
The value of this register determ ines the address to be accessed with in the RXQ fr am e buffer. W hen the Auto Increm ent
is set, it will automatically increment the RXQ Pointer on read accesses to the data register.
The counter is incremented is by one for every byte access, by two for every word access, and by four for every double
word access.
Bit Default Value R/W Description
15 - RO Reserved.
14 0x0 RW
RXFPAI RX Frame Pointer Auto Increment
When this bit is set, the RXQ Address register increments automatically on accesses to the
data register. The increment is by one for every byte access, by two for every word access,
and by four for every double word access.
When this bit is reset, the RX frame data pointer is manually controlled by user to ac c ess
the RX frame location.
13 - RO Reserved.
12 0x0 RW
WST Write Sample Time
This bit is used to select the WRN active to write data valid time as shown in Figure 10.
0: WRN active to write data valid sample time is range of 8nS (min) to 16nS (max).
1: WRN active to write data valid sample time is 4nS (max).
11 0x0
WO
(Read
back is
“0”)
EMS Endian Mode Selection
This bit is used to select either Big or Little Endian mode when Endian mode select
strapping pin (10) is NC or tied to GND.
0: is set to Little Endian Mode
1: is set to Big Endian Mode
10-0 0x000 WO
RXFP RX Frame Pointer
RX Frame data pointer index to the Data register for access.
This pointer value must reset to 0x000 before each DMA operation from the host CPU to
read RXQ frame buffer.
0x88 – 0x8B: Reserved
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 56 Revision 2.3
RX Duration Timer Threshold Regis ter (0x8C – 0x8D): RXDTTR
This register is used to program the received frame duration timer threshold.
Bit Default Value R/W Description
15-0 0x0000 RW
RXDTT Receive Duration Timer Threshold
To program received fram e duration timer threshold value in 1us interval. The maximum
value is 0xCFFF.
When bit 7 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX inte rrup t (bit 13 in
ISR) after the time starts at first received frame in RXQ buffer and exceeds the threshold set
in this regis ter.
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR
This register is used to program the received data byte count threshold.
Bit Default Value R/W Description
15-0 0x0000 RW
RXDBCT Receive Data Byte Count Threshold
To program received data byte threshold value in byte count.
When bit 6 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in
ISR) when the number of received bytes in RXQ buffer exceeds the threshold set in this
register.
Interrupt Enable Register (0x90 – 0x91): IER
This register enables the interrupts from the QMU and other sources.
Bit Default Value R/W Description
15 0x0 RW LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabl ed.
When this bit is reset, the link change interrupt is disabled.
14 0x0 RW TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
13 0x0 RW RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
12 0x0 RW Reserved
11 0x0 RW RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
10 0x0 RW Reserved
9 0x0 RW TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
8 0x0 RW RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped i nterrupt is disabled.
7 0x0 RW Reserved
6 0x0 RW TXSAIE Transmit Space Available Interrupt Enable
When this bit is set, the Transmit memory space available interrupt is enabled.
When this bit is reset, the Transmit memory space available interrupt is disabled.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 57 Revision 2.3
Interrupt Enable Register (0x90 – 0x91): IER (Continued)
Bit Default Value R/W Description
5 0x0 RW RXWFDIE Receive Wake-up Frame Detect Interrupt Enable
When this bit is set, the Receive wakeup frame detect interrupt is enabled.
When this bit is reset, the Receive wakeup frame detec t interrupt is disabled.
4 0x0 RW RXMPDIE Receive Magic Packet Detect Interrupt Enable
When this bit is set, the Receive magic packet detect interrupt is enabled.
When this bit is reset, the Receive magic packet detect interrupt is disabled.
3 0x0 RW LDIE Linkup Detect Interrupt Enable
When this bit is set, the wake-up from linkup detect interrupt is enabled.
When this bit is reset, the linkup detect inter r upt is dis abl ed.
2 0x0 RW EDIE Energy Detect Interrupt Enable
When this bit is set, the wake-up from energy detect interrupt is enabled.
When this bit is reset, the energy detect interrupt is disabled.
1 0x0 RO Reserved.
0 0x0 RW
DEDIE Delay Energy Detect Interrupt Enable
When this bit is set, the delay energy detect interrupt is enabled.
When this bit is reset, the delay energy detect interrupt is disabled.
Note: the del ay energy detect interrupt till device is ready for host access.
Interrupt Status Register (0x92 – 0x93): ISR
This r egister cont ains the s tatus bits f or all QM U and other interr upt sourc es. W hen the corres ponding enable b it is set, it
causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register bits
are not cleared when read. The user has to write “1” to clear.
Bit Default Value R/W Description
15 0x0 RO
(W1C)
LCIS Link Change Interrupt St atus
When this bit is set, i t indicates that the link status has changed from link up to link down, or
link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
14 0x0 RO
(W1C)
TXIS Transmit Interrupt Status
When this bit is set, i t indicates that the TXQ MAC has transmitted at least a frame on the
MAC interfac e and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
13 0x0 RO
(W1C)
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received at least a frame from the
MAC interfac e and the frame is ready for the host CPU to proc ess.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
12 0x0 RO Reserved
11 0x0 RO
(W1C)
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
10 0x0 RO Reserved
9 0x1 RO
(W1C)
TXPSIS Transmit Process Stopped Interrupt Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 58 Revision 2.3
Interrupt Status Register (0x92 – 0x93): ISR (Continued)
Bit Default Value R/W Description
8 0x1 RO
(W1C)
RXPSIS Receive Process Stopped Interrupt Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
7 0x0 RO Reserved
6 0x0 RO
(W1C)
TXSAIS Transmit Space Available Interrupt Status
When this bit is set, it indicates that Transmit memory space available status has occurred.
When this bit is reset, the Transmit memory space available interrupt is disabled.
5 0x0 RO RXWFDIS Re ceive Wakeup Frame Detect Interrupt Status
When this bit is set, it indicates that Receive wakeup frame detect status has occurred.
Write “1000” to PMECR[5:2] to clear this bit
4 0x0 RO RXMPDIS Receive Magic Packet Detect Interrupt Status
When this bit is set, it indicates that Receive magic packet detect status has occurred. Write
“0100” to PMECR[5:2] to clear this bit.
3 0x0 RO LDIS Linkup Detect Interrupt Status
When this bit is set, i t indicates that wake-up from linkup detect statu s has oc curre d. Write
“0010” to PMECR[5:2] to clear this bit.
2 0x0 RO
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from energy
detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it indicat es
that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
1 0x0 RO Reserved.
0 0x0 RO Reserved.
0x94 – 0x9B: Reserved
RX Frame Coun t and Threshold Register (0x9C – 0x9D): RXFCTR
This register indic ates the cur rent total amount of received fram e count in RXQ f rame buffer and also is used to pr ogram
the received frame count threshold.
Bit Default Value R/W Description
15-8 0x00 RO
RXFC RX Frame Count
To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1 in
ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read the
updated receive frame header information in RXFHSR/RXFHBCR registers after read this
RX frame count register.
7-0 0x00 RW
RXFCT Receive Frame Count Threshold
To program received fram e count threshold value.
Note: When bit 5 s et to 1 in RXQCR register, the RXFCT Receive Frame Threshold” can’t
set to 0, the KSZ8851-16MLL will set RX interrupt (bit 13 i n ISR) when the number of
received frames in RXQ buffer exceeds or equ als to the threshold set in this register.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 59 Revision 2.3
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
Bit Default Value R/W Description
15-0 0x0000 RW
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space which is required for
next total transmit fram es size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the KSZ8851-
16MLL will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available
based upon the total amount of TXQ space requested by CPU at this register.
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0
The 64-bit M AC addr es s table is us e d f or group addr e s s filterin g and it is ena bl ed b y select ing item 5 “ Has h perfec t” m ode
in Table 3 (Address Filtering Scheme). This value is defined as the six most significant bits from CRC circuit calculation
result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be used, while
the others determine which bit within the register.
Multicast table register 0.
Bit Default Value R/W Description
15-0 0x0 RW
HT0 Hash Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1
Multicast table register 1.
Bit Default Value R/W Description
15-0 0x0 RW
HT1 Hash Table 1
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing functio n is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all
multicast addresses are received regardless of the multicast table value.
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2
Multicast table register 2.
Bit Default Value R/W Description
15-0 0x0 RW
HT2 Hash Table 2
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all
multicast addresses are received regardless of the multicast table value.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 60 Revision 2.3
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3
Multicast table register 3.
Bit Default Value R/W Description
15-0 0x0 RW
HT3 Hash Table 3
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all
multicast addresses are received regardless of the multicast t able val ue.
0xA8 – 0xAF: Reserved
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR
This register is used to control the flow control for low watermark in QMU RX queue.
Bit Default Value R/W Description
15-12 - RW Reserved
11-0 0x0500 RW FCLWC Flow Control Low Watermark Configuration
These bits are used to define the QMU RX queue low watermark configuration. It is in
double words count and default is 5.12 KByte available buffer space out of 12 KByte.
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR
This register is used to control the flow control for high watermark in QMU RX queue.
Bit Default Value R/W Description
15-12 - RW Reserved
11-0 0x0300 RW FCHWC Flow Control High Watermark Configuration
These bits are used to define the QMU RX queue high watermark configuration. It is in
double words count and default is 3.072 K Byte available buffer space out of 12 KByte.
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR
This register is used to control the flow control for overrun watermark in QMU RX queue
Bit Default Value R/W Description
15-12 - RW Reserved
11-0 0x0040 RW FCLWC Flow Control Overrun Watermark Configuration
These bits are used to define the QMU RX queue overrun watermark configuration. It is in
double words count and default is 256 Bytes available buffer space out of 12 Kbyte.
0xB6 – 0xBF: Reserved
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 61 Revision 2.3
Chip ID and Enable Register (0xC0 – 0xC1): CIDER
This register contains the chip ID and the chip enable bit.
Bit Default R/W Description
15-8 0x88 RO Fa m ily ID
Chip f amil y ID
7-4 0x7 RO Chip ID
0x7 is assigned to KSZ8851-16MLL
3-1 - RO Revision ID
Note: Bits[3-1]=0 is for rev. A2 part, bits[3-1]=1 is for rev.A3 part.
0 0x0 RW Reserved
0xC2 – 0xC5: Reserved
Chip Global Control Register (0xC6 – 0xC7): CGCR
This register contains the global control for the chip function.
Bit Default R/W Description
15-12 0x0 RW
Reserved.
11-10 0x2 RW Reserved.
9 0x0 RW
LEDSEL0
This bit sets the LEDSEL0 selection for P1LED1 and P1LED0. PHY port LED indicators,
defined as below:
LEDSEL0 (bit9)
0 1
P1LED1 100BT ACT
P1LED0 LINK/ACT LINK
8 0x0 R/W Reserved.
7-0 0x35 RW
Reserved.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 62 Revision 2.3
Indirect Access Control Register (0xC8 – 0xC9): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read access is
determ ined b y bit 12).
Bit Default R/W Description
15-13 0x0 RW Reserved.
12 0x0 RW Read Enable.
1 = Read cycle is enabled (MIB counter will clear after read).
0 = No operation.
11-10 0x0 RW
Table Select
00 = reserved.
01 = reserved.
10 = reserved.
11 = MIB counter selected.
9-5 - RW Reserved.
4-0 0x00 RW Indirect Address
Bit 4-0 of indirect addres s for 32 M I B counter locatio ns.
0xCA – 0xCF: Reserved
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR
This register contains the indirect data (low word) for MIB counter.
Bit Default R/W Description
15-0 0x0000 RW Indirect Low Word Data
Bit 15-0 of indirect data.
Indirect Access Data High Register (0xD2 – 0xD3): IADHR
This register contains the indirect data (high word) for MIB counter.
Bit Default R/W Description
15-0 0x0000 RW Indirect High Word Data
Bit 31-16 of indirect data.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 63 Revision 2.3
Power Management Event Control Register (0xD4 – 0xD5): PMECR
This register is used to control the KSZ8851-16MLL power management event, capabilities, and status.
Bit Default
Value R/W Description
15 - RO Reserved.
14 0 RW
PME Dela y Enable
This bit is used to enable the delay of PME output pin assert i on.
When this bit is set to 1, the device will not assert the PME output until all the clocks in the
device are running and it is ready for host accesses.
When this bit is set to 0, the device will assert the PME output without delay.
This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1 in this register.
13 0 RW Reserved
12 0 RW
PME Output Polarity
This bit is used to control the PME output pin polarit y .
When this bit is set to 1, the PME output pin is acti ve high.
When this bit is set to 0, the PME output pin is acti ve low.
11-8 0x0 RW
Wake-on-LAN to PME Output Enable
These four bits are used to enable the PME output pin asserted when one of these wake-
on-LAN events is detected:
Bit 11: is corresponding to receive wake-up frame.
Bit 10: is corresponding to receive magic packet.
Bit 9: is corresponding to l ink change from down to up.
Bit 8: is corresponding to signal energy detected.
When the bit is set to 1, the PME pin will be asserted when a corresponding wake-on-LAN
event is occurred.
When this bit is set to 0, the PME pin will be not asserted when a corresponding wake-on-
LAN event is occurred.
7 0 RW
Auto Wake-Up Enable
This bit is used to enable automatically wak e-up from low power state to normal power state
in energy detect mode if carrier (signal energy) is present more than wake-up time in
GSWUTR register. During the normal power state, the device c an receive and transmit
packets.
When this bit is set to 1, the auto wake-up is enabled in energy detect mode.
When this bit is set to 0, the auto wake-up is disabled i n energy detect mode.
6 0 RW
Wake-Up to Normal Operation Mode
This bit is used to control the device wake-up from low power state in energy detect mode to
normal operation mode if signal energy is detected longer than the programmed wake-up
time in GSWUTR register.
When this bit is set to 1, the device will automatically go to the normal operation mode from
energy detect mode.
When this bit is set to 0, the device will not automatic ally go to the normal mode from energy
detect mode.
This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 64 Revision 2.3
Power Management Event Control Register (0xD4 – 0xD5): PMECR (Continue d )
Bit Default
Value R/W Description
5-2 0x0 RO
(W1C)
Wake-Up Event Indication
These four bits are used to indicate the KSZ8851-16MLL wake-up event status as below:
0000: No wak e-up event.
0001: Wake-up from energy event detected. (Bit 2 also set to 1 in ISR register)
0010: Wake-up from link up event detected. (Bit 3 also set to 1 in ISR register)
0100: Wake-up from magic packet event detected.
1000: Wake-up from wakeup frame event detected.
If Wake-on-LAN to PME Output Enable bit [11:8] are set, the KSZ8851-16MLL also asserts
the PME pin. These bits are cleared on power up reset or by writing 1 to bits [5-2] (W1C). It
is not modified by either hardware or software res et. When these bits are cleared, the
KSZ8851-16MLL deasserts the PME pin.
1-0 0x0 RW
Power Management Mode
These two bits are used to control the KSZ8851-16MLL power management mode as
below:
00: Normal Operation Mode.
01: Energy Detect Mode. (two states in this mode either low power or normal power)
10: Soft Power-down mode.
11: Power-saving mode.
In energy detect mode under low power state, it can wake-up to normal operation mode
from line to get the energy.
In soft power-down mode, it can wake-up to normal operation mode only from host wake-up
(host CPU issues a read cycle to GRR register).
Go-Sleep and Wake-Up Time Register (0xD6 – 0xD7): GSWUTR
This register contains the value which is used to control minimum Go-Sleep time period when the device from normal
power state to low power state or to control minimum Wake-Up time period when the device from low power state to
normal power state in energy detect mode.
Bit Default R/W Description
15-8 0x08 RW
Wake-up Time
This value is used to control the m inimum period that the energy has to be detected
consecutively before the device is waked-up from the low power state. The unit is 16 ms +/-
80%, the default wake-up time is 128 ms (16ms x 8). Zero time (0x00) is not allowed
7-0 0x0C RW
Go-sleep Time
This value is used to control th e minim um peri od that the no ener gy event ha s to be
detected consecutively before the device enters the low power state when the energy detect
mode is on. The unit is 1 sec +/-80%, the default go-sleep time is 12 sec (1s x 12). Zero time
(0x00) is not allowed
PHY Reset Register (0xD8 – 0xD9): PHYRR
This register contains a control bit to reset PHY block when write an “1”.
Bit Default R/W Description
15-1 - RW Reserved.
0 0 WO
(Self clear) PHY Reset Bit
This bit is write only and self c lear after write an “1”, it is used to reset PHY block circuitry.
0xDA – 0xDF: Reserved
0xE0 – 0xE3: Reserved
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 65 Revision 2.3
PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR
This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification.
Bit Default R/W Description Bit is same as:
15 0 RO Reserved
14 0 RW
Local (far-end) loopback (llb)
1 = perform local loopba ck at host
(host Tx -> PHY -> host Rx, see Figure 9)
0 = normal operation
13 1 RW Force 100
1 = force 100Mbps if AN i s disabled (bit 12)
0 = force 10Mbps if AN is disabled (bit 12) Bit 6 in P1CR
12 1 RW AN Enable
1 = auto-negotiation enabled.
0 = auto-negotiation disabled. Bit 7 in P1CR
11-10 0 RW Reserved
9 0 RW Restart AN
1 = restart auto-negotiation.
0 = normal operation.
Bit 13 in P1CR
8 1 RW
Force Full Duplex
1 = force full duplex
0 = force half duplex .
if AN is disabled (bit 12) or AN is enabled but failed.
Bit 5 in P1CR
7-6 0 RO
Reserved
5 1 R/W HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode. Bit 15 in P1SR
4 0 RW
Force M DI-X
1 = if auto MDI/MD I-X is disabled, force PHY into
MDI mode.
0 = if auto MDI/MD I-X is disabled, force PHY into
MDI-X mode..
Bit 9 in P1CR
3 0 RW Disable MDI-X
1 = disable auto MDI-X.
0 = normal operation. Bit 10 in P1CR
2 0 RW Reserved.
1 0 RW Disable Transmit
1 = disable transmit.
0 = normal operation. Bit 14 in P1CR
0 0 RW Disable LED
1 = disable all LEDs.
0 = normal operation. Bit 15 in P1CR
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 66 Revision 2.3
PHY 1 MII-Register Basic Status Register (0xE6 – 0x E7): P1MB SR
This register contains the MII register status for the chip function.
Bit Default R/W Description Bit is same as:
15 0 RO T4 Capable
1 = 100 BASE-T4 capable.
0 = not 100 BASE-T4 capable.
14 1 RO 100 Full Capable
1 = 100BASE-TX full-duplex capable.
0 = not 100BASE-TX full duplex.capable.
13 1 RO 100 Half Capable
1= 100BASE-TX half-duplex capable.
0= not 100BASE-TX half-duplex capable.
12 1 RO 10 Full Capable
1 = 10BASE-T full-duplex capable.
0 = not 10BASE-T full-duplex capable.
11 1 RO 10 Half Capable
1 = 10BASE-T half-duplex capable.
0 = not 10BASE-T half-duplex capable.
10-7 0x0 RO Reserved.
6 0 RO Preamble suppressed
Not supported.
5 0 RO AN Complete
1 = auto-negotiation complete.
0 = auto-negotiation not completed. Bit 6 in P1SR
4 0 RO Reserved
3 1 RO AN Capable
1 = auto-negotiation capable.
0 = not auto-negotiation capable.
2 0 RO Link Status
1 = link is up; 0 = link is down. Bit 5 in P1SR
1 0 RO Jabber test
Not supported.
0 0 RO Extended Capable
1 = extended register capable.
0 = not extended register capable.
PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR
This register contains the PHY ID (low) for the chip.
Bit
Default
R/W
Description
15-0 0x1430 RO PHYID Low
Low order PHYID bits.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 67 Revision 2.3
PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR
This register contains the PHY ID (high) for the chip.
Bit Default R/W Description
15-0 0x0022 RO PHYID High
High order PHYID bits.
PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR
This register contains the auto-negotiation advertisement for the PHY function.
Bit Default R/W Description Bit is same as:
15 0 RO Next page
Not supported.
14 0 RO Reserved
13 0 RO Remote fault
Not supported.
12-11 0x0 RO Reserved
10 1 RW Pause (flow control capabilit y)
1 = advertise pause capability.
0 = do not advertise pause capability. Bit 4 in P1CR
9 0 RW Reserved.
8 1 RW Adv 100 Full
1 = advertise 100 full-duplex capability.
0 = do not advertise 100 full-duplex capability Bit 3 in P1CR
7 1 RW Adv 100 Half
1= advertise 100 half -duplex capability.
0 = do not advertise 100 half-duplex capability. Bit 2 in P1CR
6 1 RW Adv 10 Full
1 = advertise 10 full-duplex capability.
0 = do not advertise 10 full-duplex capability.
Bit 1 in P1CR
5 1 RW Adv 10 Half
1 = advertise 10 half-duplex capability.
0 = do not advertise 10 half-duplex capability. Bit 0 in P1CR
4-0 0x01 RO Selector Field
802.3
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 68 Revision 2.3
PHY 1 Auto-Ne g o tiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR
This register contains the auto-negotiation link partner ability for the chip function.
Bit Default R/W Description Bit is same as:
15 0 RO Next page
Not supported.
14 0 RO LP ACK
Not supported.
13 0 RO Remote fault
Not supported.
12-11 0x0 RO Reserved
10 0 RO Pause
Link partner pause capability. Bit 4 in P1SR
9 0 RO Reserved.
8 0 RO Adv 100 Full
Link partner 100 full capability. Bit 3 in P1SR
7 0 RO Adv 100 Half
Link partner 100 half capability. Bit 2 in P1SR
6 0 RO Adv 10 Full
Link partner 10 full capability. Bit 1 in P1SR
5 0 RO Adv 10 Half
Link partner 10 half capability. Bit 0 in P1SR
4-0 0x01 RO Reserved.
0xF0 – 0xF3: Reserved
Port 1 PHY Spec ial Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD
This register contains the special control, status and LinkMD information of PHY1.
Bit Default R/W Description Bit is same as:
15 0 RO Reserved
14-13 0x0 RO
Vct_result
VCT result.
[00] = normal conditi on.
[01] = open condition has been detected in cable.
[10] = short condition has been detected in cable.
[11] = cable diagnostic test is failed.
12 0 RW
(Self-Clear)
Vct_en
Vct enable.
1 = the cable di agnostic test is enabled. It is self-
cleared after the VCT test is done.
0 = it indicates the cable diagnostic test is
completed and the status information is valid for
read.
11 0 RW Force_lnk
Force link.
1 = force link pass; 0 = normal operation.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 69 Revision 2.3
Port 1 PHY Spec ial Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD (Continue d )
Bit Default R/W Description Bit is same as:
10 0 RO Reserved.
9 0 RW
Remote (Near-end) loopback (rlb)
1 = perform remote loopback at PHY
(RXP1/RXM1 -> TXP1/TXM1, see Figure 9)
0 = normal operation
8-0 0x000 RO
Vct_fault_count
VCT fault count.
Distance to the fault. It’s approximately
0.4m*vct_fault_count.
Port 1 Control Register (0xF6 – 0xF7): P1CR
This register contains the global per port control for the chip function.
Bit Default R/W Description Bit is same as:
15 0 RW
LED Off
1 = Turn off all of the port 1 LEDs (P1LED3,
P1LED2, P1LED1, P1LED0). Thes e pins are driven
high if this bit is set to one.
0 = normal operation.
Bit 0 in P1MBCR
14 0 RW Txids
1 = disable the port’s transmitter.
0 = normal operation. Bit 1 in P1MBCR
13 0 RW Restart AN
1 = restart auto-negotiation.
0 = normal operation. Bit 9 in P1MBCR
12 0 RW Reserved
11 0 RW Reserved
10 0 RW Disable auto MDI/MDI-X
1 = disable auto M D I/M DI -X function.
0 = enable auto MDI/MDI-X function. Bit 3 in P1MBCR
9 0 RW
Force MDI-X
1= if auto MDI/MDI-X is disabled, force PHY into
MDI mode.
0 = if auto MDI/MDI-X is disabled, force PHY into
MDI-X mode.
Bit 4 in P1MBCR
8 0 RW
Reserved
7 1 RW
Auto Negotiation Enable
1 = auto negoti ation is enabled.
0 = disable auto negotiat ion , speed, and dup lex are
decided by bits 6 and 5 of the same register.
Bit 12 in P1MBCR
6 1 RW Force Speed
1 = force 100BT if AN is disabled (bit 7).
0 = force 10BT if AN is disabled (bit 7). Bit 13 in P1MBCR
5 1 RW
Force Duplex
1 = force full duplex if (1) AN is disabled or (2) AN
is enabled but failed.
0 = force half duplex if (1) AN is disabled or (2) AN
is enabled but failed.
Bit 8 in P1MBCR
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 70 Revision 2.3
Port 1 Control Register (0xF6 – 0xF7): P1CR (Continued)
Bit Default R/W Description Bit is same as:
4 1 RW
Advertised flow control capability
1 = advertise flow control (pause) capability.
0 = suppress flow control (pause) capability from
transmission to link partner.
Bit 10 in P1ANAR
3 1 RW
Advertised 100BT full-duplex capability
1 = advertise 100BT full-duplex capability.
0 = suppress 100BT full-duplex capability from
transmission to link partner.
Bit 8 in P1ANAR
2 1 RW
Advertised 100BT half-duplex capability
1 = advertise 100BT half-duplex capability.
0 = suppress 100BT half-duplex capability from
transmission to link partner.
Bit 7 in P1ANAR
1 1 RW
Advertised 10BT full-duplex capabi lity
1 = advertise 10BT full-duplex capability.
0 = suppress 10BT full-duplex capability from
transmission to link partner.
Bit 6 in P1ANAR
0 1 RW
Advertised 10BT half-duplex capability
1 = advertise 10BT half-duplex capability.
0 = suppress 10BT half-duplex capability from
transmission to link partner.
Bit 5 in P1ANAR
Port 1 Status Register (0xF8 – 0xF9): P1SR
This register contains the PHY port status for the chip function.
Bit Default R/W Description Bit is same as:
15 1 RW HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode. Bit 5 in P1MBCR
14 0 RO Reserved
13 0 RO Polarity Reverse
1 = polarity is reversed.
0 = polarity is not reversed.
12-11 0 RO Reserved
10 0 RO Operation Speed
1 = link speed is 100Mbps.
0 = link speed is 10Mbps.
9 0 RO Operation Duplex
1 = link duplex is full.
0 = link duplex is half.
8 0 RO Reserved
7 1 RO MDI-X status
1 = MDI.
0 = MDI-X.
6 0 RO AN Done
1 = AN done.
0 = AN not done. Bit 5 in P1MBSR
5 0 RO Link Good
1= link good.0 = link not good. Bit 2 in P1MBSR
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 71 Revision 2.3
Port 1 Status Register (0xF8 – 0xF9): P1SR (Continued)
Bit Default R/W Description Bit is same as:
4 0 RO Partner flow control capability
1 = link partner flow control (pause) capable.
0 = link partner not flow control (pause) c apable. Bit 10 in P1ANLPR
3 0 RO Partner 100BT full-duplex capability
1 = link partner 100BT full-duplex capable.
0 = link partner not 100BT full-duplex capable. Bit 8 in P1ANLPR
2 0 RO Partner 100BT half-duplex capability
1 = link partner 100BT half-duplex capable.
0= link partner not 100BT half-duplex capable. Bit 7 in P1ANLPR
1 0 RO Partner 10BT full-dup l ex cap abili ty
1= link partner 10BT full-duplex capable.
0 = link partner not 10BT full-duplex capable. Bit 6 in P1ANLPR
0 0 RO Partner 10BT half-du plex capability
1 = link partner 10BT half-duplex capable.
0 = link partner not 10BT half-duplex capable. Bit 5 in P1ANLPR
0xFA – 0xFF: Reserved
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 72 Revision 2.3
MIB (Management Information Base) Counters
The KSZ8851-16MLL provides 32 MIB counters to monitor the port activity for network management. The MIB counters
are formatted as shown below:
Table 12. Format of MIB Counters
Bit Name R/W Description Default
31-0 Counter
values RO Counter value (read clear) 0x00000000
Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F. Refer to
Table 13.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 73 Revision 2.3
Table 13. Port 1 MIB Counters Indirect Memory Offsets
Offset Counter Name Description
0x0 RxByte Rx octet count including bad packets
0x1 Reserved Reserved.
0x2 RxUndersizePkt Rx undersize packets w/ good CRC
0x3 RxFragments Rx fragment packets w/ bad CRC, symbol errors or alignment errors
0x4 RxOversize Rx oversize packets w/ good CRC (max: 1536 bytes)
0x5 RxJabbers Rx packets longer than 1536 bytes w/ either CRC errors, alignm ent errors, or symbol
errors
0x6 RxSymbolError Rx packets w/ invalid data symbol and legal packet size.
0x7 RxCRCError Rx packets within (64,2000) bytes w/ an integral number of bytes and a bad CRC
0x8 RxAlignmentError Rx packets within (64,2000) bytes w/ a non-integral number of bytes and a bad CRC
0x9 RxControl8808Pkts Number of MAC control frames received by a port with 88-08h in EtherType field
0xA RxPausePkts Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType
(88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC
0xB RxBroadcast Rx good broadcast packets (not inc l uding error broadc ast packets or valid multicast
packets)
0xC RxMulticast Rx good multicast packets (not including MAC control frames, error multicast packets or
valid broadc ast packets)
0xD RxUnicast Rx good unicast packets
0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length
0xF Rx65to127Octets Total Rx packets (bad pac k ets included) that are between 65 and 127 octets in length
0x10 Rx128to255Octets Total Rx packets (bad packets included) that are between 128 and 255 octets in l ength
0x11 Rx256to511Octets Total Rx packets (bad packets included) that are between 256 and 511 octets in length
0x12 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length
0x13 Rx1024to1521Octets Total Rx packets (bad packets included) that are between 1024 and 1521 octets in length
0x14 Rx1522to2000Octets Total Rx packets (bad packets included) that are between 1522 and 2000 octets in length
0x15 TxByte Tx good octet count, including PAUSE packets
0x16 TxLateCollision The number of times a collision is detected later than 512 bit-times into the Tx of a packet
0x17 TxPausePkts Number of PAUSE frames transmitted by a port
0x18 TxBroadcastPkts Tx good broadc ast packets (not including error broadc ast or valid multicast packets)
0x19 TxMulticastPkts Tx good multicast packets (not including error mult ica st pac k ets or valid broa dca st
packets)
0x1A TxUnicastPkts Tx good unicast packets
0x1B TxDeferred Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
0x1C TxTotalCollision Tx total collision, half duplex only
0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions
0x1E TxSingleCollision Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
0x1F TxMultipleCollision Successfully Tx frames on a port for which Tx is inhibited by more than one collision
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 74 Revision 2.3
Example:
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to reg. IACR (0xC8) with 0x1C0E (set indirect address and trigger a read MIB counters operation)
Then:
Read reg. IADHR (MIB counter value 31-16)
Read reg. IADLR (MIB counter value 15-0)
Additional MIB Information
In the heaviest condition, the b yte counter will overflow in two minutes. It is recommended that the software read all the
counters at least every 30 seconds.
MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 75 Revision 2.3
Absolute Maximum Ratings(5)
Supply Voltage (VDD_A3.3, VDD_IO) ......... –0.5V to +4.0V
Input Voltage (All Inputs). ............................. –0.5V to +4.0V
Output Voltage (All Outputs) ........................ –0.5V to +4.0V
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
HBM ESD Rating(6) ......................................................... 6kV
Operating Ratings(7)
Suppl y Voltage
VDD_A3.3 .............................................. +3.1V to +3.5V
VDD_IO (3.3V)....................................... +3.1V to +3.5V
VDD_IO (2.5V)................................... +2.35V to +2.65V
VDD_IO (1.8V)....................................... +1.7V to +1.9V
Ambient Operating Temperature (TA)
Commercial (MLL) .................................... 0°C to +70°C
Industrial (MLLI) .................................... –40°C to +85°C
Thermal Resistance(8)
Junction-to-Ambient (θJA) ................................... 76°C/W
Junction-to-Case (θJC) ....................................... 15°C/W
Electrical Characteristics(9)
TA = 25°C, bold values indicate –40°C≤ TA ≤ +85°C, unless noted.
Symbol Parameter Condition Min. Typ. Max. Units
Supply Current for 100BASE -TX Operation (Single Port @ 100% Utilization)
IDD1 100BASE-TX
(analog core + PLL + digital
core + transceiver + digital I/O)
VDD_A3.3, VDD_IO = 3.3V; Chip only (no
transformer) 85 mA
VDD_A3.3 = 3.3V, VDD_IO = 2.5V; Chip only
(no transform er) 85 mA
VDD_A3.3 = 3.3V, VDD_IO = 1.8V; Chip only
(no transformer) 85 mA
Supply Current for 10BASE-T Operation (Single Port @ 100% Utiliza tion)
IDD2 10BASE-T
(analog core + PLL + digital
core + transceiver + digital I/O)
VDD_A3.3, VDD_IO = 3.3V; Chip only (no
transformer) 75 mA
VDD_A3.3 = 3.3V, VDD_IO = 2.5V; Chip only
(no transform er) 75 mA
VDD_A3.3 = 3.3V, VDD_IO = 1.8V; Chip only
(no transform er) 75 mA
Power Management Mode
IDD3 Power-saving mode(10) Et hernet cable di sco nne cted and auto-
negotiate 70 mA
IDD4 Soft power-down mode Set Bit [1:0] = 10 in PMECR register 2 mA
IDD5 Energy-dete ct mod e At low power state 2 mA
Notes:
5. Exceeding the absolute maximum ratings may damage the device.
6. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
7. The device is not guarant eed to function outside its operat i ng ratings.
8. No (HS) heat spreader in this package. The θJC/θJA is under air velocity 0m/s.
9. Specific at i on for pack aged product only. The single port ’s transform er cons umes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V for
10BASE-T.
10. The si ngl e port’s transformer consumes less than 1mA during the power-saving mode.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 76 Revision 2.3
Electrical Characteristics(9) (Continued)
TA = 25°C, bold values indicate –40°C≤ TA ≤ +85°C, unle ss noted.
Symbol Parameter Condition Min. Typ. Max. Units
CMOS Inputs (VDD_IO = 3.3V/2.5V/1.8V)
VIH Input High Voltage 2.0
/1.8
/1.3 V
VIL Input Low Voltage 0.8
/0.7
/0.5 V
IIN Input Current VIN = GND ~ VDD_IO -10 10 µA
CMOS Outputs (VDD_IO = 3.3V/2.5V/1.8V)
VOH Output High Voltage IOH = 8mA 2.4
/2.0
/1.5 V
VOL Output Low Voltage IOL = 8mA 0.4
/0.4
/0.4 V
|IOZ| Output Tri-State Leakage 10 µA
Power Management Mode
IDD3 Power-saving mode(10) Et hernet cable di sco nne cted and auto-
negotiate 70 mA
IDD4 Soft power-down mode Set Bit [1:0] = 10 in PMECR register 2 mA
IDD5 Energy-dete ct mod e At low power state 2 mA
100BaseTX Transmit (measured differentially after 1:1 transformer)
VO Peak Differential Output Voltage 100Ω termination on the differential output ±0.95 ±1.05 V
VIMB Output Voltage Imbalance 100Ω termination on the differential output 2 %
tr/tf Rise/Fall Time 3 5 ns
Rise/Fall Imb ala nce 0 0.5 ns
Duty Cycle Di stortion ±0.25 ns
Overshoot 5 %
VSET Reference Voltage of ISET 0.5 V
Output Jitter Peak-to-peak 0.7 1.4 ns
10Base-T Receive
VSQ Squelch Threshold 5MHz square wave 400 mV
10BaseT Transmit (measured differentially after 1:1 transformer)
VP Peak Differential Output Voltage 100Ω termination on the differential output 2.2 2.5 2.8 V
Jitter Added 100Ω termination on the differential output
(peak-to-peak) 1.8 3.5 ns
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 77 Revision 2.3
Timing Specifications
Asynchronous Read and Write Timing (Processor Read and Write)
Figure 10. Asynchronous Cycle
Table 14. Asynchronous Cycle Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Units
t1 CSN, CMD valid to RDN, W RN active 0 ns
t2 RDN active to Read Data SD[15:0] valid
Note: This is KSZ8851 output delay after RDN active when the processor read
data. 24 32 ns
t3 RDN inactive to Read data invalid
Note: The processor latc h read data at RDN rising edge. 1 2 ns
t4 CSN, CMD hold after RDN, WRN inac tive 0 ns
t5 WRN active to write data valid (bit12=0 in RXFDPR) 8 16 ns
WRN active to write data valid (bit12=1 in RXFDPR)
Note: It is better if the processor can provide data less than 4ns aft er WRN active.
If the processor provides data more than 4ns after WRN active, keep the default
bit12=0 of the register RXFDPR.
4 ns
t6 RDN Read active time (low) 40 ns
WRN Write active time (low) 40 ns
t7 RDN Read inactive time (high) 10 ns
RDN Read inactive time (high) 10 ns
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 78 Revision 2.3
Auto-Negotiation Timing
Figure 11. Auto-Negotiation Timing
Table 15. Auto-Negotiation Timing Parameters
Timing Parameter Description Min. Typ. Max. Units
tBTB FLP burst to FLP burst 8 16 24 ms
tFLPW FLP burst width 2 ms
tPW Clock/data pulse width 100 ns
tCTD Clock pulse to data pulse 55.5 64 69.5 µs
tCTC Clock pulse to clock pulse 111 128 139 µs
Number of clock/ data pul se s per burs t 17 33
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 79 Revision 2.3
Reset Timing
As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing
requirem ent when the KSZ8851-16MLL use a sing le 3.3V po wer suppl y with inter nal 1.8V LDO. It is also req uirement the
power-sequ encing to po wer up the 1.8V voltage earl ier than VD DIO voltage if the internal 1. 8V LDO is not used. At leas t,
the both 1.8V voltage and VDDIO voltage should come up at the same time when do not using the internal 1.8V LDO.
The reset timing requirement is summarized in the Figure 12 and Table 16.
Figure 12. Reset Timing
Table 16. Reset Timing Parameters
Symbol Parameter Min Max Unit
tsr Stable supply voltages to reset High 10 ms
SUPPLY
VOLTAGE
RSTN
tsr
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 80 Revision 2.3
EEPROM Timing
Figure 13. EEPROM Read Cycle Timing Diagram
Table 17. EEPROM Timing Parameters
Timing Parameter Description Min Typ Max Unit
tcyc Clock cycle 0.8 (OBCR[1:0]=00 on-chip
bus speed @ 125MHz) µs
ts Setup time 20 ns
th Hold time 20 ns
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 81 Revision 2.3
Reset Circuit Diagram
Micrel recomm ends the following discrete reset circuit as shown in Figure 14 when powering up the KS8851 device. For
applications where the reset signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit
shown in Figure 15.
Figure 14. Recommended Reset Circuit
Figure 15. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
VC
R
10k
C
10µF
D1
KSZ8851
RST
D1: 1N4148
VC
R
10k
D2
C
10µF
D1
CPU/FPGA
RST_OUT_n
KSZ8851
RST
D1, D2: 1N4148
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 82 Revision 2.3
Selection of Isolation Transformers
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated comm on-mode choke
is recommended for exceeding FCC requirements.
Table 18 gives recommended transformer characteristics.
Table 18. Transformer Selection Criteria
Parameter Value Test Condition
Turns ratio 1 CT : 1 CT
Open-circuit inductance (min) 350µH 100mV, 100kHz, 8mA
Leakage induct anc e (max) 0.4µH 1MHz (min)
Inter-winding capacitance (max) 12pF
DC resistance (max) 0.9Ω
Insertion lo ss (max ) 1.0dB 0MHz – 65MHz
HIPOT (min) 1500VRMS
Table 19. Qualified Single-Port Magnetics
Magnetic Manuf act ur er Part Number Auto MDI-X Number of Port
Pulse H1102 Yes 1
Pulse (low cost) H1260 Yes 1
Transpower HB726 Yes 1
Bel Fuse S558-5999-U7 Yes 1
Delta LF8505 Yes 1
LanKom LF-H41S Yes 1
TDK (Mag J ack) TLA-6T718 Yes 1
Selection of Reference Crystal
Table 20. Typical Reference Crystal Characteristics
Chacteristics Value Units
Frequency 25 MHz
Frequency tolerance (max) ±50 ppm
Load capacitan ce (max) 20 pF
Series resistance 40 Ω
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 84 Revision 2.3
Acronyms and Glossary
BIU Bus Interface Unit The host interface function that performs code convers ion, buffering,
and the like required for communications to and from a network.
BPDU Bridge Protocol Data Unit A packet contain ing port s, add ress es, etc . to make sure data being
passed through a bridged network arrives at its proper destination.
CMOS Complementary Metal Oxide Semiconductor A common semiconductor manufacturing technique in which positive
and negative types of transistors are combined to form a current gate
that in turn forms an effective means of controlling electrical current
through a chip.
CRC Cyclic Redundancy Check A common technique for detecting data transmission errors. CRC for
Ethernet is 32 bits long.
Cut-through switch A switch typically processes received packets by reading in the full
packet (storing), then processing the packet to determine where it
needs to go, then forwarding it. A cut-through switch simply reads in
the first bit of an incoming packet and forwards the packet. Cut-
through switches do not store the packet.
DA Destination Address The address to send packets.
DMA Direct Memory Access A design in whic h memory on a chip is controlled independently of
the CPU.
EEPROM Electr onically Erasab le Progra mmable R ead-only M emory A design in which memory on a chip can be erased by exposing it to
an electrical charge.
EISA Extended Industry Standard Architecture A bus architecture designed for PCs using 80x86 processors, or an
Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32
bits wide and support multiprocessing.
EMI Electro-Magnetic Interf eren ce A naturally occurring phenomena when the electromagnetic field of
one device disrupts, impedes or degrades the electromagnetic field of
another device by coming into proximity with it. In c omputer
technology, computer devices are susceptible to EMI because
electromagnetic fields are a byproduct of passing electric i ty through a
wire. Data lines that hav e n ot been properly shielded ar e su sceptib le
to data corruption by EMI.
FCS Frame Check Sequence See CRC.
FID Frame or Filter ID Specifies the frame identifier. Alternately is the filter identifier.
IGMP Internet Group Management Protocol The protocol defined by RFC 1112 for IP multicast transmissions.
IPG Inter-Packet G ap A time delay between successive data packets mandated by the
network standard for protocol reasons. In Ethernet, the medium has
to be "silent" (i.e., no data transfer) for a short period of time before a
node can consider the network idle and start to transmit. IPG is used
to correct timing differences between a transmitter and receiver.
During the IPG, no data is transferred, and information in the gap can
be discarded or additions inserted without impact on data integrity.
ISI Inter-Symbol Interference The disruption of transmitted code caused by adjacent pulses
affecting or interfering with each other.
ISA Industry Standard Architecture A bus architecture used in the IBM PC/XT and PC/AT.
Jumbo Packet A packet larger than the standard Ethernet packet (1500 bytes).
Large packet size s allow for more effic ient use of bandw idth, lower
overhead, less processing, etc.
MDI Medium Dependent Interface An Ethernet port connection that allows network hubs or switches to
connect to other hubs or switches without a null-modem, or
crossover, c able. MDI provides the standard interface to a particular
media (copper or fiber) and is t herefore 'media dependent.'
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 85 Revision 2.3
MDI-X Medium Dependent Interface Crossover An Ethernet port connection that allows networked end stations (i.e.,
PCs or workstations) to connect to each other using a null-modem, or
crossover, c able. For 10/100 full-duplex networks, an end point (such
as a computer) and a switch are wired so that each transmitter
connects to the far end receiver. When connecting two computers
together, a cable that crosses the TX and RX is required to do this.
With auto MDI-X, the PHY senses the correct TX and RX roles,
eliminating any cable confusion.
MIB M anagement Inf or mat ion B as e The MIB comprises the management portion of network devices. This
can include things like monitoring traffic levels and faults (statistical),
and can also change operat ing parameters in network nodes (static
forwarding addresses).
MII Media Independent Interface The MII accesses PHY registers as defined in the IEEE 802.3
specification.
NIC Network Interface Card An expansion board ins erted into a computer to allow it to be
connected to a network. Most NICs are designed for a particular type
of network, protocol, and media, although some can serve multiple
networks.
NPVID Non Port VLAN ID The Port VLAN ID value is used as a VLAN reference.
PLL Phase-Locked Loop An electronic circuit that controls an oscillator so that it maintains a
constant phase angle (i.e., lock) on the frequency of an input, or
reference, signal. A PLL ensures that a communication signal is
locked on a specific frequency and can also be used to generate,
modulate, and demodulate a signal and divide a frequenc y.
PME Power Management Event An occurrence that affects the directing of power to different
components of a system.
QMU Queue Management Unit Manages packet traffic between MAC/PHY interface and the system
host. The QMU has built-in packet memories for receive and transmit
functions called TXQ (Transmit Queue) and RXQ (Receive Queue).
SA Source Address The address from which information has been sent.
TDR Time Domain Reflectometry TDR is used to pinpoint flaws and problems in underground and aerial
wire, cabling, and fiber optics. They send a signal down the conductor
and measure the time it takes for the signa l -- or part of the si gnal -- to
return.
UTP Unshielded Twisted Pair Commonly a cable containing 4 twisted pairs of wires. The wi res are
twisted in such a manner as to cancel electrical interference
generated in each wire, therefore shielding is not required.
VLAN Virtual Local Area Network A configuration of comput er s t hat acts as if all computers are
connected by the same physical network but which may be located
virtually anywhere.
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
March 12
, 2015 86 Revision 2.3
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-100 0 WEB http://www.micrel.com
Micrel, Inc. is a leadi ng global manufacturer of I C solutions for the worldwide high pe
rformance li near and power, LAN, and tim ing &
communications
markets. The Company’s products include advanced mixed
-signal, analog & power semiconductors; high-
performance communication, clock
manage
ment, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs.
Company
customers include leading manufacturers of enterprise, consumer, industri
al, mobile, telecommunications, automotive, and computer products.
Corporation headquarters and state
-of-the-
art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technol ogy design centers s itu
ated throughout the Americas, Europe, and Asia. Additionally
, the Company maintains an extensive network
of distribut ors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the inf
ormation furnished in this data
sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use.
Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice.
No license, whether
express, implied, arising by estoppel or otherwise, to any intellectual
property rights
is granted by this docum ent. E
xcept as provided in Micrel’s terms and conditions of sale for such products, Mic rel assumes no li ability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a partic ular purpose, merchant abi lit y, or inf ri ngem ent of any patent, copyright
, or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant i nto t he body or (b) support or sustain lif e, and whose fai l ure to perform can be reasonabl y expected to result in a signi ficant injury to t he us er. A
Purchaser’s use or s al e of Micrel Products for use i n l ife support appliances, devi c es or s yst ems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Mic rel for any damages resulting from such use or sale.
© 2008 Micrel, Incorporated.
