Features * Utilizes the ARM7TDMITM ARM(R) Thumb(R) Processor Core * * * * * * * * * * * * * * * * * - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In-circuit Emulation) 2K Bytes (M63200) or 3K Bytes (M43300) Internal RAM Fully Programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to 8 Chip Selects - Software Programmable 8/16-bit External Data Bus Multi-processor Interface (M63200 only) - High-performance External Processor Interface - 512 x 16-bit Dual-port RAM 8-channel Peripheral Data Controller 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request 58 Programmable I/O Lines 6-channel 16-bit Timer/Counter - 6 External Clock Inputs - 2 Multi-purpose I/O Pins per Channel 3 USARTs - 2 Dedicated Peripheral Data Controller (PDC) Channels per USART - Support for up to 9-bit Data Transfers Master/Slave SPI Interface - 2 Dedicated Peripheral Data Controller (PDC) Channels - 8- to 16-bit Programmable Data Length - 4 External Slave Chip Selects Programmable Watchdog Timer Power Management Controller (PMC) - CPU and Peripherals Can be Deactivated Individually IEEE 1149.1 JTAG Boundary Scan on all Active Pins Fully Static Operation: 0 Hz to 25 MHz (12 MHz @ 1.8V Core, 25 MHz @ 2.7V Core) 1.8V to 3.6V Core Operating Voltage Range 2.7V to 5.5V I/O Operating Voltage Range -40C to +85C Operating Temperature Range AT91M63200 in a 176-lead TQFP Package; AT91M43300 in a 144-ball BGA Package AT91 ARM(R) Thumb(R) Microcontrollers AT91M63200 AT91M43300 Electrical Characteristics Description The AT91M63200 and AT91M43300 are members of the Atmel AT91 16/32-bit Microcontroller family which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features Atmel's high-density, in-system programmable, nonvolatile memory technology. Both products have a direct connection to off-chip memory, including Flash, through the External Bus Interface. For the AT91M63200, the Multi-Processor Interface (MPI) provides a high-performance interface with an external coprocessor or a high bandwidth peripheral. Both products are manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-processor interface and a wide range of peripheral functions on a monolithic chip, the AT91M63200 and AT91M43300 provide a highly-flexible and cost-effective solution to many compute-intensive real-time applications. Rev. 1090A-04/00 1 Absolute Maximum Ratings* Operating Temperature (Commercial) ........0 to +70C *NOTICE: Operating Temperature (Industrial) .....-40C to +85C Voltage on any Input Pin with Respect to Ground.......................-0.5V to +5.5V Maximum Operating Voltage (Core) .....................3.6V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage (I/Os) ......................5.5V DC Output Current ..............................................4 mA DC Characteristics Symbol Parameter VDDCORE (1) DC Supply Voltage Core VDDIO DC Supply I/Os Condition Min Typ Max Units 1.8 3.6 V 2.7V = < VDDCORE = < 3.6V VDDCORE VDDCORE + 2.0 or 5.5 V 1.8V = < VDDCORE = < 2.7V 2.7 3.3 TA Ambient Temperature -40 85 C VIL Low-level Input Voltage -0.3 0.8 V VIH High-level Input Voltage 2 VDDIO + 0.3 V 0.4 V 0.4 V 2.7 = < VDDIO = < 3.6; IO (2) = 2 mA VOL Low-level Output Voltage VDDCORE = < VDDIO = < 5.5V; IO(2) = 4 mA 2.7 = < VDDIO = < 3.6; IO(2) = 2 mA VDDIO - 0.4 V VDDCORE = < VDDIO = < 5.5V; IO(2) = 4 mA VDDIO - 0.4 V VOH High-level Output Voltage ILEAK Input-leakage Current 100 nA IPULL Input Pull-up Current 100 A ICAP Input Capacitance 12 pF ISC Static Current 1. 2. 2 VDDIO = VDDCORE = 3.6V MCKI = 0 Hz, NRST = 1 See Table 4. IO = Output current. AT91M6300/M43300 60 A AT91M6300/M43300 Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e. VDDIO = 3.3V, VDDCORE = 3.3V or 1.8V; T = 25). They represent the power consumption on the VDDCORE power supply. Table 1. Core Power Consumption VDDCORE Mode 1.8V 3.3V 0.05 0.41 Fetch in ARM mode out of Internal SRAM All peripheral clocks activated 3.1 13.3 Fetch in ARM mode out of Internal SRAM All peripheral clocks deactivated 1.8 7.4 All peripheral clocks activated 2.0 8.7 All peripheral clocks deactivated 0.54 2.4 Conditions Reset Unit Normal mW/MHz Idle Table 2. Core Power Consumption per Peripheral VDDCORE Peripheral 1.8V 3.3V PIO Controller 0.07 0.32 Timer Counter channel 0.07 0.28 Timer Counter Block (3 channels) 0.18 0.75 USART 0.22 0.99 SPI 0.22 1.02 Unit mW/MHz 3 Conditions Environment Constraints The output delays are valid for a capacitive load of 50 pF as shown in Figure 1. Figure 1. Output/Bidir Pad Capacitive Load CL = 50 pF PAD Timing Results The output delays are for a capacitive load of 50 pF as shown in Figure 1. In order to obtain the timing for other capacitance values, the following equation should be used. t = t datasheet + factor x ( C load - 50pF ) Table 3. Derating Factor Due to Capacitive Load Variation Parameter Factor Commercial Industrial Units 0.052 0.058 ns/pF In the tables that follow, the output delays are for industrial conditions only. Voltage Ranges Although the core may be supplied between 1.8V and 3.6V, there are two voltage ranges that have been characterized for timing purposes. These are from 1.8V to 2.2V (core @ 2V), and 2.7V to 3.6V (core at 3.3V). Timing values are given for both sets of conditions, as in Table 4. Table 4. Voltage Ranges for Timing Characterization VDDCORE VDDIO Condition Minimum Maximum Minimum Maximum Core @ 2V 1.8 2.2 2.7 3.3 Core @ 3.3V 2.7 3.6 2.7 5.5 Unit V 4 AT91M6300/M43300 AT91M6300/M43300 Clock Waveforms Table 5. Clock Waveform Parameters Minimum Core @2V Symbol Parameter 1/(tCP) Oscillator Frequency tCP Main Clock Period tCH Maximum Core @3.3V Core @2V Core @3.3V Units 12 25 MHz 83 40 High Time TBD 18 tCL Low Time TBD 18 tr Rising Edge TBD 7 tf Falling Edge TBD 7 ns Table 6. Clock Propagation Times Minimum Maximum Symbol Parameter Core @2V Core @3.3V Core @2V Core @3.3V tCDLH Rising Edge Propagation Time TBD 20 TBD TBD tCDHL Falling Edge Propagation Time TBD 18 TBD TBD Units ns Figure 2. Clock Waveform tr tCH MCKI tf 0.7 VDDIO 0.3 VDDIO tCL tCP MCKO tCDLH tCDHL 5 AC Characteristics EBI Signals Relative to MCKI The following tables show timings relative to operating condition limits defined in Table 4. See Figure 3. Table 7. General Purpose EBI Signals Minimum Symbol Parameter EBI1 Core @2V Maximum Core @3.3V Core @2V Core @3.3V Units MCKI Falling to NUB Valid TBD 20 ns EBI2 MCKI Falling to NLB/A0 Valid TBD 20 ns EBI3 MCKI Falling to A7 - A1 Valid TBD 20 ns EBI4 MCKI Falling to A23 - A8 Valid TBD 20 ns EBI5 MCKI Falling to Chip Select TBD 5 TBD 20 ns EBI6 NWAIT Setup before MCKI Rising TBD 5 ns EBI7 NWAIT Hold after MCKI Rising TBD 4 ns Table 8. EBI Write Signals Minimum Symbol Parameter EBI8 MCKI Rising to NWR Active (No Wait States) TBD MCKI Rising to NWR Active (Wait States) TBD MCKI Falling to NWR Inactive (No Wait States) TBD MCKI Rising to NWR Inactive (Wait States) TBD EBI12 MCKI Rising to D0 - D15 Out Valid TBD EBI19 NWR High to A23 - A1, NUB/NLB/A0, NCS, CS Changes (No Wait States) EBI20 NWR High to A23 - A1, NCS, CS Changes (Wait States) tCP/2 ns EBI21 Data Out Valid before NWR High tCH - 5 ns EBI22 Data Out Valid after NWR High tCP/2 ns EBI9 EBI10 EBI11 6 AT91M6300/M43300 Core @2V Maximum Core @3.3V TBD 2 Core @2V Core @3.3V Units 20 ns 20 ns 20 ns 20 ns 20 ns ns AT91M6300/M43300 Table 9. EBI Read Signals Minimum Maximum Symbol Parameter EBI13 MCKI Falling to NRD Valid(1) EBI14 MCKI Rising to NRD Valid(2) EBI15 D0 - D15 in Setup before MCKI Falling TBD 0 EBI16 D0 - D15 in Hold after MCKI Falling TBD 3 EBI17 NRD High to A23 - A1, NCS, CS Changes TBD Data Hold after NRD High EBI18 Notes: 1. Early Read Protocol 2. Standard Read Protocol Core @2V Core @3.3V Core @2V Core @3.3V TBD 5 TBD 18 TBD 20 Units ns 0 TBD 0 7 Figure 3. EBI Signals Relative to MCKI MCKI EBI5 EBI5 NCS CS EBI3/EBI4 No Wait Wait A1 - A23 EBI6 EBI7 NWAIT EBI1/EBI2 NUB/NLB/A0 EBI13 EBI13 EBI17 NRD(1) EBI14 EBI18 NRD(2) EBI15 EBI16 D0 - D15 read EBI8 EBI10 EBI19 NWR (No Wait States) EBI9 EBI20 EBI11 NWR (Wait States) EBI12 EBI21 EBI22 EBI22 D0 - D15 to Write No Wait Notes: 8 1. Early Read Protocol 2. Standard Read Protocol AT91M6300/M43300 Wait AT91M6300/M43300 Peripheral Signals Relative to MCKI USART Signals Table 10. USART Outputs Minimum Symbol Parameter US1 Maximum Core @2V Core @3.3V Core @2V Core @3.3V Units MCKI Rising to SCK Output Rising/Falling TBD TBD TBD 25 ns US2 MCKI Rising to TXD Toggling TBD TBD TBD 35 ns US3 SCK Output Falling to TXD Toggling TBD TBD TBD 10 ns US4 SCK Input Falling to TXD Toggling TBD TBD TBD 2(tCP) + 35 ns The inputs can be used synchronously or asynchronously (in relation to MCKI). For synchronous and asynchronous USART inputs, certain setup/hold constraints must be met. These constraints are shown in Tables 11 and 12 and are represented in Figure 4. For asynchronous inputs, a minimum pulse-width is necessary as shown in Table 13 and as represented in Figure 4. Table 11. USART Synchronous Input Setup/Hold Constraints Symbol Type of Input Parameter Setup Hold Units US5 Synchronous RXD Toggling Relative to MCKI Falling 0 5 ns US6 Synchronous SCK Input Rising Relative to MCKI Rising 0 5 ns US7 Synchronous SCK Input Falling Relative to MCKI Rising 0 5 ns Table 12. USART Asynchronous Input Setup/Hold Constraints Symbol Type of Input Parameter Setup Hold Units US8 Asynchronous RXD Toggling Relative to SCK Input Rising tCP/2 - 2 tCP/2 + 2 ns Table 13. USART Asynchronous Input Minimum Pulse-width Symbol Type of Input Parameter US9 Asynchronous RXD/SCK Minimum Pulse-width Pulse-width Units 3(tCP/2) ns 9 Figure 4. USART Signals Relative to MCKI MCKI US1 US1 SCK Output US3 US7H US6H US7S US6S SCK Input US2 US8S US8H TXD RXD US5S US5H US9 RXD/SCK (Asynchronous) 10 AT91M6300/M43300 US4 AT91M6300/M43300 SPI Signals Table 14. SPI Signals in Master Mode Minimum Symbol Parameter tSPCK SPI Operating Period fSPCK SPI Operating Frequency SP1 Core @2V Maximum Core @3.3V Core @2V Core @3.3V Units 4(tCP) 16320(tCP) ns 1/16320(tCP) 1/4(tCP) GHz Delay before NPCS[3:0] 4(tCP) 261120(tCP) ns SP2 Delay between Chip Selects 6(tCP) 8160(tCP) ns SP3 Delay before SPCK 2(tCP) 8160(tCP) ns SP4 MISO/SPCK Setup Time SP5 MISO/SPCK Hold Time SP6 MOSI Valid after SPCK Edge TBD TBD 18 ns 0 ns TBD 7 ns Figure 5. SPI Signals SP1 SP3 NPCS[3:0] output SP2 tSPCK SPCK Output CPOL = 0 SPCK Output CPOL = 1 SP4 SP5 MISO Input MSB In Data LSB In Data LSB Out SP6 MOSI Output MSB Out 11 Timer Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total-count Detection mode. In addition there are the following delays relative to MCKI waveforms. Table 15. Timer Outputs Maximum Symbol Parameter Core @2V Core @3.3V TC1 MCKI Rising to TIOA Rising TBD 22 TC2 MCKI Rising to TIOA Falling TBD 22 TC3 MCKI Rising to TIOB Rising TBD 22 TC4 MCKI Rising to TIOB Falling TBD 22 Units ns The inputs can be used synchronously or asynchronously (in relation to MCKI). For synchronous Timer inputs, certain setup/hold constraints must be met. These constraints are shown in the Table 16 and are represented in Figure 6. For asynchronous inputs, a minimum pulse-width and a minimum input period are necessary as shown in Tables 17 and 18 and as represented in Figure 6. Table 16. Synchronous Timer Inputs Setup Hold Symbol Type of Input Parameter Core @2V Core @3.3V Core @2V Core @3.3V TC5 Synchronous TIOA/TIOB Rising Relative to MCKI Rising TBD 2 TBD 5 TC6 Synchronous TIOA/TIOB Falling Relative to MCKI Rising TBD 2 Units 5 TBD ns TC7 Synchronous TCLK Rising Relative to MCKI Rising TBD 2 TBD 5 TC8 Synchronous TCLK Falling Relative to MCKI Rising TBD 2 TBD 5 Table 17. Asynchronous Timer Input Minimum Pulse-width Symbol Type of Inputs Parameter TC9 Asynchronous TCLK/TIOA/TIOB Minimum Pulse-width Pulse-width Units 3(tCP/2) ns Input Period Units 5(tCP/2) ns Table 18. Asynchronous Timer Input Minimum Input Period Symbol Type of Inputs Parameter TC10 Asynchronous TCLK/TIOA/TIOB Minimum Input Period 12 AT91M6300/M43300 AT91M6300/M43300 Figure 6. Timer Relative to MCKI TC10 3(tCP/2) 1(tCP) MCKI Detect Detect TC9 TIOA/TIOB/TCLK Asynchronous In TC7H TC7S TC8S TC8H TCLK Synchronous Input TC5H TC5S TC6H TC6S TIOA/TIOB Synchronous Inputs TC1 TC2 TIOA Output TC3 TC4 TIOB Output 13 Watchdog Timer Signals Table 19. Watchdog Timer Outputs Maximum Symbol Parameter Core @2V Core @3.3V WD1 MCKI Rising to NWDOVF Rising TBD 20 WD2 MCKI Rising to NWDOVF Falling TBD 20 Units ns Figure 7. Watchdog Signals Relative to MCKI MCKI WD1 NWDOVF Output WD2 Z Z Reset Signals Certain setup constraints must be met. These constraints are shown in Table 20 and are represented in Figure 8. Table 20. Reset Setup Constraints Setup Symbol Parameter RST1 NRST Rising Related to MCKI Rising Core @ 2V Core @3.3V Units TBD 5 ns A minimum pulse width is necessary as shown in Table 21 and as represented in Figure 8. Table 21. Reset Minimum Pulse-width Symbol Parameter RST3 NRST Minimum Pulse-width Pulse-width Units 10(tCP) ns Figure 8. Reset Signals Relative to MCKI MCKI RST1H RST3 NRST Only the NRST rising edge is synchronized. The falling edge is asynchronous. 14 AT91M6300/M43300 RST1S AT91M6300/M43300 Advanced Interrupt Controller Signals The inputs can be used synchronously or asynchronously (in relation to MCKI). For synchronous AIC inputs, certain setup/hold constraints must be met. These constraints are shown in Table 22 and are represented in Figure 9. For asynchronous inputs, a minimum pulse width is necessary as shown in Table 23 and as represented in Figure 9. Table 22. AIC Synchronous Input Setup/Hold Constraints Setup Hold Core @ 2V Core @3.3V Core @ 2V Core @3.3V Units FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Rising Relative to MCKI Rising TBD 0 TBD 4 ns FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Falling Related to MCKI Rising TBD 0 TBD 4 ns Symbol Type Parameter AIC1 Synchronous AIC2 Synchronous Table 23. AIC Asynchronous Input Minimum Pulse-width Symbol Type Parameter AIC5 Asynchronous FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse-width Pulse-width Units 3(tCP/2) ns Input Period Units 5(tCP/2) ns Table 24. AIC Asynchronous Input Minimum Input Period Symbol Type Parameter AIC6 Asynchronous AIC Minimum Input Period Figure 9. AIC Signals Relative to MCKI AIC6 MCKI AIC5 FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Asynchronous Input AIC1H AIC1S AIC2H AIC1S FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Synchronous Input 15 Parallel I/O Signals Table 25. PIO Outputs Maximum Symbol Parameter Core @2V Core @3.3V Units PIO1 MCKI Falling to PIO Output Rising TBD 22 ns PIO2 MCKI Falling to PIO Output Falling TBD 22 ns The inputs can be used synchronously or asynchronously (in relation to MCKI). For synchronous PIO inputs, certain setup/hold constraints must be met. These constraints are shown in the Table 26 and are represented in Figure 10. For asynchronous inputs, a minimum pulse width is necessary as shown in Table 27 and as represented in Figure 10. Table 26. PIO Synchronous Input Setup/Hold Constraints Setup Hold Symbol Type Parameter Core @ 2V Core @3.3V Core @ 2V Core @3.3V PIO3 Synchronous PIO Input Rising Related to MCKI Rising TBD 2 TBD 5 PIO4 Synchronous PIO Input Falling Related to MCKI Rising TBD 2 TBD 5 Units ns Table 27. PIO Asynchronous Input Minimum Pulse-width Symbol Type Parameter PIO5 Asynchronous PIO Input Minimum Pulse-width Pulse-width Units 3(tCP/2) ns Figure 10. PIO Signals Relative to MCKI MCKI PIO3H PIO3S PIO4H PIO4S PIO Synchronous Inputs PIO5 PIO Asynchronous Inputs PIO1 PIO Outputs 16 AT91M6300/M43300 PIO2 AT91M6300/M43300 Multi-processor Interface Signals (AT91M63200 Only) Figure 11. External Arbitration MPI_BR t1 t2 MPI_BG MPI_D[15:0] Data Transfer Table 28. External Arbitration Minimum Symbol Parameter t1 MPI_BR High to MPI_BG High Delay (30 pf) t2 MPI_BR Low to MPI_BG Low Core @2V Core @3.3V Maximum Core @2V tCP Core @3.3V 2 x tCP + 12 TBD Units ns 12 17 Table 29. MPI Read Access Minimum Maximum Symbol Parameter Core @2V Core @3.3V TBD 22 Core @2V Core @3.3V tRC Read Cycle Time tAA Address Access Time TBD 22 ns tACS Chip Select Access Time TBD 22 ns tOE Output Enable to Output Valid TBD 10 ns tLB, tUB Byte Select to Output Valid TBD 10 ns tOH Output Hold from Address Change TBD 0 ns tCLZ Chip Select to Output in Low-Z TBD 0 ns tOLZ Output Enable to Output in Low-Z TBD 0 ns tLBLZ, tUBLZ Byte Select to Output in Low-Z TBD 0 ns tCHZ Chip Deselect to Output in High-Z TBD 7 ns tOHZ Output Disable to Output in High-Z TBD 7 ns tLBHZ, tUBHZ Byte Deselect to Output in High-Z TBD 7 ns ns Figure 12. MPI Read Access tRC Valid Address MPI_A[9:1] tAA tOH tCHZ tACS MPI_NCS tOE tOHZ MPI_NOE tLB tUB tLBHZ MPI_NLB, MPI_NUB tOLZ tLBLZ tUBLZ tCLZ MPI_D[15:0] 18 High Impedance AT91M6300/M43300 Units Valid Data tUBHZ AT91M6300/M43300 Table 30. MPI Write Access Minimum Symbol Parameter tWC Maximum Core @2V Core @3.3V Core @2V Write Cycle Time TBD 10 ns tAW Address Valid to End of Write TBD 10 ns tCW Chip Select to End of Write TBD 10 ns tWP Write pulse-width TBD 10 ns tLBW, tUBW Byte Select to End of Write TBD 10 ns tAS Address Setup Time TBD 0 ns tWR Write Recovery Time TBD 0 ns tDW Data Valid to End of Write TBD 10 ns tDH Data Hold Time from End of Write TBD 0 ns tOW Write Disable to Output in Low-Z TBD 10 ns tWHZ Write Enable to Output in High-Z TBD Core @3.3V 7 Unit ns Figure 13. MPI Write Access (MPI_RNW Controlled) tWC Valid Address tAW MPI_A[9:1] tAS tWR tWP MPI_RNW tCW MPI_NCS tLBW tUBW MPI_NLB, MPI_NUB tWHZ tOW high-Z MPI_Dout[15:0] tDW MPI_Din[15:0] High-Z tDH Valid Data High-Z 19 Figure 14. MPI Write Access (MPI_NCS Controlled) tWC Valid Address MPI_A[9:1] tAW tAS tWR tWP MPI_RNW tCW MPI_NCS tLBW tUBW MPI_NLB, MPI_NUB tDW MPI_Din[15:0] High-Z tDH High-Z Valid Data Figure 15. MPI Write Access (MPI_NLB, MPI_NUB Controlled) tWC Valid Address MPI_A[9:1] tAW tAS tWR tWP MPI_RNW tCW MPI_NCS tLBW tUBW MPI_NLB, MPI_NUB tDW MPI_Din[15:0] 20 High-Z AT91M6300/M43300 tDH Valid Data High-Z Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI is a trademark of ARM Ltd. All other marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1090A-04/00/0M