TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
80-mΩ High-Side MOSFET Switch
D
250 mA Continuous Current per Channel
D
Independent Thermal and Short-Circuit
Protection With Overcurrent Logic Output
D
Operating Range . . . 2.7-V to 5.5-V
D
CMOS- and TTL-Compatible Enable Inputs
D
2.5-ms Typical Rise Time
D
Undervoltage Lockout
D
10 µA Maximum Standby Supply Current
D
Bidirectional Switch
D
Available in 8-Pin and 16-Pin SOIC
Packages
D
Ambient Temperature Range, 0°C to 85°C
D
ESD Protection
description
The TPS2090, TPS2091, and TPS2092 dual and
the TPS2095, TPS2096 and TPS2097 quad
power-distribution switches are intended for
applications where heavy capacitive loads and
short circuits are likely to be encountered. The
TPS209x devices incorporate 80-mΩ N-channel
MOSFET high-side power switches for power-distribution systems that require multiple power switches in a
single package. Each switch is controlled by an independent logic enable input. Gate drive is provided by an
internal charge pump designed to control the power-switch rise times and fall times to minimize current surges
during switching. The charge pump requires no external components and allows operation from supplies as low
as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS209x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low .
When continuous heavy overloads and short circuits increase the power dissipation in the switch causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present. The TPS209x devices are designed to current limit at 0.5-A load.
TPS201xA
TPS202x
TPS203x
33 mW, single 0.2 A – 2 A
0.2 A – 2 A
0.2 A – 2 A
TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
80 mW, single 600 mA
1 A
500 mA
500 mA
250 mA
250 mA
GENERAL SWITCH CATALOG
TPS2042
TPS2052
TPS2046
TPS2056
80 mW, dual 500 mA
500 mA
250 mA
250 mA
TPS2100/1
260 mW IN1 500 mA
IN2 10 mA
OUT
IN1
IN2 TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
1.3 W
TPS2043
TPS2053
TPS2047
TPS2057
80 mW , triple
500 mA
500 mA
250 mA
250 mA
TPS2044
TPS2054
TPS2048
TPS2058
80 mW, quad
500 mA
500 mA
250 mA
250 mA
80 mW, dual
TPS2080
TPS2081
TPS2082
TPS2090
500 mA
500 mA
500 mA
250 mA
TPS2091
TPS2092 250 mA
250 mA
80 mW, quad
TPS2085
TPS2086
TPS2087
TPS2095
500 mA
500 mA
500 mA
250 mA
TPS2096
TPS2097 250 mA
250 mA
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
GND
IN1
IN2
EN1†
OC
OUT1
OUT2
EN2†
TPS2090, TPS2091, AND TPS2092
D PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
IN2
EN1†
GNDB
IN3
IN4
EN3†
OCA
OUT1
OUT2
EN2†
OCB
OUT3
OUT4
EN4†
TPS2095, TPS2096 AND TPS2097
D PACKAGE
(TOP VIEW)
†See Available Options table
†See Available Options table
(TOP VIEW)
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
DUAL POWER DISTRIBUTION SWITCHES
TA
ENABLE RECOMMENDED
MAXIMUM
CONTINUOUS
TYPICAL SHORT-
CIRCUIT CURRENT
PACKAGED
DEVICES
T
AEN1 EN2
CONTINUOUS
LOAD CURRENT
(A)
LIMIT AT 25°C
(A) SMALL OUTLINE
(D)†
Active high Active high TPS2090D
0°C to 85°CActive high Active low 0.25 0.5 TPS2091D
Active low Active low TPS2092D
QUAD POWER DISTRIBUTION SWITCHES
TA
ENABLE RECOMMENDED
MAXIMUM
CONTINUOUS
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT
PACKAGED
DEVICES
T
AEN1 EN2 EN3 EN4
CONTINUOUS
LOAD CURRENT
(A)
CURRENT
LIMIT
AT 25°C
(A) SMALL OUTLINE
(D)†
Active high Active high Active high Active high TPS2095D
0°C to 85°CActive high Active low Active high Active low 0.25 0.5 TPS2096D
Active low Active low Active low Active low TPS2097D
†The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2091DR)
TPS2092 functional block diagram
†Current sense
Thermal
Sense
Driver Current
Limit
Charge
Pump
VCC Select
and UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GND
EN1‡
IN2
EN2§
OC
OUT1
OUT2
IN1
‡Active high for TPS2090 and TPS2091
§Active high for TPS2090
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2097 functional block diagram
Thermal
Sense
Driver Current
Limit
Charge
Pump
VCC Select
and UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDA
EN1‡
IN2
EN2§
OCA
OUT1
OUT2
IN1
†Current sense
Thermal
Sense
Driver Current
Limit
Charge
Pump
VCC Select
and UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDB
EN3‡
IN4
EN4§
OCB
OUT3
OUT4
IN3
‡Active high for TPS2095 and TPS2096
§Active high for TPS2095
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
DUAL POWER-DISTRIBUTION SWITCHES
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2090 TPS2091 TPS2092
EN1 4 I Enable input. Active low turns on power switch.
EN2 5 5 I Enable input. Active low turns on power switch.
EN1 4 4 I Enable input. Active high turns on power switch.
EN2 5 I Enable input. Active high turns on power switch.
GND 1 1 1 I Ground
IN1 2 2 2 I N-Channel MOSFET Drain
IN2 3 3 3 I N-Channel MOSFET Drain
OC 8 8 8 O Overcurrent. Open drain output active low
OUT1 7 7 7 O Power-switch output
OUT2 6 6 6 O Power-switch output
QUAD POWER-DISTRIBUTION SWITCHES
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2095 TPS2096 TPS2097
EN1 4 I Enable input. Active low turns on power switch.
EN2 13 13 I Enable input. Active low turns on power switch.
EN3 8 I Enable input. Active low turns on power switch.
EN4 9 9 I Enable input. Active low turns on power switch.
EN1 4 4 I Enable input. Active high turns on power switch.
EN2 13 I Enable input. Active high turns on power switch.
EN3 8 8 I Enable input. Active high turns on power switch.
EN4 9 I Enable input. Active high turns on power switch.
GNDA 1 1 1 Ground for IN1 and IN2 switch and circuitry
GNDB 5 5 5 Ground for IN3 and IN4 switch and circuitry
IN1 2 2 2 I N-channel MOSFET drain
IN2 3 3 3 I N-channel MOSFET drain
IN3 6 6 6 I N-channel MOSFET drain
IN4 7 7 7 I N-channel MOSFET drain
OCA 16 16 16 O Overcurrent indicator for switch 1 and switch 2. Active-low open drain output.
OCB 12 12 12 O Overcurrent indicator for switch 3 and switch 4. Active low open drain output
OUT1 15 15 15 O Power-switch output
OUT2 14 14 14 O Power-switch output
OUT3 11 11 11 OPower-switch output
OUT4 10 10 10 O Power-switch output
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when
disabled. The power switch supplies a minimum of 250 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx or ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on ENx or a logic low is present on ENx. A
logic low input on ENx or logic high on ENx restores bias to the drive and control circuits and turns the power
on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open drain output is asserted (active low) when an overcurrent or over temperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS209x implements a dual thermal trip to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature
rises to approximately 140°C, the internal thermal sense circuitry checks to determine which power switch is
in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the
adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled approximately
20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The
(OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(IN) (see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO(OUTx) (see Note 1) –0.3 V to VI(IN) + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI(ENx) or VI(ENx) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(OUTx) internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ0°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine model 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged device model (CDM) 750 V. . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D-8 725 mW 5.8 mW/°C464 mW 377 mW
D-16 1123 mW 9 mW/°C719 mW 584 mW
recommended operating conditions
MIN MAX UNIT
Input voltage, VI(IN) 2.7 5.5 V
Input voltage, VI(ENx) or VI(ENx) 0 5.5 V
Continuous output current, IO (per switch) 0 250 mA
Operating virtual junction temperature, TJ0 125 °C
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = VI(INx) (unless otherwise noted)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Suppl
y
current, low-level
No Load on OUT
VI(ENx)
=
VI(IN),
TJ = 25°C 0.025 1
µA
y,
output
No
Load
on
OUT
VI(ENx)
=
VI(IN)
,
VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C 10 µ
A
Suppl
y
current,
No Load on OUT
V
I(ENx)
= 0 V
,
TJ = 25°C 85 110
µA
y,
high-level output
No
Load
on
OUT
VI(ENx)
0
V,
VI(ENx) = VI(IN) –40°C ≤ TJ ≤ 125°C 100 µ
A
Leakage current OUT connected to ground VI(ENx) = VI(IN),
VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C 100 µA
Reverse leakage current INx = high impedance VI(ENx) = 0 V,
VI(ENx) = VI(IN) TJ = 125°C 0.3 µA
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = VI(INx) (unless otherwise noted) (continued)
power switch
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
VI(IN) = 5 V, TJ = 25°C, IO = 0.25 A 80 100
VI(IN) = 5 V, TJ = 85°C, IO = 0.25 A 90 120
rDS( )
VI(IN) = 5 V, TJ = 125°C, IO = 0.25 A 100 135 mΩ
r
DS(on)
-
-
VI(IN) = 3.3 V, TJ = 25°C, IO = 0.25 A 90 125
VI(IN) = 3.3 V, TJ = 85°C, IO = 0.25 A 110 145
VI(IN) = 3.3 V, TJ = 125°C, IO = 0.25 A 120 165
t
p
VI(IN) = 5.5 V,
RL=20 ΩTJ = 25°C, CL = 1 µF, 2.5
ms
t
r
,
VI(IN) = 2.7 V,
RL=20 ΩTJ = 25°C, CL = 1 µF, 3
ms
tf
p
VI(IN) = 5.5 V,
RL=20 ΩTJ = 25°C, CL = 1 µF, 4.4
ms
t
f
,
VI(IN) = 2.7 V,
RL=20 ΩTJ = 25°C, CL = 1 µF, 2.5
ms
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input VI(ENx) or VI(ENx)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 V
VIL
Low level in
p
ut voltage
4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 V
V
IL
Low
-
level
input
voltage
2.7 V≤ VI(IN) ≤ 4.5 V 0.4
IIInput current VI(ENx) = 0 V and VI(ENx) = VI(IN), or
VI(ENx) = VI(IN) and VI(ENx) = 0 V –0.5 0.5 µA
ton T urnon time CL = 100 µF, RL=20 Ω 20 ms
toff Turnoff time CL = 100 µF, RL=20 Ω40
current limit
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND,
Device enabled into short circuit 0.3 0.5 0.7 A
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-level input voltage 2 2.5 V
Hysteresis TJ = 25°C 100 mV
overcurrent OCx
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sink current†VO = 5 V 10 mA
Output low voltage IO = 5 mA, VOL(OCx)0.5 V
Off-state current†VO = 5 V, VO = 3.3 V 1µA
†Specified by design, not production tested.
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL CL
OUTx
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUTx)
VI(ENx)
VO(OUTx)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
50% 50%
90%
10%
VI(ENx)
VO(OUTx)
ton toff
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time
With 0.1-µF Load Figure 3. Turnoff Delay and Fall Time
With 0.1-µF Load
VO(OUT)
(2 V/div)
0123456
t – Time – ms 78910
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 20 Ω
VI(EN)
(5 V/div)
04812
t – Time – ms 16 20
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 20 Ω
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
2 6 10 14 18
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4. Turnon Delay and Rise Time
With 1-µF Load Figure 5. Turnoff Delay and Fall Time
With 1-µF Load
0123456
t – Time – ms 78910
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
0 2 4 6 8 10 12
t – Time – ms 14 16 18 20
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
Figure 6. TPS2090, Short-Circuit Current,
Device Enabled Into Short Figure 7. TPS2090, Threshold Trip Current
With Ramped Load on Enabled Device
0123456
t – Time – ms 78910
IO(OUTx)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
0102030405060
t – Time – ms 70 80 90 100
IO(OUT)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
RAMP: 1A/10ms
VO(OUT)
(2 V/div)
VI(ENx)
(5 V/div)
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 8. Ramped Load on Enabled Device Figure 9. Inrush Current With 47-µF, 100-µF
and 220-µF Load Capacitance
VO(OC)
(5 V/div)
IO(OUT)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
RAMP: 1A/100 ms
0 20 40 60 80 100 120
t – Time – ms 140 160 180 200 02 4 6 81012
t – Time – ms 14 16 18 20
VI(EN)
(5 V/div)
IO(OUT)
(0.2 A/div)
47 µF
220 µF
VI(IN) = 5 V
TA = 25°C
RL = 20 Ω
100 µF
Figure 10. 4-Ω Load Connected to
Enabled Device Figure 11. 1-Ω Load Connected to
Enabled Device
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
0 200 400 600 800 1000
VO(OC)
(5 V/div)
t – Time – µs
IO(OUT)
(1 A/div)
VI(IN) = 5 V
TA = 25°C
0 200 400 600 800 1000
VO(OC)
(5 V/div)
t – Time – µs
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
3.3
3
2.7
2.42.5 3 3.5 4 4.5
Turnon Delay Time – ms
3.6
TURNON DELAY TIME
vs
INPUT VOLTAGE
3.9
5 5.5 6
VI – Input Voltage – V
CL = 1 µF
RL = 20 Ω
TA = 25°C
Figure 13
2
4
6
8
10
2.5 3 3.5 4 4.5 5 5.5 6
Turnon Delay Time – ms
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
VI – Input Voltage – V
CL = 1 µF
RL = 20 Ω
TA = 25°C
Figure 14
2
2.1
2.3
2.5
2.7
2.5 3 3.5 4 4.5 5 5.5 6
– Rise Time – ms
RISE TIME
vs
INPUT VOLTAGE
rt
VI – Input Voltage – V
2.2
2.4
2.6
CL = 1 µF
RL = 20 Ω
TA = 25°C
Figure 15
1.3
1.4
1.5
1.6
1.8
1.9
2.5 3 3.5 4 4.5 5 5.5 6
– Fall Time – ms
FALL TIME
vs
INPUT VOLTAGE
ft
VI – Input Voltage – V
1.7
CL = 1 µF
RL = 20 Ω
TA = 25°C
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 16
50
60
70
80
90
100
110
–40 0 25 85 125
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 2.7 V
VI(IN) = 3.3 V
– Supply Current, Output Enabled –
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
II(IN) Aµ
TJ – Junction Temperature – °C
Figure 17
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
– Supply Current, Output Disabled – nA
II(IN)
TJ – Junction Temperature – °C
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4.5 V
0
20
40
60
80
100
120
140
160
–40 0 25 85 125
VI(IN) = 3.3 V
VI(IN) = 2.7 V
Figure 18
20
40
60
80
100
120
140
160
0 25 85 125
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
VI(IN) = 3 V
– Static Drain-Source On-State Resistance – m
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
Ω
rDS(on)
TJ – Junction Temperature –°C
Figure 19
0
5
10
15
20
25
30
35
40
100 150 200 250
– Input-to-Output Voltage – mV
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
VI(IN) –VI(OUT)
IL – Load Current – mA
TA = 25°CVI(IN) = 2.7 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
VI(IN) = 5 V
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
400
410
420
430
440
450
460
470
480
490
500
–40 0 25 85 125
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
– Short-Circuit Output Current – mA
IOS
VI(IN) = 3.3 V
VI(IN) = 2.7 V
VI(IN) = 5 .5V VI(IN) = 4 .5V
VI(IN) = 5V
Figure 21
Threshold Trip Current – A
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
VI – Input Voltage – V
0.57
0.59
0.61
0.63
0.65
0.67
2.5 3 3.5 4 4.5 5 5.5 6
TA = 25°C
Load Ramp = 1 A/10 ms
Figure 22
2.16
2.18
2.2
2.22
2.24
2.26
2.28
2.3
2.32
2.34
2.36
–40 0 25 85 125
UVLO – Undervoltage Lockout – V
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
Start Threshold
Stop Threshold
Figure 23
0
50
100
150
200
250
300
0246810
Current Limit Response –
Peak Current – A
CURRENT LIMIT RESPONSE
vs
PEAK CURRENT
sµ
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
IN1
OC
EN1
EN2
IN2 GND
0.1 µF
2
8
4
5
3
7
6
0.1 µF 22 µF
0.1 µF 22 µF
Load
Load
1
OUT1
OUT2
TPS2092
Power Supply
2.7 V to 5.5 V
0.1 µF
Power Supply
2.7 V to 5.5 V
Figure 24. Typical Application
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS209x senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figure 10 and
11). After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 8). The TPS209x is capable of delivering current up to the current-limit threshold without
damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. The TPS209x devices are
designed to reduce false overcurrent reporting. An internal overcurrent transient filter eliminates the need to use
external components to remove unwanted pulses. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
OC response (continued)
GND
IN1
IN2
EN1
OC
EN2
OUT1
OUT2
TPS2092 Rpullup
V+
Figure 25. Typical Circuit for OC Pin
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to that of power packages; it is
good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of
the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power
dissipation per switch can be calculated by:
PD
+
rDS(on)
I2
Multiply this number by the total number of switches being used, to get the total power dissipation coming from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ
+
PD
R
q
JA
)
TA
Where: TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W (for 8 pin), 111°C/W (for 16 pin)
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS209x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal
to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The
protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal
sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch
continues to cycle in this manner until the load fault or input power is removed.
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
thermal protection (continued)
The TPS209x implements a dual thermal trip to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperature
rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is in an overcurrent
condition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacent
power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach 160°C, both
switches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrent
occurs.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.
generic hot-plug applications (see Figure 26)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS209x, these devices can be used
to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the
TPS209x also ensures the switch will be of f after the card has been removed, and the switch will be off during
the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card
or module.
Power
Supply Block of
Circuitry
TPS2092
GND
IN1
IN2
EN1
OC
OUT1
OUT2
EN2
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
Block of
Circuitry
0.1 µF
1000 µF
Optimum
Figure 26. Typical Hot-Plug Implementation
By placing the TPS209x between the VCC input and the rest of the circuitry, the input power will reach these
devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltage
ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
TPS2090, TPS2091, TPS2092 DUAL,
TPS2095, TPS2096, TPS2097 QUAD
POWER-DISTRIBUTION SWITCHES
SLVS245A – SEPTEMBER 2000 – REVISED MARCH 2001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2090D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2090DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2091D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2091DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2092D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2092DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2095D ACTIVE SOIC D 16 40 TBD CU NIPDAU Level-1-220C-UNLIM
TPS2095DR ACTIVE SOIC D 16 2500 TBD CU NIPDAU Level-1-220C-UNLIM
TPS2096D ACTIVE SOIC D 16 40 TBD CU NIPDAU Level-1-220C-UNLIM
TPS2096DR ACTIVE SOIC D 16 2500 TBD CU NIPDAU Level-1-220C-UNLIM
TPS20976D ACTIVE SOIC D 16 40 TBD Call TI Call TI
TPS2097D ACTIVE SOIC D 16 40 TBD CU NIPDAU Level-1-220C-UNLIM
TPS2097DR ACTIVE SOIC D 16 2500 TBD CU NIPDAU Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 19-Apr-2005
Addendum-Page 1
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