HYS64D128320GU-5-A - Infineon Technologies

Never stop thinking.

HYS64D32301HU–[5/6]–C

HYS[72/64]D64300HU–[5/6]–C

HYS[64/72]D128320HU–[5/6]–C

184-Pin Unbuffered Double Data Rate SDRAM

UDIMM

DDR SDRAM RoHS Compliant Products

DDR SDRAM

Data Sheet, Rev. 1.1, May. 2005

Memory Products

Edition 2005-05

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Never stop thinking.

HYS64D32301HU–[5/6]–C

HYS[72/64]D64300HU–[5/6]–C

HYS[64/72]D128320HU–[5/6]–C

184-Pin Unbuffered Double Data Rate SDRAM

UDIMM

DDR SDRAM

RoHS Compliant Products

Data Sheet, Rev. 1.1, May. 2005

Memory Products

template_mp_a4_rev302

HYS64D32301HU–[5/6]–C, HYS[72/64]D64300HU–[5/6]–C, HYS[64/72]D128320HU–[5/6]–C

Revision History: Rev. 1.1 2005-05

Previous Version: Rev. 1.0

Page Subjects (major changes since last revision)

13 changed component configuration for 256 MB to 32M ×16

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc.mp@infineon.com

Data Sheet 5 Rev. 1.1, 2005-05

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Operating ConditionsIDD Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table of Contents

Data Sheet 6 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

184-Pin Unbuffered Double Data Rate SDRAM

UDIMM

HYS64D32301HU–[5/6]–C

HYS[72/64]D64300HU–[5/6]–C

HYS[64/72]D128320HU–[5/6]–C

1Overview

1.1 Features

• 184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Workstation main memory

applications

• One rank 32M ×64, 64M ×64, 64M ×72 ,and two ranks 128M ×64 ,128M ×72 organization

• Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) and +2.6V (±0.1V)

power supply for DDR400

• Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package

• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)

• Auto Refresh (CBR) and Self Refresh

• RAS-lockout supported tRAP=tRCD

• All inputs and outputs SSTL_2 compatible

• Serial Presence Detect with E2PROM

• Standard MO-206 form factor: 133.35 mm ×31.75 mm ×4.00 mm max.

• Standard reference layout for raw cards: A, B and C

• Gold plated contacts

• RoHS Compliant Product1)

Table 1 Performance

1.2 Description

The HYS64D32301HU–[5/6]–C, HYS[72/64]D64300HU–[5/6]–C, HYS[64/72]D128320HU–[5/6]–C, and are

industry standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 32M ×64 (256 MB),

64M ×64 (512 MB), 128M ×64 (1 GB) for non-parity and 64M ×72 (512 MB), 128M ×72 (1 GB) for ECC main

memory applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A

variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence

detect (SPD) based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed

with configuration data and the second 128 bytes are available to the customer

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic

equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January

2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and

polybrominated biphenyl ethers.

Part Number Speed Code –5 –6Unit

Speed Grade Component DDR400B DDR333B —

Module PC3200–3033 PC2700–2533 —

max. Clock Frequency @CL3 fCK3 200 166 MHz

@CL2.5 fCK2.5 166 166 MHz

@CL2 fCK2 133 133 MHz

Data Sheet 7 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Overview

Table 2 Ordering Information for Lead-Free Products (RoHSCompliant Product)

Product Type1)

1) All product types end with a place code designating the silicon-die revision. Reference information available on request.

Example: HYS64D128320HU–5–C, indicating Rev.C die are used for SDRAM components.

Compliance Code2)

2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies

(for example “30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge

latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module.

Description SDRAM Technology

PC3200 (CL=3.0)

HYS64D32301HU–5–C PC3200U–30331–C3 one rank 256 MB DIMM 512 Mbit (×16)

HYS64D64300HU–5–C PC3200U–30331–A1 one rank 512 MB DIMM 512 Mbit (×8)

HYS72D64300HU–5–C PC3200U–30331–A1 one rank 512 MB ECC-DIMM 512 Mbit (×8)

HYS64D128320HU–5–C PC3200U–30331–B2 two ranks 1 GB DIMM 512 Mbit (×8)

HYS72D128320HU–5–C PC3200U–30331–B2 two ranks 1 GB ECC-DIMM 512 Mbit (×8)

PC2700 (CL=2.5)

HYS64D32301HU–6–C PC2700U–25331–C3 one rank 256 MB DIMM 512 Mbit (×16)

HYS64D64300HU–6–C PC2700U–25331–A1 one rank 512 MB DIMM 512 Mbit (×8)

HYS72D64300HU–6–C PC2700U–25331–A1 one rank 512 MB ECC-DIMM 512 Mbit (×8)

HYS64D128320HU–6–C PC2700U–25331–B2 two ranks 1 GB DIMM 512 Mbit (×8)

HYS72D128320HU–6–C PC2700U–25331–B2 two ranks 1 GB ECC-DIMM 512 Mbit (×8)

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 8 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

2 Pin Configuration

The pin configuration of the Unbuffered DDR SDRAM

DIMM is listed by function in Table 3 (184 pins). The

abbreviations used in columns Pin and Buffer Type are

explained in Table 4 and Table 5 respectively. The pin

numbering is depicted in Figure 1.

Table 3 Pin Configuration of UDIMM

Pin# Name Pin

Type

Buffer

Type

Function

Clock Signals

137 CK0 I SSTL Clock Signals 2:0

Note: For clock net

loading see block

diagram, CK0 is

NC on 1R

NC NC –

16 CK1 I SSTL

76 CK2 I SSTL

138 CK0 I SSTL Complement Clock

Signals 2:0

Note: For clock net

loading see block

diagram, CK0 is

NC on 1R

NC NC –

17 CK1 I SSTL

75 CK2 I SSTL

21 CKE0 I SSTL Clock Enable Rank 0

111 CKE1 I SSTL Clock Enable Rank 1

Note: 2-rank module

NC NC – Note: 1-rank module

Control Signals

157 S0 I SSTL Chip Select Rank 0

158 S1 I SSTL Chip Select Rank 1

Note: 2-rank module

NC NC – Note: 1-rank module

154 RAS I SSTL Row Address Strobe

65 CAS I SSTL Column Address

Strobe

63 WE I SSTL Write Enable

Address Signals

59 BA0 I SSTL Bank Address Bus

2:0

52 BA1 I SSTL

48 A0 I SSTL Address Bus 11:0

43 A1 I SSTL

41 A2 I SSTL

130 A3 I SSTL

37 A4 I SSTL

32 A5 I SSTL

125 A6 I SSTL

29 A7 I SSTL

122 A8 I SSTL Address Bus 11:0

27 A9 I SSTL

141 A10 I SSTL

AP I SSTL

118 A11 I SSTL

115 A12 I SSTL Address Signal 12

Note: Module based on

256 Mbit or larger

dies

NC NC – Note: 128 Mbit based

module

167 A13 I SSTL Address Signal 13

Note: 1 Gbit based

module

NC NC – Note: Module based on

512 Mbit or

smaller dies

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

Data Sheet 9 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Signals

2 DQ0 I/O SSTL Data Bus 63:0

4 DQ1 I/O SSTL

6 DQ2 I/O SSTL

8 DQ3 I/O SSTL

94 DQ4 I/O SSTL

95 DQ5 I/O SSTL

98 DQ6 I/O SSTL

99 DQ7 I/O SSTL

12 DQ8 I/O SSTL

13 DQ9 I/O SSTL

19 DQ10 I/O SSTL

20 DQ11 I/O SSTL

105 DQ12 I/O SSTL

106 DQ13 I/O SSTL

109 DQ14 I/O SSTL

110 DQ15 I/O SSTL

23 DQ16 I/O SSTL

24 DQ17 I/O SSTL

28 DQ18 I/O SSTL

31 DQ19 I/O SSTL

114 DQ20 I/O SSTL

117 DQ21 I/O SSTL

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

121 DQ22 I/O SSTL Data Bus 63:0

123 DQ23 I/O SSTL

33 DQ24 I/O SSTL

35 DQ25 I/O SSTL

39 DQ26 I/O SSTL

40 DQ27 I/O SSTL

126 DQ28 I/O SSTL

127 DQ29 I/O SSTL

131 DQ30 I/O SSTL

133 DQ31 I/O SSTL

53 DQ32 I/O SSTL

55 DQ33 I/O SSTL

57 DQ34 I/O SSTL

60 DQ35 I/O SSTL

146 DQ36 I/O SSTL

147 DQ37 I/O SSTL

150 DQ38 I/O SSTL

151 DQ39 I/O SSTL

61 DQ40 I/O SSTL

64 DQ41 I/O SSTL

68 DQ42 I/O SSTL

69 DQ43 I/O SSTL

153 DQ44 I/O SSTL

155 DQ45 I/O SSTL

161 DQ46 I/O SSTL

162 DQ47 I/O SSTL

72 DQ48 I/O SSTL

73 DQ49 I/O SSTL

79 DQ50 I/O SSTL

80 DQ51 I/O SSTL

165 DQ52 I/O SSTL

166 DQ53 I/O SSTL

170 DQ54 I/O SSTL

171 DQ55 I/O SSTL

83 DQ56 I/O SSTL

84 DQ57 I/O SSTL

87 DQ58 I/O SSTL

88 DQ59 I/O SSTL

174 DQ60 I/O SSTL

175 DQ61 I/O SSTL

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 10 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

178 DQ62 I/O SSTL Data Bus 63:0

179 DQ63 I/O SSTL

44 CB0 I/O SSTL Check Bit 0

Note: ECC type module

NC NC – Note: Non-ECC module

45 CB1 I/O SSTL Check Bit 1

Note: ECC type module

NC NC – Note: Non-ECC module

49 CB2 I/O SSTL Check Bit 2

Note: ECC type module

NC NC – Note: Non-ECC module

51 CB3 I/O SSTL Check Bit 3

Note: ECC type module

NC NC – Note: Non-ECC module

134 CB4 I/O SSTL Check Bit 4

Note: ECC type module

NC NC – Note: Non-ECC module

135 CB5 I/O SSTL Check Bit 5

Note: ECC type module

NC NC – Note: Non-ECC module

142 CB6 I/O SSTL Check Bit 6

Note: ECC type module

NC NC – Note: Non-ECC module

144 CB7 I/O SSTL Check Bit 7

Note: ECC type module

NC NC – Note: Non-ECC module

5 DQS0 I/O SSTL Data Strobe Bus 7:0

Note: See block

diagram for

corresponding

DQ signals

14 DQS1 I/O SSTL

25 DQS2 I/O SSTL

36 DQS3 I/O SSTL

56 DQS4 I/O SSTL

67 DQS5 I/O SSTL

78 DQS6 I/O SSTL

86 DQS7 I/O SSTL

47 DQS8 I/O SSTL Data Strobe 8

Note: ECC type module

NC NC – Note: Non-ECC module

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

97 DM0 I SSTL Data Mask Bus 7:0

107 DM1 I SSTL

119 DM2 I SSTL

129 DM3 I SSTL

149 DM4 I SSTL

159 DM5 I SSTL

169 DM6 I SSTL

177 DM7 I SSTL

140 DM8 I SSTL Data Mask 8

Note: ECC type module

NC NC – Note: Non-ECC module

EEPROM

92 SCL I CMOS Serial Bus Clock

91 SDA I/O OD Serial Bus Data

181 SA0 I CMOS Slave Address Select

Bus 2:0

182 SA1 I CMOS

183 SA2 I CMOS

Power Supplies

1VREF AI – I/O Reference Voltage

184 VDDSPD PWR – EEPROM Power

Supply

15,

22,

30,

54,

62,

77,

96,

104,

112,

128,

136,

143,

156,

164,

172,

180

VDDQ PWR – I/O Driver Power

Supply

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

Data Sheet 11 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

38,

46,

70,

85,

108,

120,

148,

168

VDD PWR – Power Supply

11,

18,

26,

34,

42,

50,

58,

66,

74,

81,

89,

93,

100,

116,

124,

132,

139,

145,

152,

160,

176

VSS GND – Ground Plane

Other Pins

82 VDDID OODVDD Identification

Note: Pin in tristate,

indicating VDD

and VDDQ nets

connected on

PCB

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

10,

71,

90,

101,

102,

103,

113,

163,

173

NC NC – Not connected

Pins not connected on

Infineon UDIMMs

Table 4 Abbreviations for Pin Type

Abbreviation Description

I Standard input-only pin. Digital levels.

O Output. Digital levels.

I/O I/O is a bidirectional input/output signal.

AI Input. Analog levels.

PWR Power

GND Ground

NC Not Connected

Table 5 Abbreviations for Buffer Type

Abbreviation Description

SSTL Serial Stub Terminated Logic (SSTL2)

LV-CMOS Low Voltage CMOS

CMOS CMOS Levels

OD Open Drain. The corresponding pin has 2

operational states, active low and tristate,

and allows multiple devices to share as a

wire-OR.

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 12 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Figure 1 Pin Configuration 184-Pin, UDIMM

MPPD0030

Pin 093

Pin 095

Pin 097

Pin 099

Pin 101

Pin 103

Pin 105

Pin 107

Pin 109

Pin 111

Pin 094

Pin 096

Pin 098

Pin 100

Pin 102

Pin 104

Pin 106

Pin 108

Pin 110

Pin 112

VSS

DQ05

DM0

DQ07

DQ12

DM1

DQ14

CKE1/NC

DQ04

DQ06

DQ13

DQ15

Pin 114

Pin 116

Pin 118

Pin 120

Pin 122

Pin 124

Pin 126

Pin 128

Pin 130

Pin 132

Pin 134

Pin 136

Pin 138

Pin 140

Pin 142

Pin 144

DQ20

A11

DQ28

CB4/NC

CK0/NC

DM8/NC

CB06/NC

CB7/NC

Pin 113

Pin 115

Pin 117

Pin 119

Pin 121

Pin 123

Pin 125

Pin 127

Pin 129

Pin 131

Pin 133

Pin 135

Pin 137

Pin 139

Pin 141

Pin 143

A12/NC

DQ21

DM2

DQ22

DQ23

DQ29

DM3

DQ30

DQ31

CB5/NC

CK0/NC

VSS

A10/AP

VDDQ

VREF

VSS

DQS0

VDD

VSS

DQ09

VDDQ

CK1

DQ10

DQ00

DQ01

DQ02

DQ03

DQ08

DQS1

CK1

VSS

DQ11

DQ17

DQ18

DQS3

DQ27

CB00/NC

BA1

CKE0

DQ16

DQS2

DQ19

DQ24

DQ25

A04

DQ26

CB01/NC

DQS8/NC

CB02/NC

CB03/NC

Pin 145

Pin 147

Pin 149

Pin 151

Pin 153

Pin 155

Pin 157

Pin 159

Pin 161

Pin 163

Pin 165

Pin 167

Pin 169

Pin 171

Pin 173

Pin 175

Pin 177

Pin 179

Pin 181

Pin 183

VSS

DQ37

DM4

DQ39

DQ44

DQ45

DM5

DQ46

DQ52

A13/NC

DM6

DQ51

DQ61

DM7

DQ63

SA0

SA2

DQ36

DQ38

RAS

S1/NC

DQ47

DQ53

DQ54

DQ60

DQ62

SA1

Pin 146

Pin 148

Pin 150

Pin 152

Pin 154

Pin 156

Pin 158

Pin 160

Pin 162

Pin 164

Pin 166

Pin 168

Pin 170

Pin 172

Pin 174

Pin 176

Pin 178

Pin 180

Pin 182

Pin 184

Pin 002

Pin 004

Pin 006

Pin 008

Pin 010

Pin 012

Pin 014

Pin 016

Pin 018

Pin 020

Pin 022

Pin 024

Pin 026

Pin 028

Pin 030

Pin 032

Pin 034

Pin 036

Pin 038

Pin 040

Pin 042

Pin 044

Pin 046

Pin 048

Pin 050

Pin 052

Pin 001

Pin 003

Pin 005

Pin 007

Pin 009

Pin 011

Pin 013

Pin 015

Pin 017

Pin 019

Pin 021

Pin 023

Pin 025

Pin 027

Pin 029

Pin 031

Pin 033

Pin 035

Pin 037

Pin 039

Pin 041

Pin 043

Pin 045

Pin 047

Pin 049

Pin 051

Pin 054

Pin 056

Pin 058

Pin 060

Pin 062

Pin 064

Pin 066

Pin 068

Pin 070

Pin 072

Pin 074

Pin 076

Pin 078

Pin 080

Pin 082

Pin 084

Pin 086

Pin 088

Pin 090

Pin 092

Pin 053

Pin 055

Pin 057

Pin 059

Pin 061

Pin 063

Pin 065

Pin 067

Pin 069

Pin 071

Pin 073

Pin 075

Pin 077

Pin 079

Pin 081

Pin 083

Pin 085

Pin 087

Pin 089

Pin 091

DQS4

DQ35

DQ41

DQ42

DQ48

CK2

DQS6

DQ51

DQ57

DQS7

DQ59

SCL

DQ32

DQ33

DQ34

BA0

DQ40

CAS

DQS5

DQ43

DQ49

CK2

VDDQ

DQ50

VSS

DQ56

VDD

DQ58

VSS

SDA

VDDQ

VSS

VDDQ

VSS

VDD

VSS

VDD

VSS

VDDQ

VSS

VDDQ

VSS

VDD

VSS

VDDID

VDDQ

VSS

VDDQ

VDD

VDDQ

VSS

VDD

VSS

VDDQ

VSS

VDDQ

VDD

VSS

VDDQ

VSS

VDDQ

VDD

VDDQ

VSS

VDDQ

VDDSPD

Data Sheet 13 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Table 6 Address Format

Density Organization Memory

Ranks

SDRAMs # of

SDRAMs

# of row/bank/

columns bits

Refresh Period Interval

256 MB 32M ×64 1 32M ×16 4 13/2/10 8K 64 ms 7.8 µs

512 MB 64M ×64 1 64M ×88 13/2/11 8K 64ms7.8µs

512 MB 64M ×72 1 64M ×89 13/2/11 8K 64ms7.8µs

1GB 128M×64 2 64M ×8 16 13/2/11 8K 64 ms 7.8 µs

1GB 128M×72 2 64M ×8 18 13/2/11 8K 64 ms 7.8 µs

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 14 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Figure 2 Block Diagram UDIMM Raw Card C ×64 1 Rank ×16

Notes

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 7.5

Ω±

MPBD1051

DM1

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

D0 DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D1 DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

BA0 - BA1

A0 - An

RAS

CAS

CKE0

BA0 - BA1: SDRAMs D0 - D3

A0 - An: SDRAMs D0 - D3

RAS: SDRAMs D0 - D3

CAS: SDRAMs D0 - D3

WE: SDRAMs D0 - D3

CKE: SDRAMs D0 - D3

LDM CS

LDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDM

UDQS

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

LDM CS

LDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDM

UDQS

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

LDM CS

LDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDM

UDQS

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

LDM CS

LDQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDM

UDQS

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

: SPD EEPROM E0

DDQ

: SDRAMs D0 - D3

REF

: SDRAMs D0 - D3

Strap: see Note 1

DDSPD

DDQ

REF

DDID

SCL

SAD

SA0

SA1

SA2

SCL

SAD

Table 7 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 NC —

CK1, CK1 2 SDRAMs —

CK2, CK2 2 SDRAMs —

Data Sheet 15 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Figure 3 Block Diagram UDIMM Raw Card A ×64 1 Rank ×8

Notes

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 5.1

Ω±



























































































 





















































































































































































































































































9













!"#$%%&'!%





9









(











(













Table 8 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 2 SDRAMs —

CK1, CK1 3 SDRAMs —

CK2, CK2 3 SDRAMs —

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 16 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Figure 4 Block Diagram UDIMM Raw Card A ×72, 1Rank, ×8, ECC

Note:

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 5.1

Ω±

MPBD1001

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM1

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D2 DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM8

DQS8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

BA0 - BA1: SDRAMs D0 - D8

A0 - An: SDRAMs D0 - D8

RAS: SDRAMs D0 - D8

CAS: SDRAMs D0 - D8

WE: SDRAMs D0 - D8

CKE: SDRAMs D0 - D8

BA0 - BA1

A0 - An

RAS

CAS

CKE0

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

: SPD EEPROM E0

DDQ

: SDRAMs D0 - D8

REF

: SDRAMs D0 - D8

Strap: see Note 1

DDSPD

DDQ

REF

DDID

SCL

SAD

SA0

SA1

SA2

SCL

SAD

Table 9 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 3 SDRAMs —

CK1, CK1 3 SDRAMs —

CK2, CK2 3 SDRAMs —

Data Sheet 17 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Figure 5 Block Diagram UDIMM Raw Card B ×64, 2 Ranks, ×8

Note:

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 3

Ω±

MPBD1031

BA0 - BA1: SDRAMs D0 - D15

A0 - An: SDRAMs D0 - D15

RAS: SDRAMs D0 - D15

CAS: SDRAMs D0 - D15

WE: SDRAMs D0 - D15

CKE: SDRAMs D0 - D7

CKE:SDRAMs D8 - D15

BA0 - BA1

A0 - An

RAS

CAS

CKE0

CKE1

DM1

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

D0 D8

D10

D11

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D15

D14

D13

DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

D12

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

: SPD EEPROM E0

DDQ

: SDRAMs D0 - D15

REF

: SDRAMs D0 - D15

Strap: see Note 1

DDSPD

DDQ

REF

DDID

SCL

SAD

SA0

SA1

SA2

SCL

SAD

Table 10 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 4 SDRAMs —

CK1, CK1 6 SDRAMs —

CK2, CK2 6 SDRAMs —

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 18 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Figure 6 Block Diagram UDIMM Raw Card B ×72, 2Ranks, ×8, ECC

Note:

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 3

Ω±

MPBD1021

DM1/DQS10

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM2/DQS11

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM3/DQS12

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D10

D11

D12

DM8/DQS17

DQS8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

D17

SCL

SAD

SA0

SA1

SA2

SCL

SAD

: SPD EEPROM E0

DDQ

: SDRAMs D0 - D17

REF

: SDRAMs D0 - D17

DM: SDRAMs D0 - D17

DDSPD

DDQ

REF

DDID

Strap: see Note 1

DM0/DQS9

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM6/DQS15

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM7/DQS16

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM4/DQS13

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D15

D14

D13

DM5/DQS14

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

D16

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

BA0 - BA1: SDRAMs D0 - D17

A0 - An: SDRAMs D0 - D17

RAS: SDRAMs D0 - D17

CAS: SDRAMs D0 - D17

WE: SDRAMs D0 - D17

CKE: SDRAMs D0 - D8

CKE:SDRAMs D9 - D17

BA0 - BA1

A0 - An

RAS

CAS

CKE0

CKE1

Table 11 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 6 SDRAMs —

CK1, CK1 6 SDRAMs —

CK2, CK2 6 SDRAMs —

Data Sheet 19 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Pin Configuration

Figure 7 Clock Net Wiring

6 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

DRAM2

DRAM3

DRAM4

DRAM5

DRAM6

4 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

DRAM2

Cap.

DRAM5

DRAM6

3 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

Cap.

DRAM3

Cap.

DRAM5

Cap.

2 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

Cap.

DRAM5

Cap.

1 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

Cap.

DRAM3

Cap.

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 20 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

3 Electrical Characteristics

3.1 Operating ConditionsIDD Current Conditions and Specification

Table 12 IDD Conditions

Parameter Symbol

Operating Current 0

one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

IDD0

Operating Current 1

one bank; active/read/precharge; Burst Length = 4; see component data sheet.

IDD1

Precharge Power-Down Standby Current

all banks idle; power-down mode; CKE ≤ VIL,MAX

IDD2P

Precharge Floating Standby Current

CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;

address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.

IDD2F

Precharge Quiet Standby Current

CS ≥ VIHMIN, all banks idle; CKE ≥VIH,MIN; VIN = VREF for DQ, DQS and DM;

address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.

IDD2Q

Active Power-Down Standby Current

one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.

IDD3P

Active Standby Current

one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC =tRAS,MAX;

DQ, DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle.

IDD3N

Operating Current Read

one bank active; Burst Length = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT =0mA

IDD4R

Operating Current Write

one bank active; Burst Length = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B

IDD4W

Auto-Refresh Current

tRC = tRFCMIN, burst refresh

IDD5

Self-Refresh Current

CKE ≤ 0.2 V; external clock on

IDD6

Operating Current 7

four bank interleaving with Burst Length = 4; see component data sheet.

IDD7

Data Sheet 21 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Table 13 IDD Specification for HYS[64/72]D[32/64/128]3xxHU–5–C

Product Type

HYS64D32301HU–5–C

HYS64D64300HU–5–C

HYS72D64300HU–5–C

HYS64D128320HU–5–C

HYS72D128320HU–5–C

Unit Note 1)2)

1) DRAM component currents only

2) Test condition for maximum values: VDD =2.7V, TA=10°C

Organization 256MB 512MB 512MB 1GB 1GB

×64 ×64 ×72 ×64 ×72

1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks

–5 –5 –5 –5 –5

Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max.

IDD0 300 360 480 600 540 680 760 940 860 1050 mA 3)

3) The module IDDx values are calculated from the component IDDx data sheet values as:

m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules

IDD1 360 440 560 680 630 770 840 1020 950 1140 mA 3)4)

4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load

conditions

IDD2P 4 18 9 37 10 41 18 74 20 83 mA 5)

5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]

IDD2F 100 120 200 240 230 270 400 480 450 540 mA 5)

IDD2Q 70 90 140 180 150 210 270 370 310 410 mA 5)

IDD3P 50 60 100 130 110 140 190 260 220 290 mA 5)

IDD3N 150 180 280 340 320 380 560 670 630 760 mA 5)

IDD4R 440 540 640 720 720 810 920 1060 1040 1190 mA 3)4)

IDD4W 460 540 680 760 770 860 960 1100 1080 1230 mA 3)

IDD5 580 760 1160 1520 1310 1710 1440 1860 620 2090 mA 3)

IDD6 6201340144526802990mA

IDD7 840 1000 1560 1840 1760 2070 1840 2180 2070 2450 mA 3)4)

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 22 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Table 14 IDD Specification for HYS[64/72]D[32/64/128]3xxHU–6–C

Product Type

HYS64D32301HU–6–C

HYS64D64300HU–6–C

HYS72D64300HU–6–C

HYS64D128320HU–6–C

HYS72D128320HU–6–C

Unit Note 1)2)

1) DRAM component currents only

2) Test condition for maximum values: VDD =2.6V, TA=10°C

Organization 256MB 512MB 512MB 1GB 1GB

×64 ×64 ×72 ×64 ×72

1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks

–6 –6 –6 –6 –6

Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max.

IDD0 280 340 480 560 540 630 740 860 830 960 mA 3)

3) The module IDDx values are calculated from the component IDDx data sheet values as:

m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules

IDD1 320 380 520 640 590 720 780 940 870 1050 mA 3)4)

4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load

conditions

IDD2P 4 18 9 37 10 41 18 74 20 83 mA 5)

5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]

IDD2F 80 100 170 200 190 230 340 400 380 450 mA 5)

IDD2Q 60 90 120 180 140 200 240 350 270 400 mA 5)

IDD3P 40 60 90 120 100 140 180 240 200 270 mA 5)

IDD3N 130 160 260 300 290 330 510 590 580 670 mA 5)

IDD4R 380 460 560 680 630 770 820 980 920 1100 mA 3)4)

IDD4W 400 480 600 720 680 810 860 1020 960 1140 mA 3)

IDD5 520 700 1040 1400 1170 1580 1300 1700 1460 1910 mA 3)

IDD6 6.4 20 12.8 40 14.4 45 25.6 80 28.8 90 mA 5)

IDD7 760 920 1400 1640 1580 1850 1660 1940 1860 2180 mA 3)4)

Data Sheet 23 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Table 15 AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter Symbol –5 –6 Unit Note/ Test

Condition 1)

DDR400B DDR333

Min. Max. Min. Max.

DQ output access time from

CK/CK

tAC –0.7 +0.5 –0.7 +0.7 ns 2)3)4)5)

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

2)3)4)5)

Clock cycle time tCK 5 8 6 12 ns CL = 3.0

2)3)4)5)

6 12 6 12 ns CL = 2.5

2)3)4)5)

7.5 12 7.5 12 ns CL = 2.0

2)3)4)5)

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

2)3)4)5)

Auto precharge write recovery

+ precharge time

tDAL (tWR/tCK) + (tRP/tCK)tCK

2)3)4)5)6)

DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5)

DQ and DM input pulse width

(each input)

tDIPW 1.75 — 1.75 — ns 2)3)4)5)6)

DQS output access time from

CK/CK

tDQSCK –0.5 +0.5 –0.6 +0.6 ns 2)3)4)5)

DQS input low (high) pulse

width (write cycle)

tDQSL,H 0.35 — 0.35 — tCK

2)3)4)5)

DQS-DQ skew (DQS and

associated DQ signals)

tDQSQ — +0.40 — +0.45 ns TSOPII

2)3)4)5)

Write command to 1st DQS

latching transition

tDQSS 0.72 1.25 0.75 1.25 tCK

2)3)4)5)

DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5)

DQS falling edge hold time

from CK (write cycle)

tDSH 0.2 — 0.2 — tCK

2)3)4)5)

DQS falling edge to CK setup

time (write cycle)

tDSS 0.2 — 0.2 — tCK

2)3)4)5)

Clock Half Period tHP min. (tCL, tCH)— min. (tCL, tCH)— ns 2)3)4)5)

Data-out high-impedance time

from CK/CK

tHZ +0.7 –0.7 +0.7 ns 2)3)4)5)7)

Address and control input hold

time

tIH 0.6 — 0.75 — ns fast slew rate

3)4)5)6)8)

0.7 — 0.8 — ns slow slew

rate

3)4)5)6)8)

Control and Addr. input pulse

width (each input)

tIPW 2.2 — 2.2 — ns 2)3)4)5)9)

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 24 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Address and control input

setup time

tIS 0.6 — 0.75 — ns fast slew rate

3)4)5)6)10)

0.7 — 0.8 — ns slow slew

rate

3)4)5)6)10)

Data-out low-impedance time

from CK/CK

tLZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7)

Mode register set command

cycle time

tMRD 2—2—tCK

2)3)4)5)

DQ/DQS output hold time tQH tHP – tQHS —tHP – tQHS —ns

2)3)4)5)

Data hold skew factor tQHS — +0.50 — +0.55 ns TSOPII

2)3)4)5)

Active to Autoprecharge delay tRAP tRCD —t

RCD —ns

2)3)4)5)

Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5)

Active to Active/Auto-refresh

command period

tRC 55 — 60 — ns 2)3)4)5)

Active to Read or Write delay tRCD 15 — 18 — ns 2)3)4)5)

Average Periodic Refresh

Interval

tREFI — 7.8 — 7.8 µs2)3)4)5)8)

Auto-refresh to Active/Auto-

refresh command period

tRFC 70 — 72 — ns 2)3)4)5)

Precharge command period tRP 15 — 18 — ns 2)3)4)5)

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

2)3)4)5)

Read postamble tRPST 0.40 0.60 0.40 0.60 tCK

2)3)4)5)

Active bank A to Active bank B

command

tRRD 10 — 12 — ns 2)3)4)5)

Write preamble tWPRE 0.25 — 0.25 — tCK

2)3)4)5)

Write preamble setup time tWPRES 0—0—ns

2)3)4)5)11)

Write postamble tWPST 0.40 0.60 0.40 0.60 tCK

2)3)4)5)12)

Write recovery time tWR 15 — 15 — ns 2)3)4)5)

Internal write to read

command delay

tWTR 2—1—tCK

2)3)4)5)

Exit self-refresh to non-read

command

tXSNR 75 — 75 — ns 2)3)4)5)

Exit self-refresh to read

command

tXSRD 200 — 200 — tCK

2)3)4)5)

1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V

(DDR400)

2) Input slew rate ≥ 1 V/ns for DDR400, DDR333

3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference

level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.

4) Inputs are not recognized as valid until VREF stabilizes.

Table 15 AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter Symbol –5 –6 Unit Note/ Test

Condition 1)

DDR400B DDR333

Min. Max. Min. Max.

Data Sheet 25 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Electrical Characteristics

5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.

6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock

cycle time.

7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

9) These parameters guarantee device timing, but they are not necessarily tested on each device.

10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,

measured between VOH(ac) and VOL(ac).

11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.

A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were

previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) degrades accordingly.

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 26 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

4SPDContents

Table 16 SPD Codes for HYS64D32301HU–[5/6]–C

Product Type HYS64D32301HU–5–C HYS64D32301HU–6–C

Organization 256 MB 256 MB

×64 ×64

1 Rank (×16) 1 Rank (×16)

Label Code PC3200U–30331 PC2700U–25331

JEDEC SPD Revision Rev 1.0 Rev 1.0

Byte# Description HEX HEX

0 Programmed SPD Bytes in E2PROM 80 80

1 Total number of Bytes in E2PROM 08 08

2 Memory Type (DDR = 07h) 07 07

3 Number of Row Addresses 0D 0D

4 Number of Column Addresses 0A 0A

5 Number of DIMM Ranks 01 01

6 Data Width (LSB) 40 40

7 Data Width (MSB) 00 00

8 Interface Voltage Levels 04 04

9 tCK @ CLmax (Byte 18) [ns] 50 60

10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70

11 Error Correction Support 00 00

12 Refresh Rate 82 82

13 Primary SDRAM Width 10 10

14 Error Checking SDRAM Width 00 00

15 tCCD [cycles] 01 01

16 Burst Length Supported 0E 0E

17 Number of Banks on SDRAM Device 04 04

18 CAS Latency 1C 0C

19 CS Latency 01 01

20 Write Latency 02 02

21 DIMM Attributes 20 20

22 Component Attributes C1 C1

23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 75

24 tAC SDRAM @ CLmax -0.5 [ns] 70 70

25 tCK @ CLmax -1 (Byte 18) [ns] 75 00

26 tAC SDRAM @ CLmax -1 [ns] 70 00

27 tRPmin [ns] 3C 48

28 tRRDmin [ns] 28 30

29 tRCDmin [ns] 3C 48

30 tRASmin [ns] 28 2A

31 Module Density per Rank 40 40

Data Sheet 27 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

32 tAS, tCS [ns] 60 75

33 tAH, tCH [ns] 60 75

34 tDS [ns] 40 45

35 tDH [ns] 40 45

36 - 40 not used 00 00

41 tRCmin [ns] 37 3C

42 tRFCmin [ns] 41 48

43 tCKmax [ns] 28 30

44 tDQSQmax [ns] 28 2D

45 tQHSmax [ns] 50 55

46 not used 00 00

47 DIMM PCB Height 01 01

48 - 61 not used 00 00

62 SPD Revision 10 10

63 Checksum of Byte 0-62 76 1A

64 JEDEC ID Code of Infineon (1) C1 C1

65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00

72 Module Manufacturer Location xx xx

73 Part Number, Char 1 36 36

74 Part Number, Char 2 34 34

75 Part Number, Char 3 44 44

76 Part Number, Char 4 33 33

77 Part Number, Char 5 32 32

78 Part Number, Char 6 33 33

79 Part Number, Char 7 30 30

80 Part Number, Char 8 31 31

81 Part Number, Char 9 48 48

82 Part Number, Char 10 55 55

83 Part Number, Char 11 35 36

84 Part Number, Char 12 43 43

85 Part Number, Char 13 20 20

86 Part Number, Char 14 20 20

87 Part Number, Char 15 20 20

88 Part Number, Char 16 20 20

89 Part Number, Char 17 20 20

Table 16 SPD Codes for HYS64D32301HU–[5/6]–C (cont’d)

Product Type HYS64D32301HU–5–C HYS64D32301HU–6–C

Organization 256 MB 256 MB

×64 ×64

1 Rank (×16) 1 Rank (×16)

Label Code PC3200U–30331 PC2700U–25331

JEDEC SPD Revision Rev 1.0 Rev 1.0

Byte# Description HEX HEX

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 28 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

90 Part Number, Char 18 20 20

91 Module Revision Code 0x 0x

92 Test Program Revision Code xx xx

93 Module Manufacturing Date Year xx xx

94 Module Manufacturing Date Week xx xx

95 - 98 Module Serial Number (1 - 4) xx xx

99 - 127 not used 00 00

Table 16 SPD Codes for HYS64D32301HU–[5/6]–C (cont’d)

Product Type HYS64D32301HU–5–C HYS64D32301HU–6–C

Organization 256 MB 256 MB

×64 ×64

1 Rank (×16) 1 Rank (×16)

Label Code PC3200U–30331 PC2700U–25331

JEDEC SPD Revision Rev 1.0 Rev 1.0

Byte# Description HEX HEX

Data Sheet 29 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

Table 17 SPD Codes for HYS[72/64]D64300HU–[5/6]–C

Product Type

HYS64D64300HU–5–C

HYS64D64300HU–6–C

HYS72D64300HU–5–C

HYS72D64300HU–6–C

Organization 512 MB 512 MB 512 MB 512 MB

×64 ×64 ×72 ×72

1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)

Label Code PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0

Byte# Description HEX HEX HEX HEX

0 Programmed SPD Bytes in

E2PROM

80 80 80 80

1 Total number of Bytes in E2PROM 08 08 08 08

2 Memory Type (DDR = 07h) 07 07 07 07

3 Number of Row Addresses 0D 0D 0D 0D

4 Number of Column Addresses 0B 0B 0B 0B

5 Number of DIMM Ranks 01 01 01 01

6 Data Width (LSB) 40 40 48 48

7 Data Width (MSB) 00 00 00 00

8 Interface Voltage Levels 04 04 04 04

9 tCK @ CLmax (Byte 18) [ns] 50 60 50 60

10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70

11 Error Correction Support 00 00 02 02

12 Refresh Rate 82 82 82 82

13 Primary SDRAM Width 08 08 08 08

14 Error Checking SDRAM Width 00 00 08 08

15 tCCD [cycles] 01 01 01 01

16 Burst Length Supported 0E 0E 0E 0E

17 Number of Banks on SDRAM Device 04 04 04 04

18 CAS Latency 1C 0C 1C 0C

19 CS Latency 01 01 01 01

20 Write Latency 02 02 02 02

21 DIMM Attributes 20 20 20 20

22 Component Attributes C1 C1 C1 C1

23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 75 60 75

24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70

25 tCK @ CLmax -1 (Byte 18) [ns] 75 00 75 00

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 30 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

26 tAC SDRAM @ CLmax -1 [ns] 70 00 70 00

27 tRPmin [ns] 3C 48 3C 48

28 tRRDmin [ns] 28 30 28 30

29 tRCDmin [ns] 3C 48 3C 48

30 tRASmin [ns] 28 2A 28 2A

31 Module Density per Rank 80 80 80 80

32 tAS, tCS [ns] 60 75 60 75

33 tAH, tCH [ns] 60 75 60 75

34 tDS [ns] 40 45 40 45

35 tDH [ns] 40 45 40 45

36 - 40 not used 00 00 00 00

41 tRCmin [ns] 37 3C 37 3C

42 tRFCmin [ns] 41 48 41 48

43 tCKmax [ns] 28 30 28 30

44 tDQSQmax [ns] 28 2D 28 2D

45 tQHSmax [ns] 50 55 50 55

46 not used 00 00 00 00

47 DIMM PCB Height 01 01 01 01

48 - 61 not used 00 00 00 00

62 SPD Revision 10 10 10 10

63 Checksum of Byte 0-62 AF 53 C1 65

64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1

65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00

72 Module Manufacturer Location xx xx xx xx

73 Part Number, Char 1 36 36 37 37

74 Part Number, Char 2 34 34 32 32

75 Part Number, Char 3 44 44 44 44

76 Part Number, Char 4 36 36 36 36

Table 17 SPD Codes for HYS[72/64]D64300HU–[5/6]–C (cont’d)

Product Type

HYS64D64300HU–5–C

HYS64D64300HU–6–C

HYS72D64300HU–5–C

HYS72D64300HU–6–C

Organization 512 MB 512 MB 512 MB 512 MB

×64 ×64 ×72 ×72

1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)

Label Code PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0

Byte# Description HEX HEX HEX HEX

Data Sheet 31 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

77 Part Number, Char 5 34 34 34 34

78 Part Number, Char 6 33 33 33 33

79 Part Number, Char 7 30 30 30 30

80 Part Number, Char 8 30 30 30 30

81 Part Number, Char 9 48 48 48 48

82 Part Number, Char 10 55 55 55 55

83 Part Number, Char 11 35 36 35 36

84 Part Number, Char 12 43 43 43 43

85 Part Number, Char 13 20 20 20 20

86 Part Number, Char 14 20 20 20 20

87 Part Number, Char 15 20 20 20 20

88 Part Number, Char 16 20 20 20 20

89 Part Number, Char 17 20 20 20 20

90 Part Number, Char 18 20 20 20 20

91 Module Revision Code 0x 0x 0x 0x

92 Test Program Revision Code xx xx xx xx

93 Module Manufacturing Date Year xx xx xx xx

94 Module Manufacturing Date Week xx xx xx xx

95 - 98 Module Serial Number (1 - 4) xx xx xx xx

99 - 127 not used 00 00 00 00

Table 17 SPD Codes for HYS[72/64]D64300HU–[5/6]–C (cont’d)

Product Type

HYS64D64300HU–5–C

HYS64D64300HU–6–C

HYS72D64300HU–5–C

HYS72D64300HU–6–C

Organization 512 MB 512 MB 512 MB 512 MB

×64 ×64 ×72 ×72

1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)

Label Code PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0

Byte# Description HEX HEX HEX HEX

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 32 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Table 18 SPD Codes for HYS[64/72]D128320HU–[5/6]–C

Product Type

HYS64D128320HU–5–C

HYS64D128320HU–6–C

HYS72D128320HU–5–C

HYS72D128320HU–6–C

Organization 1 GByte 1 GByte 1 GByte 1 GByte

×64 ×64 ×72 ×72

2 Ranks (×8) 2 Ranks

(×8)

2 Ranks

(×8)

2 Ranks

(×8)

Label Code PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0

Byte# Description HEX HEX HEX HEX

0 Programmed SPD Bytes in E2PROM 80 80 80 80

1 Total number of Bytes in E2PROM 08 08 08 08

2 Memory Type (DDR = 07h) 07 07 07 07

3 Number of Row Addresses 0D 0D 0D 0D

4 Number of Column Addresses 0B 0B 0B 0B

5 Number of DIMM Ranks 02 02 02 02

6 Data Width (LSB) 40 40 48 48

7 Data Width (MSB) 00 00 00 00

8 Interface Voltage Levels 04 04 04 04

9 tCK @ CLmax (Byte 18) [ns] 50 60 50 60

10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70

11 Error Correction Support 00 00 02 02

12 Refresh Rate 82 82 82 82

13 Primary SDRAM Width 08 08 08 08

14 Error Checking SDRAM Width 00 00 08 08

15 tCCD [cycles] 01 01 01 01

16 Burst Length Supported 0E 0E 0E 0E

17 Number of Banks on SDRAM Device 04 04 04 04

18 CAS Latency 1C 0C 1C 0C

19 CS Latency 01 01 01 01

20 Write Latency 02 02 02 02

21 DIMM Attributes 20 20 20 20

22 Component Attributes C1 C1 C1 C1

23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 75 60 75

24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70

25 tCK @ CLmax -1 (Byte 18) [ns] 75 00 75 00

Data Sheet 33 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

26 tAC SDRAM @ CLmax -1 [ns] 70 00 70 00

27 tRPmin [ns] 3C 48 3C 48

28 tRRDmin [ns] 28 30 28 30

29 tRCDmin [ns] 3C 48 3C 48

30 tRASmin [ns] 28 2A 28 2A

31 Module Density per Rank 80 80 80 80

32 tAS, tCS [ns] 60 75 60 75

33 tAH, tCH [ns] 60 75 60 75

34 tDS [ns] 40 45 40 45

35 tDH [ns] 40 45 40 45

36 - 40 not used 00 00 00 00

41 tRCmin [ns] 37 3C 37 3C

42 tRFCmin [ns] 41 48 41 48

43 tCKmax [ns] 28 30 28 30

44 tDQSQmax [ns] 28 2D 28 2D

45 tQHSmax [ns] 50 55 50 55

46 not used 00 00 00 00

47 DIMM PCB Height 01 01 01 01

48 - 61 not used 00 00 00 00

62 SPD Revision 10 10 10 10

63 Checksum of Byte 0-62 B0 54 C2 66

64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1

65 -71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00

72 Module Manufacturer Location xx xx xx xx

73 Part Number, Char 1 36 36 37 37

74 Part Number, Char 2 34 34 32 32

75 Part Number, Char 3 44 44 44 44

Table 18 SPD Codes for HYS[64/72]D128320HU–[5/6]–C (cont’d)

Product Type

HYS64D128320HU–5–C

HYS64D128320HU–6–C

HYS72D128320HU–5–C

HYS72D128320HU–6–C

Organization 1 GByte 1 GByte 1 GByte 1 GByte

×64 ×64 ×72 ×72

2 Ranks (×8) 2 Ranks

(×8)

2 Ranks

(×8)

2 Ranks

(×8)

Label Code PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0

Byte# Description HEX HEX HEX HEX

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 34 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

76 Part Number, Char 4 31 31 31 31

77 Part Number, Char 5 32 32 32 32

78 Part Number, Char 6 38 38 38 38

79 Part Number, Char 7 33 33 33 33

80 Part Number, Char 8 32 32 32 32

81 Part Number, Char 9 30 30 30 30

82 Part Number, Char 10 48 48 48 48

83 Part Number, Char 11 55 55 55 55

84 Part Number, Char 12 35 36 35 36

85 Part Number, Char 13 43 43 43 43

86 Part Number, Char 14 20 20 20 20

87 Part Number, Char 15 20 20 20 20

88 Part Number, Char 16 20 20 20 20

89 Part Number, Char 17 20 20 20 20

90 Part Number, Char 18 20 20 20 20

91 Module Revision Code 0x 0x 0x 0x

92 Test Program Revision Code xx xx xx xx

93 Module Manufacturing Date Year xx xx xx xx

94 Module Manufacturing Date Week xx xx xx xx

95 - 98 Module Serial Number (1 - 4) xx xx xx xx

99 - 127 not used 00 00 00 00

Table 18 SPD Codes for HYS[64/72]D128320HU–[5/6]–C (cont’d)

Product Type

HYS64D128320HU–5–C

HYS64D128320HU–6–C

HYS72D128320HU–5–C

HYS72D128320HU–6–C

Organization 1 GByte 1 GByte 1 GByte 1 GByte

×64 ×64 ×72 ×72

2 Ranks (×8) 2 Ranks

(×8)

2 Ranks

(×8)

2 Ranks

(×8)

Label Code PC3200U–

30331

PC2700U–

25331

PC3200U–

30331

PC2700U–

25331

JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0

Byte# Description HEX HEX HEX HEX

Data Sheet 35 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outlines

5 Package Outlines

Package Outline for HYS64D32301HU–[5/6]–C

Figure 8 Package Outline UDIMM Raw Card C (L-DIM-184-18)

±0.1

0.1 BC

2.7 MAX.

133.35 B

0.15 A C

±0.1

2.36

64.77

ø0.1 ACB

=1.27x 120.65

2.175

6.62

6.35

49.53

3 MIN.

93 0.1

±0.1

1.8 BAC

17.8

184

1.27 1±0.05 0.1 BA C

Detail of contacts

0.2

2.5

±0.2

±0.1

1.27

0.4

±0.13

31.75

128.95

3.8

±0.13

Burr max. 0.4 allowed

1) On ECC modules only

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outlines

Data Sheet 36 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Package Outline for HYS64D64300HU–[5/6]–C

Figure 9 Package Outline UDIMM Raw Card A (L-DIM-184-32)

1.27 1±0.05 0.1 BA C

Detail of contacts

3 MIN.

2.5

±0.2

3.8

±0.13

±0.1

1.8 A

0.1 CB

17.8

184

1.27±0.1

0.4

31.75

±0.13

2.7 MAX.

6.62

±0.1

2.36

64.77

95 x

CBA

ø0.1

6.35

120.651.27 =

2.175

49.53

±0.1

40.1 ABC

128.95

133.35 B

0.15 A C

Burr max. 0.4 allowed

Data Sheet 37 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outlines

Package Outline for HYS72D64300HU–[5/6]–C

Figure 10 Package Outline UDIMM Raw Card A (L-DIM-184-30)

192

±0.13

±0.05

1.27 0.1 BA C

Detail of contacts

0.2

3 MIN.

3.8

2.5 ±0.2

1.8

±0.1

0.1 B

17.8

184

4±0.1 0.1 ACB

128.95

133.35

2.7 MAX.

0.15 BA C

6.35

±0.1

2.36

64.77

ø0.1 C

A B

1.27x95 120.65=

2.175

6.62

49.53

92 B

±0.13

31.75

1.27

±0.1

0.4

Burr max. 0.4 allowed

1) On ECC modules only

HYS[64/72]D[16/32/128]3xxHU–[5/6]–C

Unbuffered DDR SDRAM Modules

Package Outlines

Data Sheet 38 Rev. 1.1, 2005-05

07192004-EH0E-I4S5

Package Outline for HYS[64/72]D128320HU–[5/6]–C

Figure 11 Package Outline UDIMM Raw Card B (L-DIM-184-31)

11 9292

±0.1

1.27

4 MAX.

0.4

0.1 B C

133.35

128.95 A

0.15 B C

±0.1

±0.13

31.75

64.77

2.36 ±0.1 ø0.1

6.35

95 x 1.27 = 120.65

6.62

CB 2.175

49.53

±0.05

1.27

0.2

Detail of contacts

0.1 ABC

2.5 ±0.2

17.8

18493

±0.13

3.8

3 MIN.

±0.1

1.8 BA

0.1 C

Burr max. 0.4 allowed

1) On ECC modules only

Published by Infineon Technologies AG