Data Sheet, Rev. 1.1, May. 2005 HYS64D32301HU-[5/6]-C HYS[72/64]D64300HU-[5/6]-C HYS[64/72]D128320HU-[5/6]-C 184-Pin Unbuffered Double Data Rate SDRAM UDIMM DDR SDRAM RoHS Compliant Products DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . Edition 2005-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, Rev. 1.1, May. 2005 HYS64D32301HU-[5/6]-C HYS[72/64]D64300HU-[5/6]-C HYS[64/72]D128320HU-[5/6]-C 184-Pin Unbuffered D ouble Data Rate SDRAM UDIMM DDR SDRAM RoHS Compliant Products Memory Products N e v e r s t o p t h i n k i n g . HYS64D32301HU-[5/6]-C, HYS[72/64]D64300HU-[5/6]-C, HYS[64/72]D128320HU-[5/6]-C Revision History: Rev. 1.1 Previous Version: Rev. 1.0 Page Subjects (major changes since last revision) 13 changed component configuration for 256 MB to 32M x16 2005-05 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com template_mp_a4_rev302 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating ConditionsIDD Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Data Sheet 5 Rev. 1.1, 2005-05 184-Pin Unbuffered Double Data Rate SDRAM UDIMM 1 Overview 1.1 Features * * * * * * * * * * * * * HYS64D32301HU-[5/6]-C HYS[72/64]D64300HU-[5/6]-C HYS[64/72]D128320HU-[5/6]-C 184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Workstation main memory applications One rank 32M x64, 64M x64, 64M x72 ,and two ranks 128M x64 ,128M x72 organization Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (0.2V) and +2.6V (0.1V) power supply for DDR400 Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh RAS-lockout supported tRAP=tRCD All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM Standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. Standard reference layout for raw cards: A, B and C Gold plated contacts RoHS Compliant Product1) Table 1 Performance Part Number Speed Code Speed Grade max. Clock Frequency -5 -6 Unit Component DDR400B DDR333B -- Module PC3200-3033 PC2700-2533 -- 200 166 MHz 166 166 MHz 133 133 MHz @CL3 @CL2.5 @CL2 1.2 fCK3 fCK2.5 fCK2 Description The HYS64D32301HU-[5/6]-C, HYS[72/64]D64300HU-[5/6]-C, HYS[64/72]D128320HU-[5/6]-C, and are industry standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 32M x 64 (256 MB), 64M x 64 (512 MB), 128M x 64 (1 GB) for non-parity and 64M x 72 (512 MB), 128M x 72 (1 GB) for ECC main memory applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Data Sheet 6 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Overview Table 2 Ordering Information for Lead-Free Products (RoHSCompliant Product) Product Type1) Compliance Code2) Description SDRAM Technology HYS64D32301HU-5-C PC3200U-30331-C3 one rank 256 MB DIMM 512 Mbit (x16) HYS64D64300HU-5-C PC3200U-30331-A1 one rank 512 MB DIMM 512 Mbit (x8) HYS72D64300HU-5-C PC3200U-30331-A1 one rank 512 MB ECC-DIMM 512 Mbit (x8) HYS64D128320HU-5-C PC3200U-30331-B2 two ranks 1 GB DIMM 512 Mbit (x8) HYS72D128320HU-5-C PC3200U-30331-B2 two ranks 1 GB ECC-DIMM 512 Mbit (x8) HYS64D32301HU-6-C PC2700U-25331-C3 one rank 256 MB DIMM 512 Mbit (x16) HYS64D64300HU-6-C PC2700U-25331-A1 one rank 512 MB DIMM 512 Mbit (x8) HYS72D64300HU-6-C PC2700U-25331-A1 one rank 512 MB ECC-DIMM 512 Mbit (x8) HYS64D128320HU-6-C PC2700U-25331-B2 two ranks 1 GB DIMM 512 Mbit (x8) HYS72D128320HU-6-C PC2700U-25331-B2 two ranks 1 GB ECC-DIMM 512 Mbit (x8) PC3200 (CL=3.0) PC2700 (CL=2.5) 1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D128320HU-5-C, indicating Rev.C die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC3200"), the latencies (for example "30330" means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module. Data Sheet 7 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration 2 Pin Configuration The pin configuration of the Unbuffered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. Table 3 Table 3 Pin Configuration of UDIMM 41 A2 I SSTL Pin Buffer Function Type Type 130 A3 I SSTL 37 A4 I SSTL 32 A5 I SSTL Pin# Name Clock Signals Pin Configuration of UDIMM (cont'd) Pin# Name Pin Buffer Function Type Type 48 A0 I SSTL 43 A1 I SSTL CK0 I SSTL Clock Signals 2:0 125 A6 I SSTL NC NC - 29 A7 I SSTL 16 CK1 I SSTL 122 A8 I SSTL 76 CK2 I SSTL Note: For clock net loading see block diagram, CK0 is NC on 1R x16 27 A9 I SSTL 138 CK0 I SSTL 141 A10 I SSTL NC NC - AP I SSTL 17 CK1 I SSTL 118 A11 I SSTL 75 CK2 I SSTL Note: For clock net loading see block diagram, CK0 is NC on 1R x16 115 A12 I SSTL 21 CKE0 I SSTL Clock Enable Rank 0 111 CKE1 I SSTL Clock Enable Rank 1 137 Complement Clock Signals 2:0 NC - Note: 1-rank module S0 I SSTL Chip Select Rank 0 158 S1 I SSTL Chip Select Rank 1 NC NC - Note: 1-rank module 154 RAS I SSTL Row Address Strobe 65 CAS I SSTL Column Address Strobe 63 WE I SSTL Write Enable Bank Address Bus 2:0 Address Signal 12 167 NC NC - Note: 128 Mbit based module A13 I SSTL Address Signal 13 Note: 1 Gbit based module Control Signals 157 Address Bus 11:0 Note: Module based on 256 Mbit or larger dies Note: 2-rank module NC Address Bus 11:0 NC Note: 2-rank module NC - Note: Module based on 512 Mbit or smaller dies Address Signals 59 BA0 I SSTL 52 BA1 I SSTL Data Sheet 8 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration Table 3 Table 3 Pin Configuration of UDIMM (cont'd) Pin# Name Pin Buffer Function Type Type Data Signals Pin# Name Pin Buffer Function Type Type 121 DQ22 I/O SSTL 123 DQ23 I/O SSTL 2 DQ0 I/O SSTL 4 DQ1 I/O SSTL 33 DQ24 I/O SSTL 6 DQ2 I/O SSTL 35 DQ25 I/O SSTL 8 DQ3 I/O SSTL 39 DQ26 I/O SSTL 94 DQ4 I/O SSTL 40 DQ27 I/O SSTL 95 DQ5 I/O SSTL 126 DQ28 I/O SSTL 98 DQ6 I/O SSTL 127 DQ29 I/O SSTL 99 DQ7 I/O SSTL 131 DQ30 I/O SSTL 12 DQ8 I/O SSTL 133 DQ31 I/O SSTL 13 DQ9 I/O SSTL 53 DQ32 I/O SSTL 19 DQ10 I/O SSTL 55 DQ33 I/O SSTL 20 DQ11 I/O SSTL 57 DQ34 I/O SSTL 105 DQ12 I/O SSTL 60 DQ35 I/O SSTL 106 DQ13 I/O SSTL 146 DQ36 I/O SSTL 109 DQ14 I/O SSTL 147 DQ37 I/O SSTL 110 DQ15 I/O SSTL 150 DQ38 I/O SSTL 23 DQ16 I/O SSTL 151 DQ39 I/O SSTL 24 DQ17 I/O SSTL 61 DQ40 I/O SSTL 28 DQ18 I/O SSTL 64 DQ41 I/O SSTL 31 DQ19 I/O SSTL 68 DQ42 I/O SSTL 114 DQ20 I/O SSTL 69 DQ43 I/O SSTL 117 DQ21 I/O SSTL 153 DQ44 I/O SSTL 155 DQ45 I/O SSTL 161 DQ46 I/O SSTL 162 DQ47 I/O SSTL 72 DQ48 I/O SSTL 73 DQ49 I/O SSTL 79 DQ50 I/O SSTL 80 DQ51 I/O SSTL 165 DQ52 I/O SSTL 166 DQ53 I/O SSTL 170 DQ54 I/O SSTL 171 DQ55 I/O SSTL 83 DQ56 I/O SSTL 84 DQ57 I/O SSTL 87 DQ58 I/O SSTL 88 DQ59 I/O SSTL 174 DQ60 I/O SSTL 175 DQ61 I/O SSTL Data Sheet Data Bus 63:0 Pin Configuration of UDIMM (cont'd) 9 Data Bus 63:0 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration Table 3 Pin Configuration of UDIMM (cont'd) Table 3 Pin Configuration of UDIMM (cont'd) Pin# Name Pin Buffer Function Type Type Pin# Name Pin Buffer Function Type Type 178 DQ62 I/O SSTL 97 DM0 I SSTL 179 DQ63 I/O SSTL 107 DM1 I SSTL 44 CB0 I/O SSTL Check Bit 0 119 DM2 I SSTL Note: ECC type module 129 DM3 I SSTL 45 49 Data Bus 63:0 NC NC - Note: Non-ECC module 149 DM4 I SSTL CB1 I/O SSTL Check Bit 1 159 DM5 I SSTL Note: ECC type module 169 DM6 I SSTL DM7 I SSTL DM8 I SSTL NC NC - Note: Non-ECC module 177 CB2 I/O SSTL Check Bit 2 140 134 135 142 NC NC - SCL I CMOS Serial Bus Clock NC NC - Note: Non-ECC module CB3 I/O SSTL Check Bit 3 EEPROM Note: ECC type module 92 Note: Non-ECC module NC NC - Note: Non-ECC module 91 SDA I/O OD CB4 I/O SSTL Check Bit 4 181 SA0 I Note: ECC type module 182 SA1 I CMOS Slave Address Select CMOS Bus 2:0 SA2 I CMOS NC NC - Note: Non-ECC module 183 CB5 I/O SSTL Check Bit 5 Power Supplies Note: ECC type module 1 184 NC NC - Note: Non-ECC module CB6 I/O SSTL Check Bit 6 NC NC - Note: Non-ECC module CB7 I/O SSTL Check Bit 7 Note: ECC type module NC NC - Note: Non-ECC module 5 DQS0 I/O SSTL Data Strobe Bus 7:0 14 DQS1 I/O SSTL 25 DQS2 I/O SSTL 36 DQS3 I/O SSTL 56 DQS4 I/O SSTL Note: See block diagram for corresponding DQ signals 67 DQS5 I/O SSTL 78 DQS6 I/O SSTL 86 DQS7 I/O SSTL 47 DQS8 I/O SSTL VREF AI - VDDSPD PWR - 15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 Note: ECC type module 144 Data Mask 8 Note: ECC type module Note: ECC type module 51 Data Mask Bus 7:0 PWR - Serial Bus Data I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply Data Strobe 8 Note: ECC type module NC Data Sheet NC - Note: Non-ECC module 10 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration Table 3 Pin Configuration of UDIMM (cont'd) Table 3 Pin Configuration of UDIMM (cont'd) Pin# Name Pin Buffer Function Type Type Pin# Name Pin Buffer Function Type Type 7, VDD 38, 46, 70, 85, 108, 120, 148, 168 PWR - Power Supply NC 3, VSS 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 GND - Ground Plane NC 9, 10, 71, 90, 101, 102, 103, 113, 163, 173 Table 4 VDDID Not connected Pins not connected on Infineon UDIMMs Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Table 5 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL2) LV-CMOS Low Voltage CMOS CMOS OD Other Pins 82 - O OD CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. VDD Identification Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB Data Sheet 11 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration VREF VSS DQS0 VDD NC VSS DQ09 VDDQ CK1 DQ10 CKE0 DQ16 DQS2 A9 A7 DQ19 DQ24 DQ25 A04 DQ26 A2 A1 CB01/NC DQS8/NC CB02/NC CB03/NC - DQ32 DQ33 DQ34 BA0 DQ40 WE CAS DQS5 DQ43 NC DQ49 CK2 VDDQ DQ50 VSS DQ56 VDD DQ58 VSS SDA - Pin 001 Pin 003 Pin 005 Pin 007 Pin 009 Pin 011 Pin 013 Pin 015 Pin 017 Pin 019 Pin 021 Pin 023 Pin 025 Pin 027 Pin 029 Pin 031 Pin 033 Pin 035 Pin 037 Pin 039 Pin 041 Pin 043 Pin 045 Pin 047 Pin 049 Pin 051 Pin 053 Pin 055 Pin 057 Pin 059 Pin 061 Pin 063 Pin 065 Pin 067 Pin 069 Pin 071 Pin 073 Pin 075 Pin 077 Pin 079 Pin 081 Pin 083 Pin 085 Pin 087 Pin 089 Pin 091 DQ00 DQ01 DQ02 DQ03 NC DQ08 DQS1 CK1 VSS DQ11 VDDQ DQ17 VSS DQ18 VDDQ A5 VSS DQS3 VDD DQ27 VSS CB00/NC VDD A0 VSS BA1 - Pin 002 Pin 004 Pin 006 Pin 008 Pin 010 Pin 012 Pin 014 Pin 016 Pin 018 Pin 020 Pin 022 Pin 024 Pin 026 Pin 028 Pin 030 Pin 032 Pin 034 Pin 036 Pin 038 Pin 040 Pin 042 Pin 044 Pin 046 Pin 048 Pin 050 Pin 052 Pin 094 Pin 096 Pin 098 Pin 100 Pin 102 Pin 104 Pin 106 Pin 108 Pin 110 Pin 112 Pin 114 Pin 116 Pin 118 Pin 120 Pin 122 Pin 124 Pin 126 Pin 128 Pin 130 Pin 132 Pin 134 Pin 136 Pin 138 Pin 140 Pin 142 Pin 144 VDDQ - Pin 054 DQS4 - Pin 056 VSS - Pin 058 DQ35 - Pin 060 VDDQ - Pin 062 DQ41 - Pin 064 VSS - Pin 066 DQ42 - Pin 068 VDD - Pin 070 DQ48 - Pin 072 VSS - Pin 074 CK2 - Pin 076 DQS6 - Pin 078 DQ51 - Pin 080 VDDID - Pin 082 DQ57 - Pin 084 DQS7 - Pin 086 DQ59 - Pin 088 NC - Pin 090 SCL - Pin 092 - DQ04 - VDDQ - DQ06 - VSS - NC - VDDQ - DQ13 - VDD - DQ15 - VDDQ - DQ20 - VSS - A11 - VDD - A8 - VSS - DQ28 - VDDQ - A3 - VSS - CB4/NC - VDDQ - CK0/NC - DM8/NC - CB06/NC - CB7/NC Pin 146 Pin 148 Pin 150 Pin 152 Pin 154 Pin 156 Pin 158 Pin 160 Pin 162 Pin 164 Pin 166 Pin 168 Pin 170 Pin 172 Pin 174 Pin 176 Pin 178 Pin 180 Pin 182 Pin 184 - DQ36 VDD DQ38 VSS RAS VDDQ S1/NC VSS DQ47 VDDQ DQ53 VDD DQ54 VDDQ DQ60 VSS DQ62 VDDQ SA1 VDDSPD Pin 093 Pin 095 Pin 097 Pin 099 Pin 101 Pin 103 Pin 105 Pin 107 Pin 109 Pin 111 Pin 113 Pin 115 Pin 117 Pin 119 Pin 121 Pin 123 Pin 125 Pin 127 Pin 129 Pin 131 Pin 133 Pin 135 Pin 137 Pin 139 Pin 141 Pin 143 - VSS DQ05 DM0 DQ07 NC NC DQ12 DM1 DQ14 CKE1/NC NC A12/NC DQ21 DM2 DQ22 DQ23 A6 DQ29 DM3 DQ30 DQ31 CB5/NC CK0/NC VSS A10/AP VDDQ Pin 145 Pin 147 Pin 149 Pin 151 Pin 153 Pin 155 Pin 157 Pin 159 Pin 161 Pin 163 Pin 165 Pin 167 Pin 169 Pin 171 Pin 173 Pin 175 Pin 177 Pin 179 Pin 181 Pin 183 - VSS DQ37 DM4 DQ39 DQ44 DQ45 S0 DM5 DQ46 NC DQ52 A13/NC DM6 DQ51 NC DQ61 DM7 DQ63 SA0 SA2 MPPD0030 Figure 1 Data Sheet Pin Configuration 184-Pin, UDIMM 12 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration Table 6 Address Format Density Organization 256 MB 32M x64 512 MB 64M x64 512 MB 64M x72 1 GB 1 GB SDRAMs # of SDRAMs # of row/bank/ columns bits Refresh Period Interval 1 32M x16 4 13/2/10 8K 64 ms 7.8 s 1 64M x8 8 13/2/11 8K 64 ms 7.8 s 1 64M x8 9 13/2/11 8K 64 ms 7.8 s 128M x64 2 64M x8 16 13/2/11 8K 64 ms 7.8 s 128M x72 2 64M x8 18 13/2/11 8K 64 ms 7.8 s Data Sheet Memory Ranks 13 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration BA0 - BA1 A0 - An RAS CAS WE CKE0 VDDSPD VDD/VDDQ VREF VSS VDDID BA0 - BA1: SDRAMs D0 - D3 A0 - An: SDRAMs D0 - D3 RAS: SDRAMs D0 - D3 CAS: SDRAMs D0 - D3 WE: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D3 VREF: SDRAMs D0 - D3 VSS: SDRAMs D0 - D3 Strap: see Note 1 S0 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D0 DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 SCL SAD SA0 SA1 SA2 VSS SCL SAD A0 A1 A2 WP D1 E0 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDM CS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D2 D3 MPBD1051 Figure 2 Block Diagram UDIMM Raw Card C x64 1 Rank x16 Notes 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 7.5 5 % Data Sheet Table 7 14 Clock Signal Loads Clock Input Number of SDRAMs Note CK0, CK0 NC -- CK1, CK1 2 SDRAMs -- CK2, CK2 2 SDRAMs -- Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration 9 99 9 9 9 9 99 9 9 !"#$%%&'!% ( 9 ( Figure 3 Block Diagram UDIMM Raw Card A x64 1 Rank x8 Notes 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 5.1 5 % Data Sheet Table 8 15 Clock Signal Loads Clock Input Number of SDRAMs Note CK0, CK0 2 SDRAMs -- CK1, CK1 3 SDRAMs -- CK2, CK2 3 SDRAMs -- Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration BA0 - BA1 A0 - An RAS CAS WE CKE0 VDDSPD VDD/VDDQ VREF VSS VDDID BA0 - BA1: SDRAMs D0 - D8 A0 - An: SDRAMs D0 - D8 RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 WE: SDRAMs D0 - D8 CKE: SDRAMs D0 - D8 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D8 VREF: SDRAMs D0 - D8 VSS: SDRAMs D0 - D8 Strap: see Note 1 S0 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 D1 D2 DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SCL SAD SA0 SA1 SA2 VSS Figure 4 SCL SAD A0 A1 A2 WP D3 D4 D5 DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM8 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 D7 D8 E0 MPBD1001 Block Diagram UDIMM Raw Card A x72, 1Rank, x8, ECC Note: 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 5.1 5 % Data Sheet Table 9 16 Clock Signal Loads Clock Input Number of SDRAMs Note CK0, CK0 3 SDRAMs -- CK1, CK1 3 SDRAMs -- CK2, CK2 3 SDRAMs -- Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration BA0 - BA1 A0 - An RAS CAS WE CKE0 CKE1 VDDSPD VDD/VDDQ VREF VSS VDDID BA0 - BA1: SDRAMs D0 - D15 A0 - An: SDRAMs D0 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 WE: SDRAMs D0 - D15 CKE: SDRAMs D0 - D7 CKE:SDRAMs D8 - D15 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D15 VREF: SDRAMs D0 - D15 VSS: SDRAMs D0 - D15 Strap: see Note 1 S0 S1 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 D1 D2 D3 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 D9 D10 D11 DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SCL SAD SA0 SA1 SA2 VSS Figure 5 D5 D6 D7 Table 10 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 3 5 % 17 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D12 D13 D14 D15 E0 MPBD1031 Block Diagram UDIMM Raw Card B x64, 2 Ranks, x8 Note: Data Sheet SCL SAD A0 A1 A2 WP D4 Clock Signal Loads Clock Input Number of SDRAMs Note CK0, CK0 4 SDRAMs -- CK1, CK1 6 SDRAMs -- CK2, CK2 6 SDRAMs -- Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration BA0 - BA1 A0 - An RAS CAS WE CKE0 CKE1 BA0 - BA1: SDRAMs D0 - D17 A0 - An: SDRAMs D0 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 WE: SDRAMs D0 - D17 CKE: SDRAMs D0 - D8 CKE:SDRAMs D9 - D17 SCL SAD SA0 SA1 SA2 VSS E0 SCL SAD A0 A1 A2 WP S0 S1 DM0/DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM1/DQS10 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM2/DQS11 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM3/DQS12 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VDDSPD VDD/VDDQ VREF VSS VDDID CS CS CS CS D0 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CS CS CS D9 DM4/DQS13 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM5/DQS14 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM6/DQS15 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM7/DQS16 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM8/DQS17 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D10 D11 D12 VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D17 VREF: SDRAMs D0 - D17 VSS: SDRAMs D0 - D17 DM: SDRAMs D0 - D17 Strap: see Note 1 CS CS CS CS CS D4 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CS CS CS CS D13 D14 D15 D16 D17 MPBD1021 Figure 6 Block Diagram UDIMM Raw Card B x72, 2Ranks, x8, ECC Note: 1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 3 5 % Data Sheet Table 11 18 Clock Signal Loads Clock Input Number of SDRAMs Note CK0, CK0 6 SDRAMs -- CK1, CK1 6 SDRAMs -- CK2, CK2 6 SDRAMs -- Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Pin Configuration 6 DRAM Loads DRAM1 DRAM2 CK R = 120 5% DIMM Connector DRAM3 4 DRAM Loads DRAM4 CK DRAM1 DRAM5 DRAM2 R = 120 5% DRAM6 DIMM Connector Cap. Cap. 3 DRAM Loads R = 120 5% DIMM Connector DRAM1 DRAM5 Cap. DRAM6 DRAM3 Cap. 2 DRAM Loads DRAM5 Cap. Cap. 1 DRAM Loads R = 120 5% DIMM Connector Cap. R = 120 5% Cap. Cap. DRAM5 Cap. DIMM Connector DRAM1 DRAM3 Cap. Cap. Cap. Cap. Figure 7 Data Sheet Clock Net Wiring 19 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Electrical Characteristics 3 Electrical Characteristics 3.1 Operating ConditionsIDD Current Conditions and Specification Table 12 IDD Conditions Parameter Symbol Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. IDD1 Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX IDD2P Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. IDD2F Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. IDD2Q Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. IDD3N Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA IDD4R Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B IDD4W Auto-Refresh Current tRC = tRFCMIN, burst refresh IDD5 Self-Refresh Current CKE 0.2 V; external clock on IDD6 Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. IDD7 Data Sheet 20 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Electrical Characteristics Table 13 IDD Specification for HYS[64/72]D[32/64/128]3xxHU-5-C HYS64D64300HU-5-C HYS72D64300HU-5-C HYS64D128320HU-5-C HYS72D128320HU-5-C Unit Note 1)2) HYS64D32301HU-5-C Product Type 256MB 512MB 512MB 1GB 1GB x64 x64 x72 x64 x72 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks -5 -5 -5 -5 -5 Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 300 360 480 600 540 680 760 940 860 1050 mA 3) 360 440 560 680 630 770 840 1020 950 1140 mA 3)4) 4 18 9 37 10 41 18 74 20 83 mA 5) 100 120 200 240 230 270 400 480 450 540 mA 5) 70 90 140 180 150 210 270 370 310 410 mA 5) 50 60 100 130 110 140 190 260 220 290 mA 5) 150 180 280 340 320 380 560 670 630 760 mA 5) 440 540 640 720 720 810 920 1060 1040 1190 mA 3)4) 460 540 680 760 770 860 960 1100 1080 1230 mA 3) 580 760 1160 1520 1310 1710 1440 1860 620 2090 mA 3) 6 20 13 40 14 45 26 80 29 90 mA 5) 840 1000 1560 1840 1760 2070 1840 2180 2070 2450 mA 3)4) Organization 1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component] Data Sheet 21 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Electrical Characteristics HYS64D128320HU-6-C HYS72D128320HU-6-C Organization HYS72D64300HU-6-C Product Type HYS64D64300HU-6-C IDD Specification for HYS[64/72]D[32/64/128]3xxHU-6-C HYS64D32301HU-6-C Table 14 256MB 512MB 512MB 1GB 1GB x64 x64 x72 x64 x72 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks -6 -6 -6 -6 -6 Unit Note 1)2) Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 280 340 480 560 540 630 740 860 830 960 mA 3) 320 380 520 640 590 720 780 940 870 1050 mA 3)4) 4 18 9 37 10 41 18 74 20 83 mA 5) 80 100 170 200 190 230 340 400 380 450 mA 5) 60 90 120 180 140 200 240 350 270 400 mA 5) 40 60 90 120 100 140 180 240 200 270 mA 5) 130 160 260 300 290 330 510 590 580 670 mA 5) 380 460 560 680 630 770 820 980 920 1100 mA 3)4) 400 480 600 720 680 810 860 1020 960 1140 mA 3) 520 700 1040 1400 1170 1580 1300 1700 1460 1910 mA 3) 6.4 20 12.8 40 14.4 45 25.6 80 28.8 90 mA 5) 760 920 1400 1640 1580 1850 1660 1940 1860 2180 mA 3)4) 1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.6 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component] Data Sheet 22 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Electrical Characteristics Table 15 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol -5 -6 DDR400B Unit Note/ Test Condition 1) DDR333 Min. Max. Min. Max. DQ output access time from CK/CK tAC -0.7 +0.5 -0.7 +0.7 ns 2)3)4)5) CK high-level width tCH tCK 0.45 0.55 0.45 0.55 tCK 2)3)4)5) 5 8 6 12 ns CL = 3.0 Clock cycle time 2)3)4)5) 6 12 6 12 ns CL = 2.5 2)3)4)5) 7.5 12 7.5 12 ns CL = 2.0 tCK tCK 2)3)4)5) 2)3)4)5) tCL Auto precharge write recovery tDAL CK low-level width 0.45 0.55 0.45 0.55 (tWR/tCK) + (tRP/tCK) 2)3)4)5)6) + precharge time 0.4 -- 0.45 -- ns 2)3)4)5) 1.75 -- 1.75 -- ns 2)3)4)5)6) DQS output access time from tDQSCK CK/CK -0.5 +0.5 -0.6 +0.6 ns 2)3)4)5) DQS input low (high) pulse width (write cycle) tDQSL,H 0.35 -- 0.35 -- tCK 2)3)4)5) DQS-DQ skew (DQS and associated DQ signals) tDQSQ -- +0.40 -- +0.45 ns TSOPII Write command to 1st DQS latching transition tDQSS 0.72 1.25 0.75 1.25 tCK 2)3)4)5) DQ and DM input setup time tDS tDSH 0.4 -- 0.45 -- ns 2)3)4)5) 0.2 -- 0.2 -- tCK 2)3)4)5) DQS falling edge to CK setup tDSS time (write cycle) 0.2 -- 0.2 -- tCK 2)3)4)5) min. (tCL, tCH) -- ns 2)3)4)5) 2)3)4)5)7) tDH DQ and DM input pulse width tDIPW DQ and DM input hold time (each input) DQS falling edge hold time from CK (write cycle) tHP Data-out high-impedance time tHZ Clock Half Period 2)3)4)5) min. (tCL, tCH) -- +0.7 -0.7 +0.7 ns -- 0.75 -- ns from CK/CK Address and control input hold tIH time 0.6 fast slew rate 3)4)5)6)8) 0.7 -- 0.8 -- ns slow slew rate 3)4)5)6)8) Control and Addr. input pulse width (each input) Data Sheet tIPW 2.2 -- 23 2.2 -- ns 2)3)4)5)9) Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Electrical Characteristics Table 15 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol -5 -6 DDR400B Address and control input setup time tIS Unit DDR333 Min. Max. Min. Max. 0.6 -- 0.75 -- ns Note/ Test Condition 1) fast slew rate 3)4)5)6)10) 0.7 -- 0.8 -- ns slow slew rate 3)4)5)6)10) Data-out low-impedance time tLZ from CK/CK -0.7 +0.7 -0.7 +0.7 ns 2)3)4)5)7) Mode register set command cycle time tMRD 2 -- 2 -- tCK 2)3)4)5) DQ/DQS output hold time tQH tQHS tHP - tQHS -- tHP - tQHS -- ns 2)3)4)5) -- +0.50 -- +0.55 ns TSOPII Data hold skew factor 2)3)4)5) ns 2)3)4)5) 70E+3 42 70E+3 ns 2)3)4)5) Active to Autoprecharge delay tRAP tRCD -- Active to Precharge command tRAS 40 tRCD -- Active to Active/Auto-refresh command period tRC 55 -- 60 -- ns 2)3)4)5) Active to Read or Write delay tRCD tREFI 15 -- 18 -- ns 2)3)4)5) -- 7.8 -- 7.8 s 2)3)4)5)8) tRFC 70 -- 72 -- ns 2)3)4)5) 15 -- 18 -- ns 2)3)4)5) 2)3)4)5) Average Periodic Refresh Interval Auto-refresh to Active/Autorefresh command period tRP Read preamble tRPRE Read postamble tRPST Active bank A to Active bank B tRRD Precharge command period 0.9 1.1 0.9 1.1 0.40 0.60 0.40 0.60 tCK tCK 10 -- 12 -- ns 2)3)4)5) tWPRE tWPRES tWPST tWR tWTR 0.25 -- 0.25 -- tCK 2)3)4)5) 0 -- 0 -- ns 2)3)4)5)11) 0.40 0.60 0.40 0.60 tCK 2)3)4)5)12) 15 -- 15 -- ns 2)3)4)5) 2 -- 1 -- tCK 2)3)4)5) tXSNR 75 -- 75 -- ns 2)3)4)5) 2)3)4)5) command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command 2)3)4)5) Exit self-refresh to read tXSRD 200 -- 200 -- tCK command 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. Data Sheet 24 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Electrical Characteristics 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. Data Sheet 25 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents 4 SPD Contents Table 16 SPD Codes for HYS64D32301HU-[5/6]-C Product Type Organization HYS64D32301HU-5-C HYS64D32301HU-6-C 256 MB 256 MB x64 x64 1 Rank (x16) 1 Rank (x16) PC3200U-30331 PC2700U-25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 1 Total number of Bytes in E2PROM 08 08 2 Memory Type (DDR = 07h) 07 07 3 Number of Row Addresses 0D 0D 4 Number of Column Addresses 0A 0A 5 Number of DIMM Ranks 01 01 6 Data Width (LSB) 40 40 7 Data Width (MSB) 00 00 8 Interface Voltage Levels 04 04 9 50 60 10 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 11 Error Correction Support 00 00 12 Refresh Rate 82 82 13 Primary SDRAM Width 10 10 14 Error Checking SDRAM Width 00 00 15 tCCD [cycles] 01 01 16 Burst Length Supported 0E 0E 17 Number of Banks on SDRAM Device 04 04 18 CAS Latency 1C 0C 19 CS Latency 01 01 20 Write Latency 02 02 21 DIMM Attributes 20 20 22 Component Attributes C1 C1 23 60 75 70 70 75 00 70 00 3C 48 28 30 3C 48 30 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 28 2A 31 Module Density per Rank 40 40 Label Code 24 25 26 27 28 29 Data Sheet 26 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Table 16 SPD Codes for HYS64D32301HU-[5/6]-C (cont'd) Product Type HYS64D32301HU-5-C HYS64D32301HU-6-C Organization 256 MB 256 MB x64 x64 1 Rank (x16) 1 Rank (x16) PC3200U-30331 PC2700U-25331 Label Code JEDEC SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 32 60 75 60 75 40 45 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 40 45 36 - 40 not used 00 00 41 37 3C 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 46 33 34 42 41 48 28 30 28 2D 50 55 not used 00 00 47 DIMM PCB Height 01 01 48 - 61 not used 00 00 62 SPD Revision 10 10 63 Checksum of Byte 0-62 76 1A 64 JEDEC ID Code of Infineon (1) C1 C1 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 72 Module Manufacturer Location xx xx 73 Part Number, Char 1 36 36 74 Part Number, Char 2 34 34 75 Part Number, Char 3 44 44 76 Part Number, Char 4 33 33 77 Part Number, Char 5 32 32 78 Part Number, Char 6 33 33 79 Part Number, Char 7 30 30 80 Part Number, Char 8 31 31 81 Part Number, Char 9 48 48 82 Part Number, Char 10 55 55 83 Part Number, Char 11 35 36 84 Part Number, Char 12 43 43 85 Part Number, Char 13 20 20 86 Part Number, Char 14 20 20 87 Part Number, Char 15 20 20 88 Part Number, Char 16 20 20 89 Part Number, Char 17 20 20 43 44 Data Sheet 27 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Table 16 SPD Codes for HYS64D32301HU-[5/6]-C (cont'd) Product Type HYS64D32301HU-5-C HYS64D32301HU-6-C Organization 256 MB 256 MB x64 x64 1 Rank (x16) 1 Rank (x16) PC3200U-30331 PC2700U-25331 Label Code JEDEC SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 90 Part Number, Char 18 20 20 91 Module Revision Code 0x 0x 92 Test Program Revision Code xx xx 93 Module Manufacturing Date Year xx xx 94 Module Manufacturing Date Week xx xx 95 - 98 Module Serial Number (1 - 4) xx xx 99 - 127 not used 00 00 Data Sheet 28 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Product Type HYS64D64300HU-6-C HYS72D64300HU-5-C HYS72D64300HU-6-C SPD Codes for HYS[72/64]D64300HU-[5/6]-C HYS64D64300HU-5-C Table 17 Organization 512 MB 512 MB 512 MB 512 MB x64 x64 x72 x72 1 Rank (x8) 1 Rank (x8) 1 Rank (x8) 1 Rank (x8) PC3200U- 30331 PC2700U- 25331 PC3200U- 30331 PC2700U- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0B 0B 0B 5 Number of DIMM Ranks 01 01 01 01 6 Data Width (LSB) 40 40 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 50 60 50 60 10 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 00 00 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 18 CAS Latency 1C 0C 1C 0C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 21 DIMM Attributes 20 20 20 20 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] 60 75 60 75 70 70 70 70 75 00 75 00 Label Code 24 25 Data Sheet 29 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Product Type HYS64D64300HU-6-C HYS72D64300HU-5-C HYS72D64300HU-6-C SPD Codes for HYS[72/64]D64300HU-[5/6]-C (cont'd) HYS64D64300HU-5-C Table 17 Organization 512 MB 512 MB 512 MB 512 MB x64 x64 x72 x72 1 Rank (x8) 1 Rank (x8) 1 Rank (x8) 1 Rank (x8) PC3200U- 30331 PC2700U- 25331 PC3200U- 30331 PC2700U- 25331 Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Label Code JEDEC SPD Revision Byte# Description HEX HEX HEX HEX 26 70 00 70 00 3C 48 3C 48 28 30 28 30 3C 48 3C 48 30 tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 28 2A 28 2A 31 Module Density per Rank 80 80 80 80 32 60 75 60 75 60 75 60 75 40 45 40 45 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 40 45 40 45 36 - 40 not used 00 00 00 00 41 37 3C 37 3C 41 48 41 48 28 30 28 30 28 2D 28 2D 27 28 29 33 34 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 50 55 50 55 46 not used 00 00 00 00 47 DIMM PCB Height 01 01 01 01 48 - 61 not used 00 00 00 00 62 SPD Revision 10 10 10 10 63 Checksum of Byte 0-62 AF 53 C1 65 64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1 65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 36 36 37 37 74 Part Number, Char 2 34 34 32 32 75 Part Number, Char 3 44 44 44 44 76 Part Number, Char 4 36 36 36 36 42 43 44 Data Sheet 30 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Product Type HYS64D64300HU-6-C HYS72D64300HU-5-C HYS72D64300HU-6-C SPD Codes for HYS[72/64]D64300HU-[5/6]-C (cont'd) HYS64D64300HU-5-C Table 17 Organization 512 MB 512 MB 512 MB 512 MB x64 x64 x72 x72 1 Rank (x8) 1 Rank (x8) 1 Rank (x8) 1 Rank (x8) PC3200U- 30331 PC2700U- 25331 PC3200U- 30331 PC2700U- 25331 Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Label Code JEDEC SPD Revision Byte# Description HEX HEX HEX HEX 77 Part Number, Char 5 34 34 34 34 78 Part Number, Char 6 33 33 33 33 79 Part Number, Char 7 30 30 30 30 80 Part Number, Char 8 30 30 30 30 81 Part Number, Char 9 48 48 48 48 82 Part Number, Char 10 55 55 55 55 83 Part Number, Char 11 35 36 35 36 84 Part Number, Char 12 43 43 43 43 85 Part Number, Char 13 20 20 20 20 86 Part Number, Char 14 20 20 20 20 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code 0x 0x 0x 0x 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 Data Sheet 31 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Product Type HYS64D128320HU-6-C HYS72D128320HU-5-C HYS72D128320HU-6-C SPD Codes for HYS[64/72]D128320HU-[5/6]-C HYS64D128320HU-5-C Table 18 Organization 1 GByte 1 GByte 1 GByte 1 GByte x64 x64 x72 x72 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) PC3200U- 30331 PC2700U- 25331 PC3200U- 30331 PC2700U- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0B 0B 0B 5 Number of DIMM Ranks 02 02 02 02 6 Data Width (LSB) 40 40 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 50 60 50 60 10 tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 00 00 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 18 CAS Latency 1C 0C 1C 0C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 Label Code 21 DIMM Attributes 20 20 20 20 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] 60 75 60 75 70 70 70 70 75 00 75 00 24 25 Data Sheet 32 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Product Type HYS64D128320HU-6-C HYS72D128320HU-5-C HYS72D128320HU-6-C SPD Codes for HYS[64/72]D128320HU-[5/6]-C (cont'd) HYS64D128320HU-5-C Table 18 Organization 1 GByte 1 GByte 1 GByte 1 GByte x64 x64 x72 x72 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) PC3200U- 30331 PC2700U- 25331 PC3200U- 30331 PC2700U- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 26 70 00 70 00 3C 48 3C 48 28 30 28 30 3C 48 3C 48 30 tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] 28 2A 28 2A 31 Module Density per Rank 80 80 80 80 32 60 75 60 75 60 75 60 75 40 45 40 45 35 tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] 40 45 40 45 36 - 40 not used 00 00 00 00 41 37 3C 37 3C 41 48 41 48 45 tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] 46 Label Code 27 28 29 33 34 42 43 28 30 28 30 28 2D 28 2D 50 55 50 55 not used 00 00 00 00 47 DIMM PCB Height 01 01 01 01 48 - 61 not used 00 00 00 00 62 SPD Revision 10 10 10 10 63 Checksum of Byte 0-62 B0 54 C2 66 44 64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1 65 -71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 36 36 37 37 74 Part Number, Char 2 34 34 32 32 75 Part Number, Char 3 44 44 44 44 Data Sheet 33 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules SPD Contents Product Type HYS64D128320HU-6-C HYS72D128320HU-5-C HYS72D128320HU-6-C SPD Codes for HYS[64/72]D128320HU-[5/6]-C (cont'd) HYS64D128320HU-5-C Table 18 Organization 1 GByte 1 GByte 1 GByte 1 GByte x64 x64 x72 x72 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) 2 Ranks (x8) PC3200U- 30331 PC2700U- 25331 PC3200U- 30331 PC2700U- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 76 Part Number, Char 4 31 31 31 31 77 Part Number, Char 5 32 32 32 32 78 Part Number, Char 6 38 38 38 38 79 Part Number, Char 7 33 33 33 33 80 Part Number, Char 8 32 32 32 32 81 Part Number, Char 9 30 30 30 30 82 Part Number, Char 10 48 48 48 48 83 Part Number, Char 11 55 55 55 55 84 Part Number, Char 12 35 36 35 36 85 Part Number, Char 13 43 43 43 43 86 Part Number, Char 14 20 20 20 20 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code 0x 0x 0x 0x 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 Label Code Data Sheet 34 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Package Outlines 5 Package Outlines Package Outline for HYS64D32301HU-[5/6]-C 0.1 A B C 133.35 0.15 A B C 128.95 2.7 MAX. A 31.75 0.13 4 0.1 1) 1 2.36 0.1 o0.1 A B C 92 6.62 B 2.175 0.4 6.35 64.77 C 1.27 0.1 49.53 0.1 A B C 93 184 17.8 1.8 0.1 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C 1) On ECC modules only Burr max. 0.4 allowed Figure 8 Data Sheet Package Outline UDIMM Raw Card C (L-DIM-184-18) 35 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Package Outlines Package Outline for HYS64D64300HU-[5/6]-C 0.1 A B C 133.35 0.15 A B C 128.95 2.7 MAX. 31.75 0.13 4 0.1 A 1 2.36 0.1 o0.1 A B C 92 6.62 B 2.175 0.4 6.35 64.77 C 1.27 0.1 49.53 0.1 A B C 93 184 17.8 1.8 0.1 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C Burr max. 0.4 allowed Figure 9 Data Sheet Package Outline UDIMM Raw Card A (L-DIM-184-32) 36 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Package Outlines Package Outline for HYS72D64300HU-[5/6]-C 0.1 A B C 133.35 0.15 A B C 128.95 2.7 MAX. A 31.75 0.13 4 0.1 1) 1 2.36 0.1 o0.1 A B C 92 6.62 B 2.175 0.4 6.35 64.77 C 1.27 0.1 49.53 0.1 A B C 93 184 17.8 1.8 0.1 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C 1) On ECC modules only Burr max. 0.4 allowed Figure 10 Data Sheet Package Outline UDIMM Raw Card A (L-DIM-184-30) 37 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 HYS[64/72]D[16/32/128]3xxHU-[5/6]-C Unbuffered DDR SDRAM Modules Package Outlines Package Outline for HYS[64/72]D128320HU-[5/6]-C 0.1 A B C 133.35 0.15 A B C 128.95 4 MAX. A 31.75 0.13 4 0.1 1) 1 2.36 0.1 o0.1 A B C 92 6.62 B C 2.175 0.4 6.35 64.77 1.27 0.1 49.53 0.1 A B C 93 184 17.8 1.8 0.1 10 3.8 0.13 95 x 1.27 = 120.65 3 MIN. 0.2 2.5 0.2 Detail of contacts 1.27 1 0.05 0.1 A B C 1) On ECC modules only Burr max. 0.4 allowed Figure 11 Data Sheet Package Outline UDIMM Raw Card B (L-DIM-184-31) 38 Rev. 1.1, 2005-05 07192004-EH0E-I4S5 www.infineon.com Published by Infineon Technologies AG