CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
PRELIMINARY
256/512/1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
Cypress Semiconductor Corporation • 3901 North First Street • Sa n Jose • CA 95134 • 40 8-943-2600
S eptember 14
,
1998
Features
• High-speed, low-power, bidirecti onal, first-in first-out
(FIFO) memories
• 256x36x2 (CY7C43622)
• 512x36x2 (CY7C43632)
• 1Kx36x2 (CY7C43642)
• 4Kx36x2 (CY7C43662)
• 16Kx36x2 (CY7C43682)
• 0.35-micr on CMOS f or optimum speed/power
• High speed 83-MHz opera tion (12 ns read/wr ite cycle
times)
• Low power
—ICC= 100 m A
—ISB= 5 mA
• Fully asynchronous and simultaneous read and write
operati on permitted
• M ailbox bypass register f or each FIFO
• P ar allel Prog ramm able Al most-Ful l and Almost -Empty
flags
• Retransmit functi on
• Standard or FWFT mode user sel ectable
• 120-pin TQFP packaging
• Pin-compatibl e, feature enhanced, density up grade to
IDT723622/32/42 family
• Easil y expandab le i n width and depth
Logic Block Diagra m
Port-A
Control
Logic Port-B
Control
Logic
Mail 1
Register
Input
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable Flag
Offset Registers Timing
Mode
Status
Flag Logic
Write
Pointer Read
Pointer
256/512/1K
4K/16K x36
Dual Ported
Memory
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail 2
Register
Output
Register
Input
Register
FIFO1,
Mail 1
Reset
Logic
FIFO2,
Mail 2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0–35
EFA/ORA
AEA
MBF2
MRS2
PRS2
FFB/IRB
AFB
FWFT/STAN
B0–35
CLKB
CSB
W/RB
ENB
MBB
RT1
EFB/ORB
AEB
MBF1
Output
Register
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
2
PRELIMINARY
CY7C43622
CY7C43632
CY7C43642
CY7C43662
CY7C43682
TQFP
Top View
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
MBF2
GND
FS0
RST1
MBA
AEA
AFA
VCC
FFA/ORA
EFA/IRA
CSA
W/RA
ENA
CLKA
GND
W/RB
VCC
CLKB
ENB
CSB
GND
EFB/IRB
FFB/ORB
AFB
AEB
VCC
MBF1
MBB
RST2
FS1
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B26
GND
B24
B25
RT1
B27
B28
B29
B30
B31
GND
B32
B33
B34
B35
B14
GND
B12
B13
B15
VCC
B16
B17
GND
B18
B19
B20
B21
B22
B23
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A3
A0
A1
A2
VCC
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
B8
B11
B10
B9
B7
VCC
B6
GND
B5
B4
B3
B2
B1
B0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A27
A23
B24
A25
A26
A28
GND
A30
A31
VCC
A32
A33
A34
A35
A14
A12
RT2
A13
A15
A16
A17
GND
A18
A19
A20
A21
VCC
A22
FWFT/STAN
A29
Pin Configuration
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
3
PRELIMINARY
Functional Description
The CY7C436X2 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports cloc k frequencies up t o 83 M Hz and has read
access times as fast as 9 ns. Two independent
256/512/1K/4K/16K x 36 dual-port SRAM FIFOs on board
each chip buffer data in opposite direct ions.
The CY7C436X2 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data tra nsfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The cl ocks for each port are in-
dependent of one another and can be asynchronous or coin-
cident. The enables for each port are arranged to provide a
simpl e bidirec tional int erfac e between micr oprocessors and/or
buses with synchronous control.
Commu nicati on betw een eac h port ma y b ypass th e FIFOs via
two mailbox registers. The mailbox registers’ width matches
the sel ected P ort B bu s width. Each mai lbox re gister has a f la g
(MBF1 and MBF2) to signal when new mail has been st ored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag pro-
gramming, or one of the three possible default flag offset set-
ti ngs, 8 , 16 , or 64 . Each FI FO has its o wn i ndependent Mast er
Reset pin, MRS1 and MRS2.
The CY7C436X2 have two modes of operation: In the CY
Standard Mode, t he first word written to an em pty FIFO is de-
posited into the memory array. A read operation is requi red to
access that word (along with all other words residing in mem-
ory). In the First Word Fall Through Mode
(FWFT), the first
w ord (36- bit wide) written to an emp ty FIFO appe ars auto mat-
ically on the outputs, no read operation required (ne vertheless,
accessing subsequent words does necessitate a formal read
request). The state of the FW FT/STAN pin during FIFO oper-
ation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
Flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not . The IR and OR funct ions are se lected in
the First Word Fall Through Mode. IR indic ates whether or not
the FIFO has availa ble memory locations . OR shows wh ether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmab le Almost Empty fl ag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words writ-
ten to FIFO memory achieve a predetermined “almost empty
state.” AFA and AFB indicate when a selected number of
words wri tten to t he memory ac hie v e a pr edet ermi ned “a lmos t
fu ll st a te. ”
IRA, IRB , AF A, and AF B are synchronized to the port clock that
writes data into its array. ORA, O RB, AEA, and AEB are syn-
chronized to the port cloc k that reads data fr om it s array. Pro -
grammable offset for AEA, AEB, AFA, and AFB are loaded in
paral lel using Port A or i n serial v ia the SD input . Thr ee d ef ault
offset set ti ngs are also provi ded. The AEA and AEB threshold
can be set at 8, 16, or 64 locations from the empty boundary
and AFA and AFB threshol d can be set at 8, 1 6, or 64 l ocations
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used i n parallel to create wider
data paths. If at any time t he FIFO is not act ively performing a
function, the chip will automatically power down. During the
power-down state, supply current consumption (ICC) is at a
minimum . In iti ating any oper ati on ( by act iv at ing cont rol inputs )
will immediately take the device out of the power-down state.
The CY7C436X2 are characterized for operation from 0°C to
70°C . Input ESD prot ection i s great er than 2001V, an d latch-up
is prevented by the use of guard rings.
Selection G uid e
CY7C43622/32/42/62/82−12 CY7C43622/32/42/62/82−15
Maximum Frequency (MHz) 83 66.7
Maximum Access Time (ns) 910
Minimum Cycle Time (ns) 12 15
Minimum Data or Enable Set-Up (ns) 4 5
Minimum Data or Enable Hold (ns) 0 0
Maxim u m Flag Delay (ns) 8 8
Active Power Supply
Current (ICC1) ( mA ) Commercial 100 100
Industrial 100 100
CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682
Density 256 x 36 512 x 36 1K x 36 4K x 36 16K x 36
Package 120 TQFP 120 TQFP 120 TQ FP 120 TQFP 120 TQFP
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
4
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
A0–35 Po rt A Data I/O 36-bit bidirectional data port for side A
AEA Port A Almost
Empty Flag O Programmable almo st-empty f lag synchroniz ed to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the almost-empty A offset register,
X2.
AEB Port B Almost
Empty Flag O Programmable almos t- em pty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the almost-empty B offset register,
X1.
AFA Port A Almost
Full Flag O Programmable almost-full flag synchronized to CLKA. It is LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the almost-full A offset
regist er, Y1.
AFB Port B Almost
Full Flag O Programmable almost-full fla g synchronized to CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the almost-full B offset
regist er, Y2.
B0–35 Po rt B Data I/O 36-bit bidirectional data port for side B.
FWFT/STAN Big Endian/First
Word F all
Through Select
I Duri ng Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW sel ects
First Word Fall Through mode . Once the timi ng m ode has been selected, the level on
FWFT/STAN must be static throughout device operation.
CLKA Port A Clock I CLKA is a cont inuous cl ock that synchronizes al l data t ransf ers thro ugh P ort A a nd can
be asynchronous or coincident to CLKB. FFA/I R A , E FA/ORA, AFA, and AEA are all
synchronized to the LOW -to-HI GH transition of CLKA.
CLKB Port B Clock I CLKB is a cont in uous clock that synchroni zes all data tr ansfer s through P ort B and can
be asynchronous or coincident to CLKA. FFB/IRB, EF B /ORB, AFB, and AEB are all
synchronized to the LOW -to-HI GH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW -t o HIGH tr ansiti on of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW -t o HIGH tr ansiti on of CLKB to read or write on
Port B. The B0–35 out puts are in the high- impedance stat e when CSB is HIG H .
EFA/ORA Por t A Empty/
Output Ready
Flag
O This i s a dual- fun ction pi n. In the CY S tandard Mode, the EF A functi on is selected. EFA
indicat es whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
functi on is sel ected. ORA indi cates the presence of valid data on A0–35 outputs, avail-
able for reading. FFA / ORA is synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ ORB Por t B Empty/
Output Ready
Flag
O This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicat es whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
functi on is sel ected. ORB indi cates the presence of valid data on B0–35 outputs, avail-
able for reading. FFB / ORB is synchronized to the LOW-to-HIGH transition of CLKB.
ENA Po rt A Enab le I ENA m ust be HI GH to ena ble a L O W -to- HIGH tra nsiti on of CLKA t o read or writ e data
on P ort A.
ENB Po rt B Enab le I ENB m ust be HI GH to ena ble a L O W -to- HIGH tra nsiti on of CLKB t o read or writ e data
on P ort B.
FFA/IRA Port A Full/Input
Ready Flag O This i s a dual-function pi n. In the CY Stand ard Mode, the FF A f unction is selecte d. FF A
indicates whether or not the FI FO1 memory is full . In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. F FA/IRA is synchronized to the LO W-to-HIGH transition of CLKA.
FFB/IRB Port B Full/Input
Ready Flag O This i s a dual- functi on pin. In the CY Standard Mode, th e FFB function is selected. FFB
indicates whether or not the FI FO2 memory is full . In the FWFT mode, the IRB function
is selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. F FB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
5
PRELIMINARY
FS1 Flag Offset
Select 1 I FS1 and FS0 are dual-purpose inputs used for flag offset register programming. During
Master Reset , FS1 and FS0, together with SPM, select the flag offset programming
method. Thr ee offset regist er prog ramming m ethods ar e av ail abl e: automat ical ly load
one of thre e preset val ues (8, 16, or 64), parallel l oad from Port A, and seria l lo ad.
When serial l oad is selected f or flag offset register progr am ming, FS1 is used as an
enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1 is LOW, a
rising edge on CLKA loads the bit present on FS0/ SD int o the X and Y regi sters. The
number of bi t writes re qui red to pro gram th e offset regist ers is 32 fo r the CY7C43622,
36 for th e CY7C43632, 40 for the CY7C43642, 48 for the CY7C43662, and 56 for the
CY7C43682. The fi rst bit write stores the Y-r egister MSB and the last bi t wri te st ores
the X-register LSB.
FS0 Flag Offset
Select 0 I
M BA Port A M a i lbox
Select I A HIGH level on M BA chooses a m ailbox register for a Port A read or write oper ation.
When the A 0–35 outp uts are active, a HIGH level on MBA selects data from the Mail 2
regist er for output and a LOW level selects FIFO2 output register data f or output.
M BB Port B M a i lbox
Select I A HIGH level on M BB chooses a m ailbox register for a Port B read or write oper ation.
When the B 0–35 outp uts are active, a HIGH level on MBB selects data from the Mail 1
regist er for output and a LOW level selects FIFO1 output register data f or output.
MBF1 Mail1 Register
Flag OMBF1 is set LOW by a LOW-t o-HIGH trans it ion of CLKA that writes data to the Mail 1
regist er. Writes to t he ma il 1 register are i nhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HI GH tr ansi tion of CLKB when a Port B r ead is select ed and MBB
is HIGH. MBF1 i s set HIGH fol lowing ei ther a Master or Partial Reset of FI FO 1.
MBF2 Mail2 Register
Flag OMBF2 is set LOW by a LOW-t o-HIGH trans it ion of CLKB that writes data to the Mail 2
regist er. Writes to t he ma il 2 register are i nhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HI GH tr ansi tion of CLKA when a Port A r ead is select ed and MBA
is HIGH. MBF2 i s set HIGH fol lowing ei ther a Master or Partial Reset of FI FO 2.
MRS1 FIFO1 Master
Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the P ort B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag def ault
offsets for FIFO1. F our LOW -to- HIGH tr ansiti ons of CLKA and f our LOW -to- HIGH tr an-
sitions of CLKB must occur whil e MRS1 is L OW.
MRS2 FIFO2 Master
Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the P ort A output register to all zeroes. A LOW pulse on MRS2 selects
one of thre e programma ble flag default offsets for FIFO2. Four LOW-to-HIGH transi-
tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is
LOW.
W/RA Port A Write/
Read Select I A HI GH selects a write operat ion and a LO W selects a read operation on Port A f or a
LOW-to-HIGH trans it ion o f CLKA. The A 0–35 output s a re in the HI GH i mpedan ce sta te
when W/RA is H IGH.
W/RB Port B Write/
Read Select I A L OW se lects a write operation and a HIGH selects a read operat ion on Port B for a
LO W -to- HIGH tr ansit ion of CL KB. T he B0–35 output s are i n the HIGH i mpeda nce state
when W/RB is LO W.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
6
PRELIMINARY
Maximum Ratings[1]
(Above which the usefu l l ife may be impa ired. F or user guide-
li nes, not tes ted.)
Storage Temperature .......................................−65°C to +150°C
Ambient Temperatur e wit h
Po wer Applied....................................................−55°C to +125°C
Supply Voltage to Ground Potenti al..................−0.5V to +7.0V
DC Voltag e Applied to Outputs
in High Z State[2] ..........................................−0.5V to VCC+0.5V
DC Input Voltage[2]........................................−0.5V to VCC+0.5V
Output Current into Outputs (LO W) .............................20 mA
Static Discharge Voltage...... .. ....... .. ........... .. .. ....... ....>2001V
(per MIL- STD-883, Method 3015 )
La tc h -U p C u rre n t.. ......... ... .. ..... ... .............. ... ......... ... .>200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70 °C 5.0V ± 0.5V
Industrial −40°C to +85°C 5.0V ± 0.5V
Electrical Characte ristics Over the Operating Range
Parameter Description Test Conditions
CY7C43622/32/42/62/82
UnitMin. Max.
VOH Output HIGH Voltage VCC = 4.5V,
IOH = −4.0 mA 2.4 V
VOL Output LOW Voltage VCC = 4.5V,
IOL = 8.0 mA 0.4 V
VIH Input HI GH Volt age 2.0 VCC V
VIL Input LOW Voltage −0.5 0.8 V
IIX Input Leakage Current VCC = Max. −10 +10 µA
IOZL
IOZH Outp ut OFF, High Z
Current OE > VIH,
VSS < VO< VCC −10 +10 µA
ICC1[3] Active Power Supply
Current Com’l 400 mA
Ind 400 mA
ISB[4] Average Standby
Current Com’l 5mA
Ind 5mA
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacit ance TA = 25°C, f = 1 MHz,
VCC = 3.3V 4pF
COUT Output Ca pacitance 8pF
Notes:
1. Stresses bey ond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the dev ice. These are stress ratings only and functional
operation of the device at these or any other condi tions beyond those indicated under “recommended operationg conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reli ability.
2. The input and output v oltage ratings may be exceeded provided the input and output current ratings are observed.
3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
4. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
5. Tested initially and after any design or process changes that may affect these parameters.
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
7
PRELIMINARY
AC Test Loads and Waveforms
Switching Charac teris t ics Ov er the Operating Range
Parameter Description
CY7C43622/32/42/62/82
–12 CY7C43622/32/42/62/82
–15
UnitMin. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 83 67 MHz
tCLK Clock Cycle Time , CLKA or CLKB 12 15 ns
tCLKH Pul se Duration, CLKA or CLKB HIGH 5 6 ns
tCLKL Pulse Duration, CLKA or CLKB LO W 5 6 ns
tDS Set-Up Time, A0–35 bef ore CLKA↑ and B0–35 be -
fo re CLKB ↑4 5 ns
tENS Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB , W/RB, ENB, and MBB before
CLKB↑
4 5 ns
tRSTS Set-Up Time, MRS1, M RS 2, PRS1, or PRS2
LOW before CLKA↑ or CLKB↑[6] 4 5 ns
tFSS Set-Up Time, FS0 and FS1 before MRS1 and
MRS2 HIGH 77.5 ns
tBES Set-Up Time, FWFT/STAN before MRS1 and
MRS2 HIGH 77.5 ns
tSDS Set-Up Time, FS0 before CLKA↑4 5 ns
tSENS Set-Up Time, FS1 before CLKA↑4 5 ns
tFWS Set-Up Ti me, FWFT before CLKA↑0 0 ns
tDH Hold Time , A0–35 after CLKA↑ and B0–35 after
CLKB↑0 0 ns
tENH Hold Time, CSA, W/R A , ENA, and MBA after
CLKA↑; CSB , W/RB, ENB, and MBB after
CLKB↑
0 0 ns
tRSTH Hold Time , MRS1, MRS2, PRS1, or PRS2 LO W
after CLKA↑ or CLKB↑[6] 4 4 ns
tFSH Hold Time , FS0 and FS1 after MRS1 and MRS2
HIGH 2 2 ns
tBEH Hold Ti me, FWFT/STAN af ter MR S1 and MR S2
HIGH 2 2 ns
Note:
6. Requirement to count the clock edge as one of at least four needed to reset a FIFO
3.0V
5V
OUTPUT
R2=680Ω
CL=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
OUTPUT 1.910V
Equivalent to: THÉ VENIN EQUIVALENT
410 Ω
ALL INPUT PULSES
R1=1.1KΩ
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
8
PRELIMINARY
tSDH Hold Time, FS0 after CLKA↑0 0 ns
tSENH Hold Time, FS1 after CLKA↑0 0 ns
tSPH Hold Time, FS1 HIGH after MRS1 and MRS2
HIGH 2 2 ns
tSKEW1[7] Skew Time between CLKA↑ a nd CLKB ↑ for
EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB 67.5 ns
tSKEW2[7] Skew Time between CLKA↑ a nd CLKB ↑ for
AEA, AEB, AFA, A F B 10 12 ns
tAAcc ess Time, CLKA↑ to A 0–35 and CLKB↑ to
B0–35 19310 ns
tWFF Propagation Delay Time, CLKA↑ to FFA/IRA and
CLKB↑ to FFB/IRB 1 8 2 8 ns
tREF Propagation Delay Time, CLKA↑ to EFA/ORA
and CLKB↑ to EFB/ORB 1 8 1 8 ns
tPAE Propagation Delay Time, CLKA↑ to AEA and
CLKB↑ to AEB 1 8 1 8 ns
tPAF Propagation Delay Time, CLKA↑ to A FA and
CLKB↑ to AFB 1 8 1 8 ns
tPMF Propagat ion Del a y Time , CLKA↑ to MB F1 LO W
or MBF2 HIGH and CLKB↑ to MBF2 LOW or
MBF1 HIGH
09012 ns
tPMR Pro pagati on De la y Tim e, CL KA↑ to B0–35[8] and
CLKB↑ to A0–35[9] 211 312 ns
tMDV Propagation Delay Time, MBA to A0–35 valid and
MBB to B0–35 valid 210 311 ns
tRSF Propagation Delay Time, MRS1 LOW to AEB
LOW , AFA HIGH, and MBF1 HIGH and MRS2 or
PRS2 LO W t o AEA LOW , AFB HIGH, and MBF2
HIGH
112 115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Active
and CSB LOW and W/RB HIGH to B0–35 Active 210 210 ns
tDIS Disable Time, CSA or W/RA HIGH to A0–35 at
high impedance and CSB HIGH or W/RB L OW
to B 0–35 at HIGH impedance
1 7 1 8 ns
Notes:
7. Skew time is not a timing constraint f or proper device operation and is only incl uded to illustrate the ti ming rel ationship between the CLKA cycle and the CLKB
cycle.
8. Writing data to the mail1 register when the B0–35 outputs are active and MBB is HIGH.
9. Writing data to the mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Charac teris t ics Ov er the Operating Range (cont inued)
Parameter Description
CY7C43622/32/42/62/82
–12 CY7C43622/32/42/62/82
–15
UnitMin. Max. Min. Max.
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
9
PRELIMINARY
Switching Wavefor ms
Note:
10. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tBES tBEH
tRSTS
tRSTS
tFWS
CLKB
MRS1
FWFT/STAN
FS1, FS0
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[10]
tRSF
tRSF
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
10
PRELIMINARY
Notes:
11. CSA=LOW, W/RA=HIGH, MBA=LOW. It i s not necessary to program offset register on consecutive clock cycles.
12. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB f or FFB/IRB to transition HIGH in the nex t cyc le. If the time between the rising
edge of CLKA and ri sing edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.
13. Written to FIFO1.
Switching Wavefor ms (continued)
Programming of the Almost- Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Mo des)
tWFF
tFSS
tDS
tFSH
tENS tENH
tDH
tSKEW1[12]
AFA Offset (Y1) AFB Offset (Y2) First Word to FIFO1
CLKA
MRS1
MRS2
FS1
FS0
FFA/IRA
ENA
A0−35
CLKB
FFB/IRB
[11]
AEB Off set (X1) AEA Offset (X2)
tCLKH tCLKL
tENS tENH
tENS tENH
tENS tENH
tENS tENH
tDS tDH
tENS tENH tENS tENH
HIGH
W1[13] W2[13]
tCLK
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0–35
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
11
PRELIMINARY
Notes:
14. Written to FIFO2.
15. Read from FIFO1.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS tENH
tENS tENH
tENS tENH
tENS tENH
tDS tDH
tENS tENH tENS tENH
HIGH
W1[14] W2[14]
tCLK
Port B Write Cycl e Timing for FIFO2 (CY Standard and FWFT Mo des)
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B0−35
OR
tCLKH tCLKL
tENS
tDIS
tENS tEN
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[15] W2[15]
W1[15] W2[15]
W3[15]
Previous Data
No Operation
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B0–35
(Standard Mode)
B0–35
(FWFT Mode)
Port B Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes )
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
12
PRELIMINARY
Note:
16. Read From FIFO2.
Switching Wavefor ms (continued)
OR
tCLKH tCLKL
tENS
tDIS
tENS tENH
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[16] W2[16]
W1[16] W2[16]
W3[16]
Previous Data
No Operation
CLKA
FFA/ORA
CSA
W/RA
MBA
ENA
A0−35
(Standard Mode)
A0−35
(FWFT Mode)
P ort A Read Cycle Timing for FIFO2 (CY Standard and FW FT Mod es)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
13
PRELIMINARY
Note:
17. tSKEW1 is the minimum time betw een a rising CLKA edge and a rising CLKB edge for ORB to transiti on HIG H and to clock the next word to the F IFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tCLK
tEN
tENS
tEN
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empt y
LOW
HIGH
LOW
Old Data in FIFO1 Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW[17]
CLKA
CSA
W/RA
MBA
ENA
IRA
A0–35
CLKB
ORB
CSB
W/RB
MBB
ENB
B0–35
ORB Flag Timi ng and Fir st Data Word Fall Through when FI FO1 is Empty (FWFT Mode)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
14
PRELIMINARY
Note:
18. ttSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empty
LOW
HIGH
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[18]
CLKA
CSA
W/RA
MBA
ENA
FFA
A0–35
CLKB
EFB
CSB
W/RB
MBB
ENB
B0–35
EFB Flag Timing and Fi rst Data Read Fall Through when FIFO1 i s
Empty (CY Standard Mode)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
15
PRELIMINARY
Notes:
19. tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
20. tSKEW1 is the minimum time betw een a rising CLKB edge and a rising CLKA edge for ORA to transiti on HIG H and to clock the next word to the F IFO2 output
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
W1
LOW
tDH
LOW
HIGH
FIFO2 Empt y
LOW
LOW
LOW
Old Data in FIFO2 Output Register W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[20]
tCLK
tDS
CLKB
CSB
W/RB
MBB
ENB
IRB
B0–35
CLKA
ORA
CSA
W/RA
MBA
ENA
A0–35
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
[19]
(FWFT Mode)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
16
PRELIMINARY
Note:
21. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA c ycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Wavefor ms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[21]
CLKB
CSB
W/RB
MBB
ENB
FFB
B0–35
CLKA
EFA
CSA
W/RA
MBA
ENA
A0–35
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
17
PRELIMINARY
Note:
22. tSKEW1 is the minimum time between a ris ing CLKB edge and a risi ng CLKA edge for IRA to transi tion HIGH in the ne xt CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO1 Fu ll
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[22]
tDH
tDS
tENH
tENS
Previous Word in FIFO1 Output Register Next Word From FIFO1
To FIFO1
CLKB
CSB
W/RB
MBB
ENB
ORB
B0–35
CLKA
IRA
CSA
W/RA
MBA
ENA
A0–35
IRA Flag Ti m ing and Fi rst Avail able Write when FIFO1 is Full (FWFT Mo de)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
18
PRELIMINARY
Note:
23. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF A to transition HIGH in the ne xt CLKA cy cle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO1 Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[23]
tDH
tDS
tENH
tENS
Previous Word in FIFO1 Output Register Next Word From FIFO1
CLKB
CSB
W/RB
MBB
ENB
ORB
B0–35
CLKA
IRA
CSA
W/RA
MBA
ENA
A0−35
FFA Flag Timing and First Avail able Write when FIFO1 is Full (CY Standard Mode)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
19
PRELIMINARY
Note:
24. tSKEW1 is the minimum time between a ris ing CLKA edge and a risi ng CLKB edge for IRB to transi tion HIGH in the ne xt CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[24]
tDH
tDS
tENH
tENS
Pr evious Wo r d in FIFO2 O ut put R egist er Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
ORA
A0–35
CLKB
IRB
CSB
W/RB
MBB
ENB
B0–35
IRB Flag Ti ming and Fir st Available Write wh en FIFO2 is Full ( FW FT Mode )
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
20
PRELIMINARY
Note:
25. tSKEW1 is the minimum time between a risi ng CLKA edge and a rising CLKB edge for FFB to transiti on HIG H in the ne xt CLKB c ycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[25]
tDH
tDS
tENH
tENS
P r ev i ous Wo r d in FIFO12 Ou t pu t Regist er Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA
A0–35
CLKB
FFB
CSB
W/RB
MBB
ENB
B0–35
FFB Flag Ti m ing and First A vailable Write when FIFO2 i s Full ( CY Standard Mode)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
21
PRELIMINARY
Notes:
26. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
27. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIF O1, respectively.
28. tSKEW2 is the minimum ti me between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then A EB may transition HIGH one CLKB cycle later than shown.
29. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), F IFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
read from the FIFO.
30. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
31. tSKEW2 is the minimum ti me between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW2, then A EA may transition HIGH one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tPAE
tPAE
tENH
tENS
tSKEW2[28]
tENS tENH
X1 Word in FIFO1 (X1+1)Words in FIFO1
CLKA
ENA
CLKB
AEB
ENB
Timing for AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[26, 27]
tPAE
tPAE
tENH
tENS
tSKEW2[31]
tENS tENH
X2 Word in FIFO2 (X2+1)Words in FIFO2
CLKB
ENB
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[ 29, 30]
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
22
PRELIMINARY
Notes:
32. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LO W), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LO W). Data i n the FIFO1 output register has been
read from the FIFO.
33. D = Maximum FIFO Depth = 256 for the CY7C43622, 512 f or the CY7C43632, 1K f or the CY 7C43642, 4K for the CY7C43662, and 16K for the CY7C43682.
34. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
35. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA c ycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
36. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), F IFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
read from the FIFO.
37. D = Maximum FIFO Depth = 256 for the CY7C43622, 512 f or the CY7C43632, 1K f or the CY 7C43642, 4K for the CY7C43662, and 16K for the CY7C43682.
38. tSKEW2 is the minimum ti me between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW2, then A FB may transition HIGH one CLKA cycle later than shown.
Switching Wavefor ms (continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO1 (D–Y1)Words in FIFO1
tSKEW2[35]
CLKA
ENA
AFA
CLKB
ENB
[32, 33, 34 ]
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y2+1)] Words in FIFO2 (D–Y2)Words in FIFO2
tSKEW2[38]
CLKB
ENB
AFB
CLKA
ENA
Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)[36, 37]
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
23
PRELIMINARY
Switching Wavefor ms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO1 Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB
MBB
ENB
Timing for Mail1 Regi ster and MBF1 Flag (CY Standard and FWFT Modes)
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
24
PRELIMINARY
Notes:
39. Retransmit is performed in the same manner for FIFO2.
40. Clocks are free running in this case.
41. The flags may change state during Retransmit as a resu lt of the offset of the read and write pointers, but flags will be valid at tRTR.
42. For the synchronous PAE and PAF flags (SMODE), a n appr opriate c lock cycle i s neces sary after tRTR to upda te the se flags .
Switching Wavefor ms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail2 Regi ster and MBF2 Flag (CY Standard and FWFT Modes)
FIFO1 Retransmit Timing
ENB
RT1
tPRT tRTR
EFB/FFA
[39, 40, 41 , 42]
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
25
PRELIMINARY
Signal Description
Reset (MR S 1 , MR S 2)
Each of the two FIFO memories of the CY7C436X2 undergoes
a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LO W f or at leas t four P ort A clock (CLKA)
and four Port B clocks (CLKB) LOW-to-HIGH transitions. The
Mast er Reset i nputs can switch asynch ronously t o the clocks.
A Master Reset initializes the internal read and write pointers
and f orces the Full /I nput Ready f lag (FF A/IRA, FFB/I RB) LO W ,
the Empty /Out put Ready fla g (EFA/ORA, EFB/ORB) LOW , the
Almost Empty flag (AEA, AEB) LOW, and the Al most Full flag
(AFA, AFB) HIGH. A Master Rese t also f orces the Mai lbo x flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
aft er tw o cl ock cyc les t o begin normal oper at ion. A Master Re-
set m ust be p erf ormed on the FIFO aft er power up , b efore data
is written to its memory.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) for
choosing the Almost Full and Almost Empty offset program-
ming method (see Almost Empty and Almost Full flag offset
programming below).
First Word Fall Thr ough (FWFT /STD)
Af ter Mast er Res et, the FW FT selec t functio n is acti ve , permi t-
ting a choice between two possible timing modes: CY Stan-
dard Mo de or Firs t Word F a ll Through (FWFT) Mode . Once th e
Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the
FWFT/STAN input during the next LOW-to-HIGH transition of
CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Stan-
dard Mode. This mode uses the Empty Flag function (EFA,
EFB) t o indi ca te wheth er or not there are an y wor ds pres ent i n
the FIFO memory. It uses the Full Flag funct ion (FFA, FFB) to
indicate w hether or not the FIFO memory has any free space
for writing. In CY Standard mode, every word read from the
FIFO, including the first, must be requested using a formal
read operati on.
Onc e the Master Reset ( M RS1 , MRS2) input is HIGH, a LOW
on the FWFT/STAN input during the next LOW-to-HIGH tran-
sition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT Mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the dat a output s ( A0–35 or B0–35). It also uses the Inpu t Ready
function (IRA, IRB) to indicate whether or not the FIFO mem-
ory has any free spac e f or writi ng. In t he FWFT mode , the f irst
word wr itten to an empty FIFO goes directly to data outputs,
no read request necessary. Subsequent words must be ac-
cessed by performing a formal read operation.
Following Master Reset, the level applied to the FWFT/STD
input to choose the desired timing mode must remain static
throughout th e FIFO operatio n.
Programming the A lmost Empty and Almost Full Flags
Four registers in the CY7C436X2 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Por t A Almost Empty flag (AEA) offset register is labeled X2.
The Por t A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset registe r is labe led
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel us-
ing the FIFO’s Port A data in puts (see
Tabl e 1
).
To pro gram t he X1, X2, Y1, and Y2 regis ters from P ort A, per -
form a Master Reset on both FIFOs simultaneously with SPM
HIGH and FS0 and FS1 LOW during the LOW-to-HIGH tran-
siti on of MRS1 and MRS2. After this reset is complete, the first
four writes to FIFO1 do not store data in RAM but load the
offset registers in the order Y1, X1, Y2, X2. The Port A data
inputs used by the offset registers are (A7–0), (A8–0), (A9–0),
(A11–0), or (A 13–0), for the CY7C436X2, respectively. The high-
est numbered input is used as the most significant bit of the
binary number in each case . Valid pr ogr ammi ng va lues for the
regis ters range from 1 to 252 for the CY7C43622; 1 to 508 for
the CY7C43632; 1 to 1012 for the CY7C43642; 1 to 4092 for
the CY7C43662; 1 to 16380 for the CY7C43682. After all the
offset registers are programmed from P ort A, the Port B Full/In-
put Ready (FFB/IRB) is set HIGH and both FIFOs begin nor-
mal operation.
FS0 and FS1 functi on the same wa y in bot h CY Standard and
FWFT modes.
FIFO Write/ Read O peration
The state of the Port A data (A 0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LO W-to-HIGH transit ion of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW , an d FF A/IRA is HI GH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see
Ta bl e 2
).
FIFO reads and wri tes on Port A are independent of an y con-
current Port B operation.
The Port B contr ol signal s are identical to t hose of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Por t A Write/Read select (W/RA). The state of
the Por t B data (B0–35) lines is controlled by the Port B Chip
Select (CSB ) and P ort B Write/Re ad select (W/RB) . The B0–35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B0–35 lines are active outputs
when CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0–35 inputs on a
LO W-to-HIGH transit ion of CLKB when CSB is LOW, W/RB is
LO W, ENB is HIGH, MBB is LO W, and FF B/I RB is HIGH. Data
is read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and EFB/ORB is HIGH (see
Ta b l e 3
).
FIFO reads and wri tes on Port B are independent of an y con-
current Port A operation.
The set-up and hold t ime constraints t o the port cloc ks for the
port Chip Selects and Write/Read selects are only for enabling
write and read operations and are not related to high-imped-
ance cont rol of t he data outp uts. If a port e nable is LOW during
a clock cycle, the port’s Chip Select and Write/Read select
ma y change s tat es during th e set-up and hold time window of
the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag i s LO W, the next word wri tten is automatically sent
to the FIFO’s out put register by the LOW-to -HIGH transit ion of
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
26
PRELIMINARY
the port clock that sets the Output Ready flag HIGH, data re-
sidi ng in th e FIFO’s memory arra y is cl oc ke d t o the ou tput r eg-
ist er onl y when a read i s sel ect ed usin g the port’s Chip Sel ect,
Write/Read select, Enable, and Mailbox select.
When operat ing t he FI FO in CY Stan dard Mode , regardl ess of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Read select, Enable, and Mailbox select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least
two fli p-fl op stage s. Th is i s done t o im prov e flag- signal rel iabil-
ity by reducing the probability of the m etastable events when
CLKA and CLKB operate asynchronously to one another.
EFA/ORA, AEA, FF A/IRA, and AFA are syn chronize d to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to
CLKB.
Table 4
and
Table 5
show the relationship of each port
flag t o FIFO1 and FIFO2.
Empty/Output Ready Flags (EFA/ ORA, EFB/ORB)
These are dual-purp ose flags. In the FW FT M ode, the Output
Ready (ORA, ORB) function is selected. When the Out-
put- Ready flag is HIGH, new d ata is pr esent in the FIFO out put
regi ster . When t he Output r eady flag i s LOW, the pre vious data
word is present in the FIFO output register and attempted
FIFO reads are ignor ed.
In th e CY Stand ard Mode, the Empty Fl ag (EF A , EFB) function
is sel ected . When th e Empty Flag i s HIGH, dat a is availabl e in
the FIFO’s RAM memory for reading to the output register.
When the Empty Flag is LOW, the previous data word is
prese nt in the FI FO output re giste r and attempt ed FI FO reads
are ignored.
The Empty/ Output Ready flag of a FIFO is synchroniz ed to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is increment-
ed each tim e a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer com parator that indicates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, fr om the time a w ord is written to a FI FO, it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output ready flag is LOW if a word in memor y is the
next data to be sent to the FIFO output register and three cy-
cles have not elapse d since the t ime the word was writ ten . The
Output Ready flag of the FIFO remains LOW until the third
LO W-to-HI G H transition of the sync hronizing clock occurs, si -
mu ltaneo usly forc ing t he Out put Ready f lag HIGH and s hift ing
the word to the FIFO output regist er.
In the CY St andard Mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data avail-
able for re ading in a minimum of two cycles of the Empty Flag
synchronizing clock. Therefore, an Empty Flag is LOW if a
w ord in memory is the ne xt data t o be sent to the FI FO output
register and two cycles have not elapsed since the time the
word was written. The Em pty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
cloc k occurs , forcing t he Empty Fl ag HIGH ; onl y then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizi ng clock beg ins the f irst synchroni zation cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the wr ite. Otherwise, the subsequent clock cycle can be
the fi rst synchronization cycle.
Full/ Input Ready Fla gs (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT M ode, the Input Ready
(IRA and I RB) function is selected. In CY Standard M ode, the
Full Flag (FFA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
locat ion i s free in the SRAM to rec eive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FI FO are ignored.
The Ful l/Input Ready flag of a FI FO is synch ronized to the port
cloc k that writes data to i ts arra y . F or both FWFT and CY Stan -
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a
Full/ Input Ready fl ag mo nitor s a write poi nt er and r ead poi nte r
comparator that indicate s when the FI FO SRAM status is full,
full–1, or full–2. From the time a word is read from a FIFO, its
previous memor y location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have el apsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the r ead sets the Ful l/In-
put Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer com parator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X1 for AEB and regi ster X2 for AEA. These register s are load-
ed with preset values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost Empty flag and
Almost Full flag offset pr ogram ming abo v e). An Almost Empty
flag is LOW when its FIFO contains X or less words and is
HIGH when its FIFO contains (X+1) or more words. A data
word present in the FIFO output register has been read from
memory.
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty flag to refl ect the new level of fi ll. Therefore, the Almost
Full flag of a FIFO containing (X+1) or more words remains
LO W i f two cycles of its synchronizing cloc k have not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to t he (X+1) l evel . A LOW- to- HIGH trans it io n of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time tSKEW2 or greater after
the write that fills the FIFO to (X+1) words. Otherwise, the sub-
sequent synchronizing clock cycle may be the first synchroni-
zation cycle.
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
27
PRELIMINARY
Almost Full Flags (AFA, AFB)
The Al mo st Full flag of a FIFO is synchr onized t o the port clock
that writes data t o its array. The st at e machine tha t cont rols a n
Almost F ull flag monito rs a write poi nter and read pointer com-
parator that i ndicates when the FIFO SRAM status is almost
full, almost full–1, or almost full–2. The Almost Full state is
defi ned b y the co ntents of regis ter Y1 for AFA and regi ster Y2
fo r AF B . These registers are loaded with pr eset val ues during
a FIFO reset, programmed from Por t A, or programmed seri-
ally (see Almost Empty flag and Almost Full flag offset pro-
gramming above). An Almost Full flag is LOW when the num-
ber of words in its FIFO is greater than or equal to (256–Y),
(512–Y), (1024–Y), (4096–Y), or (16384–Y) for the
CY7C436X2 respectively. An Almost Full flag is HIGH when
the number of words in its FIFO is less than or equal to
[256–(Y+1)], [512–(Y+1)], [1024–(Y+1)], [4096–(Y+1)], or
[16384–(Y+1)], for the CY7C436X2 respectively. Note that a
data word present in the FIFO output register has been read
from memory.
Two LOW-to-HI G H transitions of the Alm ost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [256/512/1024/4096/16384–(Y+1)]
or less words remains LOW if two cycles of its synchronizing
cloc k hav e not el apsed sinc e the read that reduced the n umber
of words in memo ry to [256/512/1024/4096/16384–(Y+1)]. An
Almost Full f lag i s set HIGH b y the seco nd LO W -t o-HIGH t r an-
sit ion of its sy nchroni zing c loc k af ter t he FIF O rea d that re duc-
es the number of words in memory to
[256/512/1024/4096/16384–(Y+1)]. A LOW-to-HIGH transition
of an Almost Full fl ag synchronizing clock begins t he firs t syn-
chr oni zation cyc le if it o ccur s at time tSKEW2 or greate r after
the read that reduces the number of words in memory to
[256/512/1024/4096/16384–(Y+1)]. Otherwise, the subse-
quent synchronizing cl ock cycle may be the first synchr oniza-
tion cycle.
Mailbox Registers
Each FI FO ha s a 36-bit byp ass regist er t o pas s com mand an d
control infor mation between Por t A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of b oth the Mail1 and Mail2 r egis-
ters matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0−35 data to the
Mail 1 Regist er when a Port A write is select ed b y CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register em-
plo ys data li nes A0−35. If the s elected P ort A bus siz e is 18 bits ,
then t he us abl e width of the Mai l1 Re gister em plo ys data lines
A0−17. (I n th is case , A18−35 are don’ t car e i nputs .) If the sel ect-
ed Po rt A bus size is 9 bits, then the usable wi dth of the Mai l1
Regis ter emplo ys data lin es B0−8. (In this case, A9−35 are don’t
care i nputs.)
A LOW-to-HIGH transition on CLKB writes B0–35 data to the
Mail2 Regi ster wh en a Port B write is se lected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
plo ys data li nes B0–35. If th e selected P ort B bus siz e is 18 bit s,
then th e usab le wi dth of the M ail 2 Regist er emp lo ys data l ines
B0–17. (In this case, B18–35 ar e don’t care i nputs .) I f the s elect -
ed Port B bus size is 9 bit s, then t he usable width of the Mail2
Regist er empl oys data lines B0−8. (In this case, B9−35 are don’t
care inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is se-
l ec ted by CS B, W/RB, and ENB with MBB HIGH. For a 36-bit
bus size, 36 bits of mailbox data are placed on B0–35. For an
18-bit bus siz e, 18 bits of ma ilbox data ar e placed on B0–17. (In
this case , B18–35 are ind ete rminat e.) F or a 9-bit b us size , 9 bits
of mailbox data are placed on B0–8. (In this case, B9–35 are
indeterminate.)
The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by CSA,
W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are placed
on A0–17. (In this case, A18–35 are indeterminate.) For a 9-bit
bus size, 9 bits of mailbox data are placed on A0–8. (In this
case, A9–35 are indeter minate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Sel ect feature has no effect on the mailb ox data.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferr ing packets
of data. It enabl es the receipt of data to be acknowledged by
the recei ver and ret ransmitted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at l east one word has be en read si nce the l ast rese t
cycle . A LO W pu ls e on R T1, RT2 resets the internal read point-
er to the first physical location of the FIFO. CLKA and CLKB
ma y be free runni ng but must be disabl ed during an d tRTR after
the retransmit pul se. With every v alid read cycle after retrans-
mit, previously accessed data is read and the read pointer is
incremented until it is equal to the write pointer . Flags are gov-
er ned by the rel ative locations of the read and write pointers
and are updated duri ng a retran sm it cycle . Data written to the
FIFO after activation of RT1, RT2 are tr ansm itted also.
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
28
PRELIMINARY
Table 1. Flag Programming
FS1 FS0 MRS1 MRS2 X1 and Y1 Register s [43] X2 and Y2 Registers[44]
H H ↑X64 X
H H X ↑X64
H L ↑X16 X
H L X ↑X16
L H ↑X 8 X
L H X ↑X 8
L L ↑ ↑ Programming via Port A Programming via Port A
Table 2. Po rt A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Outputs Port Function
H X X X X In high-im pedance state None
L H L X X In hi gh-i m pedance state None
LHHL↑In hi gh-impedance state FIFO1 write
LHHH↑In hi gh-i m pedance state Mail1 writ e
L L L L X Active, FIFO2 output register None
LL HL↑Active, FIF O2 output register FIFO2 read
L L L H X Active, mail2 register None
LL HH↑Active, mail2 register Mail2 read (set MBF2 HIGH)
Table 3. P ort B Enabl e Function
CSB W/RB ENB MBB CLKB B0–35 Outputs Port Function
H X X X X In high-impeda nce state None
L L L X X In high-im pedance state None
LLHL↑In high-impedance state FIFO2 write
LL HH↑In high-i mpedance state Mail2 write
L H L L X Active, FIFO1 output reg ister None
LH HL↑A c t ive, FI FO1 o utp ut re gist e r FIFO1 re ad
L H L H X Active, mail1 register None
LH HH↑Active, mail1 register Mail1 read (set MBF1 HIGH)
Notes:
43. X1 register holds the offset for AEB; Y1 register hol d s the offset for AFA.
44. X2 register holds the offset for AEA; Y2 register hol d s the offset for AFB.
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
29
PRELIMINARY
Notes:
45. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or
port A programming.
46. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
47. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the
output register (no read operation necessary), it is not included in the FIFO memory count.
48. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.
49. X2 is the almost-empty offset f o r FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or
port A programming.
Table 4. FIFO1 Flag Operat ion ( C Y Standard and FWFT modes)
Number of Words in FIFO Memory[45,46,47,48] Synchronized to
CLKB Synchronized to
CLKA
CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 EFB/ORB AEB AFA FFA/IRA
0 0 0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to
[256–(Y1+1)] (X1+1) to
[512–(Y1+1)] (X1+ 1) to
[1024–(Y1+1)] (X1+1) to
[4096–(Y1+1)] (X1+1) to
[16384–(Y1+1)] H H H H
(256–Y1) to
255 (512–Y1) to
511 (1024–Y1) to
1023 (4096–Y1) to
4095 (16384–Y1) to
16383 H H L H
256 512 1024 4096 16384 H H L L
Table 5. FIFO2 Flag Operation (CY Standard and FWFT m odes)
Number of Words in FIFO Memory[46,47,48,49] Synchroni zed to
CLKA Synchronized to
CLKB
CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 EFA/ORA AEA AFB FFB/IRB
00 0 0 0LLHH
1 TO X2 1 TO X2 1 T O X2 1 T O X2 1 TO X2 H L H H
(X2+1) to
[256–(Y2+1)] (X2+1) to
[512–(Y2+1)] (X2+1) to
[1024–(Y2+1)] (X2+1) to
[4096–(Y2+1)] (X2+1) to
[16384–(Y2+)1] HHHH
(256–Y2) to
255 (512–Y2) to
511 (1024–Y2) to
1023 (4096–Y2) to
4095 (16384–Y2) to
16383 HHL H
256 512 1024 4096 16384 H H L L
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
30
PRELIMINARY
512 x36 x2 Bidirectional Synchronous FI FO
1K x36 x2 Bidir ectional Sync hronous FIFO
4K x36 x2 Bidir ectional Sync hronous FIFO
16K x36 x2 Bidirectional Synchronous FIFO
Document #: 38-00698
256 x36 x2 Bidirectional Synchronous FIFO
Speed
(ns) O rd e ring C o de Package
Name Package
Type Operating
Range
12 CY7C43622–12AC A120 120-Lead Thin Quad Flat Package Commercial
12 CY7C43622–12AI A120 120-Lead Thin Quad Flat Package Industrial
15 CY7C43622–15A C A120 120-Lead Thin Quad Flat Package Commercial
Speed
( ns ) O r d e ring C o de Package
Name Package
Type Operating
Range
12 CY7C43632–12AC A120 120-Lead Thin Quad Flat Package Commercial
12 CY7C43632–12AI A120 120-Lead Thi n Q uad Flat Package Industrial
15 CY7C43632–15AC A120 120-Lead Thin Quad Flat Package Commercial
Speed
( ns ) O r d e ring C o de Package
Name Package
Type Operating
Range
12 CY7C43642–12AC A120 120-Lead Thin Quad Flat Package Commercial
12 CY7C43642–12AI A120 120-Lead Thi n Q uad Flat Package Industrial
15 CY7C43642–15AC A120 120-Lead Thin Quad Flat Package Commercial
Speed
( ns ) O r d e ring C o de Package
Name Package
Type Operating
Range
12 CY7C43662–12AC A120 120-Lead Thin Quad Flat Package Commercial
12 CY7C43662–12AI A120 120-Lead Thi n Q uad Flat Package Industrial
15 CY7C43662–15AC A120 120-Lead Thin Quad Flat Package Commercial
Speed
( ns ) O r d e ring C o de Package
Name Package
Type Operating
Range
12 CY7C43682–12AC A120 120-Lead Thin Quad Flat Package Commercial
12 CY7C43682–12AI A120 120-Lead Thi n Q uad Flat Package Industrial
15 CY7C43682–15AC A120 120-Lead Thin Quad Flat Package Commercial
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
PRELIMINARY
© Cypress Semiconductor Cor poration, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circu itry embodied i n a Cypress Sem ic onductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authoriz e
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems applicati on implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
1998
Package Di ag r am
120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120
51-85100
