CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO * Fully asynchronous and simultaneous read and write operation permitted * Mailbox bypass register for each FIFO * Parallel Programmable Almost-Full and Almost-Empty flags * Retransmit function * Standard or FWFT mode user selectable * 120-pin TQFP packaging * Pin-compatible, feature enhanced, density upgrade to IDT723622/32/42 family * Easily expandable in width and depth Features * High-speed, low-power, bidirectional, first-in first-out (FIFO) memories * 256x36x2 (CY7C43622) * 512x36x2 (CY7C43632) * 1Kx36x2 (CY7C43642) * 4Kx36x2 (CY7C43662) * 16Kx36x2 (CY7C43682) * 0.35-micron CMOS for optimum speed/power * High speed 83-MHz operation (12 ns read/write cycle times) * Low power -- ICC= 100 mA -- ISB= 5 mA Logic Block Diagram MBF1 CLKA Port-A Control Logic MBA RT2 MRS1 PRS1 256/512/1K 4K/16K x36 Dual Ported Memory Input Register ENA FIFO1, Mail 1 Reset Logic Write Pointer FFA/IRA Output W/RA Register Mail 1 Register CSA Port-B Control Logic Read Pointer Status Flag Logic AFA SPM FS0/SD FS1/SEN CLKB CSB W/RB ENB MBB RT1 Programmable Flag Offset Registers EFB/ORB AEB B0-35 Timing Mode FWFT/STAN A0-35 Status Flag Logic AEA Read Pointer Write Pointer Output Register FFB/IRB AFB FIFO2, Mail 2 Reset Logic Input Register EFA/ORA 256/512/1K 4K/16K x36 Dual Ported Memory MRS2 PRS2 Mail 2 Register MBF2 Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 September 14, 1998 PRELIMINARY Pin Configuration RST2 MBB MBF1 VCC 104 103 102 101 100 99 98 97 96 95 94 93 92 91 CSA EFA/IRA FFA/ORA VCC AFA AEA MBF2 MBA RST1 FS0 GND FS1 CY7C43662 CY7C43682 2 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 B4 B5 GND B6 VCC B7 B8 B9 B10 B11 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A12 CY7C43642 B0 B1 B2 B3 A18 GND A17 A16 A15 A14 A13 RT2 CY7C43632 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND FWFT/STAN A22 VCC A21 A20 A19 CY7C43622 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 GND A29 A28 A27 A26 A25 B24 A23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND A11 A10 A9 A35 A34 A33 A32 VCC A31 A30 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 GND CLKA ENA W/RA TQFP Top View AEB AFB FFB/ORB EFB/IRB GND CSB W/RB ENB CLKB VCC CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 RT1 B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the CY Standard Mode. EF indicates whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through Mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Functional Description The CY7C436X2 is a monolithic, high-speed, low-power, CMOS Bidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 9 ns. Two independent 256/512/1K/4K/16K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The CY7C436X2 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Each FIFO has a programmable Almost Empty flag (AEA and AEB) and a programmable Almost Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words written to FIFO memory achieve a predetermined "almost empty state." AFA and AFB indicate when a selected number of words written to the memory achieve a predetermined "almost full state." Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers' width matches the selected Port B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. IRA, IRB, AFA, and AFB are synchronized to the port clock that writes data into its array. ORA, ORB, AEA, and AEB are synchronized to the port clock that reads data from its array. Programmable offset for AEA, AEB, AFA, and AFB are loaded in parallel using Port A or in serial via the SD input. Three default offset settings are also provided. The AEA and AEB threshold can be set at 8, 16, or 64 locations from the empty boundary and AFA and AFB threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Master Reset initializes the read and write pointers to the first location of the memory array, and selects parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or 64. Each FIFO has its own independent Master Reset pin, MRS1 and MRS2. The CY7C436X2 have two modes of operation: In the CY Standard Mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through Mode (FWFT), the first word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT/STAN pin during FIFO operation determines the mode in use. Two or more devices may be used in parallel to create wider data paths. If at any time the FIFO is not actively performing a function, the chip will automatically power down. During the power-down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the power-down state. The CY7C436X2 are characterized for operation from 0C to 70C. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Selection Guide CY7C43622/32/42/62/82-12 CY7C43622/32/42/62/82-15 83 66.7 Maximum Access Time (ns) 9 10 Minimum Cycle Time (ns) 12 15 Minimum Data or Enable Set-Up (ns) 4 5 Minimum Data or Enable Hold (ns) 0 0 Maximum Frequency (MHz) Maximum Flag Delay (ns) Active Power Supply Current (ICC1 ) (mA) 8 8 Commercial 100 100 Industrial 100 100 CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 Density 256 x 36 512 x 36 1K x 36 4K x 36 16K x 36 Package 120 TQFP 120 TQFP 120 TQFP 120 TQFP 120 TQFP 3 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Pin Definitions Signal Name Description I/O Function A0-35 Port A Data I/O 36-bit bidirectional data port for side A AEA Port A Almost Empty Flag O Programmable almost-empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the almost-empty A offset register, X2. AEB Port B Almost Empty Flag O Programmable almost-empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the almost-empty B offset register, X1. AFA Port A Almost Full Flag O Programmable almost-full flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the almost-full A offset register, Y1. AFB Port B Almost Full Flag O Programmable almost-full flag synchronized to CLKB. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the almost-full B offset register, Y2. I/O B0-35 Port B Data FWFT/STAN Big Endian/First Word Fall Through Select I During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT/STAN must be static throughout device operation. CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all synchronized to the LOW-to-HIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on Port A. The A0-35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on Port B. The B0-35 outputs are in the high-impedance state when CSB is HIGH. EFA/ORA Port A Empty/ Output Ready Flag O This is a dual-function pin. In the CY Standard Mode, the EFA function is selected. EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A 0-35 outputs, available for reading. FFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. EFB/ORB Port B Empty/ Output Ready Flag O This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on B 0-35 outputs, available for reading. FFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. FFA/IRA Port A Full/Input Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA. FFB/IRB Port B Full/Input Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FFB function is selected. FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB. 36-bit bidirectional data port for side B. 4 PRELIMINARY CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 Pin Definitions (continued) Signal Name Description I/O Function FS1 and FS0 are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1 and FS0, together with SPM, select the flag offset programming method. Three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from Port A, and serial load. When serial load is selected for flag offset register programming, FS1 is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1 is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32 for the CY7C43622, 36 for the CY7C43632, 40 for the CY7C43642, 48 for the CY7C43662, and 56 for the CY7C43682. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. FS1 Flag Offset Select 1 I FS0 Flag Offset Select 0 I MBA Port A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-35 outputs are active, a HIGH level on MBA selects data from the Mail2 register for output and a LOW level selects FIFO2 output register data for output. MBB Port B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-35 outputs are active, a HIGH level on MBB selects data from the Mail1 register for output and a LOW level selects FIFO1 output register data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1 register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1. MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2. MRS1 FIFO1 Master Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects the programming method (serial or parallel) and one of three programmable flag default offsets for FIFO1. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW. MRS2 FIFO2 Master Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW. W/RA Port A Write/ Read Select I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0-35 outputs are in the HIGH impedance state when W/RA is HIGH. W/RB Port B Write/ Read Select I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of CLKB. The B0-35 outputs are in the HIGH impedance state when W/RB is LOW. 5 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Maximum Ratings[1] Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current ...................................................... >200mA Storage Temperature ....................................... -65C to +150C Operating Range Ambient Temperature with Power Applied .................................................... -55C to +125C Supply Voltage to Ground Potential..................-0.5V to +7.0V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State[2] ..........................................-0.5V to VCC+0.5V DC Input Voltage[2] ........................................-0.5V to VCC+0.5V Commercial 0C to +70C 5.0V 0.5V -40C to +85C 5.0V 0.5V Industrial Output Current into Outputs (LOW) ............................. 20 mA Electrical Characteristics Over the Operating Range CY7C43622/32/42/62/82 Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = 4.5V, IOH = -4.0 mA VOL Output LOW Voltage VCC = 4.5V, IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage -0.5 0.8 V IIX Input Leakage Current VCC = Max. -10 +10 A IOZL IOZH Output OFF, High Z Current OE > VIH, VSS < VO< VCC -10 +10 A ICC1[3] Active Power Supply Current Com'l 400 mA Ind 400 mA Average Standby Current Com'l 5 mA Ind 5 mA ISB[4] 2.4 V 2.0 0.4 V VCC V Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. Unit 4 pF 8 pF Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operationg conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC. 4. All inputs = VCC - 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded. 5. Tested initially and after any design or process changes that may affect these parameters. 6 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY AC Test Loads and Waveforms R1=1.1K ALL INPUT PULSES 5V OUTPUT 3.0V CL=30 pF R2=680 GND 3 ns INCLUDING JIG AND SCOPE Equivalent to: 90% 10% 90% 10% THEVENIN EQUIVALENT 410 OUTPUT 3 ns 1.910V Switching Characteristics Over the Operating Range CY7C43622/32/42/62/82 -12 Parameter Description Min. Max. CY7C43622/32/42/62/82 -15 Min. 83 Max. Unit 67 MHz fS Clock Frequency, CLKA or CLKB tCLK Clock Cycle Time, CLKA or CLKB 12 15 ns tCLKH Pulse Duration, CLKA or CLKB HIGH 5 6 ns tCLKL Pulse Duration, CLKA or CLKB LOW 5 6 ns tDS Set-Up Time, A 0-35 before CLKA and B 0-35 before CLKB 4 5 ns tENS Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA; CSB, W/RB, ENB, and MBB before CLKB 4 5 ns tRSTS Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA or CLKB[6] 4 5 ns tFSS Set-Up Time, FS0 and FS1 before MRS1 and MRS2 HIGH 7 7.5 ns tBES Set-Up Time, FWFT/STAN before MRS1 and MRS2 HIGH 7 7.5 ns tSDS Set-Up Time, FS0 before CLKA 4 5 ns tSENS Set-Up Time, FS1 before CLKA 4 5 ns tFWS Set-Up Time, FWFT before CLKA 0 0 ns tDH Hold Time, A0-35 after CLKA and B0-35 after CLKB 0 0 ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and MBB after CLKB 0 0 ns tRSTH Hold Time, MRS1, MRS2, PRS1, or PRS2 LOW after CLKA or CLKB[6] 4 4 ns tFSH Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH 2 2 ns tBEH Hold Time, FWFT/STAN after MRS1 and MRS2 HIGH 2 2 ns Note: 6. Requirement to count the clock edge as one of at least four needed to reset a FIFO 7 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Characteristics Over the Operating Range (continued) CY7C43622/32/42/62/82 -12 Parameter Description Min. Max. CY7C43622/32/42/62/82 -15 Min. Max. Unit tSDH Hold Time, FS0 after CLKA 0 0 ns tSENH Hold Time, FS1 after CLKA 0 0 ns tSPH Hold Time, FS1 HIGH after MRS1 and MRS2 HIGH 2 2 ns tSKEW1[7] Skew Time between CLKA and CLKB for EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB 6 7.5 ns tSKEW2[7] Skew Time between CLKA and CLKB for AEA, AEB, AFA, AFB 10 12 ns Access Time, CLKA to A0-35 and CLKB to B0-35 1 9 3 10 ns tWFF Propagation Delay Time, CLKA to FFA/IRA and CLKB to FFB/IRB 1 8 2 8 ns tREF Propagation Delay Time, CLKA to EFA/ORA and CLKB to EFB/ORB 1 8 1 8 ns tPAE Propagation Delay Time, CLKA to AEA and CLKB to AEB 1 8 1 8 ns tPAF Propagation Delay Time, CLKA to AFA and CLKB to AFB 1 8 1 8 ns tPMF Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH 0 9 0 12 ns tPMR Propagation Delay Time, CLKA to B 0-35[8] and CLKB to A0-35[9] 2 11 3 12 ns tMDV Propagation Delay Time, MBA to A0-35 valid and MBB to B0-35 valid 2 10 3 11 ns tRSF Propagation Delay Time, MRS1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH 1 12 1 15 ns tEN Enable Time, CSA or W/RA LOW to A0-35 Active and CSB LOW and W/RB HIGH to B0-35 Active 2 10 2 10 ns tDIS Disable Time, CSA or W/RA HIGH to A0-35 at high impedance and CSB HIGH or W/RB LOW to B0-35 at HIGH impedance 1 7 1 8 ns tA Notes: 7. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle. 8. Writing data to the mail1 register when the B0-35 outputs are active and MBB is HIGH. 9. Writing data to the mail2 register when the A0-35 outputs are active and MBA is HIGH. 8 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight [10] CLKA CLKB t RSTS tRSTS MRS1 tBES tBEH tFSS t FSH t FWS FWFT/STAN FS1, FS0 tRSF tWFF FFA/IRA t RSF EFB/ORB tRSF AEB tRSF AFA tRSF MBF1 Note: 10. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value. 9 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (CY Standard and FWFT Modes) [11] CLKA MRS1 MRS2 tFSS tFSH FS1 FS0 tWFF FFA/IRA t ENH tENS tSKEW1 [12] ENA tDS tDH A0-35 AFA Offset (Y1) AEB Offset (X1) AFB Offset (Y2) AEA Offset (X2) First Word to FIFO1 CLKB FFB/IRB Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes) tCLK tCLKH tCLKL CLKA FFA/IRA HIGH tENS tENH CSA tENS tENH W/RA tENS tENH tENS tENH tDS tDH MBA tENS tENH tENS tENH ENA A0-35 [13] W1 W2 [13] Notes: 11. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. 12. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown. 13. Written to FIFO1. 10 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) Port B Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes) tCLK tCLKH t CLKL CLKB FFB/IRB HIGH tENS tENH CSB tENS tENH W/RB tENS tENH tENS tENH tDS tDH MBB tENS tENH tENH tENS ENB B0-35 W1 [14] W2 [14] Port B Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes) tCLK tCLKH tCLKL CLKB EFB/ORB CSB W/RB MBB tENS tENH tENS tENH t ENS tEN ENB B0-35 (Standard Mode) OR B0-35 (FWFT Mode) t EN tMDV tA tA [15] W1 Previous Data tEN t MDV No Operation W2 tDIS tA tA [15] W2 [15] W1 Notes: 14. Written to FIFO2. 15. Read from FIFO1. 11 tDIS [15] W3 [15] CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes) tCLK t CLKH tCLKL CLKA FFA/ORA CSA W/RA MBA tENS tENH tENS tENH tENS tENH ENA A0-35 (Standard Mode) OR A0-35 (FWFT Mode) tEN tA tMDV tA W1 [16] Previous Data tEN tMDV No Operation W2 tDIS tA tA W2[16] W1[16] Note: 16. Read From FIFO2. 12 tDIS [16] W3[16] CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode) tCLK tCLKH tCLKL CLKA CSA LOW W/RA HIGH tENS tEN MBA t ENS tEN ENA IRA HIGH t DS tDH A0-35 W1 tSKEW[17] CLKB tCLKH tCLKL tREF tCLK ORB CSB tREF FIFO1 Empty LOW W/RB HIGH MBB LOW tENS tENH ENB tA B0-35 W1 Old Data in FIFO1 Output Register Note: 17. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1 , then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB cycle later than shown. 13 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (CY Standard Mode) tCLK tCLKH t CLKL CLKA CSA LOW W/RA HIGH tENS tENH MBA tENS tENH ENA FFA HIGH tDS tDH A0-35 W1 tSKEW1[18] tCLKH tCLKL CLKB tCLK EFB FIFO1 Empty CSB LOW W/RB HIGH MBB LOW tREF tREF t ENS tENH ENB tA B0-35 W1 Note: 18. ttSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1 , then the transition of EFB HIGH may occur one CLKB cycle later than shown. 14 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty [19] (FWFT Mode) tCLK tCLKH tCLKL CLKB CSB LOW W/RB LOW tENS tENH MBB tENSt ENH ENB IRB HIGH tDS tDH B0-35 W1 [20] tSKEW1 tCLKH tCLKL CLKA tREF tCLK ORA FIFO2 Empty CSA LOW W/RA LOW MBA LOW tREF tENStENH ENA tA A0-35 W1 Old Data in FIFO2 Output Register Notes: 19. tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. 20. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1 , then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA cycle later than shown. 15 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode) tCLK t CLKH tCLKL CLKB CSB LOW W/RB LOW tENS tENH MBB tENS tENH ENB FFB HIGH tDS tDH B0-35 W1 tSKEW1[21] tCLKH tCLKL CLKA tCLK EFA FIFO2 Empty CSA LOW W/RA LOW MBA LOW tREF t REF tENStENH ENA tA A0-35 W1 Note: 21. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. 16 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode) tCLK tCLKH tCLKL CLKB CSB LOW W/RB HIGH MBB tENS tENH ENB ORB HIGH tA B0-35 Previous Word in FIFO1 Output Register tSKEW1 Next Word From FIFO1 [22] tCLKH tCLKL CLKA tCLK IRA FIFO1 Full CSA LOW W/RA HIGH tWFF tWFF t ENS tENH MBA tENS tENH ENA tDS tDH A0-35 To FIFO1 Note: 22. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown. 17 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode) tCLK tCLKH tCLKL CLKB CSB LOW W/RB HIGH MBB tENS tENH ENB ORB HIGH tA B0-35 Previous Word in FIFO1 Output Register tSKEW1[23] Next Word From FIFO1 tCLKH tCLKL CLKA tCLK IRA FIFO1 Full CSA LOW W/RA HIGH tWFF t WFF tENS tENH MBA t ENS tENH ENA tDS tDH A0-35 Note: 23. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown. 18 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode) tCLK t CLKH tCLKL CLKA CSA LOW W/RA LOW MBA LOW tENS tENH ENA ORA HIGH tA A0-35 Previous Word in FIFO2 Output Register tSKEW1[24] Next Word From FIFO2 tCLKH tCLKL CLKB tCLK IRB FIFO2 Full CSB LOW W/RB LOW tWFF tWFF tENS tENH MBB tENS tENH ENB tDS tDH B0-35 To FIFO2 Note: 24. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown. 19 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode) t CLK tCLKH tCLKL CLKA CSA LOW W/RA LOW MBA LOW tENSt ENH ENA EFA HIGH tA A0-35 Previous Word in FIFO12 Output Register tSKEW1 [25] Next Word From FIFO2 tCLKH tCLKL CLKB tCLK FFB FIFO2 Full CSB LOW W/RB LOW tWFF tWFF tENS tENH MBB tENS tENH ENB tDS tDH B0-35 To FIFO2 Note: 25. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown. 20 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) Timing for AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes) [26, 27] CLKA tENS tENH ENA tSKEW2[28] CLKB tPAE tPAE AEB (X1+1)Words in FIFO1 X1 Word in FIFO1 t ENS tENH ENB Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes) [29, 30] CLKB tENS tENH ENB tSKEW2 [31] CLKA tPAE tPAE AEA (X2+1)Words in FIFO2 tENS X2 Word in FIFO2 tENH ENA Notes: 26. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 27. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively. 28. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2 , then AEB may transition HIGH one CLKB cycle later than shown. 29. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 30. If Port B size is word or byte, t SKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. 31. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2 , then AEA may transition HIGH one CLKA cycle later than shown. 21 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes) [32, 33, 34] tSKEW2[35] CLKA tENS tENH ENA tPAF AFA [D-(Y1+1)] Words in FIFO1 t PAF (D-Y1)Words in FIFO1 CLKB tENH tENS ENB Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes) [36, 37] tSKEW2 [38] CLKB tENS tENH ENB tPAF AFB [D-(Y2+1)] Words in FIFO2 tPAF (D-Y2)Words in FIFO2 CLKA tENH tENS ENA Notes: 32. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 33. D = Maximum FIFO Depth = 256 for the CY7C43622, 512 for the CY7C43632, 1K for the CY7C43642, 4K for the CY7C43662, and 16K for the CY7C43682. 34. If Port B size is word or byte, t SKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. 35. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown. 36. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 37. D = Maximum FIFO Depth = 256 for the CY7C43622, 512 for the CY7C43632, 1K for the CY7C43642, 4K for the CY7C43662, and 16K for the CY7C43682. 38. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2 , then AFB may transition HIGH one CLKA cycle later than shown. 22 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) CLKA tENS tENH CSA tENS t ENH tENS tENH tENS t ENH tDS tDH W/RA MBA ENA A0-35 W1 CLKB tPMF tPMF MBF1 CSB W/RB MBB tENS tENH ENB t EN tMDV tPMR FIFO1 Output Register tDIS W1 (Remains valid in Mail1 Register after read) 23 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Switching Waveforms (continued) Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) CLKB tENS tENH tENS tENH t ENS tENH tENS tENH tDS t DH CSB W/RB MBB ENB B0-35 W1 CLKA tPMF tPMF MBF2 CSA W/RA MBA tENS tENH ENA tMDV tEN A0-35 FIFO1 Retransmit Timing tPMR tDIS FIFO2 Output Register W1 (Remains valid in Mail2 Register after read) [39, 40, 41, 42] RT1 tPRT tRTR ENB EFB/FFA Notes: 39. Retransmit is performed in the same manner for FIFO2. 40. Clocks are free running in this case. 41. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 42. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. 24 PRELIMINARY CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 Signal Description values during the reset of a FIFO, programmed in parallel using the FIFO's Port A data inputs (see Table 1). Reset (MRS1, MRS2) To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the offset registers are (A7-0), (A 8-0), (A9-0), (A11-0), or (A13-0), for the CY7C436X2, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 252 for the CY7C43622; 1 to 508 for the CY7C43632; 1 to 1012 for the CY7C43642; 1 to 4092 for the CY7C43662; 1 to 16380 for the CY7C43682. After all the offset registers are programmed from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH and both FIFOs begin normal operation. Each of the two FIFO memories of the CY7C436X2 undergoes a complete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A clock (CLKA) and four Port B clocks (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can switch asynchronously to the clocks. A Master Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master Reset must be performed on the FIFO after power up, before data is written to its memory. A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2) input latches the values of the Flag select (FS0, FS1) for choosing the Almost Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset programming below). FS0 and FS1 function the same way in both CY Standard and FWFT modes. FIFO Write/Read Operation The state of the Port A data (A 0-35) lines is controlled by Port A Chip Select (CSA) and Port A Write/Read Select (W/RA). The A 0-35 lines are in the high-impedance state when either CSA or W/RA is HIGH. The A0-35 lines are active outputs when both CSA and W/RA are LOW. First Word Fall Through (FWFT/STD) After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: CY Standard Mode or First Word Fall Through (FWFT) Mode. Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the FWFT/STAN input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Standard Mode. This mode uses the Empty Flag function (EFA, EFB) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function (FFA, FFB) to indicate whether or not the FIFO memory has any free space for writing. In CY Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. Data is loaded into FIFO1 from the A0-35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A 0-35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and writes on Port A are independent of any concurrent Port B operation. The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read select (W/RA). The state of the Port B data (B0-35) lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-35 lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-35 lines are active outputs when CSB is LOW and W/RB is HIGH. Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the FWFT/STAN input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT Mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A 0-35 or B0-35). It also uses the Input Ready function (IRA, IRB) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Data is loaded into FIFO2 from the B0-35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B 0-35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and writes on Port B are independent of any concurrent Port A operation. Following Master Reset, the level applied to the FWFT/STD input to choose the desired timing mode must remain static throughout the FIFO operation. The set-up and hold time constraints to the port clocks for the port Chip Selects and Write/Read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port's Chip Select and Write/Read select may change states during the set-up and hold time window of the cycle. Programming the Almost Empty and Almost Full Flags Four registers in the CY7C436X2 are used to hold the offset values for the Almost Empty and Almost Full flags. The Port B Almost Empty flag (AEB) offset register is labeled X1 and the Port A Almost Empty flag (AEA) offset register is labeled X2. The Port A Almost Full flag (AFA) offset register is labeled Y1 and the Port B Almost Full flag (AFB) offset register is labeled Y2. The index of each register name corresponds with preset When operating the FIFO in FWFT Mode and the Output Ready flag is LOW, the next word written is automatically sent to the FIFO's output register by the LOW-to-HIGH transition of 25 PRELIMINARY CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle. the port clock that sets the Output Ready flag HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/Read select, Enable, and Mailbox select. Full/Input Ready Flags (FFA/IRA, FFB/IRB) When operating the FIFO in CY Standard Mode, regardless of whether the Empty Flag is LOW or HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/Read select, Enable, and Mailbox select. This is a dual-purpose flag. In FWFT Mode, the Input Ready (IRA and IRB) function is selected. In CY Standard Mode, the Full Flag (FFA and FFB) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. Synchronized FIFO Flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Table 4 and Table 5 show the relationship of each port flag to FIFO1 and FIFO2. The Full/Input Ready flag of a FIFO is synchronized to the port clock that writes data to its array. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls a Full/Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input Ready flag HIGH. Empty/Output Ready Flags (EFA/ORA, EFB/ORB) These are dual-purpose flags. In the FWFT Mode, the Output Ready (ORA, ORB) function is selected. When the Output-Ready flag is HIGH, new data is present in the FIFO output register. When the Output ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle. In the CY Standard Mode, the Empty Flag (EFA, EFB) function is selected. When the Empty Flag is HIGH, data is available in the FIFO's RAM memory for reading to the output register. When the Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. Almost Empty Flags (AEA, AEB) The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. In FWFT Mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. In the CY Standard Mode, from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then can data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a 26 PRELIMINARY Almost Full Flags (AFA, AFB) CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 A LOW-to-HIGH transition on CLKB writes B0-35 data to the Mail2 Register when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If the selected Port B bus size is also 36 bits, then the usable width of the Mail2 Register employs data lines B0-35. If the selected Port B bus size is 18 bits, then the usable width of the Mail2 Register employs data lines B0-17. (In this case, B18-35 are don't care inputs.) If the selected Port B bus size is 9 bits, then the usable width of the Mail2 Register employs data lines B 0-8. (In this case, B9-35 are don't care inputs.) The Almost Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The Almost Full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (256-Y), (512-Y), (1024-Y), (4096-Y), or (16384-Y) for the CY7C436X2 respectively. An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], [1024-(Y+1)], [4096-(Y+1)], or [16384-(Y+1)], for the CY7C436X2 respectively. Note that a data word present in the FIFO output register has been read from memory. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on B0-17. (In this case, B18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on B 0-8. (In this case, B9-35 are indeterminate.) Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [256/512/1024/4096/16384-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [256/512/1024/4096/16384-(Y+1)]. An Almost Full flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [256/512/1024/4096/16384-(Y+1)]. A LOW-to-HIGH transition of an Almost Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [256/512/1024/4096/16384-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on A0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on A0-17. (In this case, A18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on A0-8. (In this case, A9-35 are indeterminate.) The data in a mail register remains intact after it is read and changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data. Mailbox Registers Retransmit (RT1, RT2) Each FIFO has a 36-bit bypass register to pass command and control information between Port A and Port B without putting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port B. The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last reset cycle. A LOW pulse on RT1, RT2 resets the internal read pointer to the first physical location of the FIFO. CLKA and CLKB may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT1, RT2 are transmitted also. A LOW-to-HIGH transition on CLKA writes A0-35 data to the Mail1 Register when a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the selected Port A bus size is also 36 bits, then the usable width of the Mail1 Register employs data lines A 0-35. If the selected Port A bus size is 18 bits, then the usable width of the Mail1 Register employs data lines A0-17. (In this case, A18-35 are don't care inputs.) If the selected Port A bus size is 9 bits, then the usable width of the Mail1 Register employs data lines B 0-8. (In this case, A9-35 are don't care inputs.) 27 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Table 1. Flag Programming FS1 FS0 MRS1 MRS2 X1 and Y1 Registers[43] X2 and Y2 Registers[44] H H X 64 X H H X X 64 H L X 16 X H L X X 16 L H X 8 X L H X X 8 L L Programming via Port A Programming via Port A Table 2. Port A Enable Function CSA W/RA ENA MBA CLKA A0-35 Outputs Port Function H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L In high-impedance state FIFO1 write L H H H In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H Active, mail2 register Mail2 read (set MBF2 HIGH) Table 3. Port B Enable Function CSB W/RB ENB MBB CLKB B0-35 Outputs Port Function H X X X X In high-impedance state None L L L X X In high-impedance state None L L H L In high-impedance state FIFO2 write L L H H In high-impedance state Mail2 write L H L L X Active, FIFO1 output register None L H H L Active, FIFO1 output register FIFO1 read L H L H X Active, mail1 register None L H H H Active, mail1 register Mail1 read (set MBF1 HIGH) Notes: 43. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 44. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. 28 CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes) Synchronized to CLKB Number of Words in FIFO Memory[45,46,47,48] Synchronized to CLKA CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 EFB/ORB AEB AFA FFA/IRA 0 0 0 0 0 L L H H 1 TO X1 1 TO X1 1 TO X1 1 TO X1 1 TO X1 H L H H (X1+1) to [256-(Y1+1)] (X1+1) to [512-(Y1+1)] (X1+1) to (X1+1) to (X1+1) to [1024-(Y1+1)] [4096-(Y1+1)] [16384-(Y1+1)] H H H H (256-Y1) to 255 (512-Y1) to 511 (1024-Y1) to 1023 (4096-Y1) to 4095 (16384-Y1) to 16383 H H L H 256 512 1024 4096 16384 H H L L Table 5. FIFO2 Flag Operation (CY Standard and FWFT modes) Synchronized to CLKA Number of Words in FIFO Memory[46,47,48,49] Synchronized to CLKB CY7C43622 CY7C43632 CY7C43642 CY7C43662 CY7C43682 EFA/ORA AEA AFB FFB/IRB 0 0 0 0 0 L L H H 1 TO X2 1 TO X2 1 TO X2 1 TO X2 1 TO X2 H L H H (X2+1) to [256-(Y2+1)] (X2+1) to [512-(Y2+1)] (X2+1) to [1024-(Y2+1)] (X2+1) to [4096-(Y2+1)] (X2+1) to [16384-(Y2+)1] H H H H (256-Y2) to 255 (512-Y2) to 511 (1024-Y2) to 1023 (4096-Y2) to 4095 (16384-Y2) to 16383 H H L H 256 512 1024 4096 16384 H H L L Notes: 45. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming. 46. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 47. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 48. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode. 49. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming. 29 PRELIMINARY CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 256 x36 x2 Bidirectional Synchronous FIFO Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C43622-12AC A120 120-Lead Thin Quad Flat Package Commercial 12 CY7C43622-12AI A120 120-Lead Thin Quad Flat Package Industrial 15 CY7C43622-15AC A120 120-Lead Thin Quad Flat Package Commercial 512 x36 x2 Bidirectional Synchronous FIFO Speed (ns) Ordering Code Package Name A120 Package Type 120-Lead Thin Quad Flat Package Operating Range 12 CY7C43632-12AC Commercial 12 CY7C43632-12AI A120 120-Lead Thin Quad Flat Package Industrial 15 CY7C43632-15AC A120 120-Lead Thin Quad Flat Package Commercial 1K x36 x2 Bidirectional Synchronous FIFO Speed (ns) Ordering Code Package Name A120 Package Type 120-Lead Thin Quad Flat Package Operating Range 12 CY7C43642-12AC Commercial 12 CY7C43642-12AI A120 120-Lead Thin Quad Flat Package Industrial 15 CY7C43642-15AC A120 120-Lead Thin Quad Flat Package Commercial 4K x36 x2 Bidirectional Synchronous FIFO Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C43662-12AC A120 120-Lead Thin Quad Flat Package Commercial 12 CY7C43662-12AI A120 120-Lead Thin Quad Flat Package Industrial 15 CY7C43662-15AC A120 120-Lead Thin Quad Flat Package Commercial 16K x36 x2 Bidirectional Synchronous FIFO Speed (ns) Ordering Code Package Name A120 Package Type 120-Lead Thin Quad Flat Package Operating Range 12 CY7C43682-12AC 12 CY7C43682-12AI A120 120-Lead Thin Quad Flat Package Industrial 15 CY7C43682-15AC A120 120-Lead Thin Quad Flat Package Commercial Document #: 38-00698 30 Commercial PRELIMINARY CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 1998 Package Diagram 120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120 51-85100 (c) Cypress Semiconductor Corporation, 1998. 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