EP7312 FEATURES High-Performance, Low-Power System on Chip with SDRAM and Improved Digital Audio Interface ARM720T processor -- ARM7TDMI CPU -- 8 Kbytes of four-way set-associative cache -- MMU with 64-entry TLB (translation look-aside buffer) -- Write Buffer -- Thumb code support enabled Dynamically programmable clock speeds of OVERVIEW 18, 36, 49, and 74 MHz at 2.5 V TM MaverickKey IDs The MaverickTM EP7312 is designed for ultra-low-power applications such as PDAs, two-way pagers, smart cellular phones or any hand-held device that features the added capability of digital audio decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 Kbytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft(R) Windows CE. -- 32-bit unique SDMI ID -- 128-bit random ID Ultra low power -- Designed for applications that require long battery life while using standard AA/AAA batteries or rechargeable cells -- Typical power numbers 90 mW at 74 MHz in the Operating State 30 mW at 18 MHz in the Operating State 10 mW in the Idle State (clock to the CPU stopped, everything else running) <1 mW in the Standby State (real-time clock "on," everything else stopped) The EP7312 also includes a 32-bit real-time clock and comparator. (Continued on Page 3) BLOCK DIAGRAM 13-MHZ INPUT 3.6864 MHZ PLL 32.768 KHZ 32.768-KHZ OSCILLATOR INTERNAL DATA BUS D[0-31] ARM720T NPOR, RUN, RESET, WAKEUP STATE CONTROL BATOK, EXTPWR PWRFL, BATCHG POWER MANAGEMENT MEMORY CONTROLLER ARM7TDMI CPU CORE CL-PS6700 INTF EXPANSION CNTRL 8-KBYTE CACHE SDRAM CNTRL MMU EINT[1-3], FIQ, MEDCHG FLASHING LED DRIVE INTERRUPT CONTROLLER RTC PORTS A, B, D (8-BIT) PORT E (3-BIT) KEYBD DRIVERS (0-7) GPIO DC TO DC PWM ADCCLK, ADCIN, ADCOUT, SMPCLK, ADCCS SSICLK, SSITXFR, SSITXDA, SSIRXDA, SSIRSFR WRITE BUFFER EXPCLK, WORD, NCS[0-3], EXPRDY, WRITE MOE, MWE, SDCLK, SDQM[0-1], SDRAS, SDCAS A[0-27], DRA[0-14] LCD DMA ICE-JTAG TIMER COUNTERS(2) SSI1 (ADC) ON-CHIP BOOT ROM DAI SSI2 CODEC P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com INTERNAL ADDRESS BUS PB[0-1], NCS[4-5] LCD CONTROLLER ON-CHIP SRAM 48 KBYTES EPB BRIDGE EPB BUS TEST AND DEVELOPMENT LCD DRIVE IrDA LED AND PHOTODIODE UART1 ASYNC INTERFACE 1 UART2 ASYNC INTERFACE 2 Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved) DS508PP1 SEP `00 1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface FEATURES (cont.) -- ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbits/s operation) Advanced audio decoder / decompression capability -- Allows for support of multiple audio decompression algorithms -- Supports MPEG 1, 2, and 2.5 layer 3 audio decoding, including ISO compliant MPEG 1 and 2 layer 3 support for all standard sample rates and bit rates -- Supports bit streams with adaptive bit rates -- Improved DAI (Digital Audio Interface) providing glueless interface to low-power DACs, ADCs, and CODECs SDRAM controller -- Supports four internal memory banks totaling 256 Mbits in size -- SDRAM memory interface is programmable from 4 to 32 bits wide. LCD controller -- Interfaces directly to a single-scan panel monochrome or color STN LCD -- Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments -- Video frame buffer size programmable up to 128 kbytes -- Bits per pixel of 1, 2, or 4 bits Memory controller -- Decodes up to 6 separate memory segments of up to 256 Mbytes each -- Each segment can be configured as 8, 16, or 32 bits wide and supports page-mode access -- Programmable access time for conventional ROM / SRAM / FLASH memory -- Supports Removable FLASH card interface -- Enables connection to removable FLASH card for addition of expansion FLASH memory modules 48 kbytes (0x9600) of on-chip SRAM for fast pro- gram execution and / or as a frame buffer Synchronous serial interface On-chip ROM; for manufacturing support 27-bits of general-purpose I/O -- Three 8-bit and one 3-bit GPIO port -- Supports scanning keyboard matrix Two UARTs (16550 type) -- Supports bit rates up to 115.2 kbits/s -- Contains two 16-byte FIFOs for TX and RX -- UART1 supports modem control signals SIR (up to 115.2 kbits/s infrared encoder / decoder -- IrDA (Infrared Data Association) SIR protocol encoder / decoder DC-to-DC converter interface (PWM) -- Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a DC to DC converter Two timer counters Available in 208-pin LQFP or 256-ball PBGA packages Evaluation kit available with BOM, schematics, sample code, and design database Support for up to two ultra-low-power CL-PS6700 PC Card controllers Dedicated LED flasher pin from the RTC Full JTAG boundary scan and Embedded ICE support Commercial and industrial operating temperature range versions The EP7312 is optimized for low power dissipation and is fabricated on a fully static 0.25 micron CMOS process. Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface OVERVIEW (cont.) Power Management yielding industry-leading code density. The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. The device has three basic power states: The second is the programmable 4- or 32-bit-wide SDRAM interface that allows direct connection of up to four internal banks of SDRAM, totaling 256 Mbits. To assure the lowest possible power consumption, the EP7312 supports self-refresh DRAMs, which are placed in a lowpower state by the device when it enters the low-power Standby State. Operating -- This state is the full performance state. All the clocks and peripheral logic are enabled. Idle -- This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press. Standby -- This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wakeup the processor. MaverickKeyTM Unique ID A DMA address generator is also provided that fetches video display data for the LCD controller from main SDRAM memory. The display frame buffer start address is programmable. In addition, the built-in LCD controller can utilize external or internal SRAM for memory, thus eliminating the need for SDRAMs. Digital Audio Capability MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. The EP7312 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7312. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today's Internet appliances. The EP7312 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbits/s. An IrDA SIR protocol encoder / decoder can be optionally switched into the RX / TX signals to / from one of the UARTs to enable these signals to drive an infrared communication interface directly. Memory Interfaces There are two main external memory interfaces. The first one is the ROM / SRAM / FLASH-style interface that has programmable wait-state timings and includes burst-mode capability, with eight chip selects decoding six 256 Mbyte sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32-bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and DS508PP1 Serial Interfaces Improved Digital Audio Interface (DAI) The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal CS43L41 / 42 / 43 low-power audio DACs and the Crystal CS53L32 low-power ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Packaging The EP7312 is available in a 208-pin LQFP package and a 256-ball PBGA package. System Design As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7312 completes a low-power system solution. All necessary interface logic is integrated on-chip. 3 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface OVERVIEW (cont.) CRYSTAL MOSCIN DD[0-3] CRYSTAL RTCIN nCS[4] PB0 EXPCLK CL1 CL2 FRM M LCD COL[0-7] CL-PS6700 PC CARD CONTROLLER PC CARD SOCKET KEYBOARD D[0-31] PA[0-7] A[0-27] PB[0-7] nMOE WRITE PD[0-7] SDRAS/ SDCAS x16 SDRAM x16 SDRAM x16 SDRAM x16 SDRAM SDCS[0] SDQM[0-3] EP7312 PE[0-2] nPOR nPWRFL BATOK nEXTPWR nBATCHG RUN WAKEUP SDQM[0-3] nCS[0] nCS[1] DRIVE[0-1] x16 FLASH x16 FLASH SSICLK SSITXFR SSITXDA SSIRXDA SSIRXFR x16 FLASH x16 FLASH LEDDRV PHDIN CS[n] WORD BUFFERS nCS[2] nCS[3] ADDITIONAL I/O NOTE: BUFFERS AND LATCHES DC INPUT BATTERY SDCS[1] FB[0-1] EXTERNAL MEMORYMAPPED EXPANSION POWER SUPPLY UNIT AND COMPARATORS LEDFLSH RXD1/2 TXD1/2 DSR CTS DCD ADCCLK nADCCS ADCOUT ADCIN SMPCLK DC-TO-DC CONVERTERS CODEC/SSI2/ DAI IR LED AND PHOTODIODE 2x RS-232 TRANSCEIVERS ADC DIGITIZER A system can only use one of the following peripheral interfaces at any given time: SSI2, CODEC, or DAI. Figure 1. A Maximum EP7312 Based System 4 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface TABLE OF CONTENTS 1. 2. 3. 4. 5. 6. Power Management ................................................................................................................. 3 MaverickKeyTM Unique ID ........................................................................................................ 3 Memory Interfaces .................................................................................................................... 3 Digital Audio Capability ............................................................................................................ 3 Serial Interfaces ....................................................................................................................... 3 Improved Digital Audio Interface (DAI) ..................................................................................... 3 Packaging ................................................................................................................................. 3 System Design ......................................................................................................................... 3 CONVENTIONS ........................................................................................................................ 6 1.1. Acronyms and Abbreviations .............................................................................................. 6 1.2. Units of Measurement ....................................................................................................... 8 1.3. General Conventions .......................................................................................................... 8 1.4. Pin Description Conventions .............................................................................................. 8 ELECTRICAL SPECIFICATIONS ............................................................................................. 9 2.1. Absolute Maximum Ratings ................................................................................................ 9 2.2. Recommended Operating Conditions ................................................................................ 9 2.3. DC Characteristics ............................................................................................................. 9 2.4. AC Characteristics ............................................................................................................ 13 208-PIN LQFP PACKAGE CHARACTERISTICS .................................................................. 22 3.1. 208-Pin LQFP Pin Diagram .............................................................................................. 22 3.2. 208-Pin LQFP Package Specifications ............................................................................ 23 3.3. 208-Pin LQFP Numeric Pin Listing ................................................................................... 24 3.4. JTAG Boundary Scan Signal Ordering for 208-Pin LQFP ................................................ 27 256-PIN PBGA PACKAGE CHARACTERISTICS .................................................................. 29 4.1. 256-Pin PBGA Pin Diagram ............................................................................................. 29 4.2. EP7312 256-Ball PBGA (17 x 17 x 1.61-mm Body) Dimensions .................................... 30 4.3. 256-Ball PBGA Ball Listing ............................................................................................... 31 ORDERING INFORMATION ................................................................................................... 34 INDEX ...................................................................................................................................... 35 LIST OF FIGURES Figure 1. A Maximum EP7312 Based System ............................................................................... 4 Figure 2. Consecutive Memory Read Cycles with Minimum Wait States ..................................... 15 Figure 3. Sequential Page Mode Read Cycles with Minimum Wait States .................................. 16 Figure 4. Consecutive Memory Write Cycles with Minimum Wait States ..................................... 17 Figure 5. SDRAM Read Cycles SDCAS Latency = 2 ................................................................... 18 Figure 6. SDRAM Read Cycles SDCAS Latency = 3 ................................................................... 19 Figure 7. SDRAM Write Cycles .................................................................................................... 19 Figure 8. SDRAM Refresh Cycles ................................................................................................ 20 Figure 9. LCD Controller Timings ................................................................................................. 20 Figure 10. SSI1 Interface for AD7811/2 ....................................................................................... 21 Figure 11. SSI2 Interface Timings ................................................................................................ 21 Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram .......................................... 22 Figure 13. 208-Pin LQFP Package Outline Drawing .................................................................... 23 Figure 14. 256-Ball Plastic Ball Grid Array Diagram ..................................................................... 29 Figure 15. 256-Ball Pin Diagram .................................................................................................. 29 Figure 16. 256-Ball PBGA Package Drawing ............................................................................... 30 5 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface LIST OF TABLES Table 1. Acronyms and Abbreviations ........................................................................................... 7 Table 2. Unit of Measurement ........................................................................................................ 8 Table 3. Pin Description Conventions ............................................................................................ 8 Table 4. Absolute Maximum Ratings ............................................................................................. 9 Table 5. Recommended Operating Conditions .............................................................................. 9 Table 6. DC Characteristics ........................................................................................................... 9 Table 7. AC Timing Characteristics .............................................................................................. 13 Table 8. 208-Pin LQFP Numeric Pin Listing ................................................................................ 24 Table 9. JTAG Boundary Scan Signal Ordering for 208-Pin LQFP Package .............................. 27 Table 10. 256-Ball PBGA Ball Listing ........................................................................................... 31 DS508PP1 6 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 1. CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. 1.1. Acronyms and Abbreviations Table 1 lists abbreviations and acronyms used in this data sheet. Acronym/ Abbreviation Definition Acronym/ Abbreviation Definition IrDA Infrared Data Association JTAG Joint Test Action Group LCD liquid crystal display LED light-emitting diode LQFP low profile quad flat pack LSB least significant bit MIPS millions of instructions per second MMU memory management unit MSB most significant bit PBGA plastic ball grid array PCB printed circuit board PDA personal digital assistant PIA peripheral interface adapter A/D analog-to-digital ADC analog-to-digital converter CMOS complementary metal oxide semiconductor CODEC coder / decoder PLL phase locked loop D/A digital-to-analog PSU power supply unit DMA direct-memory access p/u pull-up resistor EPB embedded peripheral bus RISC reduced instruction set computer FCS frame check sequence RTC Real-Time Clock FIFO first in / first out SIR slow (9600-115.2 kbps) infrared FIQ fast interrupt request SRAM static random access memory GPIO general purpose I/O SSI synchronous serial interface ICT in circuit test TAP test access port IR infrared TLB translation lookaside buffer IRQ standard interrupt request UART universal asynchronous receiver Table 1. Acronyms and Abbreviations 7 Table 1. Acronyms and Abbreviations (cont.) DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 1.2. Units of Measurement Symbol Unit of Measure C degree Celsius fs sample frequency Hz hertz (cycle per second) kbits/s kilobits per second kbyte kilobyte (1,024 bytes) kHz kilohertz k kilohm Mbits/s megabits (1,048,576 bits) per second Mbyte megabyte (1,048,576 bytes) Mbyte/s megabytes per second MHz megahertz (1,000 kilohertz) A microampere F microfarad W microwatt s microsecond (1,000 nanoseconds) mA milliampere mW milliwatt ms millisecond (1,000 microseconds) ns nanosecond V volt W watt 1.3. General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase "h" appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, `11' designates a binary number). Numbers not indicated by an "h", 0x or quotation marks are decimal. Registers are referred to by acronym, with bits listed in brackets separated by a hyphen (-) (for example, CODR[0-7]), and are described in the EP7312 User's Manual, The use of "tbd" indicates values that are "to be determined," "n/a" designates "not available," and "n/c" indicates a pin that is a "no connect." 1.4. Pin Description Conventions Abbreviations used for signal directions are listed in Table 3. Abbreviation Direction I Input O Output I/O Input or Output Table 2. Unit of Measurement Table 3. Pin Description Conventions DS508PP1 8 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 2. ELECTRICAL SPECIFICATIONS 2.1. Absolute Maximum Ratings DC Core, PLL, and RTC Supply Voltage 2.9 V DC I/O Supply Voltage (Pad Ring) 3.6 V DC Pad Input Current 10 mA/pin; 100 mA cumulative Storage Temperature, No Power -40C to +125C Table 4. Absolute Maximum Ratings 2.2. Recommended Operating Conditions DC core, PLL, and RTC Supply Voltage 2.5 V 0.2 V DC I/O Supply Voltage (Pad Ring) 2.3V - 3.6V DC Input / Output Voltage O-I/O supply voltage Operating Temperature Extended -20C to +70C; Commercial 0C to +70C; Industrial -40C to +85C Table 5. Recommended Operating Conditions 2.3. DC Characteristics All characteristics are specified at VDD = 2.5 volts and VSS = 0 volts over an operating temperature of 0C to +70C for all frequencies of operation. The Symbol VIH VIL VT+ VTVhst VOH VOL IIN IOZ CIN Parameter CMOS input high voltage CMOS input low voltage current consumption figures relate to typical conditions at 2.5 V, 18.432 MHz operation with the PLL switched "on." Min 1.7 -0.3 Typ Schmitt trigger positive going thresh- 1.6 (Typ) old Schmitt trigger negative going 0.8 threshold Schmitt trigger hysteresis 0.1 CMOS output high voltage VDD - 0.2 Output drive 1 2.5 Output drive 2 2.5 CMOS output low voltage Max Unit Conditions V VDD = 2.5 V VDD + 0.3 0.8 V VDD = 2.5 V 2.0 V 1.2 (Typ) V 0.4 V V V V Output drive 1 0.3 0.5 0.5 V V V Output drive 2 Input leakage current 1 Output three-state leakage current 2 3 Input capacitance 1.0 100 10.0 A A pF 25 8 VIL to VIH IOH = 0.1 mA IOH = 4 mA IOH = 12 mA IOL = -0.1 mA IOL = -4 mA IOL = -12 mA VIN = VDD or GND VOUT = VDD or GND Table 6. DC Characteristics 9 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Symbol Parameter COUT Output capacitance CI/O Transceiver capacitance IDDstartup Startup current consumption IDDstandby Standby current consumption Core, Osc, RTC @2.5V I/O @ 2.5V IDDidle Core, Osc, RTC @2.5V I/O @ 3.3V Idle current consumption At 13 MHz Core, Osc, RTC @2.5V I/O @ 2.5V Min 8 8 Typ Max 10.0 10.0 15.0 De-Rating Curves to be added De-Rating Curves to be added 4.2 TBD TBD Core, Osc, RTC @2.5V I/O @ 3.3V TBD TBD At 18 MHz Core, Osc, RTC @2.5V I/O @ 2.5V TBD TBD Core, Osc, RTC @2.5V I/O @ 3.3V TBD TBD At 36 MHz Core, Osc, RTC @2.5V I/O @ 2.5V TBD TBD Core, Osc, RTC @2.5V I/O @ 3.3 TBD TBD Unit Conditions pF pF A Initial 100 ms from power up, Cache disabled, 32 kHz oscillator not stable, POR signal at VIL, all other I/O static, VIH = VDD 0.1 V, VIL = GND 0.1 V A Just 32 kHz oscillator running, Cache disabled, all other I/O static, VIH = VDD 0.1 V, VIL = GND 0.1 V mA Both oscillators running, CPU static, Cache disabled, LCD refresh active, VIH = VDD 0.1 V, VIL = GND 0.1 V 6.0 12.0 Table 6. DC Characteristics (cont.) DS508PP1 10 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Symbol Parameter IDDoperatin Operating current consumption At 13 MHz Core, Osc, RTC @2.5V I/O @ 2.5V Min Typ 14 TBD TBD Core, Osc, RTC @2.5V I/O @ 3.3V TBD TBD At 18 MHz Core, Osc, RTC @2.5V I/O @ 2.5V TBD TBD Core, Osc, RTC @2.5V I/O @ 3.3V TBD TBD At 36 MHz Core, Osc, RTC @2.5V I/O @ 2.5V TBD TBD Core, Osc, RTC @2.5V I/O @ 3.3V TBD TBD Unit Conditions mA All system active, running typical program, cache disabled, and LCD inactive 30 40 At 49 MHz Core, Osc, RTC @2.5V I/O @ 2.5V Core, Osc, RTC @2.5V I/O @ 3.3V Max 50 TBD TBD TBD TBD At 74 MHz Core, Osc, RTC @2.5V I/O @ 2.5V TBD TBD Core, Osc, RTC @2.5V I/O @ 3.3V TBD TBD 68 Table 6. DC Characteristics (cont.) 11 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Symbol Parameter VDDstandby Standby supply voltage Min TBD Typ Max Unit Conditions V Minimum standby voltage for state retention and RTC operation only Table 6. DC Characteristics (cont.) 1 The leakage value given assumes that the pin is configured as an input pin but is not currently being driven. An input pin not driven will have a maximum leakage of 1 A. When the pin is driven, there will be no leakage. 2 Assumes buffer has no pull-up or pull-down resistors. 3 The leakage value given assumes that the pin is configured as an output pin but is not currently being driven. An output pin not driven will have leakage between 25 A and 100 A. When the pin is driven, there will be no leakage. Note that this applies to all output pins and all I/O pins configured as outputs. Notes: 1) All power dissipation values can be derived from taking the particular IDD current and multiplying by 2.5 V. 2) The RTC of the EP7312 should be brought up at room temperature. This is required because the RTC OSC will NOT function properly if it is brought up at -40C. Once operational, it will continue to operate down to -20C extended and 0C commercial. 3) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be compatible with 3.3 V powered external logic (i.e., 3.3 V DRAMs). 4) Pull-up current = 50 A typical at VDD = 3.3 volts. DS508PP1 12 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 2.4. AC Characteristics All characteristics are specified at VDD = 2.3 to 2.7 volts and VSS = 0 volts over an operating temperature of 0C to +70C. Those characteristics marked with a # will be significantly different for 13 MHz mode because the EXPCLK is provided as an input rather than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 VDD. 13 MHz Symbol Parameter 18/36 MHz Min Max Min Max Units t1 Falling CS to data bus Hi-Z 0 35 0 25 ns t2 Address change to valid write data 0 45 0 35 ns t3 DATA in to falling EXPCLK setup time 0 # -- 18 -- ns t4 DATA in to falling EXPCLK hold time 10 # -- 0 -- ns t5 EXPRDY to falling EXPCLK setup time 0# -- 18 -- ns t6 Falling EXPCLK to EXPRDY hold time 10 # 50 0 50 ns t7 Rising nMWE to data invalid hold time 10 -- 5 -- ns t8 Sequential data valid to falling nMWE setup time -10 10 -10 10 ns t9 Row address to falling nSDRAS setup time TBD - TBD - ns t10 Falling nSDRAS to row address hold time TBD - TBD - ns t11 Column address to falling nSDCAS setup time TBD - TBD - ns t12 Falling nSDCAS to column address hold time TBD - TBD - ns t13 Write data valid to falling nSDCAS setup time TBD - TBD - ns t14 Write data valid from falling nSDCAS hold time TBD - TBD - ns t15 LCD CL2 low time 80 3,475 80 3,475 ns t16 LCD CL2 high time 80 3,475 80 3,475 ns t17 LCD falling CL[2] to rising CL[1] delay 0 25 0 25 ns t18 LCD falling CL[1] to rising CL[2] 80 3,475 80 3,475 ns t19 LCD CL[1] high time 80 3,475 80 3,475 ns t20 LCD falling CL[1] to falling CL[2] 200 6,950 200 6,950 ns t21 LCD falling CL[1] to FRM toggle 300 10,425 300 10,425 ns t22 LCD falling CL[1] to M toggle -10 20 -10 20 ns t23 LCD rising CL[2] to display data change -10 20 -10 20 ns t24 Falling EXPCLK to address valid -- 33 # -- 5 ns Table 7. AC Timing Characteristics 13 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 13 MHz Symbol Parameter 18/36 MHz Min Max Min Max Units t25 Data valid to falling nMWE for non sequential access only 5 -- 5 -- ns t31 SSICLK period (slave mode) 0 512 0 512 kHz t32 SSICLK high 925 1025 925 1025 ns t33 SSICLK low 925 1025 925 1025 ns t34 SSICLK rise / fall time 7 7 ns t35 SSICLK rising to RX and / or TX frame sync 528 528 ns t36 SSICLK rising edge to frame sync low 448 448 ns t37 SSICLK rising edge to TX data valid 80 80 ns t38 SSIRXDA data set-up time 30 30 ns t39 SSIRXDA data hold time 40 40 ns t40 SSITXFR and / or SSIRXFR period 750 750 ns tnCSRD Negative strobe (nCS[0-5]) zero wait state read access time TBD TBD TBD tnCSWR Negative strobe (nCS[0-5]) zero wait state write access time TBD TBD TBD tEXBST Sequential expansion burst mode read access time TBD TBD TBD tRC SDRAM cycle time TBD - TBD - TBD tRAC Access time from SDRAS TBD - TBD - TBD tRP SDRAS precharge time TBD - TBD - TBD tCAS SDCAS pulse width TBD - TBD - TBD tCP SDCAS precharge in page mode TBD - TBD - TBD tPC Page mode cycle time TBD - TBD - TBD tCSR SDCAS set-up time for auto refresh TBD - TBD - TBD tRAS SDRAS pulse width TBD - TBD - TBD Table 7. AC Timing Characteristics (cont.) Notes: All SDRAM 36 MHz timings are for SDRAM operation. The values for 36 MHz include 1 wait state, and the 18 MHz values have 0 wait states. DS508PP1 14 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface EXPCLK tNCSRD nCS[5:0] nMOE A[27:0] WORD t1 tADRD tPCSRD D[31:0] t3 t4 Data in Bus held t5 t3 t4 Data in t6 EXPRDY Figure 2. Consecutive Memory Read Cycles with Minimum Wait States Notes: 1) tnCSRD = 50 ns at 36.864 MHz 70 ns at 18.432 MHz 120 ns at 13.0 MHz Maximum values for minimum wait states. This time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible. 3) tnCSRD = tADRD = tPCSRD 4) When the EP7312 device implements consecutive reads(e.g., use of the LDM instruction), regardless of the state of the SQAEN bit, the signals nMOE and nCSx will always remain low through the entire multi-read access. They will not toggle in-between each different address access. In order to have these signals toggle, single access read instructions (e.g., LDR) must be used. 15 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface EXPCLK nCS[5:0] nMOE A[27:4] tEXBST A[3:0] 0 tEXBST 4 8 WORD t1 tEXRD D[31:0] t3 t4 Data in Bus held t5 t4 t3 Data in t3 t4 Data in t6 EXPRDY Figure 3. Sequential Page Mode Read Cycles with Minimum Wait States Notes: 1) tEXBST = 35 ns at 36.864 MHz 35 ns at 18.432 MHz 55 ns at 13.0 MHz (Value for 36.864 MHz assumes 1 wait state.) Maximum values for minimum wait states. This time can be extended by integer multiples of the clock period (27 nsec at 36 MHz, 54 nsec at 18.432 MHz and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible. DS508PP1 16 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface eXPCLK tnCSWR nCS[5:0] t8 tADWR nMWE A[27:0] WORD t2 D[31:0] Bus held t7 t2 Write data Write data t6 t5 nEXPRDY Figure 4. Consecutive Memory Write Cycles with Minimum Wait States Notes: 1) tnCSWR = 35 nsec at 36.864 MHz 70 ns at 18.432 MHz 120 ns at 13.0 MHz Maximum values for minimum wait states. This time can be extended by integer multiples of the clock period (27 nsec at 36 MHz, 54 nsec at 18.432 MHz, and 77 nsec at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible. 3) Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. 17 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK CKE 1 dev nCS 1 dev CAS lat 2 nRAS / nCAS / nWE NOP ACT NOP READ NOP NOP NOP NOP tRCD NOP NOP NOP (ACT) tRP tRAS auto precharge tRC DQM DI0 DQ Bank sel bank A10 (prech sel) row addr row DI1 DI2 DI3 bank col Figure 5. SDRAM Read Cycles SDCAS Latency = 2 Notes: 1. 2. 3. 4. 5. DS508PP1 tRCD (delay time ACT to READ/WRITE command) = 30 ns or 2 cycles at 36 MHz. tRP (PRE to ACT command period) = 30 ns or 2 cycles at 36 MHz. tRAS (ACT to PRE command period) = 60 ns or 3 cycles at 36 MHz. tRC (ACT to REF/ACT command period [operation]) = 90 ns or 4 cycles at 36 MHz. For SDCAS latency 3, there will be an extra cycle between T4 and T5. 18 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CLK CKE 1 dev nCS 1 dev CAS lat 3 nRAS / nCAS / nWE NOP ACT NOP READ NOP NOP NOP NOP NOP NOP tRCD NOP NOP (ACT) tRP tRAS auto precharge tRC DQM DI0 DQ Bank sel bank A10 (prech sel) row addr row DI1 DI2 DI3 bank col Figure 6. SDRAM Read Cycles SDCAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 CLK CKE nCS nRAS / nCAS / nWE NOP 1 dev 1 dev ACT NOP WRITE NOP NOP NOP tRCD NOP tDPL tRAS NOP (ACT) tRP auto precharge tRC DQM DO0 DQ Bank sel bank A10 (prech sel) row addr row DO1 DO2 DO3 bank col Figure 7. SDRAM Write Cycles Note: tDPL (data in to PRE command period command) = 10 ns or 1 cycle at 36 MHz. 19 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface T0 T1 T2 T3 T4 CLK CKE all nCS nRAS / nCAS / nWE NOP REF NOP tRP NOP NOP (ACT) tRC1 auto precharge DQM DQ Bank sel A10 (prech sel) addr Figure 8. SDRAM Refresh Cycles Note: tRC1 (REF to REF/ACT command period [refresh]) = 90 ns or 4 cycles at 36 MHz. t20 t15 t16 CL[2] t17 t19 t18 t21 CL[1] FRM t22 M t23 DD[3:0] Figure 9. LCD Controller Timings Notes: 1) The figure shows the end of a line. 2) If FRM is high during the CL[1] pulse, this marks the first line in the display. 3) CL[2] low time is doubled during the CL[1] high pulse. DS508PP1 20 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 1 2 DI9 DI8 3 4 5 7 6 8 9 DI1 DI0 10 11 12 13 15 14 22 23 DO1 DO0 ADCCLK (SCLK) nADCCS (nRFS/TFS) ADCIN DI7 DI6 DI5 DI4 DI3 DI2 (Din) ADCOUT DO9 (Dout) DO8 Figure 10. SSI1 Interface for AD7811/2 t33 t31 t32 SSICLK t40 t35 SSI RX/TXFR t36 t37 D7 SSITXDA t38 SSIRXDA D2 D1 D0 D2 D1 D0 t39 D7 Figure 11. SSI2 Interface Timings 21 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 3. 208-PIN LQFP PACKAGE CHARACTERISTICS 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 NURESET NMEDCHG/NBROM NPOR BATOK NEXTPWR NBATCHG D[7] VSSIO A[7] D[8] A[8] D[9] A[9] D[10] A[10] D[11] VSSIO VDDIO A[11] D[12] A[12] D[13] A[13]\DRA[14] D[14] A[14]/DRA[13] D[15] A[15]/DRA[12] D[16] A[16]/DRA[11] D[17] A[17]/DRA[10] NTRST VSSIO VDDIO D[18] A[18/DRA[9] D[19] A[19]/DRA[8] D[20] A[20]/DRA[7] VSSIO D[21] A[21]/DRA[6] D[22] A[22]/DRA[5] D[23] A[23]/DRA[4] D[24] VSSIO VDDIO A[24]/DRA[3] HALFWORD 3.1. 208-Pin LQFP Pin Diagram EP7312 208-Pin LQFP (Top View) 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 D[25] A[25]/DRA[2] D[26] A[26]/DRA[1] D[27] A[27]/DRA[0] VSSIO D[28] D[29] D[30] D[31] BUZ COL[0] COL[1] TCLK VDDIO COL[2] COL[3] COL[4] COL[5] COL[6] COL[7] FB[0] VSSIO FB[1] SMPCLK ADCOUT ADCCLK DRIVE[0] DRIVE[1] VDDIO VSSIO VDDCORE VSSCORE NADCCS ADCIN SSIRXFR SSIRXDA SSITXDA SSITXFR VSSIO SSICLK PD[0]/LEDFLSH PD[1] PD[2] PD[3] TMS VDDIO PD[4] PD[5] PD[6]/SDQM[0] PD[7]/SDQM[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 NCS[5] VDDIO VSSIO EXPCLK WORD WRITE/NSDRAS RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/PRDY[2] PB[0]/PRDY[1] VDDIO TDO PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS RXD[1] DCD DSR NTEST[1] NTEST[0] EINT[3] NEINT[2] NEINT[1] NEXTFIQ PE[2]/CLKSEL PE[1]BOOTSEL[1] PE[0]BOOTSEL[0] VSSRTC RTCOUT RTCIN VDDRTC N/C VDDOSC MOSCIN MOSCOUT VSSOSC WAKEUP NPWRFL A[6] D[6] A[5] D[5] VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSSCORE VDDCORE VSSIO VDDIO CL[2] CL[1] FRM M DD[3] DD[2] VSSIO DD[1] DD[0] NSDCS[1] NSDCS[0] SDQM[3] SDQM[2] VDDIO VSSIO SDCKE SDCLK NMWE/NSDWE NMOE/NSDCAS VSSIO NCS[0] NCS[1] NCS[2] NCS[3] NCS[4] Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram Notes: 1. N/C should not be grounded but left as no connects. 2. Pin differences between the EP7212 and the EP7312 are bolded. DS508PP1 22 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 3.2. 208-Pin LQFP Package Specifications 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) EP7312 29.60 (1.165) 30.40 (1.197) 208-Pin LQFP 0.50 (0.0197) BSC Pin 1 Indicator Pin 208 Pin 1 0.45 (0.018) 0.75 (0.030) 1.35 (0.053) 1.45 (0.057) 1.00 (0.039) BSC 0.09 (0.004) 0.20 (0.008) 0 MIN 7 MAX 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006) Figure 13. 208-Pin LQFP Package Outline Drawing Notes: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) Drawing above does not reflect exact package pin count. 23 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 4) For pin locations, please see Figure 12. For pin descriptions see the EP7312 User's Manual. DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 3.3. 208-Pin LQFP Numeric Pin Listing Pin No. 1 2 3 4 5 6 Type Out Pad Pwr Pad Gnd I/O Out Out Strength 1 O In Out In In Pad Gnd I/O I/O I/O I/O I/O I/O I/O 1 1 1 21 22 Signal nCS[5] VDDIO VSSIO EXPCLK WORD WRITE/ nSDRAS RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/ PRDY2 PB[0]/ PRDY1 VDDIO TDO 23 24 25 26 27 28 29 30 31 32 33 34 35 PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS I/O I/O I/O I/O I/O I/O I/O I/O Out Out Pad Gnd In In 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 1 1 Reset State High Low Low Low High with p/u* 46 47 1 1 1 1 1 1 1 Input Input Input Input Input Input Input 1 Input 48 49 50 51 52 53 54 I/O Pad Pwr Out 1 1 1 1 1 1 1 1 1 1 1 1 Three state Input Input Input Input Input Input Input Input Low High High Table 8. 208-Pin LQFP Numeric Pin Listing DS508PP1 Pin No. 36 37 38 39 40 41 42 43 44 45 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal RXD[1] DCD DSR nTEST[1] nTEST[0] EINT[3] nEINT[2] nEINT[1] nEXTFIQ PE[2]/ CLKSEL PE[1]/ BOOTSEL[1] PE[0]/ BOOTSEL[0] VSSRTC RTCOUT RTCIN VDDRTC N/C PD[7]/ SDQM[1] PD[6]/ SDQM[0] PD[5] PD[4] VDDIO TMS PD[3] PD[2] PD[1] PD[0]/ LEDFLSH SSICLK VSSIO SSITXFR SSITXDA SSIRXDA SSIRXFR ADCIN nADCCS Reset State Type In In In In In In In In In I/O Strength 1 Input I/O 1 Input I/O 1 Input I/O 1 Low I/O 1 Low I/O I/O Pad Pwr In I/O I/O I/O I/O 1 1 Low Low with p/u* 1 1 1 1 Low Low Low Low 1 Input 1 1 Low Low With p/u* With p/u* RTC Gnd Out In RTC power I/O Pad Gnd I/O Out In I/O In Out Input 1 High Table 8. 208-Pin LQFP Numeric Pin Listing (cont.) 24 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Pin No. 71 72 73 74 75 Signal VSSCORE VDDCORE VSSIO VDDIO DRIVE[1] 76 DRIVE[0] I/O 2 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 ADCCLK ADCOUT SMPCLK FB[1] VSSIO FB[0] COL[7] COL[6] COL[5] COL[4] COL[3] COL[2] VDDIO TCLK COL[1] COL[0] BUZ D[31] D[30] D[29] D[28] VSSIO A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25] HALFWORD A[24]/DRA[3] VDDIO VSSIO Out Out Out In Pad Gnd In Out Out Out Out Out Out Pad Pwr In Out Out Out I/O I/O I/O I/O Pad Gnd Out I/O Out I/O Out I/O Out Out Pad Pwr Pad Gnd 1 1 1 High / Low High / Low Low Low Low 1 1 1 1 1 1 High High High High High High 1 1 1 1 1 1 1 High High Low Low Low Low Low 2 1 2 1 2 1 1 1 Low Low Low Low Low Low Low Low -- -- Type Strength Core Gnd Core Pwr Pad Gnd Pad Pwr I/O 2 Reset State Table 8. 208-Pin LQFP Numeric Pin Listing (cont.) 25 Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Signal D[24] A[23]/DRA[4] D[23] A[22]/DRA[5] D[22] A[21]/DRA[6] D[21] VSSIO A[20]/DRA[7] D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] VDDIO VSSIO nTRST A[17]/ DRA[10] D[17] A[16]/ DRA[11] D[16] A[15]/ DRA[12] D[15] A[14]/ DRA[13] D[14] A[13]/ DRA[14] D[13] A[12] D[12] A[11] VDDIO VSSIO D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7] Type I/O Out I/O Out I/O Out I/O Pad Gnd Out I/O Out I/O Out I/O Pad Pwr Pad Gnd In Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out Pad Pwr Pad Gnd I/O Out I/O Out I/O Out I/O Out Strength 1 1 1 1 1 1 1 Reset State Low Low Low Low Low Low Low 1 1 1 1 1 1 Low Low Low Low Low Low 1 1 1 1 1 1 1 1 1 1 1 1 1 Low Low Low Low Low Low Low Low Low Low Low Low Low 1 1 1 1 1 1 1 1 Low Low Low Low Low Low Low Low Table 8. 208-Pin LQFP Numeric Pin Listing (cont.) DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Pin No. 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 Signal VSSIO D[7] nBATCHG nEXTPWR BATOK nPOR nMEDCHG/ nBROM nURESET VDDOSC MOSCIN MOSCOUT VSSOSC WAKEUP nPWRFL A[6] D[6] A[5] D[5] VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSS CORE VDD CORE VSSIO VDDIO CL[2] CL[1] FRM M Type Pad Gnd I/O In In In In In Strength Reset State 1 Low In Osc Pwr Osc Osc Osc Gnd In In Out I/O Out I/O Pad Pwr Pad Gnd Out I/O Out I/O Out Pad Gnd I/O Out I/O Out I/O Core Gnd Core Pwr Pad Gnd Pad Pwr Out Out Out Out Schmitt Schmitt Schmitt 1 1 1 1 Low Low Low Low 1 1 2 1 2 Low Low Low Low Low 1 2 1 2 1 Low Low Low Low Low 1 1 1 1 Low Low Low Low Pin No. Signal 188 DD[3] 189 DD[2] 190 VSSIO 191 DD[1] 192 DD[0] 193 nSDCS[1] 194 nSDCS[0] 195 SDQM[3] 196 SDQM[2] 197 VDDIO 198 VSSIO 199 SDCKE 200 SDCLK 201 nMWE/nSDWE 202 nMOE/ nSDCAS 203 VSSIO 204 nCS[0] 205 nCS[1] 206 nCS[2] 207 nCS[3] 208 nCS[4] Type I/O I/O Pad Gnd I/O I/O Out Out I/O I/O Pad Pwr Pad Gnd I/O I/O Out Out Pad Gnd Out Out Out Out Out Strength 1 1 Reset State Low Low 1 1 1 1 2 2 Low Low High High Low Low 2 2 1 1 Low Low High High 1 1 1 1 1 High High High High High Note: `With p/u' means with internal pull-up on the pin. Table 8. 208-Pin LQFP Numeric Pin Listing (cont.) Table 8. 208-Pin LQFP Numeric Pin Listing (cont.) DS508PP1 26 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 3.4. JTAG Boundary Scan Signal Ordering for 208-Pin LQFP Pin No. 1 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Signal NCS[5] EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD2 RXD2 PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/PRDY2 PB[0]/PRDY1 PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD1 PHDIN CTS RXD1 DCD DSR NTEST1 NTEST0 EINT3 NEINT2 NEINT1 NEXTFIQ PE[2]/CLKSEL PE[1]/BOOTSEL1 PE[0]/BOOTSEL0 Type Out I/O Out Out O I Out In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Out Out In In In In In In In In In In In I/O I/O I/O Position 1 3 6 8 10 13 14 16 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 67 69 70 71 72 73 74 75 76 77 78 79 80 83 86 Table 9. JTAG Boundary Scan Signal Ordering for 208Pin LQFP Package 27 Pin No. 53 54 55 56 59 60 61 62 68 69 70 75 76 77 78 79 80 82 83 84 85 86 87 88 91 92 93 94 95 96 97 99 100 101 102 103 104 105 106 109 110 111 112 113 Signal PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSIRXFR ADCIN NADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPCLK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25] HALFWORD A[24]/DRA[3] D[24] A[23]/DRA[4] D[23] A[22]/DRA[5] D[22] Type I/O I/O I/O I/O I/O I/O I/O O I/O In Out I/O I/O Out Out Out In In Out Out Out Out Out Out Out Out Out I/O I/O I/O I/O Out I/O Out I/O Out I/O Out Out I/O Out I/O Out I/O Position 89 92 95 98 101 104 107 110 122 125 126 128 131 134 136 138 140 141 142 144 146 148 150 152 154 156 158 160 163 166 169 172 174 177 179 182 184 187 189 191 194 196 199 201 Table 9. JTAG Boundary Scan Signal Ordering for 208Pin LQFP Package (cont.) DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Pin No. 114 115 117 118 119 120 121 122 126 127 128 129 130 131 132 133 134 135 136 137 138 141 142 143 144 145 146 147 148 150 151 152 153 154 155 156 161 162 163 164 165 166 169 170 Signal A[21]/DRA[6] D[21] A[20]/DRA[7] D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] A[17]/DRA[10] D[17] A[16]/DRA[11] D[16] A[15]/DRA[12] D[15] A[14] D[14] A[13] D[13] A[12] D[12] A[11] D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7] D[7] NBATCHG NEXTPWR BATOK NPOR NMEDCHG/BROM NURESET WAKEUP NPWRFL A[6] D[6] A[5] D[5] A[4] D[4] Type Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O In In In In In In In In Out I/O Out I/O Out I/O Position 204 206 209 211 214 216 219 221 224 226 229 231 234 236 239 241 244 246 249 251 254 256 259 261 264 266 269 271 274 276 279 280 281 282 283 284 285 286 287 289 292 294 297 299 Pin No. 171 172 173 175 176 177 178 179 184 185 186 187 188 189 191 192 193 194 195 196 199 200 201 202 204 205 206 207 208 Signal A[3] D[3] A[2] D[2] A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] nSDRAS[1] nSDRAS[0] nSDCAS[3] nSDCAS[2] nSDCAS[1] nSDCAS[0] NMWE NMOE NCS[0] NCS[1] NCS[2] NCS[3] NCS[4] Type Out I/O Out I/O Out I/O Out I/O Out Out Out Out I/O I/O I/O I/O Out Out I/O I/O I/O I/O Out Out Out Out Out Out Out Position 302 304 307 309 312 314 317 319 322 324 326 328 330 333 336 339 342 344 346 349 352 355 358 360 362 364 366 368 370 Table 9. JTAG Boundary Scan Signal Ordering for 208Pin LQFP Package (cont.) Notes: 1) See EP7312 Users' Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. Table 9. JTAG Boundary Scan Signal Ordering for 208Pin LQFP Package (cont.) DS508PP1 28 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 4. 256-PIN PBGA PACKAGE CHARACTERISTICS 4.1. 256-PIN PBGA PIN DIAGRAM 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T 256-Ball PBGA (Bottom View) Figure 13. 256-Ball Pin Diagram Note: 29 For package specifications, please see Figure 14. DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 4.2. EP7312 256-Ball PBGA (17 x 17 x 1.61-mm Body) Dimensions 0.85 (0.034) 0.05 (.002) 17.00 (0.669) 0.20 (.008) Pin 1 Corner D1 0.40 (0.016) 0.05 (.002) 15.00 (0.590) 0.20 (.008) 30 TYP Pin 1 Indicator 17.00 (0.669) 0.20 (.008) E1 15.00 (0.590) 0.20 (.008) 2 Layer 0.36 (0.014) 0.09 (0.004) TOP VIEW SIDE VIEW D 17.00 (0.669) Pin 1 Corner 1.00 (0.040) 1.00 (0.040) REF E 16 15 14 13 12 11 10 9 8 7 6 5 1.00 (0.040) REF 4 321 A B C D E F G H J K L M N P R 1.00 (0.040) 0.50 R 3 Places 17.00 (0.669) BOTTOM VIEW JEDEC #: MO-151 Ball Diameter: 0.50 mm 0.10 mm Figure 14. 256-Ball PBGA Package Drawing Notes: DS508PP1 1. For pin locations, please see Figure 13. For pin descriptions, See the EP7312 User's Manual. 2. Dimensions are in millimeters (inches), and controlling dimension is millimeter. 3. Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information. 30 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 4.3. 256-Ball PBGA Ball Listing Ball Location A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Name VDDIO nCS[4] nCS[1] SDCLK nSDQM3 DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO nCS[5] VDDIO nCS[3] nMOE/nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO Type Pad power O O O O O O Pad power I/O I/O O Pad power O O Oscillator power Pad ground O Pad power O O Pad power O O O Core power I/O O O O I Pad power I Pad power I Pad ground Pad power Pad ground Pad ground Pad ground Pad power Pad ground Pad ground Pad ground Table 10. 256-Ball PBGA Ball Listing 31 Ball Location C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 Name VDDIO VSSIO VSSIO nPOR nEXTPWR WRITE/nSDRAS EXPRDY VSSIO VDDIO nCS[2] nMWE/nSDWE nSDCS[0] CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] RXD[2] PB[7] TDI WORD VSSIO nCS[0] SDQM[2] FRM A[0] D[5] VSSOSC VSSIO nMEDCHG/nBROM VDDIO D[9] D[10] PB[5] PB[3] VSSIO TXD[2] RUN/CLKEN VSSIO Type Pad power Pad ground Pad ground I I O I Pad ground Pad power O O O O Core ground I/O I I Pad power Pad ground I/O I/O I I I O Pad ground O O O O I/O Oscillator ground Pad ground I Pad power I/O I/O I I Pad ground O O Pad ground Table 10. 256-Ball PBGA Ball Listing (cont.) DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Ball Location F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 Name SDCKE DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO PB[1]/PRDY[2] VDDIO TDO PB[4] PB[6] VSSRTC VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] PA[7] PA[5] VSSIO PA[4] PA[6] PB[0]/PRDY[1] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13]/DRA[14] VSSIO D[14] D[15] PA[3] PA[1] VSSIO Type O O O I/O RTC ground I I Pad ground I/O Pad power I Pad power O I I Core ground RTC ground O I/O RTC ground O O O Pad ground I/O I/O I I Pad ground I I I I RTC ground RTC ground O O O O Pad ground I/O I/O I I Pad ground Table 10. 256-Ball PBGA Ball Listing (cont.) DS508PP1 Ball Location J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 Name PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17]/DRA[10] A[16]/DRA[11] A[15]/DRA[12] A[14]/DRA[13] nTRST D[16] D[17] LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO RXD[1] DSR VDDIO nEINT[1] PE[2]/CLKSEL VSSRTC PD[0]/LEDFLSH VSSRTC COL[6] D[31] VSSRTC A[22]/DRA[5] A[21]/DRA[6] VSSIO A[18]/DRA[9] A[19]/DRA[8] Type I I O I RTC ground RTC ground O O O O I I/O I/O O I Pad ground I I I RTC ground I O I I/O I/O I/O Pad ground Pad power Pad power I I Pad power I I RTC ground I/O Core ground O I/O RTC ground O O Pad ground O O Table 10. 256-Ball PBGA Ball Listing (cont.) 32 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface Ball Location M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 Name nTEST[0] nEINT[2] VDDIO PE[0]/BOOTSEL[0] TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23]/DRA[4] VDDIO A[20]/DRA[7] D[21] nEXTFIQ PE[1]/BOOTSEL[1] VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO Type I I Pad power I I Pad power I/O I/O I O I/O Pad ground O Pad power O I/O I I Pad ground Pad power I/O I/O I/O O O O I/O I/O O Pad ground I/O I/O RTC ground O Pad ground Pad ground Pad power Pad ground Pad ground Pad power Pad ground Pad power Pad ground Ball Location P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Name VSSIO VDDIO VSSIO D[24] VDDIO RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27]/DRA[0] A[25]/DRA[2] VDDIO A[24]/DRA[3] VDDRTC PD[7]/SDQM[1] PD[6]/SDQM[0] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26]/DRA[1] D[25] VSSIO Type Pad ground Pad power Pad ground I/O Pad power I/O Pad power I/O I/O O O Pad power O O O O I/O O O Pad power O RTC power I/O I/O I/O I/O - Core power I/O I O Pad power O I/O O I/O Pad ground Table 10. 256-Ball PBGA Ball Listing (cont.) Table 10. 256-Ball PBGA Ball Listing (cont.) 33 DS508PP1 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 5. ORDERING INFORMATION The order number for the device is: EP7312 -- CV -- A Revision Package Type: V = Low Profile Quad Flat Pack B = Plastic Ball Grid Array (17 mm x 17 mm) Part Number Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version Product Line: Embedded Processor Note: Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. DS508PP1 34 EP7312 High-Performance System-on-Chip with SDRAM and Digital Audio Interface 6. INDEX A absolute maximum ratings 9 AC characteristics 13 C clock speeds list of 1 D DC charactteristics 9 E electrical specifications 9 J JTAG boundary scan signal ordering 27 serial interfaces 3 system design 3 T timing diagrams consecutive memory read cycles with minimum wait states 15 consecutive memory write cycles with minimum wait states 17 SDRAM read cycles SDCAS latency=2 18 SDRAM read cycles SDCAS latency=3 19 SDRAM refresh cycles 20 SDRAM write cycles 19 sequential page mode read cycles with minimum wait states 16 U UART 1-2 M memory interfaces 3 Microwire 2 O operating conditions recommended 9 ordering information how to order 34 P package specifications 208-pin LQFP 23 256-ball PBGA 30 packaging 3 pin diagram 22 pin diagrams 208 LQFP 22 256-pin PBGA 29 pin listing 208-pin LQFP 24 power use description of 1 power management 3 S serial interface Microwire compatible 2 SPI compatible 2 35 DS508PP1