Document Number: 91022 www.vishay.com
S10-1442-Rev. C, 05-Jul-10 1
Power MOSFET
IRF540S, SiHF540S
Vishay Siliconix
FEATURES
•Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• 175 °C Operating Temperature
•Fast Switching
• Ease of Paralleling
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.
Note
a. See device orientation.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 440 μH, Rg = 25 , IAS = 28 A (see fig. 12).
c. ISD 28 A, dI/dt 170 A/μs, VDD VDS, TJ 175 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
PRODUCT SUMMARY
VDS (V) 100
RDS(on) ()V
GS = 10 V 0.077
Qg (Max.) (nC) 72
Qgs (nC) 11
Qgd (nC) 32
Configuration Single
N-Channel MOSFET
G
D
S
D
2
PAK (TO-263)
GD
S
ORDERING INFORMATION
Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHF540S-GE3 SiHF540STRL-GE3aSiHF540STRR-GE3a
Lead (Pb)-free IRF540SPbF IRF540STRLPbFaIRF540STRRPbFa
SiHF540S-E3 SiHF540STL-E3aSiHF540STR-E3a
SnPb IRF540S IRF540STRLaIRF540STRRa
SiHF540S SiHF540STLaSiHF540STRa
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 100 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at 10 V TC = 25 °C ID
28
A
TC = 100 °C 20
Pulsed Drain CurrentaIDM 110
Linear Derating Factor 1.0 W/°C
Linear Derating Factor (PCB Mount)e0.025
Single Pulse Avalanche EnergybEAS 230 mJ
Avalanche CurrentaIAR 28 A
Repetitive Avalanche EnergyaEAR 15 mJ
Maximum Power Dissipation TC = 25 °C PD
150 W
Maximum Power Dissipation (PCB Mount)eTA = 25 °C 3.7
Peak Diode Recovery dV/dtcdV/dt 5.5 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 175 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91022
2S10-1442-Rev. C, 05-Jul-10
IRF540S, SiHF540S
Vishay Siliconix
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -62
°C/W
Maximum Junction-to-Ambient
(PCB Mount)aRthJA -40
Maximum Junction-to-Case (Drain) RthJC -1.0
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 100 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.13 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 100 V, VGS = 0 V - - 25 μA
VDS = 80 V, VGS = 0 V, TJ = 150 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 17 Ab- - 0.077
Forward Transconductance gfs VDS = 50 V, ID = 17 Ab8.7 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
- 1700 -
pFOutput Capacitance Coss - 560 -
Reverse Transfer Capacitance Crss - 120 -
Total Gate Charge Qg
VGS = 10 V ID = 17 A, VDS = 80 V,
see fig. 6 and 13b
--72
nC Gate-Source Charge Qgs --11
Gate-Drain Charge Qgd --32
Turn-On Delay Time td(on)
VDD = 50 V, ID = 17 A,
Rg = 9.1 , RD = 2.9 , see fig. 10b
-11-
ns
Rise Time tr -44-
Turn-Off Delay Time td(off) -53-
Fall Time tf -43-
Internal Drain Inductance LD Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance LS-7.5-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--28
A
Pulsed Diode Forward CurrentaISM - - 110
Body Diode Voltage VSD TJ = 25 °C, IS = 28 A, VGS = 0 Vb--2.5V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 17 A, dI/dt = 100 A/μsb- 180 360 ns
Body Diode Reverse Recovery Charge Qrr -1.32.8μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
D
S
G
S
D
G
Document Number: 91022 www.vishay.com
S10-1442-Rev. C, 05-Jul-10 3
IRF540S, SiHF540S
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 175 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
91022_01
Bottom
To p
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TC = 25 °C
4.5 V
VDS, Drain-to-Source Voltage (V)
ID, Drain Current (A)
100101
102
101
10-1
V
DS,
Drain-to-Source Voltage (V)
I
D
, Drain Current (A)
4.5 V
Bottom
To p
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TC = 175 °C
91022_02
100101
102
101
10-1
20 µs Pulse Width
VDS = 50 V
102
101
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
56 78910
4
25 °C
175 °C
91022_03
I
D
= 17 A
V
GS
= 10 V
3.0
0.0
0.5
1.0
1.5
2.0
2.5
T
J,
Junction Temperature (°C)
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
91022_04
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160180
www.vishay.com Document Number: 91022
4S10-1442-Rev. C, 05-Jul-10
IRF540S, SiHF540S
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
3000
2400
1800
1200
0
600
100101
Capacitance (pF)
VDS, Drain-to-Source Voltage (V)
Ciss
Crss
Coss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
91022_05
Q
G
, Total Gate Charge (nC)
V
GS
, Gate-to-Source Voltage (V)
20
16
12
8
0
4
04020 30
10
I
D
= 17 A
V
DS
= 20 V
V
DS
= 50 V
For test circuit
see figure 13
V
DS
= 80 V
91022_06
70
6050
101
100
VSD, Source-to-Drain Voltage (V)
ISD, Reverse Drain Current (A)
0.4 1.61.20.8
25 °C
150 °C
V
GS
= 0 V
91022_07
10-1
10 µs
100 µs
1 ms
10 ms
Operation in this area limited
by RDS(on)
V
DS
, Drain-to-Source Voltage (V)
I
D
, Drain Current (A)
TC = 25 °C
TJ = 175 °C
Single Pulse
102
0.1
2
5
2
5
1
2
5
10
25
125
10 25
10225
10325
104
91022_08
103
Document Number: 91022 www.vishay.com
S10-1442-Rev. C, 05-Jul-10 5
IRF540S, SiHF540S
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
ID, Drain Current (A)
TC, Case Temperature (°C)
5
10
15
20
25
30
25 1501251007550
91022_09
0
175
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
RD
VGS
Rg
D.U.T.
10 V
+
-
VDS
VDD
VDS
VGS
10
1
0.1
10-2
10-5 10-4 10-3 10-2 0.1 1 10
PDM
t1
t2
t
1
, Rectangular Pulse Duration (s)
Thermal Response (Z
thJC
)
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
D = 0.5
0.2
0.1
0.05
0.02
0.01
91022_11
www.vishay.com Document Number: 91022
6S10-1442-Rev. C, 05-Jul-10
IRF540S, SiHF540S
Vishay Siliconix
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
Rg
IAS
0.01 Ω
tp
D.U.T
L
VDS
+
-VDD
10 V
Vary tp to obtain
required IAS
I
AS
V
DS
V
DD
V
DS
t
p
600
0
100
200
300
400
500
25 150
125
10075
50
Starting T
J
, Junction Temperature (°C)
E
AS
, Single Pulse Energy (mJ)
Bottom
To p
ID
11 A
20 A
28 A
VDD = 25 V
91022_12c
175
QGS QGD
QG
V
G
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91022 www.vishay.com
S10-1442-Rev. C, 05-Jul-10 7
IRF540S, SiHF540S
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91022.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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Vishay
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