Hitachi 16-Bit Microcomputer
H8/3008
Hardware Manual
ADE-602-221
Rev. 1.0
9/14/00
Hitachi, Ltd.
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Preface
The H8/3008 is a high-performance microcontroller that integrates system supporting functions
together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),
an A/D converter, a D/A converter, I/O ports, and other facilities. The two-channel SCI supports a
smart card interface handling ISO/IEC7816-3 character transmission as an expansion function.
Functions have also been added to reduce power consumption in battery-powered applications:
individual modules can be placed in standby mode, and the frequency of the system clock supplied
to the chip can be divided under program control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently for each area, simplifying the connection of different types of memory. Six
MCU operating modes (modes 1 to 4) are provided, offering a choice of initial data bus width and
address space size.
With these features, the H8/3008 enables easy implementation of compact, high-performance
systems.
This manual describes the H8/3008 hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
i
Contents
Section 1 Overview.............................................................................................................. 1
1.1 Overview............................................................................................................................ 1
1.2 Block Diagram.................................................................................................................... 5
1.3 Pin Description................................................................................................................... 6
1.3.1 Pin Arrangement ................................................................................................... 6
1.3.2 Pin Functions......................................................................................................... 9
1.3.3 Pin Assignments in Each Mode ............................................................................ 13
Section 2 CPU........................................................................................................................ 17
2.1 Overview............................................................................................................................ 17
2.1.1 Features ................................................................................................................. 17
2.1.2 Differences from H8/300 CPU.............................................................................. 18
2.2 CPU Operating Modes ....................................................................................................... 18
2.3 Address Space .................................................................................................................... 19
2.4 Register Configuration ....................................................................................................... 20
2.4.1 Overview............................................................................................................... 20
2.4.2 General Registers.................................................................................................. 21
2.4.3 Control Registers................................................................................................... 22
2.4.4 Initial CPU Register Values.................................................................................. 23
2.5 Data Formats ...................................................................................................................... 24
2.5.1 General Register Data Formats ............................................................................. 24
2.5.2 Memory Data Formats .......................................................................................... 25
2.6 Instruction Set .................................................................................................................... 27
2.6.1 Instruction Set Overview ...................................................................................... 27
2.6.2 Instructions and Addressing Modes...................................................................... 28
2.6.3 Tables of Instructions Classified by Function....................................................... 29
2.6.4 Basic Instruction Formats...................................................................................... 38
2.6.5 Notes on Use of Bit Manipulation Instructions .................................................... 39
2.7 Addressing Modes and Effective Address Calculation...................................................... 41
2.7.1 Addressing Modes................................................................................................. 41
2.7.2 Effective Address Calculation............................................................................... 43
2.8 Processing States................................................................................................................ 47
2.8.1 Overview............................................................................................................... 47
2.8.2 Program Execution State....................................................................................... 47
2.8.3 Exception-Handling State ..................................................................................... 48
2.8.4 Exception Handling Operation.............................................................................. 49
2.8.5 Bus-Released State................................................................................................ 50
2.8.6 Reset State............................................................................................................. 50
2.8.7 Power-Down State ................................................................................................ 51
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2.9 Basic Operational Timing .................................................................................................. 51
2.9.1 Overview............................................................................................................... 51
2.9.2 On-Chip Memory Access Timing......................................................................... 51
2.9.3 On-Chip Supporting Module Access Timing........................................................ 52
2.9.4 Access to External Address Space........................................................................ 53
Section 3 MCU Operating Modes.................................................................................... 55
3.1 Overview............................................................................................................................ 55
3.1.1 Operating Mode Selection .................................................................................... 55
3.1.2 Register Configuration.......................................................................................... 56
3.2 Mode Control Register (MDCR)........................................................................................ 56
3.3 System Control Register (SYSCR).................................................................................... 57
3.4 Operating Mode Descriptions ............................................................................................ 59
3.4.1 Mode 1 .................................................................................................................. 59
3.4.2 Mode 2 .................................................................................................................. 59
3.4.3 Mode 3 .................................................................................................................. 59
3.4.4 Mode 4 .................................................................................................................. 60
3.4.5 Modes 5 and 7 ....................................................................................................... 60
3.5 Pin Functions in Each Operating Mode.............................................................................. 60
3.6 Memory Map in Each Operating Mode.............................................................................. 61
3.6.1 Reserved Areas...................................................................................................... 61
Section 4 Exception Handling........................................................................................... 63
4.1 Overview............................................................................................................................ 63
4.1.1 Exception Handling Types and Priority................................................................ 63
4.1.2 Exception Handling Operation.............................................................................. 63
4.1.3 Exception Vector Table ........................................................................................ 64
4.2 Reset................................................................................................................................... 66
4.2.1 Overview............................................................................................................... 66
4.2.2 Reset Sequence...................................................................................................... 66
4.2.3 Interrupts after Reset............................................................................................. 68
4.3 Interrupts ............................................................................................................................ 69
4.4 Trap Instruction.................................................................................................................. 69
4.5 Stack Status after Exception Handling............................................................................... 70
4.6 Notes on Stack Usage......................................................................................................... 71
Section 5 Interrupt Controller............................................................................................ 73
5.1 Overview............................................................................................................................ 73
5.1.1 Features ................................................................................................................. 73
5.1.2 Block Diagram...................................................................................................... 74
5.1.3 Pin Configuration.................................................................................................. 75
5.1.4 Register Configuration.......................................................................................... 75
5.2 Register Descriptions.......................................................................................................... 75
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5.2.1 System Control Register (SYSCR)....................................................................... 75
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB).............................................. 76
5.2.3 IRQ Status Register (ISR)..................................................................................... 81
5.2.4 IRQ Enable Register (IER) ................................................................................... 82
5.2.5 IRQ Sense Control Register (ISCR)...................................................................... 83
5.3 Interrupt Sources ................................................................................................................ 84
5.3.1 External Interrupts................................................................................................. 84
5.3.2 Internal Interrupts.................................................................................................. 85
5.3.3 Interrupt Exception Handling Vector Table.......................................................... 85
5.4 Interrupt Operation............................................................................................................. 89
5.4.1 Interrupt Handling Process.................................................................................... 89
5.4.2 Interrupt Exception Handling Sequence ............................................................... 94
5.4.3 Interrupt Response Time....................................................................................... 95
5.5 Usage Notes........................................................................................................................ 96
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction....................... 96
5.5.2 Instructions that Inhibit Interrupts......................................................................... 97
5.5.3 Interrupts during EEPMOV Instruction Execution............................................... 97
Section 6 Bus Controller..................................................................................................... 99
6.1 Overview............................................................................................................................ 99
6.1.1 Features ................................................................................................................. 99
6.1.2 Block Diagram...................................................................................................... 100
6.1.3 Pin Configuration.................................................................................................. 101
6.1.4 Register Configuration.......................................................................................... 102
6.2 Register Descriptions.......................................................................................................... 102
6.2.1 Bus Width Control Register (ABWCR)................................................................ 102
6.2.2 Access State Control Register (ASTCR) .............................................................. 103
6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 104
6.2.4 Bus Release Control Register (BRCR) ................................................................. 108
6.2.5 Bus Control Register (BCR) ................................................................................. 109
6.2.6 Chip Select Control Register (CSCR)................................................................... 111
6.2.7 Address Control Register (ADRCR)..................................................................... 112
6.3 Operation................................................................................................................................. 113
6.3.1 Area Division........................................................................................................ 113
6.3.2 Bus Specifications................................................................................................. 115
6.3.3 Memory Interfaces................................................................................................ 116
6.3.4 Chip Select Signals................................................................................................ 116
6.3.5 Address Output Method........................................................................................ 117
6.4 Basic Bus Interface............................................................................................................. 119
6.4.1 Overview............................................................................................................... 119
6.4.2 Data Size and Data Alignment.............................................................................. 119
6.4.3 Valid Strobes........................................................................................................ 120
6.4.4 Memory Areas....................................................................................................... 121
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6.4.5 Basic Bus Control Signal Timing.......................................................................... 122
6.4.6 Wait Control.......................................................................................................... 129
6.5 Idle Cycle............................................................................................................................ 131
6.5.1 Operation............................................................................................................... 131
6.5.2 Pin States in Idle Cycle ......................................................................................... 133
6.6 Bus Arbiter ......................................................................................................................... 133
6.6.1 Operation............................................................................................................... 134
6.7 Register and Pin Input Timing ........................................................................................... 136
6.7.1 Register Write Timing .......................................................................................... 136
6.7.2 BREQ Pin Input Timing........................................................................................ 137
Section 7 I/O Ports................................................................................................................ 139
7.1 Overview............................................................................................................................ 139
7.2 Port 4 .................................................................................................................................. 142
7.2.1 Overview............................................................................................................... 142
7.2.2 Register Descriptions............................................................................................ 143
7.3 Port 6 .................................................................................................................................. 145
7.3.1 Overview............................................................................................................... 145
7.3.2 Register Descriptions............................................................................................ 145
7.4 Port 7 .................................................................................................................................. 148
7.4.1 Overview............................................................................................................... 148
7.4.2 Register Description.............................................................................................. 148
7.5 Port 8 .................................................................................................................................. 149
7.5.1 Overview............................................................................................................... 149
7.5.2 Register Descriptions............................................................................................ 150
7.6 Port 9 .................................................................................................................................. 153
7.6.1 Overview............................................................................................................... 153
7.6.2 Register Descriptions............................................................................................ 153
7.7 Port A.................................................................................................................................. 156
7.7.1 Overview............................................................................................................... 156
7.7.2 Register Descriptions............................................................................................ 157
7.8 Port B.................................................................................................................................. 166
7.8.1 Overview............................................................................................................... 166
7.8.2 Register Descriptions............................................................................................ 167
Section 8 16-Bit Timer........................................................................................................ 171
8.1 Overview............................................................................................................................ 171
8.1.1 Features ................................................................................................................. 171
8.1.2 Block Diagrams..................................................................................................... 173
8.1.3 Pin Configuration.................................................................................................. 176
8.1.4 Register Configuration.......................................................................................... 177
8.2 Register Descriptions.......................................................................................................... 178
8.2.1 Timer Start Register (TSTR)................................................................................. 178
v
8.2.2 Timer Synchro Register (TSNC) .......................................................................... 179
8.2.3 Timer Mode Register (TMDR) ............................................................................. 180
8.2.4 Timer Interrupt Status Register A (TISRA).......................................................... 183
8.2.5 Timer Interrupt Status Register B (TISRB).......................................................... 186
8.2.6 Timer Interrupt Status Register C (TISRC).......................................................... 189
8.2.7 Timer Counters (16TCNT).................................................................................... 191
8.2.8 General Registers (GRA, GRB)............................................................................ 192
8.2.9 Timer Control Registers (16TCR) ........................................................................ 193
8.2.10 Timer I/O Control Register (TIOR)...................................................................... 195
8.2.11 Timer Output Level Setting Register C (TOLR) .................................................. 197
8.3 CPU Interface..................................................................................................................... 199
8.3.1 16-Bit Accessible Registers .................................................................................. 199
8.3.2 8-Bit Accessible Registers .................................................................................... 201
8.4 Operation............................................................................................................................ 202
8.4.1 Overview............................................................................................................... 202
8.4.2 Basic Functions ..................................................................................................... 202
8.4.3 Synchronization .................................................................................................... 210
8.4.4 PWM Mode........................................................................................................... 212
8.4.5 Phase Counting Mode ........................................................................................... 216
8.4.6 16-Bit Timer Output Timing................................................................................. 218
8.5 Interrupts ............................................................................................................................ 219
8.5.1 Setting of Status Flags........................................................................................... 219
8.5.2 Timing of Clearing of Status Flags ....................................................................... 221
8.5.3 Interrupt Sources ................................................................................................... 222
8.6 Usage Notes........................................................................................................................ 223
Section 9 8-Bit Timers ........................................................................................................ 235
9.1 Overview............................................................................................................................ 235
9.1.1 Features ................................................................................................................. 235
9.1.2 Block Diagram...................................................................................................... 237
9.1.3 Pin Configuration.................................................................................................. 238
9.1.4 Register Configuration.......................................................................................... 239
9.2 Register Descriptions.......................................................................................................... 240
9.2.1 Timer Counters (8TCNT)...................................................................................... 240
9.2.2 Time Constant Registers A (TCORA).................................................................. 241
9.2.3 Time Constant Registers B (TCORB) .................................................................. 242
9.2.4 Timer Control Register (8TCR)............................................................................ 243
9.2.5 Timer Control/Status Registers (8TCSR) ............................................................. 246
9.3 CPU Interface..................................................................................................................... 251
9.3.1 8-Bit Registers....................................................................................................... 251
9.4 Operation............................................................................................................................ 253
9.4.1 8TCNT Count Timing........................................................................................... 253
9.4.2 Compare Match Timing........................................................................................ 254
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9.4.3 Input Capture Signal Timing................................................................................. 255
9.4.4 Timing of Status Flag Setting................................................................................ 256
9.4.5 Operation with Cascaded Connection................................................................... 257
9.4.6 Input Capture Setting ............................................................................................ 260
9.5 Interrupt.............................................................................................................................. 261
9.5.1 Interrupt Sources ................................................................................................... 261
9.5.2 A/D Converter Activation..................................................................................... 262
9.6 8-Bit Timer Application Example...................................................................................... 262
9.7 Usage Notes........................................................................................................................ 263
9.7.1 Contention between 8TCNT Write and Clear....................................................... 263
9.7.2 Contention between 8TCNT Write and Increment ............................................... 264
9.7.3 Contention between TCOR Write and Compare Match ....................................... 265
9.7.4 Contention between TCOR Read and Input Capture............................................ 266
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 267
9.7.6 Contention between TCOR Write and Input Capture........................................... 268
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection) ......................................................................................... 269
9.7.8 Contention between Compare Matches A and B.................................................. 270
9.7.9 8TCNT Operation and Internal Clock Source Switchover ................................... 270
Section 10 Programmable Timing Pattern Controller (TPC).................................. 273
10.1 Overview............................................................................................................................ 273
10.1.1 Features ................................................................................................................. 273
10.1.2 Block Diagram...................................................................................................... 274
10.1.3 Pin Configuration.................................................................................................. 275
10.1.4 Register Configuration.......................................................................................... 276
10.2 Register Descriptions.......................................................................................................... 277
10.2.1 Port A Data Direction Register (PADDR)............................................................ 277
10.2.2 Port A Data Register (PADR)............................................................................... 277
10.2.3 Port B Data Direction Register (PBDDR) ............................................................ 278
10.2.4 Port B Data Register (PBDR)................................................................................ 278
10.2.5 Next Data Register A (NDRA) ............................................................................. 279
10.2.6 Next Data Register B (NDRB).............................................................................. 281
10.2.7 Next Data Enable Register A (NDERA)............................................................... 283
10.2.8 Next Data Enable Register B (NDERB) ............................................................... 284
10.2.9 TPC Output Control Register (TPCR).................................................................. 285
10.2.10 TPC Output Mode Register (TPMR).................................................................... 287
10.3 Operation............................................................................................................................ 289
10.3.1 Overview............................................................................................................... 289
10.3.2 Output Timing....................................................................................................... 290
10.3.3 Normal TPC Output.............................................................................................. 291
10.3.4 Non-Overlapping TPC Output.............................................................................. 293
10.3.5 TPC Output Triggering by Input Capture ............................................................. 295
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10.4 Usage Notes........................................................................................................................ 296
10.4.1 Operation of TPC Output Pins.............................................................................. 296
10.4.2 Note on Non-Overlapping Output......................................................................... 296
Section 11 Watchdog Timer.............................................................................................. 299
11.1 Overview............................................................................................................................ 299
11.1.1 Features ................................................................................................................. 299
11.1.2 Block Diagram...................................................................................................... 300
11.1.3 Pin Configuration.................................................................................................. 300
11.1.4 Register Configuration.......................................................................................... 301
11.2 Register Descriptions.......................................................................................................... 301
11.2.1 Timer Counter (TCNT)......................................................................................... 301
11.2.2 Timer Control/Status Register (TCSR)................................................................. 302
11.2.3 Reset Control/Status Register (RSTCSR)............................................................. 304
11.2.4 Notes on Register Access...................................................................................... 305
11.3 Operation............................................................................................................................ 307
11.3.1 Watchdog Timer Operation .................................................................................. 307
11.3.2 Interval Timer Operation ...................................................................................... 308
11.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 308
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ................................... 309
11.4 Interrupts ............................................................................................................................ 310
11.5 Usage Notes........................................................................................................................ 310
Section 12 Serial Communication Interface................................................................. 311
12.1 Overview............................................................................................................................ 311
12.1.1 Features ................................................................................................................. 311
12.1.2 Block Diagram...................................................................................................... 313
12.1.3 Pin Configuration.................................................................................................. 314
12.1.4 Register Configuration.......................................................................................... 315
12.2 Register Descriptions.......................................................................................................... 316
12.2.1 Receive Shift Register (RSR)................................................................................ 316
12.2.2 Receive Data Register (RDR) ............................................................................... 316
12.2.3 Transmit Shift Register (TSR).............................................................................. 317
12.2.4 Transmit Data Register (TDR).............................................................................. 317
12.2.5 Serial Mode Register (SMR)................................................................................. 318
12.2.6 Serial Control Register (SCR)............................................................................... 321
12.2.7 Serial Status Register (SSR).................................................................................. 325
12.2.8 Bit Rate Register (BRR)........................................................................................ 330
12.3 Operation............................................................................................................................ 338
12.3.1 Overview............................................................................................................... 338
12.3.2 Operation in Asynchronous Mode........................................................................ 341
12.3.3 Multiprocessor Communication............................................................................ 350
12.3.4 Synchronous Operation......................................................................................... 357
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12.4 SCI Interrupts ..................................................................................................................... 365
12.5 Usage Notes........................................................................................................................ 366
12.5.1 Notes on Use of SCI.............................................................................................. 366
Section 13 Smart Card Interface ...................................................................................... 371
13.1 Overview............................................................................................................................ 371
13.1.1 Features ................................................................................................................. 371
13.1.2 Block Diagram...................................................................................................... 372
13.1.3 Pin Configuration.................................................................................................. 372
13.1.4 Register Configuration.......................................................................................... 373
13.2 Register Descriptions.......................................................................................................... 374
13.2.1 Smart Card Mode Register (SCMR)..................................................................... 374
13.2.2 Serial Status Register (SSR).................................................................................. 376
13.2.3 Serial Mode Register (SMR)................................................................................. 377
13.2.4 Serial Control Register (SCR)............................................................................... 378
13.3 Operation............................................................................................................................ 379
13.3.1 Overview............................................................................................................... 379
13.3.2 Pin Connections .................................................................................................... 379
13.3.3 Data Format........................................................................................................... 380
13.3.4 Register Settings.................................................................................................... 382
13.3.5 Clock ..................................................................................................................... 384
13.3.6 Transmitting and Receiving Data.......................................................................... 386
13.4 Usage Notes........................................................................................................................ 393
Section 14 A/D Converter.................................................................................................. 397
14.1 Overview............................................................................................................................ 397
14.1.1 Features ................................................................................................................. 397
14.1.2 Block Diagram...................................................................................................... 398
14.1.3 Pin Configuration.................................................................................................. 399
14.1.4 Register Configuration.......................................................................................... 400
14.2 Register Descriptions.......................................................................................................... 400
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 400
14.2.2 A/D Control/Status Register (ADCSR) ................................................................ 401
14.2.3 A/D Control Register (ADCR).............................................................................. 403
14.3 CPU Interface..................................................................................................................... 404
14.4 Operation............................................................................................................................ 406
14.4.1 Single Mode (SCAN = 0)...................................................................................... 406
14.4.2 Scan Mode (SCAN = 1)........................................................................................ 408
14.4.3 Input Sampling and A/D Conversion Time .......................................................... 410
14.4.4 External Trigger Input Timing.............................................................................. 411
14.5 Interrupts ............................................................................................................................ 412
14.6 Usage Notes........................................................................................................................ 412
ix
Section 15 D/A Converter.................................................................................................. 417
15.1 Overview............................................................................................................................ 417
15.1.1 Features ................................................................................................................. 417
15.1.2 Block Diagram...................................................................................................... 418
15.1.3 Pin Configuration.................................................................................................. 419
15.1.4 Register Configuration.......................................................................................... 419
15.2 Register Descriptions.......................................................................................................... 420
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 420
15.2.2 D/A Control Register (DACR).............................................................................. 420
15.2.3 D/A Standby Control Register (DASTCR)........................................................... 422
15.3 Operation............................................................................................................................ 422
15.4 D/A Output Control............................................................................................................ 424
Section 16 RAM.................................................................................................................... 425
16.1 Overview............................................................................................................................ 425
16.1.1 Block Diagram...................................................................................................... 426
16.1.2 Register Configuration.......................................................................................... 426
16.2 System Control Register (SYSCR).................................................................................... 427
16.3 Operation............................................................................................................................ 428
Section 17 Clock Pulse Generator ................................................................................... 429
17.1 Overview............................................................................................................................ 429
17.1.1 Block Diagram...................................................................................................... 429
17.2 Oscillator Circuit................................................................................................................ 430
17.2.1 Connecting a Crystal Resonator............................................................................ 430
17.2.2 External Clock Input ............................................................................................. 432
17.3 Duty Adjustment Circuit.................................................................................................... 434
17.4 Prescalers............................................................................................................................ 434
17.5 Frequency Divider.............................................................................................................. 434
17.5.1 Register Configuration.......................................................................................... 435
17.5.2 Division Control Register (DIVCR) ..................................................................... 435
17.5.3 Usage Notes .......................................................................................................... 436
Section 18 Power-Down State.......................................................................................... 437
18.1 Overview............................................................................................................................ 437
18.2 Register Configuration ....................................................................................................... 439
18.2.1 System Control Register (SYSCR)....................................................................... 439
18.2.2 Module Standby Control Register H (MSTCRH)................................................. 440
18.2.3 Module Standby Control Register L (MSTCRL).................................................. 442
18.3 Sleep Mode......................................................................................................................... 444
18.3.1 Transition to Sleep Mode...................................................................................... 444
18.3.2 Exit from Sleep Mode ........................................................................................... 444
18.4 Software Standby Mode..................................................................................................... 444
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18.4.1 Transition to Software Standby Mode .................................................................. 444
18.4.2 Exit from Software Standby Mode........................................................................ 445
18.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 445
18.4.4 Sample Application of Software Standby Mode................................................... 447
18.4.5 Note....................................................................................................................... 447
18.5 Hardware Standby Mode.................................................................................................... 448
18.5.1 Transition to Hardware Standby Mode................................................................. 448
18.5.2 Exit from Hardware Standby Mode...................................................................... 448
18.5.3 Timing for Hardware Standby Mode.................................................................... 448
18.6 Module Standby Function.................................................................................................. 449
18.6.1 Module Standby Timing........................................................................................ 449
18.6.2 Read/Write in Module Standby............................................................................. 449
18.6.3 Usage Notes .......................................................................................................... 449
18.7 System Clock Output Disabling Function.......................................................................... 450
Section 19 Electrical Characteristics — Preliminary —.......................................... 451
19.1 Absolute Maximum Ratings............................................................................................... 451
19.2 DC Characteristics.............................................................................................................. 452
19.3 AC Characteristics.............................................................................................................. 462
19.4 A/D Conversion Characteristics......................................................................................... 468
19.5 D/A Conversion Characteristics......................................................................................... 470
19.6 Operational Timing ............................................................................................................ 471
19.6.1 Clock Timing ........................................................................................................ 471
19.6.2 Control Signal Timing .......................................................................................... 472
19.6.3 Bus Timing............................................................................................................ 474
19.6.4 TPC and I/O Port Timing...................................................................................... 478
19.6.5 Timer Input/Output Timing .................................................................................. 478
19.6.6 SCI Input/Output Timing...................................................................................... 479
Appendix A Instruction Set................................................................................................ 481
A.1 Instruction List.................................................................................................................... 481
A.2 Operation Code Maps......................................................................................................... 496
A.3 Number of States Required for Execution.......................................................................... 499
Appendix B Internal I/O Registers.................................................................................. 508
B.1 Address List........................................................................................................................ 508
B.2 Functions............................................................................................................................ 523
Appendix C I/O Port Block Diagrams............................................................................ 587
C.1 Port 4 Block Diagram......................................................................................................... 587
C.2 Port 6 Block Diagrams ....................................................................................................... 588
C.3 Port 7 Block Diagrams ....................................................................................................... 592
C.4 Port 8 Block Diagrams ....................................................................................................... 593
xi
C.5 Port 9 Block Diagrams ....................................................................................................... 597
C.6 Port A Block Diagrams...................................................................................................... 603
C.7 Port B Block Diagrams ...................................................................................................... 606
Appendix D Pin States ........................................................................................................ 612
D.1 Port States in Each Mode ................................................................................................... 612
D.2 Pin States at Reset .............................................................................................................. 615
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode................................................................................................ 617
Appendix F Product Code Lineup ................................................................................... 618
Appendix G Package Dimensions.................................................................................... 619
Appendix H Comparison of H8/300H Series Product Specifications.................. 622
H.1 Differences between H8/3067 and H8/3062 Series, H8/3048 Series,
H8/3006 and H8/3007, and H8/3008.................................................................................. 622
H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)........ 625
1
Section 1 Overview
1.1 Overview
The H8/3008 is a microcontroller (MCU) that integrates system supporting functions together with
an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include RAM, a 16-bit timer, an 8-bit timer, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities.
Six MCU operating modes offer a choice of bus width and address space size. The modes (modes
1 to 4) include four expanded modes.
Table 1.1 summarizes the features of the H8/3008.
xii
2
Table 1.1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
High-speed operation
• Maximum clock rate: 25 MHz
• Add/subtract: 80 ns
• Multiply/divide: 560 ns
16-Mbyte address space
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
Memory H8/3008
• RAM: 4 kbytes
Interrupt
controller • Seven external interrupt pins: NMI, IRQ0 to IRQ5
• 27 internal interrupts
• Three selectable interrupt priority levels
Bus controller • Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of two wait modes
• Number of program wait states selectable for each area
• Bus arbitration function
• Two address update modes
3
Feature Description
16-bit timer,
3 channels • Three 16-bit timer channels, capable of processing up to six pulse outputs or
six pulse inputs
• 16-bit timer counter (channels 0 to 2)
• Two multiplexed output compare/input capture pins (channels 0 to 2)
• Operation can be synchronized (channels 0 to 2)
• PWM mode available (channels 0 to 2)
• Phase counting mode available (channel 2)
8-bit timer,
4 channels • 8-bit up-counter (external event count capability)
• Two time constant registers
• Two channels can be connected
Programmable
timing pattern
controller (TPC)
• Maximum 16-bit pulse output, using 16-bit timer as time base
• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
• Non-overlap mode available
Watchdog
timer (WDT),
1 channel
• Internal reset signal can be generated by overflow
• Reset signal can be output externally
• Usable as an interval timer
Serial
communication
interface (SCI),
2 channels
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
• Smart card interface functions added
A/D converter • Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• A/D conversion can be started by an external trigger or 8-bit timer compare-
match
D/A converter • Resolution: 8 bits
• Two channels
• D/A outputs can be sustained in software standby mode
I/O ports • 35 input/output pins
• 12 input-only pins
4
Feature Description
Operating modes Six MCU operating modes
Mode Address
Space Address
Pins Initial Bus
Width Max. Bus Width
Mode 1 1 Mbyte A19 to A08 bits 16 bits
Mode 2 1 Mbyte A19 to A016 bits 16 bits
Mode 3 16 Mbytes A23 to A08 bits 16 bits
Mode 4 16 Mbytes A23 to A016 bits 16 bits
• On-chip ROM is disabled in modes 1 to 4
Power-down
state • Sleep mode
• Software standby mode
• Hardware standby mode
• Module standby function
• Programmable system clock frequency division
Other features • On-chip clock pulse generator
Product lineup Product Type Model Package
(Hitachi Package Code)
H8/3008 5 V operation HD6413008F 100-pin QFP (FP-100B)
HD6413008TE 100-pin TQFP (TFP-100B)
HD6413008FP 100-pin QFP (FP-100A)
3 V operation HD6413008VF 100-pin QFP (FP-100B)
HD6413008VTE 100-pin TQFP (TFP-100B)
HD6413008VFP 100-pin QFP (FP-100A)
5
1.2 Block Diagram
Figure 1.1 shows an internal block diagram.
V
V
V
V
V
V
V
V
V
CL*
CC
CC
SS
SS
SS
SS
SS
SS
D
D
D
D
D
D
D
D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Port 3 Port 4
Port 5Port 9
A
A
A
A
19
18
17
16
A
A
A
A
A
A
A
A
P9 /SCK /IRQ
P9 /SCK /IRQ
P9 /RxD
P9 /RxD
P9 /TxD
P9 /TxD
5
4
3
2
1
0
1
0
1
0
1
0
5
4
DA1/AN7/P77
DA0/AN6/P76
AN5/P75
AN4/P74
AN3/P73
AN2/P72
AN1/P71
AN0/P70
Port 7
A20/TIOCB2/TP7/PA7
A21/TIOCA2/TP6/PA6
A22/TIOCB1/TP5/PA5
A23/TIOCA1/TP4/PA4
TCLKD/TIOCB0/TP3/PA3
TCLKC/TIOCA0/TP2/PA2
TCLKB/TP1/PA1
TCLKA/TP0/PA0
Port A
TP15/PB7
TP14/PB6
TP13/PB5
TP12/PB4
CS4/TMIO3/TP11/PB3
CS5/TMO2/TP10/PB2
CS6/TMIO1/TP9/PB1
CS7/TMO0/TP8/PB0
Port 8
CS0/P84
ADTRG/CS1/IRQ3/P83
CS2/IRQ2/P82
CS3/IRQ1/P81
IRQ0/P80
MD
MD
MD
EXTAL
XTAL
STBY
RES
RESO
NMI
2
1
0
H8/300H CPU
Clock pulse
generator
Interrupt controller
Serial communication
interface
(SCI) 2 channels
×
Watchdog timer
(WDT)
15
14
13
12
11
10
9
8
Address bus
Data bus (upper)
Data bus (lower)
15
14
13
12
11
10
9
8
Port 2
A
A
A
A
A
A
A
A
Port 1
7
6
5
4
3
2
1
0
φ/P67
LWR
HWR
RD
AS
BACK/P62
BREQ/P61
WAIT/P60
RAM
16-bit timer unit
8-bit timer unit
A/D converter
D/A converter
Port 6
Bus controller
Programmable
timing pattern
controller (TPC)
Port B
VREF
AVCC
AVSS
Note: *The 5 V operation models have a VCL pin, and require the connection of an external capacitor.
Figure 1.1 Block Diagram
6
1.3 Pin Description
1.3.1 Pin Arrangement
The pin arrangement of the H8/3008 is shown in figures 1.2 and 1.3. Differences in the H8/3008
pin arrangements are shown in table 1.2. Except for the differences shown in table 1.2, the pin
arrangements are the same.
Table 1.2 Comparison of H8/3008 Pin Arrangements
H8/3064F-ZTAT H8/3062F-ZTAT
A-Mask Version H8/3008 ROMless
Pin Operation Model
Package Number 5 V 3 V 5 V 3 V 5 V 3 V
FP-100B 1 VCL VCC VCL VCC VCL VCC
(TFP-100B) 10 FWE FWE FWE FWE RESO RESO
FP-100A 3 VCL VCC VCL VCC VCL VCC
12 FWE FWE FWE FWE RESO RESO
7
VCC/VCL*
CS7/TMO0/TP8/PB0
CS6/ TMIO1/TP9/PB1
CS5/TMO2/TP10/PB2
CS4/ TMIO3/TP11/PB3
TP12/PB4
TP13/PB5
TP14/PB6
TP15/PB7
0
1
2
3
4
5
0
1
2
3
4
5
6
RESO
VSS
TxD /P9
TxD /P9
RxD /P9
RxD /P9
IRQ /SCK /P9
IRQ /SCK /P9
D /P4
D /P4
D /P4
D /P4
D /P4
D /P4
D /P4
MD
MD
MD
LWR
HWR
RD
AS
V
XTAL
EXTAL
V
NMI
RES
STBY
P67/φ
P6 /BACK
P6 /BREQ
P6 /WAIT
V
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
0
1
0
1
0
1
0
1
2
3
4
5
6
4
5
2
1
0
2
1
0
CS2/IRQ2/P82
ADTRG/CS1/IRQ3/P83
CS0/P84
VSS
TCLKA/TP0/PA0
TCLKB/TP1/PA1
TCLKC/TIOCA0/TP2/PA2
TCLKD/TIOCB0/TP3/PA3
A23/TIOCA1/TP4/PA4
A22/TIOCB1/TP5/PA5
A21/TIOCA2/TP6/PA6
A20/TIOCB2/TP7/PA7
/P8 /IRQCS /P8 IRQ
AV
P7 /AN /DA
P7 /AN /DA
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
V
AV
1
0
7
6
5
4
3
2
1
0
1
0
7
6
5
4
3
2
1
0
Top view
(FP-100B,TFP-100B)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
CC
SS
SS
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SS
REF
CC
1
0
VSS
3
Note: *VCL pin in 5 V operation models, VCC pin in 3 V operation models.
An external capacitor must be connected to the VCL pin.
1
0.1 µF
A13
A12
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VCC
D15
D14
D13
D12
D11
D10
D9
D8
D7/P47
A19
A18
Figure 1.2 Pin Arrangement of H8/3008 (FP-100B or TFP-100B Package, Top View)
8
P7
0
/AN
0
V
REF
AV
CC
MD
2
MD
1
MD
0
LWR
HWR
RD
AS
V
CC
XTAL
EXTAL
V
SS
NMI
RES
STBY
P6
7
/φ
P6
2
/BACK
P6
1
/BREQ
P6
0
/WAIT
V
SS
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A /TIOCA /TP /PA
A /TIOCB /TP /PA
CS /TMO /TP /PB
CS /TMIO /TP /PB
CS /TMO /TP /PB
CS /TMIO /TP /PB
TP /PB
TP /PB
TP /PB
TP /PB
RESO
TxD /P9
TxD /P9
RxD /P9
RxD /P9
IRQ /SCK /P9
IRQ /SCK /P9
D /P4
D /P4
D /P4
D /P4
D /P4
D /P4
D /P4
D /P4
D8
D9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
P80/IRQ0
P81/IRQ1/CS3
P82/IRQ2/CS2
P83/IRQ3/CS1/ADTRG
P84/CS0
VSS
PA0/TP0/TCLKA
PA1/TP1/TCLKB
PA2/TP2/TIOCA0/TCLKC
PA3/TP3/TIOCB0/TCLKD
PA4/TP4/TIOCA1/A23
PA5/TP5/TIOCB1/A22
21 26 6
20 27 7
08 0
191
11
3
43
15 7
4
12 5
13 6
14
7
2102
5
6
SS
0
1
0
1
404
515
0
1
0
1
2
3
0
1
2
3
2
3
4
5
6
4
5
6
7
7
VCC/VCL*
VSS
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D10
11
12
13
15
14
VCC
VSS
0
1
2
3
4
5
6
7
8
9
10
11
80
79
78
77
76
V
Top view
(FP-100A)
3
0.1 µF
Note: *VCL pin in 5 V operation models, VCC pin in 3 V operation models.
An external capacitor must be connected to the VCL pin.
Figure 1.3 Pin Arrangement of H8/3008 (FP-100A Package, Top View)
9
1.3.2 Pin Functions
Table 1.3 summarizes the pin functions. The 5 V operation models have a VCL pin, and require the
connection of an external capacitor.
Table 1.3 Pin Functions
Pin No.
Type Symbol FP-100B
TFP-100B FP-100A I/O Name and Function
Power VCC 1, 35,
68 3, 37,
70 Input Power: For connection to the power supply.
Connect all VCC pins to the system power
supply.
VSS 11, 22,
44, 57,
65, 92
13, 24,
46, 59,
67, 94
Input Ground: For connection to ground (0 V).
Connect all VSS pins to the 0-V system power
supply.
Internal
step-down
pin
VCL 1* 3* Output Connect an external capacitor between this
pin and GND (0 V). Do not connect to VCC.
0.1 µF
VCL
Clock XTAL 67 69 Input For connection to a crystal resonator.
For examples of crystal resonator and external
clock input, see section 20, Clock Pulse
Generator.
EXTAL 66 68 Input For connection to a crystal resonator or input
of an external clock signal. For examples of
crystal resonator and external clock input, see
section 20, Clock Pulse Generator.
φ61 63 Output System clock: Supplies the system clock to
external devices.
Operating
mode
control
MD2 to
MD0
75 to 73 77 to 75 Input Mode 2 to mode 0: For setting the operating
mode, as follows. Inputs at these pins must
not be changed during operation.
MD2MD1MD0Operating Mode
0 0 0 Setting prohibited
0 0 1 Mode 1
0 1 0 Mode 2
0 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Setting prohibited
1 1 0 Setting prohibited
1 1 1 Setting prohibited
10
Pin No.
Type Symbol FP-100B
TFP-100B FP-100A I/O Name and Function
System
control RES 63 65 Input Reset input: When driven low, this pin resets
the chip. This pin must be driven low at power-
up.
RESO 10 12 Output Reset output: Outputs the reset signal
generated by the watchdog timer to external
devices
STBY 62 64 Input Standby: When driven low, this pin forces
a transition to hardware standby mode
BREQ 59 61 Input Bus request: Used by an external bus master
to request the bus right
BACK 60 62 Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus
master
Interrupts NMI 64 66 Input Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ5 to
IRQ0
17, 16,
90 to 87 19, 18,
92 to 89 Input Interrupt request 5 to 0: Maskable interrupt
request pins
Address
bus A23 to A097 to 100,
56 to 45,
43 to 36
99, 100,
1, 2,
58 to 47,
45 to 38
Output Address bus: Outputs address signals
Data bus D15 to D034 to 23,
21 to 18 36 to 25,
23 to 20 Input/
output Data bus: Bidirectional data bus
Bus
control CS7 to
CS0
2 to 5,
88 to 91 4 to 7,
90 to 93 Output Chip select: Select signals for areas 7 to 0
AS 69 71 Output Address strobe: Goes low to indicate valid
address output on the address bus
RD 70 72 Output Read: Goes low to indicate reading from the
external address space
HWR 71 73 Output High write: Goes low to indicate writing to the
external address space; indicates valid data
on the upper data bus (D15 to D8).
LWR 72 74 Output Low write: Goes low to indicate writing to the
external address space; indicates valid data
on the lower data bus (D7 to D0).
WAIT 58 60 Input Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
11
Pin No.
Type Symbol FP-100B
TFP-100B FP-100A I/O Name and Function
16-bit
timer TCLKD to
TCLKA 96 to 93 98 to95 Input Clock input D to A: External clock inputs
TIOCA2 to
TIOCA0
99, 97, 95 1, 99, 97 Input/
output Input capture/output compare A2 to A0:
GRA2 to GRA0 output compare or input
capture, or PWM output
TIOCB2 to
TIOCB0
100, 98,
96 2, 100,
98 Input/
output Input capture/output compare B2 to B0:
GRB2 to GRB0 output compare or input
capture
8-bit timer TMO0,
TMO2
2, 4 4, 6 Output Compare match output: Compare match
output pins
TMIO1,
TMIO3
3, 5 5, 7 Input/
output Input capture input/compare match output:
Input capture input or compare match output
pins
TCLKD to
TCLKA 96 to 93 98 to 95 Input Counter external clock input: These pins
input an external clock to the counters.
Program-
mable
timing
pattern
controller
(TPC)
TP15 to
TP0
9 to 2,
100 to 93 11 to 4,
2, 1,
100 to
95
Output TPC output 15 to 0: Pulse output
Serial
communi- TxD1,
TxD0
13, 12 15, 14 Output Transmit data (channels 0, 1): SCI data
output
cation
interface
(SCI)
RxD1,
RxD0
15, 14 17, 16 Input Receive data (channels 0, 1): SCI data input
SCK1,
SCK0
17, 16 19, 18 Input/
output Serial clock (channels 0, 1): SCI clock
input/output
A/D
converter AN7 to
AN0
85 to 78 87 to 80 Input Analog 7 to 0: Analog input pins
ADTRG 90 92 Input A/D conversion external trigger input:
External trigger input for starting A/D
conversion
D/A
converter DA1, DA085, 84 87, 86 Output Analog output: Analog output from the
D/A converter
Analog
power
supply
AVCC 76 78 Input Power supply pin for the A/D and D/A
converters. Connect to the system power
supply when not using the A/D and D/A
converters.
12
Pin No.
Type Symbol FP-100B
TFP-100B FP-100A I/O Name and Function
Analog
power AVSS 86 88 Input Ground pin for the A/D and D/A converters.
Connect to system ground (0 V).
supply VREF 77 79 Input Reference voltage input pin for the A/D and
D/A converters. Connect to the system power
supply when not using the A/D and
D/A converters.
I/O ports P47 to P4026 to 23,
21 to 18 28 to 25,
23 to 20 Input/
output Port 4: Eight input/output pins. The direction
of each pin can be selected in the port 4 data
direction register (P4DDR).
P67,
P65 to P60
61,
60 to 58 63,
62 to 60 Input/
output Port 6: Eight input/output pins. The direction
of each pin can be selected in the port 6 data
direction register (P6DDR).
P77 to P7085 to 78 87 to 80 Input Port 7: Eight input pins
P84 to P8091 to 87 93 to 89 Input/
output Port 8: Five input/output pins. The direction of
each pin can be selected in the port 8 data
direction register (P8DDR).
P95 to P9017 to 12 19 to 14 Input/
output Port 9: Six input/output pins. The direction of
each pin can be selected in the port 9 data
direction register (P9DDR).
PA7 to
PA0
100 to 93 2, 1,
100 to
95
Input/
output Port A: Eight input/output pins. The direction
of each pin can be selected in the port A data
direction register (PADDR).
PB7 to
PB0
9 to 2 11 to 4 Input/
output Port B: Eight input/output pins. The direction
of each pin can be selected in the port B data
direction register (PBDDR).
Note: * In 5 V operation models. This is a VCC pin in 3 V operation models.
13
1.3.3 Pin Assignments in Each Mode
Table 1.4 lists the pin assignments in each mode.
Table 1.4 Pin Assignments in Each Mode (FP-100B, TFP-100B, or FP-100A)
Pin No. Pin Name
FP-100B
TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4
13 v
CC (vCL)*3vCC vCC vCC
24 PB
0/TP8/
TMO0/CS7
PB0/TP8/
TMO0/CS7
PB0/TP8/
TMO0/CS7
PB0/TP8/
TMO0/CS7
35 PB
1/TP9/
TMIO1/CS6
PB1/TP9/
TMIO1/CS6
PB1/TP9/
TMIO1/CS6
PB1/TP9/
TMIO1/CS6
46 PB
2/TP10/
TMO2/CS5
PB2/TP10/
TMO2/CS5
PB2/TP10/
TMO2/CS5
PB2/TP10/
TMO2/CS5
57 PB
3/TP11/
TMIO3/CS4
PB3/TP11/
TMIO3/CS4
PB3/TP11/
TMIO3/CS4
PB3/TP11/
TMIO3/CS4
68 PB
4/TP12 PB4/TP12 PB4/TP12 PB4/TP12
79 PB
5/TP13 PB5/TP13 PB5/TP13 PB5/TP13
810PB
6/TP14 PB6/TP14 PB6/TP14 PB6/TP14
911PB
7/TP15 PB7/TP15 PB7/TP15 PB7/TP15
10 12 RESO RESO RESO RESO
11 13 VSS VSS VSS VSS
12 14 P90/TxD0P90/TxD0P90/TxD0P90/TxD0
13 15 P91/TxD1P91/TxD1P91/TxD1P91/TxD1
14 16 P92/RxD0P92/RxD0P92/RxD0P92/RxD0
15 17 P93/RxD1P93/RxD1P93/RxD1P93/RxD1
16 18 P94 /SCK0/
IRQ4
P94 /SCK0/
IRQ4
P94 /SCK0/
IRQ4
P94 /SCK0/
IRQ4
17 19 P95 /SCK1/
IRQ5
P95 /SCK1/
IRQ5
P95 /SCK1/
IRQ5
P95 /SCK1/
IRQ5
18 20 P40/D0*1P40/D0*2P40/D0*1P40/D0*2
19 21 P41/D1*1P41/D1*2P41/D1*1P41/D1*2
20 22 P42/D2*1P42/D2*2P42/D2*1P42/D2*2
21 23 P43/D3*1P43/D3*2P43/D3*1P43/D3*2
22 24 VSS VSS VSS VSS
23 25 P44/D4*1P44/D4*2P44/D4*1P44/D4*2
24 26 P45/D5*1P45/D5*2P45/D5*1P45/D5*2
25 27 P46/D6*1P46/D6*2P46/D6*1P46/D6*2
14
Pin No. Pin Name
FP-100B
TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4
26 28 P47/D7*1P47/D7*2P47/D7*1P47/D7*2
27 29 D8D8D8D8
28 30 D9D9D9D9
29 31 D10 D10 D10 D10
30 32 D11 D11 D11 D11
31 33 D12 D12 D12 D12
32 34 D13 D13 D13 D13
33 35 D14 D14 D14 D14
34 36 D15 D15 D15 D15
35 37 VCC VCC VCC VCC
36 38 A0A0A0A0
37 39 A1A1A1A1
38 40 A2A2A2A2
39 41 A3A3A3A3
40 42 A4A4A4A4
41 43 A5A5A5A5
42 44 A6A6A6A6
43 45 A7A7A7A7
44 46 VSS VSS VSS VSS
45 47 A8A8A8A8
46 48 A9A9A9A9
47 49 A10 A10 A10 A10
48 50 A11 A11 A11 A11
49 51 A12 A12 A12 A12
50 52 A13 A13 A13 A13
51 53 A14 A14 A14 A14
52 54 A15 A15 A15 A15
53 55 A16 A16 A16 A16
54 56 A17 A17 A17 A17
55 57 A18 A18 A18 A18
56 58 A19 A19 A19 A19
57 59 VSS VSS VSS VSS
58 60 P60/WAIT P60/WAIT P60/WAIT P60/WAIT
15
Pin No. Pin Name
FP-100B
TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4
59 61 P61/BREQ P61/BREQ P61/BREQ P61/BREQ
60 62 P62/BACK P62/BACK P62/BACK P62/BACK
61 63 φφφφ
62 64 STBY STBY STBY STBY
63 65 RES RES RES RES
64 66 NMI NMI NMI NMI
65 67 VSS VSS VSS VSS
66 68 EXTAL EXTAL EXTAL EXTAL
67 69 XTAL XTAL XTAL XTAL
68 70 VCC VCC VCC VCC
69 71 AS AS AS AS
70 72 RD RD RD RD
71 73 HWR HWR HWR HWR
72 74 LWR LWR LWR LWR
73 75 MD0MD0MD0MD0
74 76 MD1MD1MD1MD1
75 77 MD2MD2MD2MD2
76 78 AVCC AVCC AVCC AVCC
77 79 VREF VREF VREF VREF
78 80 P70/AN0P70/AN0P70/AN0P70/AN0
79 81 P71/AN1P71/AN1P71/AN1P71/AN1
80 82 P72/AN2P72/AN2P72/AN2P72/AN2
81 83 P73/AN3P73/AN3P73/AN3P73/AN3
82 84 P74/AN4P74/AN4P74/AN4P74/AN4
83 85 P75/AN5P75/AN5P75/AN5P75/AN5
84 86 P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0
85 87 P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1
86 88 AVSS AVSS AVSS AVSS
87 89 P80/IRQ0P80/IRQ0P80/IRQ0P80/IRQ0
88 90 P81/IRQ1/ CS3P81/IRQ1/ CS3P81/IRQ1/ CS3P81/IRQ1/ CS3
89 91 P82/IRQ2/ CS2P82/IRQ2/ CS2P82/IRQ2/ CS2P82/IRQ2/ CS2
16
Pin No. Pin Name
FP-100B
TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4
90 92 P83/IRQ3/
CS1/ADTRG P83/IRQ3/
CS1/ADTRG P83/IRQ3/
CS1/ADTRG P83/IRQ3/
CS1/ADTRG
91 93 P84/CS0P84/CS0P84/CS0P84/CS0
92 94 VSS VSS VSS VSS
93 95 PA0/TP0/
TCLKA PA0/TP0/
TCLKA PA0/TP0/
TCLKA PA0/TP0/
TCLKA
94 96 PA1/TP1/
TCLKB PA1/TP1/
TCLKB PA1/TP1
/TCLKB PA1/TP1/
TCLKB
95 97 PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
96 98 PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
97 99 PA4/TP4/
TIOCA1
PA4/TP4/
TIOCA1
PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1/A23
98 100 PA5/TP5/
TIOCB1
PA5/TP5/
TIOCB1
PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1/A22
99 1 PA6/TP6/
TIOCA2
PA6/TP6/
TIOCA2
PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2/A21
100 2 PA7/TP7/
TIOCB2
PA7/TP7/
TIOCB2
A20 A20
Notes: 1. In modes 1 and 3 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a
reset, but they can be changed by software.
2. In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a
reset, but they can be changed by software.
3. This pin functions as VCL in 5 V operation models, and as VCC in 3 V operation models.
17
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• 64 basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
• 16-Mbyte linear address space
• High-speed operation
All frequently-used instructions execute in two to four states
Maximum clock frequency: 25 MHz
8/16/32-bit register-register add/subtract: 80 ns@25 MHz
8 × 8-bit register-register multiply: 560 ns@25 MHz
16 ÷ 8-bit register-register divide: 560 ns@25 MHz
16 × 16-bit register-register multiply: 880 ns@25 MHz
32 ÷ 16-bit register-register divide: 880 ns@25 MHz
18
• Two CPU operating modes
Normal mode
Advanced mode
• Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
Advanced mode supports a maximum 16-Mbyte address space.
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
Signed multiply/divide instructions and other instructions have been added.
2.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.
CPU operating modes
Normal mode
Advanced mode
Maximum 64 kbytes, program
and data areas combined
Maximum 16 Mbytes, program
and data areas combined
Figure 2.1 CPU Operating Modes
19
2.3 Address Space
Figure 2.2 shows a simple memory map for the H8/3008. The H8/300H CPU can address a linear
address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced
mode. For further details see section 3.6, Memory Map in Each Operating Mode.
The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'00000
H'FFFFF
H'000000
H'FFFFFF
a. 1-Mbyte mode b. 16-Mbyte mode
H'0000
H'FFFF
Advanced modeNormal mode
Figure 2.2 Memory Map
20
2.4 Register Configuration
2.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:
general registers and control registers.
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
0707015
(SP)
23 0
PC
7
CCR 6543210
IUIHUNZVC
General Registers (ERn)
Control Registers (CR)
Legend:
SP:
PC:
CCR:
I:
UI:
H:
U:
N:
Z:
V:
C:
Stack pointer
Program counter
Condition code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Figure 2.3 CPU Registers
21
2.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
ER0 to ER7
E registers
(extended registers)
E0 to E7
R registers
R0 to R7
RH registers
R0H to R7H
RL registers
R0L to R7L
Figure 2.4 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
22
Free area
Stack area
SP (ER7)
Figure 2.5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC
bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, Interrupt Controller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the
sign bit.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
23
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and
cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must
therefore be initialized by an MOV.L instruction executed immediately after a reset.
24
2.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,
2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as
two digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
7
RnH
RnL
RnH
RnL
RnH
RnL
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
6543210
70
Don’t care
76543210
70
Don’t care
Don’t care
70
43
Lower digitUpper digit
743
Lower digitUpper digit
Don’t care 0
70
Don’t care
MSB LSB
Don’t care 70
MSB LSB
Data Type Data Format
General
Register
Legend:
RnH: General register RH
RnL: General register RL
Figure 2.6 General Register Data Formats
25
Rn
En
ERn
Word data
Word data
Longword data
15 0
MSB LSB
General
RegisterData Type Data Format
15 0
MSB LSB
31 16
MSB
15 0
LSB
Legend:
ERn:
En:
Rn:
MSB:
LSB:
General register
General register E
General register R
Most significant bit
Least significant bit
Figure 2.7 General Register Data Formats
2.5.2 Memory Data Formats
Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
26
76543210Address L
Address L
LSB
MSB
MSB
LSB
70
MSB LSB
1-bit data
Byte data
Word data
Longword data
AddressData Type Data Format
Address 2M
Address 2M + 1
Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
Figure 2.8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
27
2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 64 types of instructions, which are classified in table 2.1.
Table 2.1 Instruction Classification
Function Instruction Types
Data transfer MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*25
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,
MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU 18
Logic operations AND, OR, XOR, NOT 4
Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,
BIXOR, BLD, BILD, BST, BIST 14
Branch Bcc*3, JMP, BSR, JSR, RTS 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9
Block data transfer EEPMOV 1
Total 64 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. Not available in the H8/3008.
3. Bcc is a generic branching instruction.
28
2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2 Instructions and Addressing Modes
Addressing Modes
Function Instruction #xx Rn @ERn
@
(d:16,
ERn)
@
(d:24,
ERn) @ERn+/
@–ERn @
aa:8 @
aa:16 @
aa:24
@
(d:8,
PC)
@
(d:16,
PC) @@
aa:8 —
Data MOV BWL BWL BWL BWL BWL BWL B BWL BWL ————
transfer POP, PUSH —————— ——————WL
MOVFPE, —————— ———————
MOVTPE
Arithmetic ADD, CMP BWL BWL ———— ———————
operations SUB WL BWL ———— ———————
ADDX, SUBX B B ———— ———————
ADDS, SUBS —L———— ———————
INC, DEC —BWL ———— ———————
DAA, DAS —B———— ———————
MULXU, —BW ———— ———————
MULXS,
DIVXU,
DIVXS
NEG —BWL ———— ———————
EXTU, EXTS —WL ———— ———————
Logic
operations AND, OR, XOR —BWL ———— ———————
NOT —BWL ———— ———————
Shift instructions —BWL ———— ———————
Bit manipulation —BB——— B——————
Branch Bcc, BSR —————— ———————
JMP, JSR —— ——— ——— ——
RTS —————— —— —— —
System TRAPA —————— ——————
control RTE —————— ——————
SLEEP —————— ——————
LDC B B W W W W —WW———
STC —BWWWW —WW————
ANDC, ORC,
XORC B————— ———————
NOP —————— ——————
Block data transfer —————— ——————BW
29
2.6.3 Tables of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)*
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
–Subtraction
×Multiplication
÷Division
∧AND logical
∨OR logical
⊕Exclusive OR logical
→Move
¬NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
30
Table 2.3 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register and
memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in the H8/3008.
MOVTPE B Rs → (EAs)
Cannot be used in the H8/3008.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W
Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
31
Table 2.4 Arithmetic Operation Instructions
Instruction Size* Function
ADD,SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data cannot
be subtracted from data in a general register. Use the SUBX or ADD
instruction.)
ADDX,
SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two general
registers, or on immediate data and data in a general register.
INC,
DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands can
be incremented or decremented by 1 only.)
ADDS,
SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA,
DAS B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
32
Instruction Size* Function
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits ÷ 8
bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient
and 16-bit remainder
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷ 8
bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register or
with immediate data, and sets CCR according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a general
register.
EXTS W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
EXTU W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
33
Table 2.5 Logic Operation Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another general
register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another general
register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and another
general register or immediate data.
NOT B/W/L ¬ Rd → Rd
Takes the one’s complement (logical complement) of general register
contents.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Instruction Size* Function
SHAL,
SHAR B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL,
SHLR B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL,
ROTR B/W/L Rd (rotate) → Rd
Rotates general register contents.
ROTXL,
ROTXR B/W/L Rd (rotate) → Rd
Rotates general register contents, including the carry bit.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
34
Table 2.7 Bit Manipulation Instructions
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower 3 bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
35
Instruction Size* Function
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the carry
flag.
The bit number is specified by 3-bit immediate data.
BILD B ¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
The bit number is specified by 3-bit immediate data.
BIST B C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
36
Table 2.8 Branching Instructions
Instruction Size Function
Bcc —Branches to a specified address if address specified condition is met. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
Bcc (BHS) Carry clear (high or same) C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
JMP —Branches unconditionally to a specified address
BSR —Branches to a subroutine at a specified address
JSR —Branches to a subroutine at a specified address
RTS —Returns from a subroutine
37
Table 2.9 System Control Instructions
Instruction Size* Function
TRAPA —Starts trap-instruction exception handling
RTE —Returns from an exception-handling routine
SLEEP —Causes a transition to the power-down state
LDC B/W (EAs) → CCR
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data is
read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP —PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
38
Table 2.10 Block Transfer Instruction
Instruction Size Function
EEPMOV.B —if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
EEPMOV.W —if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Block transfer instruction. This instruction transfers the number of data bytes
specified by R4L or R4, starting from the address indicated by ER5, to the
location starting at the address indicated by ER6. At the end of the transfer,
the next instruction is executed.
2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.9 shows examples of instruction formats.
39
op NOP, RTS, etc.
op rn rm
op rn rm
EA (disp)
Operation field only
ADD.B Rn, Rm, etc.
Operation field and register fields
MOV.B @(d:16, Rn), Rm
Operation field, register fields, and effective address extension
BRA d:8
Operation field, effective address extension, and condition field
op cc EA (disp)
Figure 2.9 Instruction Formats
2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
Step Description
1 Read Read one data byte at the specified address
2 Modify Modify one bit in the data byte
3 Write Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under
the following conditions.
P47, P46: Input pins
P45 – P40: Output pins
The intended purpose of this BCLR instruction is to switch P40 from output to input.
40
Before Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Input Input Output Output Output Output Output Output
DDR 00111111
Execution of BCLR Instruction
BCLR #0, P4DDR ; Execute BCLR instruction on DDR
After Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Output Output Output Output Output Output Output Input
DDR 11111110
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47 and P46 output pins.
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the
IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when
using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling
routine, for instance, it is not necessary to read the flag ahead of time.
41
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement @ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8, PC)/@(d:16, PC)
8 Memory indirect @@aa:8
1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
42
4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible
address ranges.
Table 2.12 Absolute Address Access Ranges
Absolute
Address 1-Mbyte Modes 16-Mbyte Modes
8 bits (@aa:8) H'FFF00 to H'FFFFF
(1048320 to 1048575) H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
16 bits (@aa:16) H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32767, 1015808 to 1048575)
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32767, 16744448 to 16777215)
24 bits (@aa:24) H'00000 to H'FFFFF
(0 to 1048575) H'000000 to H'FFFFFF
(0 to 16777215)
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-
43
extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The first
byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The
upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to
255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area.
For further details see section 5, Interrupt Controller.
Specified by @aa:8 Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2 Effective Address Calculation
Table 2.13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
44
Table 2.13 Effective Address Calculation
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Register direct (Rn)
1Operand is general
register contents
op rm rn
Register indirect (@ERn)
2
op r
General register contents
31 0 23 0
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
3
op r
General register contents
31 0
23 0
Sign extension disp
Register indirect with post-increment
or pre-decrement
4
General register contents
31 0 23 0
1, 2, or 4
op r
General register contents
31 0
23 0
1, 2, or 4
op r
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
1 for a byte operand,
2 for a word operand,
4 for a longword operand
45
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Absolute address
@aa:8
5
op
Program-counter relative
@(d:8, PC) or @(d:16, PC)
70
23 0
abs
23 087
@aa:16
@aa:24
op abs
23 016 15
H'FFFF
Sign
extension
op
23 0
abs
Immediate
#xx:8, #xx:16, or #xx:32
6Operand is immediate data
op disp
23 0
PC contents
disp
op IMM
Sign
extension
46
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
8
Legend:
r, rm, rn:
op:
disp:
IMM:
abs:
Register field
Operation field
Displacement
Immediate data
Absolute address
Memory indirect @@aa:8
8
op
23 0
abs 23 087
H'0000
15 0
abs
16 15
Normal mode
op
23 0
abs 23 087
H'0000
0
abs
Advanced mode
31
H'00Memory contents
Memory contents
47
2.8 Processing States
2.8.1 Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing
states. Figure 2.13 indicates the state transitions.
Processing states Program execution state
Bus-released state
Reset state
Power-down state
The CPU executes program instructions in sequence
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
The external bus has been released in response to a bus request
signal from a bus master other than the CPU
The CPU and all on-chip supporting modules are initialized and halted
The CPU is halted to conserve power
Sleep mode
Software standby mode
Hardware standby mode
Exception-handling state
Figure 2.11 Processing States
2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
48
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Priority Type of Exception Detection Timing Start of Exception Handling
High Reset Synchronized with clock Exception handling starts immediately
when RES changes from low to high
Interrupt End of instruction
execution or end of
exception handling*
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Low Trap instruction When TRAPA instruction
is executed Exception handling starts when a trap
(TRAPA) instruction is executed
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
E
xception
s
ources
Reset
Interrupt
Trap instruction
External interrupts
Internal interrupts (from on-chip supporting modules)
Figure 2.12 Classification of Exception Sources
49
Bus-released state
Exception-handling state
Reset state
Program execution state
Sleep mode
Software standby mode
Hardware standby mode
Power-down state
Bus request
End of bus release
End of bus
release Bus
request
End of
exception
handling
Exception
handling source
Interrupt source
SLEEP
instruction
with SSBY = 0
SLEEP instruction
with SSBY = 1
NMI, IRQ , IRQ ,
or IRQ interrupt
STBY="High", RES ="Low"
RES = "High"
01
2
*1 *2
Notes: 1.
2.
From any state except hardware standby mode, a transition to the reset state occurs
whenever goes low.
From any state, a transition to hardware standby mode occurs when goes low.
RES STBY
Figure 2.13 State Transitions
2.8.4 Exception Handling Operation
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
50
Figure 2.14 shows the stack after the exception-handling sequence.
SP–4
SP–3
SP–2
SP–1
SP (ER7)
Before exception
handling starts
SP (ER7)
SP+1
SP+2
SP+3
SP+4
After exception
handling ends
Stack area
CCR
PC
Even
address
Pushed on stack
Legend:
CCR:
SP: Condition code register
Stack pointer
Notes: 1.
2.
PC is the address of the first instruction executed after the return from the
exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
2.8.5 Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU is an external bus master. While the bus is released, the CPU
halts except for internal operations. Interrupt requests are not accepted. For details see section 6.6,
Bus Arbiter.
2.8.6 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 11,
Watchdog Timer.
51
2.8.7 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 18, Power-Down State.
2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin
states. The H8/3008 has a function for changing the method of outputting addresses from the
address pins. For details see section 6.3.5, Address Output Method.
52
T state
Bus cycle
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
φ
1T state
2
Read data
Address
Write data
Figure 2.15 On-Chip Memory Access Cycle
T
, , ,AS
φ
1T2
Address bus
D to D
15 0
RD HWR LWR High
Address
High impedance
Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1)
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
53
Address bus
Internal read signal
Internal data bus
Internal write signal
Address
Internal data bus
φ
T state
Bus cycle
1T state
2T state
3
Read
access
Write
access Write data
Read data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
T
, , ,AS
φ
1T2
Address bus
D to D
15 0
RD HWR LWR High
High impedance
T3
Address
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it is accessed
in two or three states. For details see section 6, Bus Controller.
54
55
Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
The H8/3008 has four operating modes (modes 1 to 4) that are selected by the mode pins (MD2 to
MD0) as indicated in table 3.1. The input at these pins determines the size of the address space and
the initial bus mode.
Table 3.1 Operating Mode Selection
Description
Operating Mode Pins Address Initial Bus On-Chip On-Chip
Mode MD2MD1MD0Space Mode*1ROM RAM
— 0 0 0 Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited
Mode 1 0 0 1 Expanded
mode 8 bits Disabled Enabled*2
Mode 2 0 1 0 Expanded
mode 16 bits Disabled Enabled*2
Mode 3 0 1 1 Expanded
mode 8 bits Disabled Enabled*2
Mode 4 1 0 0 Expanded
mode 16 bits Disabled Enabled*2
— 1 0 1 Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited
— 1 1 0 Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited
— 1 1 1 Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited
Notes: 1. In modes 1 to 4, an 8-bit or 16-bit data bus can be selected on a per-area basis by
settings made in the area bus width control register (ABWCR). For details see
section 6, Bus Controller.
2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.
For the address space size there are three choices: 1 Mbyte or 16 Mbyte. The external data bus is
either 8 or 16 bits wide depending on ABWCR settings. 8-bit bus mode is used only if 8-bit access
is selected for all areas. For details see section 6, Bus Controller.
56
Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral
devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space
of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.
The H8/3008 can be used only in modes 1 to 4. The inputs at the mode pins must select one of
these four modes. The inputs at the mode pins must not be changed during operation. Set the reset
state before changing the inputs at these pins.
3.1.2 Register Configuration
The H8/3008 has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2
to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.
Table 3.2 Registers
Address* Name Abbreviation R/W Initial Value
H'EE011 Mode control register MDCR R Undetermined
H'EE012 System control register SYSCR R/W H'09
Note: * Lower 20 bits of the address in advanced mode.
3.2 Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3008.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—
R
*
2
MDS2
—
R
1
MDS1
—
R**
Mode select 2 to 0
Bits indicating the current
operating mode
Reserved bits
Note: Determined by pins MD to MD .* 20
Bits 7 and 6—Reserved: These bits can not be modified and are always read as 1.
Bits 5 to 3—Reserved: These bits can not be modified and are always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to
57
MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when
MDCR is read.
3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3008.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
SSOE
0
R/W
Software standby
Enables transition to software standby mode
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
NMI edge select
Selects the valid edge
of the NMI input
RAM enable
Enables or
disables
on-chip RAM
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Selects the output state
of the address bus and
bus control signals in
software standby mode
Software standby
output port enable
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 18, Power-Down State.)
When software standby mode is exited by an external interrupt, and a transition is made to normal
operation, this bit remains set to 1. To clear this bit, write 0.
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sleep mode (Initial value)
1 SLEEP instruction causes transition to software standby mode
58
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time
the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when
software standby mode is exited by an external interrupt.
When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the
system clock rate.
For further information about waiting time selection, see section 18.4.3, Selection of Waiting
Time for Exit from Software Standby Mode.
Bit 6
STS2 Bit 5
STS1 Bit 4
STS0 Description
0 0 0 Waiting time = 8,192 states (Initial value)
0 0 1 Waiting time = 16,384 states
0 1 0 Waiting time = 32,768 states
0 1 1 Waiting time = 65,536 states
1 0 0 Waiting time = 131,072 states
1 0 1 Waiting time = 262,144 states
1 1 0 Waiting time = 1,024 states
1 1 1 Illegal setting
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as an interrupt mask bit
1 UI bit in CCR is used as a user bit (Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG Description
0 An interrupt is requested at the falling edge of NMI (Initial value)
1 An interrupt is requested at the rising edge of NMI
59
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS0 to CS7, AS, RD, HWR , LWR ) are kept as outputs or fixed high, or
placed in the high-impedance state in software standby mode.
Bit 1
SSOE Description
0 In software standby mode, the address bus and bus control signals are all high-
impedance (Initial value)
1 In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2 Mode 2
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR). (In this mode A20 is always used for address output.)
60
3.4.4 Mode 4
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to
8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always
used for address output.)
3.4.5 Modes 5 to 7
These modes cannot be used in the H8/3008. Pin settings must not be made for these modes.
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3
indicates their functions in each operating mode.
Table 3.3 Pin Functions in Each Mode
Port Mode 1 Mode 2 Mode 3 Mode 4
Port 1 A7 to A0A7 to A0A7 to A0A7 to A0
Port 2 A15 to A8A15 to A8A15 to A8A15 to A8
Port 3 D15 to D8D15 to D8D15 to D8D15 to D8
Port 4 P47 to P40*1D7 to D0*1P47 to P40*1D7 to D0*1
Port 5 A19 to A16 A19 to A16 A19 to A16 A19 to A16
Port A PA7 to PA4PA7 to PA4PA6 to PA4, A20*2PA6 to PA4, A20*2
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.
2. Initial state. A20 is always an address output pin. PA6 to PA4 are switched over to A23 to
A21 output by writing 0 in bits 7 to 5 of BRCR.
61
3.6 Memory Map in Each Operating Mode
Figures 3.1 and 3.2 show memory maps of the H8/3008. In the expanded modes, the address space
is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte
modes (modes 1 and 2) and the 16-Mbyte modes (modes 3 and 4). The address range specifiable
by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.
3.6.1 Reserved Areas
The H8/3008 memory map includes reserved areas to which access (reading or writing) is
prohibited. Normal operation cannot be guaranteed if the following reserved areas are accessed.
Reserved Area in Internal I/O Register Space: The H8/3008 internal I/O register space includes
a reserved area to which access is prohibited. For details see Appendix B, Internal I/O Registers.
62
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address space
External
address space
Vector area
On-chip RAM*
On-chip RAM*
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'FEF1F
H'FEF20
H'FFF00
H'FFF1F
H'FFF20
H'FFFE9
H'FFFEA
H'FFFFF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address space
Vector area
External
address space
8-bit absolute addresses
16-bit absolute addresses
H'FF8000
H'FFEF1F
H'FFEF20
H'FFFF1F
H'FFFF20
H'FFFF00
H'FFFFE9
H'FFFFEA
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'FEE000
H'FEE0FF
Note: * External addresses can be accessed by disabling on-chip RAM.
Internal I/O
registers (1)
Internal I/O
registers (1)
Internal I/O
registers (2)
Internal I/O
registers (2)
External
address space
H'EE000
H'EE0FF
External
address space
Figure 3.1 Memory Map of H8/3008 in Each Operating Mode
63
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the RES pin
Interrupt Interrupt requests are handled when execution of the current
instruction or handling of the current exception is completed
Low Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt mask bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
Note: For a reset exception, steps 2 and 3 above are carried out.
64
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vectors are assigned to
different exception sources. Table 4.2 lists the exception sources and their vector addresses.
Exception
sources
• Reset
• Interrupts
• Trap instruction
External interrupts:
Internal interrupts:
NMI, IRQ to IRQ
27 interrupts from on-chip
supporting modules
0 5
Figure 4.1 Exception Sources
65
Table 4.2 Exception Vector Table
Vector Address*1
Exception Source Vector Number Advanced Mode Normal Mode
Reset 0 H'0000 to H'0003 H'0000 to H'0001
Reserved for system use 1 H'0004 to H'0007 H'0002 to H'0003
2 H'0008 to H'000B H'0004 to H'0005
3 H'000C to H'000F H'0006 to H'0007
4 H'0010 to H'0013 H'0008 to H'0009
5 H'0014 to H'0017 H'000A to H'000B
6 H'0018 to H'001B H'000C to H'000D
External interrupt (NMI) 7 H'001C to H'001F H'000E to H'000F
Trap instruction (4 sources) 8 H'0020 to H'0023 H'0010 to H'0011
9 H'0024 to H'0027 H'0012 to H'0013
10 H'0028 to H'002B H'0014 to H'0015
11 H'002C to H'002F H'0016 to H'0017
External interrupt IRQ012 H'0030 to H'0033 H'0018 to H'0019
External interrupt IRQ113 H'0034 to H'0037 H'001A to H'001B
External interrupt IRQ214 H'0038 to H'003B H'001C to H'001D
External interrupt IRQ315 H'003C to H'003F H'001E to H'001F
External interrupt IRQ416 H'0040 to H'0043 H'0020 to H'0021
External interrupt IRQ517 H'0044 to H'0047 H'0022 to H'0023
Reserved for system use 18 H'0048 to H'004B H'0024 to H'0025
19 H'004C to H'004F H'0026 to H'0027
Internal interrupts*220
to
63
H'0050 to H'0053
to
H'00FC to H'00FF
H'0028 to H'0029
to
H'007E to H'007F
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
66
4.2 Reset
4.2.1 Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the RES pin changes from
low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 11,
Watchdog Timer.
4.2.2 Reset Sequence
The chip enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 10 system clock (ø) cycles. In the versions
with on-chip flash memory, the RES pin must be held low for at least 20 system clock cycles. See
appendix D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows.
• The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
• The contents of the reset vector address (H'0000 to H'0003 in advanced mode, H'0000 to
H'0001 in normal mode) are read, and program execution starts from the address indicated in
the vector address.
Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in
modes 2 and 4.
67
φ
Address
bus
RES
RD
HWR
D to D
15 8
Vector fetch Internal
processing Prefetch of
first program
instruction
(1), (3), (5), (7)
(2), (4), (6), (8)
(9)
(10)
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Address of reset exception handling vector: (1) = H'000000, (3) = H'000001, (5) = H'000002, (7) = H'000003
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
High
(1) (3) (5) (7) (9)
(2) (4) (6) (8) (10)
LWR,
Figure 4.2 Reset Sequence (Modes 1 and 3)
68
φ
Address bus
RES
RD
HWR
D to D
15 0
Vector fetch Internal
processing Prefetch of first
program instruction
(1), (3)
(2), (4)
(5)
(6)
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
High
LWR,
Address of reset exception handling vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
(2) (4)
(3)(1) (5)
(6)
Figure 4.3 Reset Sequence (Modes 2 and 4)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset exception handling. The first instruction of
the program is always executed immediately after the reset state ends. This instruction should
initialize the stack pointer (example: MOV.L #xx:32, SP).
69
4.3 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5), and
27 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
timer, 8-bit timer, serial communication interface (SCI), and A/D converter. Each interrupt source
has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Interrupts
External interrupts
Internal interrupts
NMI (1)
IRQ to IRQ (6)
WDT* (1)
16-bit timer (9)
8-bit timer (8)
SCI (8)
A/D converter (1)
Notes: Numbers in parentheses are the number of interrupt sources.
*When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
0 5
Figure 4.4 Interrupt Sources and Number of Interrupts
4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1 in CCR. The TRAPA instruction
fetches a start address from a vector table entry corresponding to a vector number from 0 to 3,
which is specified in the instruction code.
70
4.5 Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
SP (ER7)
SP+1
SP+2
SP+3
SP+4
→
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
SP (ER7)
SP+1
SP+2
SP+3
SP+4
→
Before exception handling
Before exception handling
After exception handling
Stack area
Stack area
CCR
CCR
PC
PC
CCR
PC
PC
PC
H
L
E
H
L
*
After exception handling
Even address
Even address
Pushed on stack
Pushed on stack
a. Normal mode
b. Advanced mode
Legend
PCE:
PCH:
PCL:
CCR:
SP:
Notes: PC indicates the address of the first instruction that will be executed after return.
Registers must be saved in word or longword size at even addresses.
Ignored at return.
1.
2.
*
Bits 23 to 16 of program counter (PC)
Bits 15 to 8 of program counter (PC)
Bits 7 to 0 of program counter (PC)
Condition code register
Stack pointer
Figure 4.5 Stack after Completion of Exception Handling
71
4.6 Notes on Stack Usage
When accessing word data or longword data, the H8/3008 regards the lowest address bit as 0. The
stack should always be accessed by word access or longword access, and the value of the stack
pointer (SP:ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W Rn (or MOV.W Rn, @–SP)
PUSH.L ERn (or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what
happens when the SP value is odd.
72
TRAPA instruction executed
CCR
Legend
CCR:
PC:
R1L:
SP:
SP
PC
R1L
PC
SP
SP
MOV. B R1L, @-ER7
SP set to H'FFFEFF Data saved above SP CCR contents lost
Condition code register
Program counter
General register R1L
Stack pointer
Note: The diagram illustrates modes 3 and 4.
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFE
H'FFFEFF
Figure 4.6 Operation when SP Value is Odd
73
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level enabling/disabling by the I and UI bits in the CPU’s condition code register (CCR)
and the UE bit in the system control register (SYSCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ5 to IRQ0, sensing of the falling edge or level sensing can be selected
independently.
74
5.1.2 Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
ISCR IER IPRA, IPRB
.
.
.
OVF
TME
TEI
TEIE
.
.
.
.
.
.
.
CPU
CCR
I
UI
UE
SYSCR
NMI
input
IRQ input IRQ input
section ISR
Interrupt controller
Priority
decision logic
Interrupt
request
Vector
number
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register A
Interrupt priority register B
System control register
Legend:
ISCR:
IER:
ISR:
IPRA:
IPRB:
SYSCR:
Figure 5.1 Interrupt Controller Block Diagram
75
5.1.3 Pin Configuration
Table 5.1 lists the interrupt pins.
Table 5.1 Interrupt Pins
Name Abbreviation I/O Function
Nonmaskable interrupt NMI Input Nonmaskable interrupt, rising edge or
falling edge selectable
External interrupt request 5 to 0 IRQ5 to IRQ0Input Maskable interrupts, falling edge or level
sensing selectable
5.1.4 Register Configuration
Table 5.2 lists the registers of the interrupt controller.
Table 5.2 Interrupt Controller Registers
Address*1Name Abbreviation R/W Initial Value
H'EE012 System control register SYSCR R/W H'09
H'EE014 IRQ sense control register ISCR R/W H'00
H'EE015 IRQ enable register IER R/W H'00
H'EE016 IRQ status register ISR R/(W)*2H'00
H'EE018 Interrupt priority register A IPRA R/W H'00
H'EE019 Interrupt priority register B IPRB R/W H'00
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written, to clear flags.
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
76
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
SSOE
0
R/W
Software standby
Standby timer
select 2 to 0
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
NMI edge select
Selects the NMI input edge
Software standby
output port enable
RAM enable
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as interrupt mask bit
1 UI bit in CCR is used as user bit (Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG Description
0 Interrupt is requested at falling edge of NMI input (Initial value)
1 Interrupt is requested at rising edge of NMI input
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
77
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
Initial value
Read/Write
7
IPRA7
0
R/W
6
IPRA6
0
R/W
5
IPRA5
0
R/W
4
IPRA4
0
R/W
3
IPRA3
0
R/W
0
IPRA0
0
R/W
2
IPRA2
0
R/W
1
IPRA1
0
R/W
Priority level A7
Selects the priority level of IRQ interrupt requests
Priority level A3
Selects the priority level of WDT,
and A/D converter interrupt requests
Priority level A2
Selects the priority level of
16-bit timer channel 0 interrupt
requests
Priority level A1
Selects the priority level
of 16-bit timer channel 1
interrupt requests
Priority
level A0
Selects the
priority level
of 16-bit timer
channel 2
interrupt
requests
Selects the priority level of IRQ interrupt requests
Priority level A6
Selects the priority level of IRQ and IRQ interrupt requests
Priority level A5
Selects the priority level of IRQ and IRQ
interrupt requests
Priority level A4
0
1
23
45
IPRA is initialized to H'00 by a reset and in hardware standby mode.
78
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.
Bit 7
IPRA7 Description
0 IRQ0 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ0 interrupt requests have priority level 1 (high priority)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Bit 6
IPRA6 Description
0 IRQ1 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ1 interrupt requests have priority level 1 (high priority)
Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests.
Bit 5
IPRA5 Description
0 IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority)
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests.
Bit 4
IPRA4 Description
0 IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority)
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, and A/D converter
interrupt requests.
Bit 3
IPRA3 Description
0 WDT, and A/D converter interrupt requests have priority level 0 (low priority)
(Initial value)
1 WDT, and A/D converter interrupt requests have priority level 1 (high priority)
79
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt
requests.
Bit 2
IPRA2 Description
0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1 16-bit timer channel 0 interrupt requests have priority level 1 (high priority)
Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt
requests.
Bit 1
IPRA1 Description
0 16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1 16-bit timer channel 1 interrupt requests have priority level 1 (high priority)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt
requests.
Bit 0
IPRA0 Description
0 16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (Initial value)
1 16-bit timer channel 2 interrupt requests have priority level 1 (high priority)
80
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
Initial value
Read/Write
7
IPRB7
0
R/W
6
IPRB6
0
R/W
5
—
0
R/W
4
—
0
R/W
3
IPRB3
0
R/W
0
—
0
R/W
2
IPRB2
0
R/W
1
—
0
R/W
Priority level B7
Selects the priority level of 8-bit timer channel 0, 1 interrupt requests
Priority level B3
Selects the priority level of SCI
channel 0 interrupt requests
Priority level B2
Selects the priority level of
SCI channel 1 interrupt requests
Reserved bit
Reserved bits
Selects the priority level of 8-bit timer channel 2, 3 interrupt requests
Priority level B6
IPRB is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt
requests.
Bit 7
IPRB7 Description
0 8-bit timer channel 0 and 1 interrupt requests have priority level 0 (low priority)
(Initial value)
1 8-bit timer channel 0 and 1 interrupt requests have priority level 1 (high priority)
81
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt
requests.
Bit 6
IPRB6 Description
0 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority)
(Initial value)
1 8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority)
Bits 5 and 4—Reserved: These bits can be written and read, but they do not affect interrupt
priority.
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.
Bit 3
IPRB3 Description
0 SCI0 channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1 SCI0 channel 0 interrupt requests have priority level 1 (high priority)
Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2
IPRB2 Description
0 SCI1 channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1 SCI1 channel 1 interrupt requests have priority level 1 (high priority)
Bits 1 and 0—Reserved: These bits can be written and read, but they do not affect interrupt
priority.
5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt
requests.
82
Bit
Initial value
Read/Write
7
—
0
—
These bits indicate IRQ to IRQ flag
interrupt request status
Note: Only 0 can be written, to clear flags.*
6
—
0
—
5
IRQ5F
0
R/(W) *
4
IRQ4F
0
R/(W) *
3
IRQ3F
0
R/(W) *
2
IRQ2F
0
R/(W) *
1
IRQ1F
0
R/(W) *
0
IRQ0F
0
R/(W) *
50
IRQ to IRQ flags
50
Reserved bits
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can not be modified and are always read as 0.
Bits 5 to 0—IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to
IRQ0 interrupt requests.
Bits 5 to 0
IRQ5F to IRQ0F Description
0 [Clearing conditions] (Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1 [Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ5 to IRQ0 interrupt requests.
Bit
Initial value
Read/Write
7
—
0
R/W
These bits enable or disable IRQ to IRQ interrupts
6
—
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
50
IRQ to IRQ enable
50
Reserved bits
IER is initialized to H'00 by a reset and in hardware standby mode.
83
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable
IRQ5 to IRQ0 interrupts.
Bits 5 to 0
IRQ5E to IRQ0E Description
0 IRQ5 to IRQ0 interrupts are disabled (Initial value)
1 IRQ5 to IRQ0 interrupts are enabled
5.2.5 IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ5 to IRQ0.
Bit
Initial value
Read/Write
7
—
0
R/W
These bits select level sensing or falling-edge
sensing for IRQ to IRQ interrupts
6
—
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
IRQ3SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
0
IRQ0SC
0
R/W
50
IRQ to IRQ sense control
50
Reserved bits
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0—IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether
interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge
sensing.
Bits 5 to 0
IRQ5SC to IRQ0SC Description
0 Interrupts are requested when IRQ5 to IRQ0 inputs are low (Initial value)
1 Interrupts are requested by falling-edge input at IRQ5 to IRQ0
84
5.3 Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ5 to IRQ0) and 27 internal interrupts.
5.3.1 External Interrupts
There are seven external interrupts: NMI, and IRQ5 to IRQ0. Of these, NMI, IRQ2, IRQ1, and
IRQ0 can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the
I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
IRQ5 to IRQ0 Interrupts: These interrupts are requested by input signals at pins IRQ5 to IRQ0.
The IRQ5 to IRQ0 interrupts have the following features.
• ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ5 to IRQ0, or by the falling edge.
• IER settings can enable or disable the IRQ5 to IRQ0 interrupts. Interrupt priority levels can be
assigned by four bits in IPRA (IPRA7 to IPRA4).
• The status of IRQ5 to IRQ0 interrupt requests is indicated in ISR. The ISR flags can be cleared
to 0 by software.
Figure 5.2 shows a block diagram of interrupts IRQ5 to IRQ0.
input
Edge/level
sense circuit
IRQnSC
IRQnF
S
R
Q
IRQnE
IRQn interrupt
request
Clear signal
IRQn
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0
85
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
φ
IRQn
IRQnF
input pin
Note: n = 5 to 0
Figure 5.3 Timing of Setting of IRQnF
Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, SCI input/output, or A/D
external trigger input.
5.3.2 Internal Interrupts
Twenty-Seven internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
5.3.3 Interrupt Exception Handling Vector Table
Table 5.3 lists the interrupt exception handling sources, their vector addresses, and their default
priority order. In the default priority order, smaller vector numbers have higher priority. The
priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a
reset is the default order shown in table 5.3.
86
Table 5.3 Interrupt Sources, Vector Addresses, and Priority
Vector Vector Address*
Interrupt Source Origin Number Advanced Mode Normal Mode IPR Priority
NMI External 7 H'001C to H'001F H'000E to H'000F —High
IRQ0pins 12 H'0030 to H'0033 H'0018 to H'0019 IPRA7
IRQ113 H'0034 to H0037 H'001A to H'001B IPRA6
IRQ2
IRQ3
14
15 H'0038 to H'003B
H'003C to H'003F H'001C to H'001D
H'001E to H'001F IPRA5
IRQ4
IRQ5
16
17 H'0040 to H'0043
H'0044 to H'0047 H'0020 to H'0021
H'0022 to H'0023 IPRA4
Reserved —18
19 H'0048 to H'004B
H'004C to H'004F H'0024 to H'0025
H'0026 to H'0027
WOVI
(interval timer) Watchdog
timer 20 H'0050 to H'0053 H'0028 to H'0029 IPRA3
Reserved —21 H'0054 to H'0057 H'002A to H'002B
22 H'0058 to H'005B H'002C to H'002D
ADI (A/D end) A/D 23 H'005C to H'005F H'002E to H'002F
IMIA0
(compare match/
input capture A0)
IMIB0
(compare match/
input capture B0)
OVI0 (overflow 0)
16-bit timer
channel 0 24
25
26
H'0060 to H'0063
H'0064 to H'0067
H'0068 to H'006B
H'0030 to H'0031
H'0032 to H'0033
H'0034 to H'0035
IPRA2
Reserved —27 H'006C to H'006F H'0036 to H'0037
IMIA1
(compare match/
inputcapture A1)
IMIB1
(compare match/
input capture B1)
OVI1 (overflow 1)
16-bit timer
channel 1 28
29
30
H'0070 to H'0073
H'0074 to H'0077
H'0078 to H'007B
H'0038 to H'0039
H'003A to H'003B
H'003C to H'003D
IPRA1
Reserved —31 H'007C to H'007F H'003E to H'003F Low
87
Vector Vector Address*
Interrupt Source Origin Number Advanced Mode Normal Mode IPR Priority
IMIA2
(compare match/
input capture A2)
IMIB2
(compare match/
input capture B2)
OVI2 (overflow 2)
16-bit timer
channel 2 32
33
34
H'0080 to H'0083
H'0084 to H'0087
H'0088 to H'008B
H'0040 to H'0041
H'0042 to H'0043
H'0044 to H'0045
IPRA0 High
Reserved —35 H'008C to H'008F H'0046 to H'0047
CMIA0
(compare match
A0)
CMIB0
(compare match
B0)
CMIA1/CMIB1
(compare match
A1/B1)
TOVI0/TOVI1
(overflow 0/1)
8-bit timer
channel 0/1 36
37
38
39
H'0090 to H'0093
H'0094 to H'0097
H'0098 to H'009B
H'009C to H'009F
H'0048 to H'0049
H'004A to H'004B
H'004C to H'004D
H'004E to H'004F
IPRB7
CMIA2
(compare match
A2)
CMIB2
(compare match
B2)
CMIA3/CMIB3
(compare match
A3/B3)
TOVI2/TOVI3
(overflow 2/3)
8-bit timer
channel 2/3 40
41
42
43
H'00A0 to H'00A3
H'00A4 to H'00A7
H'00A8 to H'00AB
H'00AC to H'00AF
H'0050 to H'0051
H'0052 to H'0053
H'0054 to H'0055
H'0056 to H'0057
IPRB6
Reserved —44
45
46
47
H'00B0 to H'00B3
H'00B4 to H'00B7
H'00B8 to H'00BB
H'00BC to H'00BF
H'0058 to H'0059
H'005A to H'005B
H'005C to H'005D
H'005E to H'005F
—
48
49
50
51
H'00C0 to H'00C3
H'00C4 to H'00C7
H'00C8 to H'00CB
H'00CC to H'00CF
H'0060 to H'0061
H'0062 to H'0063
H'0064 to H'0065
H'0066 to H'0067 Low
88
Vector Vector Address*
Interrupt Source Origin Number Advanced Mode Normal Mode IPR Priority
ERI0
(receive error 0)
RXI0 (receive
data full 0)
TXI0 (transmit
data empty 0)
TEI0
(transmit end 0)
SCI
channel 0 52
53
54
55
H'00D0 to H'00D3
H'00D4 to H'00D7
H'00D8 to H'00DB
H'00DC to H'00DF
H'0068 to H'0069
H'006A to H'006B
H'006C to H'006D
H'006E to H'006F
IPRB3 High
ERI1
(receive error 1)
RXI1 (receive
data full 1)
TXI1 (transmit
data empty 1)
TEI1 (transmit
end 1)
SCI
channel 1 56
57
58
59
H'00E0 to H'00E3
H'00E4 to H'00E7
H'00E8 to H'00EB
H'00EC to H'00EF
H'0070 to H'0071
H'0072 to H'0073
H'0074 to H'0075
H'0076 to H'0077
IPRB2
Reserved —60
61
62
63
H'00F0 to H'00F3
H'00F4 to H'00F7
H'00F8 to H'00FB
H'00FC to H'00FF
H'0078 to H'0079
H'007A to H'007B
H'007C to H'007D
H'007E to H'007F
—
Low
Note: * Lower 16 bits of the address.
89
5.4 Interrupt Operation
5.4.1 Interrupt Handling Process
The H8/3008 handles interrupts differently depending on the setting of the UE bit. When UE = 1,
interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI
bits.
NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts
and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests
are ignored when the enable bits are cleared to 0.
Table 5.4 UE, I, and UI Bit Settings and Interrupt Handling
SYSCR CCR
UE I UI Description
10—All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1—No interrupts are accepted except NMI.
00—All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1 0 NMI and interrupts with priority level 1 are accepted.
1 No interrupts are accepted except NMI.
UE = 1: Interrupts IRQ5 to IRQ0 and interrupts from the on-chip supporting modules can all be
masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure
5.4 is a flowchart showing how interrupts are accepted when UE = 1.
90
Program execution state
Interrupt requested?
NMI
No
Yes
No
Yes
No
Priority level 1?
No
IRQ 0
Yes No
IRQ 1
Yes TEI1
Yes
No
IRQ 0
Yes No
IRQ 1
Yes TEI1
Yes
No
I = 0
Yes
Save PC and CCR
I 1
Branch to interrupt
service routine
←
Pending
Yes
Read vector address
Figure 5.4 Process Up to Interrupt Acceptance when UE = 1
91
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of
IRQ0 to IRQ5 interrupts and interrupts from the on-chip supporting modules.
• Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked
when the I bit is cleared to 0.
• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and
are unmasked when either the I bit or the UI bit is cleared to 0.
For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to
H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other
interrupts), interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …).
b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked.
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
Figure 5.5 shows the transitions among the above states.
92
All interrupts are
unmasked Only NMI, IRQ , and
IRQ are unmasked
Exception handling,
or I 1, UI 1
a. b. 2
3
All interrupts are
masked except NMI
c.
UI 0I 0 Exception handling,
or UI 1
I 0
I 1, UI 0
←← ←←
←
←
←←
Figure 5.5 Interrupt Masking State Transitions (Example)
Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and
the UI bit is cleared to 0, only interrupts with priority level 1 are accepted; interrupt requests
with priority level 0 are held pending. If the I bit and UI bit are both set to 1, all other interrupt
requests are held pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
93
Program execution state
Interrupt requested?
NMI
No
Yes
No
Yes
No
Priority level 1?
No
IRQ 0
Yes No
IRQ 1
Yes TEI1
Yes
No
IRQ 0
Yes No
IRQ 1
Yes TEI1
Yes
No
I = 0
Yes
No
I = 0
Yes
UI = 0
Yes
No
Save PC and CCR
I 1, UI 1
←
Pending
Branch to interrupt
service routine
Yes
←
Read vector address
Figure 5.6 Process Up to Interrupt Acceptance when UE = 0
94
5.4.2 Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and
stack are in an external memory area accessed in two states via a 16-bit bus.
φ
Address
bus
Interrupt
request
signal
RD
HWR
D to D
15 8
(1)
(2), (4)
(3)
(5)
(7)
Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.
LWR,
Interrupt level
decision and wait
for end of instruction
Interrupt accepted
Instruction
prefetch Internal
processing Stack Vector fetch Internal
processing
Prefetch of
interrupt
service routine
instruction
High
Instruction prefetch address (not executed;
return address, same as PC contents)
Instruction code (not executed)
Instruction prefetch address (not executed)
SP – 2
SP – 4
(6), (8)
(9), (11)
(10), (12)
(13)
(14)
PC and CCR saved to stack
Vector address
Starting address of interrupt service routine (contents of
vector address)
Starting address of interrupt service routine; (13) = (10), (12)
First instruction of interrupt service routine
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Figure 5.7 Interrupt Exception Handling Sequence
95
5.4.3 Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5 Interrupt Response Time
External Memory
On-Chip 8-Bit Bus 16-Bit Bus
No. Item Memory 2 States 3 States 2 States 3 States
1 Interrupt priority
decision 2*12*12*12*12*1
2 Maximum number
of states until end of
current instruction
1 to 23 1 to 27 1 to 31*41 to 23 1 to 25*4
3 Saving PC and CCR
to stack 4 8 12*446*
4
4 Vector fetch 4 8 12*446*
4
5 Instruction fetch*24 8 12*446*
4
6 Internal processing*344 4 4 4
Total 19 to 41 31 to 57 43 to 73 19 to 41 25 to 49
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after vector
fetch.
4. The number of states increases if wait states are inserted in external memory access.
96
5.5 Usage Notes
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag to 0.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the 16-bit timer’s TISRA
register.
IMIA exception handlingTISRA write cycle by CPU
φ
TISRA address
Internal
address bus
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
97
5.5.2 Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt-inhibiting instructions, however, when the instruction is
completed the CPU always continues by executing the next instruction.
5.5.3 Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
98
99
Section 6 Bus Controller
6.1 Overview
The H8/3008 has an on-chip bus controller (BSC) that manages the external address space divided
into eight areas. The bus specifications, such as bus width and number of access states, can be set
independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function that controls the operation of the internal bus
masters—the CPU can release the bus to an external device.
6.1.1 Features
The features of the bus controller are listed below.
• Manages external address space in area units
Manages the external space as eight areas (0 to 7) of 128 kbytes in 1M-byte modes, or 2
Mbytes in 16-Mbyte modes
Bus specifications can be set independently for each area
• Basic bus interface
Chip select (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
Two-state access or three-state access can be selected for each area
Program wait states can be inserted for each area
Pin wait insertion capability is provided
• Idle cycle insertion
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted when an external read cycle is immediately followed by an
external write cycle
• Bus arbitration function
A built-in bus arbiter grants the bus right to the CPU, or an external bus master
• Other features
Choice of two address update modes
100
6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
Internal address bus
ABWCR
ASTCR
BCR
CSCR
ADRCR
Area
decoder Chip select
control signals
CS0 to CS7
Bus control
circuit
WCRH
WCRL
BRCR
Legend:
Wait state
controller
WAIT
BACK
BREQ
Internal data bus
CPU bus request signal
CPU bus acknowledge signal Bus arbiter
Bus mode control signal
Internal signals
Internal signals
Bus size control signal
Access state control signal
Wait request signal
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus release control register
Chip select control register
ASTCR:
WCRH:
WCRL:
BRCR:
CSCR: Address control register
ADRCR:
ABWCR:
BCR: Bus control register
Figure 6.1 Block Diagram of Bus Controller
101
6.1.3 Pin Configuration
Table 6.1 summarizes the input/output pins of the bus controller.
Table 6.1 Bus Controller Pins
Name Abbreviation I/O Function
Chip select 0 to 7 CS0 to CS7Output Strobe signals selecting areas 0 to 7
Address strobe AS Output Strobe signal indicating valid address output
on the address bus
Read RD Output Strobe signal indicating reading from the
external address space
High write HWR Output Strobe signal indicating writing to the external
address space, with valid data on the upper
data bus (D15 to D8)
Low write LWR Output Strobe signal indicating writing to the external
address space, with valid data on the lower
data bus (D7 to D0)
Wait WAIT Input Wait request signal for access to external
three-state access areas
Bus request BREQ Input Request signal for releasing the bus to an
external device
Bus acknowledge BACK Output Acknowledge signal indicating release of the
bus to an external device
102
6.1.4 Register Configuration
Table 6.2 summarizes the bus controller’s registers.
Table 6.2 Bus Controller Registers
Address*1Name Abbreviation R/W Initial Value
H'EE020 Bus width control register ABWCR R/W H'FF*2
H'EE021 Access state control register ASTCR R/W H'FF
H'EE022 Wait control register H WCRH R/W H'FF
H'EE023 Wait control register L WCRL R/W H'FF
H'EE013 Bus release control register BRCR R/W H'FE*3
H'EE01F Chip select control register CSCR R/W H'0F
H'EE01E Address control register ADRCR R/W H'FF
H'EE024 Bus control register BCR R/W H'C6
Notes: 1. Lower 20 bits of the address in advanced mode.
2. In modes 2 and 4, the initial value is H'00.
3. In modes 3 and 4, the initial value is H'EE.
6.2 Register Descriptions
6.2.1 Bus Width Control Register (ABWCR)
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
7
ABW7
1
R/W
0
R/W
6
ABW6
1
R/W
0
R/W
5
ABW5
1
R/W
0
R/W
4
ABW4
1
R/W
0
R/W
3
ABW3
1
R/W
0
R/W
2
ABW2
1
R/W
0
R/W
1
ABW1
1
R/W
0
R/W
0
ABW0
1
R/W
0
R/W
Bit
Modes
1 and 3 Initial value
Read/Write
Initial value
Read/Write
Modes
2 and 4
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus
mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one
bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to
D0). In modes 1 and 3, ABWCR is initialized to H'FF by a reset and in hardware standby mode.
In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode. It is
not initialized in software standby mode.
103
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or
16-bit access for the corresponding areas.
Bits 7 to 0
ABW7 to ABW0 Description
0 Areas 7 to 0 are 16-bit access areas
1 Areas 7 to 0 are 8-bit access areas
ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip
memory and registers is fixed, and does not depend on ABWCR settings.
6.2.2 Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
AST3 AST2 AST1 AST0
1Initial value 1111111
Read/Write R/W R/W R/W R/WR/W R/W R/W R/W
76543210
Bits selecting number of states for access to each area
AST7 AST6 AST5 AST4
Bit
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0 Description
0 Areas 7 to 0 are accessed in two states
1 Areas 7 to 0 are accessed in three states (Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings.
104
6.2.3 Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
On-chip memory and registers are accessed in a fixed number of states that does not depend on
WCRH/WCRL settings.
WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not
initialized in software standby mode.
WCRH
W51 W50 W41 W40
1Initial value 1111111
Read/Write R/W R/W R/W R/WR/W R/W R/W R/W
76543210
W71 W70 W61 W60
Bit
Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of
program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set
to 1.
Bit 7
W71 Bit 6
W70 Description
0 0 Program wait not inserted when external space area 7 is accessed
1 1 program wait state inserted when external space area 7 is accessed
1 0 2 program wait states inserted when external space area 7 is accessed
1 3 program wait states inserted when external space area 7 is accessed
(Initial value)
105
Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of
program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set
to 1.
Bit 5
W61 Bit 4
W60 Description
0 0 Program wait not inserted when external space area 6 is accessed
1 1 program wait state inserted when external space area 6 is accessed
1 0 2 program wait states inserted when external space area 6 is accessed
1 3 program wait states inserted when external space area 6 is accessed
(Initial value)
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of
program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set
to 1.
Bit 3
W51 Bit 2
W50 Description
0 0 Program wait not inserted when external space area 5 is accessed
1 1 program wait state inserted when external space area 5 is accessed
1 0 2 program wait states inserted when external space area 5 is accessed
1 3 program wait states inserted when external space area 5 is accessed
(Initial value)
Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of
program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set
to 1.
Bit 1
W41 Bit 0
W40 Description
0 0 Program wait not inserted when external space area 4 is accessed
1 1 program wait state inserted when external space area 4 is accessed
1 0 2 program wait states inserted when external space area 4 is accessed
1 3 program wait states inserted when external space area 4 is accessed
(Initial value)
106
WCRL
W11 W10 W01 W00
1Initial value 1111111
Read/Write R/W R/W R/W R/WR/W R/W R/W R/W
76543210
W31 W30 W21 W20
Bit
Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of
program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set
to 1.
Bit 7
W31 Bit 6
W30 Description
0 0 Program wait not inserted when external space area 3 is accessed
1 1 program wait state inserted when external space area 3 is accessed
1 0 2 program wait states inserted when external space area 3 is accessed
1 3 program wait states inserted when external space area 3 is accessed
(Initial value)
Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of
program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set
to 1.
Bit 5
W21 Bit 4
W20 Description
0 0 Program wait not inserted when external space area 2 is accessed
1 1 program wait state inserted when external space area 2 is accessed
1 0 2 program wait states inserted when external space area 2 is accessed
1 3 program wait states inserted when external space area 2 is accessed
(Initial value)
107
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3
W11 Bit 2
W10 Description
0 0 Program wait not inserted when external space area 1 is accessed
1 1 program wait state inserted when external space area 1 is accessed
1 0 2 program wait states inserted when external space area 1 is accessed
1 3 program wait states inserted when external space area 1 is accessed
(Initial value)
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
W01 Bit 0
W00 Description
0 0 Program wait not inserted when external space area 0 is accessed
1 1 program wait state inserted when external space area 0 is accessed
1 0 2 program wait states inserted when external space area 0 is accessed
1 3 program wait states inserted when external space area 0 is accessed
(Initial value)
108
6.2.4 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20 and
enables or disables release of the bus to an external device.
7
A23E
1
—
1
R/W
Address 23 to 20 enable
These bits enable PA7 to PA4 to be
used for A23 to A20 address output
6
A22E
1
—
1
R/W
5
A21E
1
—
1
R/W
4
A20E
1
—
0
—
3
—
1
—
1
—
2
—
1
—
1
—
1
—
1
—
1
—
0
BRLE
0
R/W
0
R/W
Bit
Modes
1 and 2 Initial value
Read/Write
Initial value
Read/Write
Modes
3 and 4
Reserved bits
Bus release enable
Enables or disables release
of the bus to an external device
BRCR is initialized to H'FE in modes 1 and 2, and to H'EE in modes 3 and 4, by a reset and in
hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin.
Writing 0 in this bit enables A23 output from PA4. In modes other than 3 and 4, this bit cannot be
modified and PA4 has its ordinary port functions.
Bit 7
A23E Description
0PA
4 is the A23 address output pin
1PA
4 is an input/output pin (Initial value)
Bit 6—Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin.
Writing 0 in this bit enables A22 output from PA5. In modes other than 3 and 4, this bit cannot be
modified and PA5 has its ordinary port functions.
Bit 6
A22E Description
0PA
5 is the A22 address output pin
1PA
5 is an input/output pin (Initial value)
109
Bit 5—Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin.
Writing 0 in this bit enables A21 output from PA6. In modes other than 3 and 4, this bit cannot be
modified and PA6 has its ordinary port functions.
Bit 5
A21E Description
0PA
6 is the A21 address output pin
1PA
6 is an input/output pin (Initial value)
Bit 4—Address 20 Enable (A20E): Enables PA7 to be used as an address output pin. When 0 is
written to this bit, PA7 functions as address output A20. In modes 3 and 4, PA7 functions as an
address output pin, and in modes 1 and 2, as a normal port pin.
Bit 4
A20E Description
0PA
7 is the A20 address output pin (In mode 3 or 4)
1PA
7 is an input/output pin (In mode 1 or 2)
Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE Description
0 The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins (Initial value)
1 The bus can be released to an external device
6.2.5 Bus Control Register (BCR)
——RDEA WAITE
1Initial value 1 0*
1
0*
1
0*
1
1*
2
10
Read/Write ——R/W R/WR/W R/W ——
76543210
ICIS1 ICIS0 ——
Bit
Notes: 1. 1 must not be written in bits 5 to 3.
2. 0 must not be written in bit 2.
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, selects the extended memory map, and enables or disables WAIT pin input.
110
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1 Description
0 No idle cycle inserted in case of consecutive external read cycles for different
areas
1 Idle cycle inserted in case of consecutive external read cycles for different
areas (Initial value)
Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0 Description
0 No idle cycle inserted in case of consecutive external read and write cycles
1 Idle cycle inserted in case of consecutive external read and write cycles
(Initial value)
Bits 5 to 3—Reserved (must not be set to 1): These bits can be read and written, but must not be
set to 1. Normal operation cannot be guaranteed if 1 is written in these bits.
Bit 2— Reserved (must not be set to 0): This bit can be read and written, but must not be set to
0. Normal operation cannot be guaranteed if 0 is written in this bit.
Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit
is valid in modes 3 and 4, and is invalid in modes 1 and 2.
Bit 1
RDEA Description
0 Area divisions are as follows: Area 0: 2 Mbytes Area 4: 1.93 Mbytes
Area 1: 2 Mbytes Area 5: 4 kbytes
Area 2: 8 Mbytes Area 6: 23.75 kbytes
Area 3: 2 Mbytes Area 7: 22 bytes
1 Areas 0 to 7 are the same size (2 Mbytes) (Initial value)
111
Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT
pin.
Bit 0
WAITE Description
0WAIT pin wait input is disabled, and the WAIT pin can be used as an
input/output port (Initial value)
1WAIT pin wait input is enabled
6.2.6 Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(CS7 to CS4).
If output of a chip select signal CS7 to CS4 is enabled by a setting in this register, the
corresponding pin functions a chip select signal (CS7 to CS4) output regardless of any other
settings.
————
0Initial value 0001111
Read/Write ————R/W R/W R/W R/W
76543210
Reserved bits
CS7E CS6E CS5E CS4E
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
Bit
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n
CSnE Description
0 Output of chip select signal CSn is disabled (Initial value)
1 Output of chip select signal CSn is enabled
Note: n = 7 to 4
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.
112
6.2.7 Address Control Register (ADRCR)
ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address
update mode 2 as the address output method.
———
ADRCTL
1Initial value 1111111
Read/Write ———R/W————
76543210
Reserved bits
————
Address control
Selects address
update mode 1 or
address update
mode 2
Bit
ADRCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Address Control (ADRCTL): Selects the address output method.
Bit 0
ADRCTL Description
0 Address update mode 2 is selected
1 Address update mode 1 is selected (Initial value)
113
6.3 Operation
6.3.1 Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-
Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the
memory map.
H' 00000
H' 1FFFF
H' 20000
H' 3FFFF
H' 40000
H' 5FFFF
H' 60000
H' 7FFFF
H' 80000
H' 9FFFF
H' A0000
H' BFFFF
H' C0000
H' DFFFF
H' E0000
H' FFFFF
Area 0 (128 kbytes)
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
Area 7 (128 Mbytes)
H' 000000
H' 1FFFFF
H' 200000
H' 3FFFFF
H' 400000
H' 5FFFFF
H' 600000
H' 7FFFFF
H' 800000
H' 9FFFFF
H' A00000
H' BFFFFF
H' C00000
H' DFFFFF
H' E00000
H' FFFFFF
Area 0 (2 Mbytes)
Area 1 (2 Mbytes)
Area 2 (2 Mbytes)
Area 3 (2 Mbytes)
Area 4 (2 Mbytes)
Area 5 (2 Mbytes)
Area 6 (2 Mbytes)
Area 7 (2 Mbytes)
(a) 1-Mbyte modes (modes 1 and 2) (b) 16-Mbyte modes (modes 3 and 4)
Figure 6.2 Access Area Map for Each Operating Mode
Chip select signals (CS0 to CS7) can be output for areas 0 to 7. The bus specifications for each
area are selected in ABWCR, ASTCR, WCRH, and WCRL.
In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR.
114
H'000000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'FEE000
H'FEE0FF
H'FEE100
H'FF7FFF
H'FF8000
H'FF8FFF
H'FF9000
H'FFEF1F
H'FFEF20
H'FFFEFF
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
Area 0
2 Mbytes
Area 1
2 Mbytes
Area 2
2 Mbytes
Area 3
2 Mbytes
Area 4
2 Mbytes
Area 5
2 Mbytes
Area 6
2 Mbytes
Area 7
1.93 Mbytes
Internal I/O registers (1)
Area 7
67.5 kbytes
On-chip RAM
4 kbytes
Internal I/O registers (2)
Area 7
22 bytes
Area 0
2 Mbytes
Area 1
2 Mbytes
Area 2
8 Mbytes
Area 3
2 Mbytes
Area 4
1.93 Mbytes
Area 5
4 kbytes
On-chip RAM
4 kbytes*
Internal I/O registers (2)
Area 7
22 bytes
Area 6
23.75 kbytes
Internal I/O registers (1)
2 Mbytes2 Mbytes2 Mbytes2 Mbytes2 Mbytes 2 Mbytes2 Mbytes2 Mbytes
Absolute
address 16 bits
Absolute
address 8 bits
(A) Memory map when RDEA = 1
Note: * Area 6 when the RAME bit is cleared.
(b) Memory map when RDEA = 0
Reserved 39.75 kbytes
Figure 6.3 Memory Map in 16-Mbyte Mode
115
6.3.2 Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and number of program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-
bit access, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which two-state access is selected functions as a two-state access space, and an area for which
three-state access is selected functions as a three-state access space.
When two-state access space is designated, wait insertion is disabled.
Number of Program Wait States: When three-state access space is designated in ASTCR, the
number of program wait states to be inserted automatically is selected with WCRH and WCRL.
From 0 to 3 program wait states can be selected.
Table 6.3 shows the bus specifications for each basic bus interface area.
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH/WCRL Bus Specifications (Basic Bus Interface)
ABWn ASTn Wn1 Wn0 Bus Width Access States Program Wait States
00——16 2 0
100 3 0
11
10 2
13
10——82 0
100 3 0
11
10 2
13
Note: n = 0 to 7
116
6.3.3 Memory Interfaces
As its memory interface, the H8/3008 has only a basic bus interface that allows direct connection
of ROM, SRAM, and so on. It is not possible to select a DRAM interface that allows direct
connection of DRAM, or a burst ROM interface that allows direct connection of burst ROM.
6.3.4 Chip Select Signals
For each of areas 0 to 7, the H8/3008 can output a chip select signal (CS0 to CS7) that goes low
when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of
a CSn signal.
Output of CS0 to CS3: Output of CS0 to CS3 is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS0 in the output state and
pins CS1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS0 to CS3 in the input state. To output chip select signals CS0 to CS3, the corresponding DDR
bits must be set to 1. For details, see section 7, I/O Ports.
Output of CS4 to CS7: Output of CS4 to CS7 is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS4 to CS7 in the input state. To output chip select signals
CS4 to CS7, the corresponding CSCR bits must be set to 1. For details, see section 7, I/O Ports.
φ
Address bus External address in area n
CSn
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS0 to CS7 remain
high. The CSn signals are decoded from the address signals. They can be used as chip select
signals for SRAM and other devices.
117
6.3.5 Address Output Method
The H8/3008 provides a choice of two address update methods: either the same method as in the
previous H8/300H Series (address update mode 1), or a method in which address updating is
restricted to external space accesses (address update mode 2).
Figure 6.5 shows examples of address output in these two update modes.
On-chip
memory cycle On-chip
memory cycle
External
read cycle On-chip
memory cycle External
read cycle
Address bus
(Address update
mode 1)
Address bus
(Address update
mode 2)
RD
Figure 6.5 Sample Address Output in Each Address Update Mode
(Basic Bus Interface, 3-State Space)
Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H
Series. Addresses are always updated between bus cycles.
Address Update Mode 2: In address update mode 2, address updating is performed only in
external space accesses. In this mode, the address can be retained between an external space read
cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory.
Address update mode 2 is therefore useful when connecting a device that requires address hold
time with respect to the rise of the RD strobe.
Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in
ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing
compatibility with the previous H8/300H Series.
Cautions: The address output methods are designed so that the initial state with the bit selection
method is compatible with the H8/3062F-ZTAT (HD64F3062) (i.e. address update mode 1).
However, the following points should be noted.
118
• ADRCR is allocated to address H'FEE01E. In the H8/3062F-ZTAT, the corresponding
address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E
in the program.
• When address update mode 2 is selected, the address in an internal space (on-chip memory or
internal I/O) access cycle is not output externally.
• In order to secure address holding with respect to the rise of RD, when address update mode 2
is used an external space read access must be completed within a single access cycle. For
example, in a word access to 8-bit access space, the bus cycle is split into two as shown in
figure 6.6, and so there is not a single access cycle. In this case, address holding is not
guaranteed at the rise of RD between the first (even address) and second (odd address) access
cycles (area inside the ellipse in the figure).
On-chip
memory cycle On-chip
memory cycle
External read cycle
(8-bit space word access)
Address update
mode 2
RD
Even address Odd address
Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2
119
6.4 Basic Bus Interface
6.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL
(see table 6.4).
6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications
for the area being accessed (8-bit access area or 16-bit access area) and the data size.
8-Bit Access Areas: Figure 6.7 illustrates data alignment control for 8-bit access space. With 8-
bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data
that can be accessed at one time is one byte: a word access is performed as two byte accesses, and
a longword access, as four byte accesses.
D15 D8D7D0
Upper data bus Lower data bus
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Byte size
Word size
Longword size
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Area)
16-Bit Access Areas: Figure 6.8 illustrates data alignment control for 16-bit access areas. With
16-bit access areas, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for
accesses. The amount of data that can be accessed at one time is one byte or one word, and a
longword access is executed as two word accesses.
120
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
D15 D8D7D0
Upper data bus Lower data bus
1st bus cycle
2nd bus cycle
Byte size
Longword size
· Even address
· Odd address
Word size
Byte size
Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area)
6.4.3 Valid Strobes
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.4 Data Buses Used and Valid Strobes
Area Access
Size Read/
Write Address Valid
Strobe Upper Data Bus
(D15 to D8)Lower Data Bus
(D7 to D0)
8-bit access Byte Read —RD Valid Invalid
area Write —HWR Undetermined data
16-bit access Byte Read Even RD Valid Invalid
area Odd Invalid Valid
Write Even HWR Valid Undetermined data
Odd LWR Undetermined data Valid
Word Read —RD Valid Valid
Write —HWR,
LWR Valid Valid
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
121
6.4.4 Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width
is selected according to the operating mode.
Areas 0 to 6: In the H8/3008, the entire space of areas 0 to 6 is external space.
When area 0 to 6 external space is accessed, the CS0 to CS6 pin signals respectively can be output.
The size of areas 0 to 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In the H8/3008, the space
excluding the on-chip RAM and I/O registers is external space. The on-chip RAM is enabled
when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is
cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space .
When area 7 external space is accessed, the CS7 signal can be output.
The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
122
6.4.5 Basic Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The
LWR pin is always high. Wait states can be inserted.
Bus cycle
External address in area n
Valid
Invalid
Valid
Undetermined data
High
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2T3
Figure 6.9 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
123
8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR
pin is always high. Wait states cannot be inserted.
Bus cycle
External address in area n
Valid
Invalid
Valid
Undetermined data
High
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2
Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
124
16-Bit, Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals
for a 16-bit, three-state-access area. In these areas, the upper data bus (D15 to D8) is used in
accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait
states can be inserted.
Bus cycle
Even external address in area n
Valid
Invalid
Valid
High
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2T3
Undetermined data
Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
125
Bus cycle
Odd external address in area n
Valid
Invalid
Valid
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2T3
High
Undetermined data
Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)
126
Bus cycle
External address in area n
Valid
Valid
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2T3
Valid
Valid
Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access)
127
16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for
a 16-bit, two-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to
even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states cannot
be inserted.
Bus cycle
Even external address in area n
Valid
Invalid
Valid
High
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2
Undetermined data
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
128
Bus cycle
Odd external address in area n
Valid
Invalid
Valid
High
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2
Undetermined data
Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address)
129
Bus cycle
External address in area n
Valid
Valid
φ
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Read access
Write access
Note: n = 7 to 0
T1T2
Valid
Valid
Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access)
6.4.6 Wait Control
When accessing external space, the H8/3008 can extend the bus cycle by inserting wait states (Tw).
There are two ways of inserting wait states: program wait insertion and pin wait insertion using the
WAIT pin.
Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2
state and T3 state on an individual area basis in three-state access space, according to the settings
of WCRH and WCRL.
130
Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the
WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the
WAIT pin is low at the falling edge of φ in the last T2 or TW state, another TW state is inserted. If
the WAIT pin is held low, TW states are inserted until it goes high.
This is useful when inserting four or more TW states, or when changing the number of TW states for
different external devices.
The WAITE bit setting applies to all areas.
Figure 6.17 shows an example of the timing for insertion of one program wait state in 3-state
space.
φ
WAIT
Address bus
Data bus
Read access
Write access Data bus
AS
RD
T1T2TwTwTwT3
HWR, LWR
Note: indicates the timing of WAIT pin sampling.
Inserted
by program wait Inserted by WAIT pin
Read data
Write data
Figure 6.17 Example of Wait State Insertion Timing
131
6.5 Idle Cycle
6.5.1 Operation
When the H8/3008 chip accesses external space, it can insert a 1-state idle cycle (Ti) between bus
cycles in the following cases: when read accesses between different areas occur consecutively, and
when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible,
for example, to avoid data collisions between ROM, which has a long output floating time, and
high-speed memory, I/O interfaces, and so on.
The initial value of the ICIS1 and ICIS0 bits in BCR is 1, so that idle cycle insertion is performed
in the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.18 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is
inserted, and a data collision is prevented.
φT1T2T3
RD
T1T2φT1T2T3TiT2
T1
Address bus
Data bus
RD
Address bus
Data bus
Bus cycle A Bus cycle B Bus cycle A Bus cycle B
Data collision
Long buffer-off time
(a) Idle cycle not inserted (b) Idle cycle inserted
Figure 6.18 Example of Idle Cycle Operation (ICIS1 = 1)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.19 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data
from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
132
φT1T2T3
RD
Address bus
Data bus
T1T2T1T2T3TiT2
T1
HWR
φ
RD
Address bus
Data bus
HWR
Bus cycle A Bus cycle B Bus cycle A Bus cycle B
Long buffer-off time Data collision
(a) Idle cycle not inserted (b) Idle cycle inserted
Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1)
Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall
(assertion) of CSn may occur simultaneously. Figure 6.20 shows an example of the operation in
this case.
If consecutive reads to a different external area occur while the ICIS1 bit in BCR is cleared to 0, or
if an external read is followed by a write cycle for a different external area while the ICIS0 bit is
cleared to 0, negation of RD in the first read cycle and assertion of CSn in the following bus cycle
will occur simultaneously. Depending on the output delay time of each signal, therefore, it is
possible that the RD low output in the previous read cycle and the CSn low output in the following
bus cycle will overlap.
As long as RD and CSn do not change simultaneously, or if there is no problem even if they do,
non-insertion of an idle cycle can be specified.
φT1T2T3
RD
Address bus
T1T2T1T2T3TiT2
T1
CSn
φ
RD
Address bus
CSn
Bus cycle A Bus cycle B Bus cycle A Bus cycle B
Simultaneous change of RD and
CSn: possibility of mutual overlap
(a) Idle cycle not inserted (b) Idle cycle inserted
Figure 6.20 Example of Idle Cycle Operation
133
6.5.2 Pin States in Idle Cycle
Table 6.5 shows the pin states in an idle cycle.
Table 6.5 Pin States in Idle Cycle
Pins Pin State
A23 to A0Next cycle address value
D15 to D0High impedance
CSn High
AS High
RD High
HWR High
LWR High
6.6 Bus Arbiter
The bus controller has a built-in bus arbiter that arbitrates between different bus masters. The bus
master can be either the CPU or an external bus master. When a bus master has the bus right it can
carry out read and write operations. Each bus master uses a bus request signal to request the bus
right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to
grant the bus to a bus master, which can the operate using the bus.
The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and
returns an acknowledge signal to the bus master. When two or more bus masters request the bus,
the highest-priority bus master receives an acknowledge signal. The bus master that receives an
acknowledge signal can continue to use the bus until the acknowledge signal is deactivated.
The bus master priority order is:
(High) External bus master > CPU (Low)
The bus arbiter samples the bus request signals and determines priority at all times, but it does not
always grant the bus immediately, even when it receives a bus request from a bus master with
higher priority than the current bus master. Each bus master has certain times at which it can
release the bus to a higher-priority bus master.
134
6.6.1 Operation
CPU: The CPU is the lowest-priority bus master. If an external bus master requests the bus while
the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it.
The bus right is transferred at the following times:
• The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two
consecutive byte accesses, however, the bus right is not transferred between the two byte
accesses.
• If another bus master requests the bus while the CPU is performing internal operations, such as
executing a multiply or divide instruction, the bus right is transferred immediately. The CPU
continues its internal operations.
• If another bus master requests the bus while the CPU is in sleep mode, the bus right is
transferred immediately.
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter driving the BREQ signal low. Once the external bus master acquires the bus, it
keeps the bus until the BREQ signal goes high. While the bus is released to an external bus
master, the H8/3008 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and
LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK
pin in the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock (φ). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the
bus-release cycle.
Figure 6.21 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state access area. There is a minimum interval of three states from when the
BREQ signal goes low until the bus is released.
135
φ
RD
BACK
(1) (2) (3) (4) (5) (6)
BREQ
HWR, LWR
T0T1T2
AS
Data bus
Address bus
CPU cycles CPU cyclesExternal bus released
High
Address
Minimum 3 cycles
High-impedance
High-impedance
High-impedance
High-impedance
High-impedance
Figure 6.21 Example of External Bus Master Operation
When making a transition to software standby mode, if there is contention with a bus request from
an external bus master, the BACK and strobe states may be indefinite when the transition is made.
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
136
6.7 Register and Pin Input Timing
6.7.1 Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
φT1T2T3T1T2T3T1T2
Address bus
3-state access to area 0 2-state access to area 0
ASTCR address
Figure 6.22 ASTCR Write Timing
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T3 state of
the DDR write cycle. Figure 6.23 shows the timing when the CS1 pin is changed from generic
input to CS1 output.
φT1T2T3
CS1
Address bus
High-impedance
P8DDR address
Figure 6.23 DDR Write Timing
BRCR Write Timing: Data written to BRCR to switch between A23, A22, A21, or A20 output and
generic input or output takes effect starting from the T3 state of the BRCR write cycle. Figure
6.24 shows the timing when a pin is changed from generic input to A23, A22, A21, or A20 output.
137
φT1T2T3
PA7 to PA4
(A23 to A20)
Address bus BRCR address
High-impedance
Figure 6.24 BRCR Write Timing
6.7.2 BREQ Pin Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes lows, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
138
139
Section 7 I/O Ports
7.1 Overview
The H8/3008 has six input/output ports (ports 4, 6, 8, 9, A, and B) and one input-only port (port
7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed as shown in
table 7.1.
Each port has a data direction register (DDR) for selecting input or output, and a data register
(DR) for storing output data. In addition to these registers, port 4 has an input pull-up control
register (PCR) for switching input pull-up transistors on and off.
Ports 4, 6, and 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive
one TTL load and a 30-pF capacitive load. Ports 4, 6, 8, 9, A, and B can drive a darlington pair.
Pins P82 to P80, PA7 to PA0 have Schmitt-trigger input circuits.
For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
Table 7.1 Port Functions
Expanded Modes
Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4
Port 4 • 8-bit I/O port
• Built-in input pull-
up transistors
P47 to P40/D7 to D0Data input/output (D7 to D0) and 8-bit generic input/output
8-bit bus mode: generic input/output
16-bit bus mode: data input/output
Port 6 • 8-bit I/O port P67/φClock output (φ) and generic input
P66/LWR
P65/HWR
P64/RD
P63/AS
Bus control signal output (LWR, HWR, RD, AS)
P62/BACK
P61/BREQ
P60/WAIT
Bus control signal input/output (BACK, BREQ, WAIT) and 3-
bit generic input/output
Port 7 • 8-bit I/O port P77/AN7/DA1
P76/AN6/DA0
Analog input (AN7, AN6) to A/D converter, analog output (DA1,
DA0) from D/A converter, and generic input
P75 to P70/
AN5 to AN0
Analog input (AN5 to AN0) to A/D converter, and generic input
140
Expanded Modes
Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4
Port 8 • 5-bit I/O port P84/CS0DDR = 0: generic input
DDR = 1 (reset value): CS0 output
• P82 to P80 have
schmitt inputs P83/IRQ3/CS1/
ADTRG
IRQ3 input, CS1 output, external trigger input (ADTRG) to A/D
converter, and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS1 output
P82/IRQ2/CS2
P81/IRQ1/CS3
IRQ2 and IRQ1 input, CS2 and CS3 output, and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS2 and CS3 output
P80/IRQ0IRQ0 input, and generic input/output
Port 9 • 6-bit I/O port P95/IRQ5 /SCK1
P94/IRQ4 /SCK0
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for
serial communication interfaces 1 and 0 (SCI1/0), IRQ5 and
IRQ4 input, and 6-bit generic input/output
Port A • 8-bit I/O port
• Schmitt inputs PA7/TP7/
TIOCB2/A20
Output (TP7) from pro-
grammable timing pattern
controller (TPC), input or
output (TIOCB2) for 16-bit
timer and generic input/output
Address output (A20)
PA6/TP6/TIOCA2/
A21
PA5/TP5/TIOCB1/
A22
PA4/TP4/TIOCA1/
A23
TPC output (TP6 to TP4), 16-bit timer input and output
(TIOCA2, TIOCB1, TIOCA1), and generic input/output
PA3/TP3/TIOCB0/
TCLKD
PA2/TP2/TIOCA0/
TCLKC
PA1/TP1/TCLKB
PA0/TP0/TCLKA
TPC output (TP3 to TP0), 16-bit timer input and output
(TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA), 8-bit
timer input (TCLKD, TCLKC, TCLKB, TCLKA), and generic
input/output
141
Expanded Modes
Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4
Port B • 8-bit I/O port PB7/TP15
PB6/TP14
PB5/TP13
PB4/TP12
TPC output (TP15 to TP12) and generic input/output
PB3/TP11/TMIO3/
CS4
PB2/TP10/TMO2/
CS5
PB1/TP9/TMIO1/
CS6
PB0/TP8/TMO0/
CS7
TPC output (TP11 to TP8), 8-bit timer input and output (TMIO3,
TMO2, TMIO1, TMO0), CS7 to CS4 output, and generic
input/output
Legend:
SCI0: Serial communication interface channel 0
SCI1: Serial communication interface channel 1
TPC: Programmable timing pattern controller
16TIM: 16-bit timer
8TIM: 8-bit timer
142
7.2 Port 4
7.2.1 Overview
Port 4 is an 8-bit input/output port which also functions as a data bus. It’s pin configuration is
shown in figure 7.1. The pin functions differ depending on the operating mode.
In the H8/3008, when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-
access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at
least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode
and port 4 becomes part of the data bus.
Port 4 has software-programmable built-in pull-up transistors.
Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 4
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P4 (input/output)/D7 (input/output)
P4 (input/output)/D6 (input/output)
P4 (input/output)/D5 (input/output)
P4 (input/output)/D4 (input/output)
P4 (input/output)/D3 (input/output)
P4 (input/output)/D2 (input/output)
P4 (input/output)/D1 (input/output)
P4 (input/output)/D0 (input/output)
7
6
5
4
3
2
1
0
Port 4 pins Modes 1 to 4
Figure 7.1 Port 4 Pin Configuration
143
7.2.2 Register Descriptions
Table 7.2 summarizes the registers of port 4.
Table 7.2 Port 4 Registers
Address* Name Abbreviation R/W Initial Value
H'EE003 Port 4 data direction register P4DDR W H'00
H'FFFD3 Port 4 data register P4DR R/W H'00
H'EE03E Port 4 input pull-up MOS control
register P4PCR R/W H'00
Note: * Lower 20 bits of the address in advanced mode.
Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select
input or output for each pin in port 4.
Bit
Initial value
Read/Write
7
P4 DDR
0
W
Port 4 data direction 7 to 0
These bits select input or output for port 4 pins
7
6
P4 DDR
0
W
6
5
P4 DDR
0
W
5
4
P4 DDR
0
W
4
3
P4 DDR
0
W
3
2
P4 DDR
0
W
2
1
P4 DDR
0
W
1
0
P4 DDR
0
W
0
When all areas are designated as 8-bit-access areas by the bus controller’s bus width control
register (ABWCR), selecting 8-bit bus mode, port 4 functions as an input/output port. In this case,
a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input
port if this bit is cleared to 0.
When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4
functions as part of the data bus, regardless of the P4DDR settings.
P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is
made to software standby mode while port 4 is functioning as an input/output port and a P4DDR
bit is set to 1, the corresponding pin maintains its output state.
Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data
for port 4. When port 4 functions as an output port, the value of this register is output. When a bit
144
in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a
bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin logic level is read.
Bit
Initial value
Read/Write
7
P4
0
R/W
Port 4 data 7 to 0
These bits store data for port 4 pins
7
6
P4
0
R/W
6
5
P4
0
R/W
5
4
P4
0
R/W
4
3
P4
0
R/W
3
2
P4
0
R/W
2
1
P4
0
R/W
1
0
P4
0
R/W
0
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 4 Input Pull-Up MOS Control Register (P4PCR): P4PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 4.
Bit
Initial value
Read/Write
7
P4 PCR
0
R/W
Port 4 input pull-up MOS control 7 to 0
These bits control input pull-up transistors built into port 4
7
6
P4 PCR
0
R/W
6
5
P4 PCR
0
R/W
5
4
P4 PCR
0
R/W
4
3
P4 PCR
0
R/W
3
2
P4 PCR
0
R/W
2
1
P4 PCR
0
R/W
1
0
P4 PCR
0
R/W
0
In 8-bit bus mode in modes 1 to 4 (expanded modes), when a P4DDR bit is cleared to 0 (selecting
generic input), if the corresponding P4PCR bit is set to 1, the input pull-up transistor is turned on.
P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 7.3 summarizes the states of the input pull-up MOS in each operating mode.
Table 7.3 Input Pull-Up Transistor States (Port 4)
Mode Reset Hardware
Standby Mode Software
Standby Mode Other Modes
1 to 4 8-bit bus mode Off Off On/off On/off
16-bit bus mode Off Off
Legend
Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.
145
7.3 Port 6
7.3.1 Overview
Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals
(LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock (φ) output.
The port 6 pin configuration is shown in figure 7.2.
See table 7.4 for the selection of the pin functions.
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 6
P6 /
P6 /
P6 /
P6 /
P6 /
P6 /
P6 /
P6 /
7
6
5
4
3
2
1
0
φ
LWR
HWR
RD
AS
BACK
BREQ
WAIT
Port 6 pins Modes 1 to 4
(expanded modes)
P67 (input)/φ (output)
LWR (output)
HWR (output)
RD (output)
AS (output)
P62 (input/output)/BACK (output)
P61 (input/output)/BREQ (input)
P60 (input/output)/WAIT (input)
Figure 7.2 Port 6 Pin Configuration
7.3.2 Register Descriptions
Table 7.4 summarizes the registers of port 6.
Table 7.4 Port 6 Registers
Address* Name Abbreviation R/W Initial Value
H'EE005 Port 6 data direction register P6DDR W H'80
H'FFFD5 Port 6 data register P6DR R/W H'80
Note: * Lower 20 bits of the address in advanced mode.
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select
input or output for each pin in port 6.
146
Bit 7 is reserved. It is fixed at 1, and cannot be modified.
Bit
Initial value
Read/Write
7
—
1
—
6
P6 DDR
0
W
6
5
P6 DDR
0
W
5
4
P6 DDR
0
W
4
3
P6 DDR
0
W
3
2
P6 DDR
0
W
2
1
P6 DDR
0
W
1
0
P6 DDR
0
W
0
Port 6 data direction 6 to 0
These bits select input or output for port 6 pins
Reserved bit
• Modes 1 to 4 (Expanded Modes)
P67 functions as the clock output pin (φ) or an input port. P67 is the clock output pin (ø) if the
PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input port if this bit is set to 1.
P66 to P63 function as bus control output pins (LWR, HWR, RD, and AS), regardless of the
settings of bits P66DDR to P63DDR.
P62 to P60 function as bus control input/output pins (BACK, BREQ, and WAIT) or
input/output ports. For the method of selecting the pin functions, see table 7.7.
When P62 to P60 function as input/output ports, the pin becomes an output port if the
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a
value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the
P67 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be
modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding
bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the
corresponding bit in P6DDR is set to 1.
Bit
Initial value
Read/Write
7
P67
1
R
6
P6
0
R/W
6
5
P6
0
R/W
5
4
P6
0
R/W
4
3
P6
0
R/W
3
2
P6
0
R/W
2
1
P6
0
R/W
1
0
P6
0
R/W
0
Port 6 data 7 to 0
These bits store data for port 6 pins
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
147
Table 7.5 Port 6 Pin Functions in Modes 1 to 4
Pin Pin Functions and Selection Method
P67/φBit PSTOP in MSTCRH selects the pin function.
PSTOP 0 1
Pin function φ output P67 input
LWR Functions as LWR regardless of the setting of bit P66DDR
P66DDR 0 1
Pin function LWR output
HWR Functions as HWR regardless of the setting of bit P65DDR
P65DDR 0 1
Pin function HWR output
RD Functions as RD regardless of the setting of bit P64DDR
P64DDR 0 1
Pin function RD output
AS Functions as AS regardless of the setting of bit P63DDR
P63DDR 0 1
Pin function AS output
P62/BACK Bit BRLE in BRCR and bit P62DDR select the pin function as follows.
BRLE 0 1
P62DDR 0 1 —
Pin function P62 input P62 output BACK output
P61/BREQ Bit BRLE in BRCR and bit P61DDR select the pin function as follows.
BRLE 0 1
P61DDR 0 1 —
Pin function P61 input P61 output BREQ input
P60/WAIT Bit WAITE in BCR and bit P60DDR select the pin function as follows.
WAITE 0 1
P60DDR 0 1 0*
Pin function P60 input P60 output WAIT input
Note: * Do not set bit P60DDR to 1.
148
7.4 Port 7
7.4.1 Overview
Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog
output from the D/A converter. The pin functions are the same in all operating modes. Figure 7.3
shows the pin configuration of port 7.
See section 14, A/D Converter, for details of the A/D converter analog input pins, and section 15,
D/A Converter, for details of the D/A converter analog output pins.
Port 7
P7 (input)/AN (input)/DA (output)
P7 (input)/AN (input)/DA (output)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Port 7 pins
1
0
Figure 7.3 Port 7 Pin Configuration
7.4.2 Register Description
Table 7.6 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction
register.
Table 7.6 Port 7 Data Register
Address* Name Abbreviation R/W Initial Value
H'FFFD6 Port 7 data register P7DR R Undetermined
Note: * Lower 20 bits of the address in advanced mode.
149
Port 7 Data Register (P7DR)
Bit
Initial value
Read/Write
0
P7
—
R*
Note: *
0
1
P7
—
R*
1
2
P7
—
R*
2
3
P7
—
R*
3
4
P7
—
R*
4
5
P7
—
R*
5
6
P7
—
R*
6
7
P7
—
R*
7
70
Determined by pins P7 to P7 .
When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.
7.5 Port 8
7.5.1 Overview
Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, IRQ3 to IRQ0 input, and
A/D converter ADTRG input. Figure 7.4 shows the pin configuration of port 8.
In the H8/3008, port 8 can provide CS3 to CS0 output, IRQ3 to IRQ0 input, and ADTRG input. See
table 7.8 for the selection of pin functions in expanded modes.
See section 14, A/D Converter, for a description of the A/D converter’s ADTRG input pin.
The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for
input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts.
Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Pins P82 to P80 have Schmitt-trigger inputs.
Port 8
P8 /
P8 / /
P8 / /
P8 / /
P8 /
4
3
2
1
0
0
1
2
3
Port 8 pins
CS
CS
CS
CS
3
2
1
IRQ / ADTRG
IRQ
IRQ
IRQ
0
P8 (input)/ (output)
P8 (input)/ (output)/ (input) / ADTRG (input)
P8 (input)/ (output)/ (input)
P8 (input)/ (output)/ (input)
P8 (input/output)/ (input)
4
3
2
1
0
0
1
2
3
CS
CS
CS
CS
3
2
1
IRQ
IRQ
IRQ
IRQ
0
Figure 7.4 Port 8 Pin Configuration
150
7.5.2 Register Descriptions
Table 7.7 summarizes the registers of port 8.
Table 7.7 Port 8 Registers
Address* Name Abbreviation R/W Initial Value
H'EE007 Port 8 data direction register P8DDR W H'F0
H'FFFD7 Port 8 data register P8DR R/W H'E0
Note: * Lower 20 bits of the address in advanced mode.
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
7
—
1
—
6
—
1
—
5
—
1
—
4
P8 DDR
1
W
4
3
P8 DDR
0
W
3
2
P8 DDR
0
W
2
1
P8 DDR
0
W
1
0
P8 DDR
0
W
0
Reserved bits Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
Bit
Initial value
Read/Write
When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to CS3 output pins. When bits in
P8DDR are cleared to 0, the corresponding pins become input ports.
In the H8/3008, following a reset P84 functions as the CS0 output, while CS1 to CS3 are input ports.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
P8DDR retains its previous setting. Therefore, if a transition is made to software standby mode
while port 8 is functioning as an input/output port and a P8DDR bit is set to 1, the corresponding
pin maintains its output state.
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data
for port 8. When port 8 functions as an output port, the value of this register is output. When a bit
in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned. When a
bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin logic level is read.
151
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
P8
0
R/W
4
3
P8
0
R/W
3
2
P8
0
R/W
2
1
P8
0
R/W
1
0
P8
0
R/W
0
Reserved bits Port 8 data 4 to 0
These bits store data
for port 8 pins
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
152
Table 7.8 Port 8 Pin Functions in Modes 1 to 4
Pin Pin Functions and Selection Method
P84/CS0Bit P84DDR selects the pin function as follows.
P84DDR 0 1
Pin function P84 input CS0 output
P83/CS1/IRQ3/ Bit P83DDR selects the pin function as follows
ADTRG P83DDR 0 1
Pin function P83 input CS1 output
IRQ3 input
ADTRG input
P82/CS2/IRQ2Bit P82DDR selects the pin function as follows.
P82DDR 0 1
Pin function P82 input CS2 output
IRQ2 input
P81/CS3/IRQ1Bit P81DDR selects the pin function as follows.
P81DDR 0 1
Pin function P81 input CS3 output
IRQ1 input
P80/IRQ0Bit P80DDR selects the pin function as follows.
P80DDR 0 1
Pin function P80 input P80 output
IRQ0 input
153
7.6 Port 9
7.6.1 Overview
Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1,
SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5
and IRQ4 input. See table 7.10 for the selection of pin functions.
The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used
for input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts.
Port 9 has the same set of pin functions in all operating modes. Figure 7.5 shows the pin
configuration of port 9.
Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair.
Port 9
P9 (input/output)/SCK
P9 (input/output)/SCK
P9 (input/output)/RxD (input)
P9 (input/output)/RxD (input)
P9 (input/output)/TxD (output)
P9 (input/output)/TxD (output)
5
4
3
2
1
0
Port 9 pins
1
0
(input/output)/IRQ (input)
(input/output)/IRQ (input)
5
4
1
0
1
0
Figure 7.5 Port 9 Pin Configuration
7.6.2 Register Descriptions
Table 7.9 summarizes the registers of port 9.
Table 7.9 Port 9 Registers
Address* Name Abbreviation R/W Initial Value
H'EE008 Port 9 data direction register P9DDR W H'C0
H'FFFD8 Port 9 data register P9DR R/W H'C0
Note: * Lower 20 bits of the address in advanced mode.
154
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select
input or output for each pin in port 9.
Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
P9 DDR
0
W
5
4
P9 DDR
0
W
4
3
P9 DDR
0
W
3
2
P9 DDR
0
W
2
1
P9 DDR
0
W
1
0
P9 DDR
0
W
0
Reserved bits Port 9 data direction 5 to 0
These bits select input or
output for port 9 pins
When port 9 functions as an input/output port, a pin in port 9 becomes an output port if the
corresponding P9DDR bit is set to 1, and an input port if this bit is cleared to 0. For the method of
selecting the pin functions, see table 7.10.
P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port 9 is functioning as an input/output port and a P9DDR bit is set to 1, the corresponding pin
maintains its output state.
Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data
for port 9. When port 9 functions as an output port, the value of this register is output. When a bit
in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a
bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read.
Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
P9
0
R/W
4
P9
0
R/W
4
3
P9
0
R/W
3
2
P9
0
R/W
2
1
P9
0
R/W
1
0
P9
0
R/W
0
Reserved bits Port 9 data 5 to 0
These bits store data
for port 9 pins
5
P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
155
Table 7.10 Port 9 Pin Functions
Pin Pin Functions and Selection Method
P95/SCK1/IRQ5Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P95DDR
select the pin function as follows.
CKE1 0 1
C/A01—
CKE0 0 1 ——
P95DDR 0 1 ———
Pin function P95
input P95
output SCK1
output SCK1
output SCK1
input
IRQ5 input
P94/SCK0/IRQ4Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P94DDR
select the pin function as follows.
CKE1 0 1
C/A01—
CKE0 0 1 ——
P94DDR 0 1 ———
Pin function P94
input P94
output SCK0
output SCK0
output SCK0
input
IRQ4 input
P93/RxD1Bit RE in SCR of SCI1, bit SMIF in SCMR, and bit P93DDR select the pin
function as follows.
SMIF 0 1
RE 0 1 —
P93DDR 0 1 ——
Pin function P93 input P93 output RxD1 input RxD1 input
P92/RxD0Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin
function as follows.
SMIF 0 1
RE 0 1 —
P92DDR 0 1 ——
Pin function P92 input P92 output RxD0 input RxD0 input
156
Pin Pin Functions and Selection Method
P91/TxD1Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P91DDR select the pin
function as follows.
SMIF 0 1
TE 0 1 —
P91 DDR 0 1 ——
Pin function P91 input P91 output TxD1 output TxD1 output*
Note: * Functions as the TxD1 output pin, but there are two states: one in
which the pin is driven, and another in which the pin is at high-
impedance.
P90/TxD0Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin
function as follows.
SMIF 0 1
TE 0 1 —
P90DDR 0 1 ——
Pin function P90 input P90 output TxD0 output TxD0 output*
Note: * Functions as the TxD0 output pin, but there are two states: one in
which the pin is driven, and another in which the pin is at high-
impedance.
7.7 Port A
7.7.1 Overview
Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable
timing pattern controller (TPC), input and output (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0,
TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, clock input (TCLKD, TCLKC,
TCLKB, TCLKA) to the 8-bit timer, and address output (A23 to A20). A reset or hardware standby
transition leaves port A as an input port, except that in modes 3 and 4, one pin is always used for
A20 output. See tables 7.12 to 7.14 for the selection of pin functions.
Usage of pins for TPC, 16-bit timer, and 8-bit timer input and output is described in the sections
on those modules. For output of address bits A23 to A20 in modes 3 and 4, see section 6.2.4, Bus
Release Control Register (BRCR). Pins not assigned to any of these functions are available for
generic input/output. Figure 7.6 shows the pin configuration of port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair. Port A has Schmitt-trigger inputs.
157
Port A
PA /TP /TIOCB /A
PA /TP /TIOCA /A
21
PA /TP /TIOCB /A
22
PA /TP /TIOCA /A
23
PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TCLKB
PA /TP /TCLKA
7
6
5
4
3
2
1
0
Port A pins
7
6
5
4
3
2
1
0
2
2
1
1
0
0
7
6
5
4
3
2
1
0
Pin functions in modes 1 and 2
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
7
6
5
4
3
2
1
0
2
2
1
1
0
0
20
6
5
4
3
2
1
0
Pin functions in modes 3 and 4
A (output)
PA (input/output)/TP (output)/TIOCA (input/output)/A (output)
PA (input/output)/TP (output)/TIOCB (input/output)/A (output)
PA (input/output)/TP (output)/TIOCA (input/output)/A (output)
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
6
5
4
3
2
1
0
2
1
1
0
0
20
21
22
23
Figure 7.6 Port A Pin Configuration
7.7.2 Register Descriptions
Table 7.11 summarizes the registers of port A.
Table 7.11 Port A Registers
Initial Value
Address* Name R/W Modes 1 and 2 Modes 3 and 4
H'EE009 Port A data direction
register PADDR W H'00 H'80
H'FFFD9 Port A data register PADR R/W H'00 H'00
Note: * Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
158
7
PA DDR
1
—
0
W
Port A data direction 7 to 0
These bits select input or output for port A pins
7
6
PA DDR
0
W
0
W
6
5
PA DDR
0
W
0
W
5
4
PA DDR
0
W
0
W
4
3
PA DDR
0
W
0
W
3
2
PA DDR
0
W
0
W
2
1
PA DDR
0
W
0
W
1
0
PA DDR
0
W
0
W
0
Bit
Modes
3 and 4 Initial value
Read/Write
Initial value
Read/Write
Modes
1 and 2
The pin functions that can be selected for pins PA7 to PA4 differ between modes 1 and 2, and
modes 3 and 4. For the method of selecting the pin functions, see tables 7.12 and 7.13.
The pin functions that can be selected for pins PA3 to PA0 are the same in modes 1 to 4. For the
method of selecting the pin functions, see table 7.14.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA7DDR is fixed at 1 and PA7 functions as the A20 address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1 and 2. It is
initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software standby
mode it retains its previous setting. Therefore, if a transition is made to software standby mode
while port A is functioning as an input/output port and a PADDR bit is set to 1, the corresponding
pin maintains its output state.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
Bit
Initial value
Read/Write
0
PA
0
R/W
0
1
PA
0
R/W
1
2
PA
0
R/W
2
3
PA
0
R/W
3
4
PA
0
R/W
4
5
PA
0
R/W
5
6
PA
0
R/W
6
7
PA
0
R/W
7
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
159
Table 7.12 Port A Pin Functions (Modes 1 and 2)
Pin Pin Functions and Selection Method
PA7/TP7/
TIOCB2
Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit
PA7DDR select the pin function as follows.
16-bit timer
channel 2 settings (1) in table below (2) in table below
PA7DDR —011
NDER7 ——01
Pin function TIOCB2 output PA7
input PA7
output TP7
output
TIOCB2 input*
Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.
16-bit timer
channel 2 settings (2) (1) (2)
IOB2 0 1
IOB1 0 0 1 —
IOB0 0 1 ——
PA6/TP6/
TIOCA2
Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit
PA6DDR select the pin function as follows.
16-bit timer
channel 2 settings (1) in table below (2) in table below
PA6DDR —011
NDER6 ——01
Pin function TIOCA2 output PA6
input PA6
output TP6
output
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
16-bit timer
channel 2 settings (2) (1) (2) (1)
PWM2 0 1
IOA2 0 1 —
IOA1 0 0 1 ——
IOA0 0 1 —— —
160
Pin Pin Functions and Selection Method
PA5/TP5/
TIOCB1
Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit
PA5DDR select the pin function as follows.
16-bit timer
channel 1 settings (1) in table below (2) in table below
PA5DDR —011
NDER5 ——01
Pin function TIOCB1 output PA5
input PA5
output TP5
output
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
16-bit timer
channel 1 settings (2) (1) (2)
IOB2 0 1
IOB1 0 0 1 —
IOB0 0 1 ——
PA4/TP4/
TIOCA1
Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit
PA4DDR select the pin function as follows.
16-bit timer
channel 1 settings (1) in table below (2) in table below
PA4DDR —011
NDER4 ——01
Pin function TIOCA1 output PA4
input PA4
output TP4
output
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
16-bit timer
channel 1 settings (2) (1) (2) (1)
PWM1 0 1
IOA2 0 1 —
IOA1 0 0 1 ——
IOA0 0 1 —— —
161
Table 7.13 Port A Pin Functions (Modes 3 and 4)
Pin Pin Functions and Selection Method
A20 Always used as A20 output.
Pin function A20 output
PA6/TP6/
TIOCA2/A21
Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in
BRCR, and bit PA6DDR select the pin function as follows.
A21E 1 0
16-bit timer
channel 2 settings (1) in table below (2) in table below —
PA6DDR —011—
NDER6 ——01—
Pin function TIOCA2 output PA6
input PA6
output TP6
output A21
output
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
16-bit timer channel 2 settings (2) (1) (2) (1)
PWM2 0 1
IOA2 0 1 —
IOA1 0 0 1 ——
IOA0 0 1 ———
162
Pin Pin Functions and Selection Method
PA5/TP5/
TIOCB1/A22
Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in
BRCR, and bit PA5DDR select the pin function as follows.
A22E 1 0
16-bit timer
channel 1 settings (1) in table below (2) in table below —
PA5DDR —011—
NDER5 ——01—
Pin function TIOCB1 output PA5
input PA5
output TP5
output A22
output
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
16-bit timer
channel 1 settings (2) (1) (2)
IOB2 0 1
IOB1 0 0 1 —
IOB0 0 1 ——
PA4/TP4/
TIOCA1/A23
Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in
BRCR, and bit PA4DDR select the pin function as follows.
A23E 1 0
16-bit timer
channel 1 settings (1) in table below (2) in table below —
PA4DDR —011—
NDER4 ——01—
Pin function TIOCA1 output PA4
input PA4
output TP4
output A23
output
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
16-bit timer
channel 1 settings (2) (1) (2) (1)
PWM1 0 1
IOA2 0 1 —
IOA1 0 0 1 ——
IOA0 0 1 —— —
163
Table 7.14 Port A Pin Functions (Modes 1 to 4)
Pin Pin Functions and Selection Method
PA3/TP3/
TIOCB0/
TCLKD
Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to
16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit
NDER3 in NDERA, and bit PA3DDR select the pin function as follows.
16-bit timer
channel 0 settings (1) in table below (2) in table below
PA3DDR —011
NDER3 ——01
Pin function TIOCB0
output PA3
input PA3
output TP3
output
TIOCB0 input*1
TCLKD input*2
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.
2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to
16TCR0, or bits CKS2 to CKS0 in 8TCR2 are as shown in (3) in the table
below.
16-bit timer
channel 0 settings (2) (1) (2)
IOB2 0 1
IOB1 0 0 1 —
IOB0 0 1 ——
8-bit timer
channel 2 settings (4) (3)
CKS2 0 1
CKS1 —01
CKS0 —01 —
164
Pin Pin Functions and Selection Method
PA2/TP2/
TIOCA0/
TCLKC
Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to
16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit
NDER2 in NDERA, and bit PA2DDR select the pin function as follows.
16-bit timer
channel 0 settings (1) in table below (2) in table below
PA2DDR —011
NDER2 ——01
Pin function TIOCA0 output PA2
input PA2
output TP2
output
TIOCA0 input*1
TCLKC input*2
Notes: 1. TIOCA0 input when IOA2 = 1.
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of
16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (3)
in the table below.
16-bit timer
channel 0 settings (2) (1) (2) (1)
PWM0 0 1
IOA2 0 1 —
IOA1 0 0 1 ——
IOA0 0 1 —— —
8-bit timer
channel 0 settings (4) (3)
CKS2 0 1
CKS1 —01
CKS0 —01 —
165
Pin Pin Functions and Selection Method
PA1/TP1/
TCLKB Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit
PA1DDR select the pin function as follows.
PA1DDR 0 1 1
NDER1 —01
Pin function PA1 input PA1 output TP1 output
TCLKB input*
Note: * CLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and
TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR3 are
as shown in (1) in the table below.
8-bit timer
channel 3 settings (2) (1)
CKS2 0 1
CKS1 —01
CKS0 —01 —
PA0/TP0/
TCLKA Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit
PA0DDR select the pin function as follows.
PA0DDR 0 1
NDER0 —01
Pin function PA0 input PA0 output TP0 output
TCLKA input*
Note: * TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1 and TPSC1 = 0, and
TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR1 are
as shown in (1) in the table below.
8-bit timer
channel 1 settings (2) (1)
CKS2 0 1
CKS1 —01
CKS0 —01 —
166
7.8 Port B
7.8.1 Overview
Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the
programmable timing pattern controller (TPC), input/output (TMIO3, TMO2, TMIO1, TMO0) by
the 8-bit timer, and CS7 to CS4 output. See table 7.15 for the selection of pin functions. A reset or
hardware standby transition leaves port B as an input/output port.
For output of CS7 to CS4 in modes 1 to 4, see section 6.3.4, Chip Select Signals. Pins not assigned
to any of these functions are available for generic input/output. Figure 7.7 shows the pin
configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington
transistor pair.
Port B
PB7/TP
15
PB6/TP
14
PB5/TP
13
PB4/TP
12
PB3/TP /TMIO3/CS411
PB2/TP /TMO2/CS510
PB1/TP /TMIO1/CS69
PB0/TP /TMO0/CS78
Port B pins
PB7 (input/output)/TP15 (output)
PB6 (input/output)/TP14 (output)
PB5 (input/output)/TP13 (output)
PB4 (input/output)/TP12 (output)
PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /CS4 (output)
PB2 (input/output)/TP10 (output) /TMO2 (output) /CS5 (output)
PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /CS6 (output)
PB0 (input/output)/TP8 (output) /TMO0 (output) /CS7 (output)
Pin functions in modes 1 to 4
Figure 7.7 Port B Pin Configuration
167
7.8.2 Register Descriptions
Table 7.15 summarizes the registers of port B.
Table 7.15 Port B Registers
Address* Name Abbreviation R/W Initial Value
H'EE00A Port B data direction register PBDDR W H'00
H'FFFDA Port B data register PBDR R/W H'00
Note: * Lower 20 bits of the address in advanced mode.
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
Initial value
Read/Write
7
PB DDR
0
W
Port B data direction 7 to 0
These bits select input or output for port B pins
7
6
PB DDR
0
W
6
5
PB DDR
0
W
5
4
PB DDR
0
W
4
3
PB DDR
0
W
3
2
PB DDR
0
W
2
1
PB DDR
0
W
1
0
PB DDR
0
W
0
For the method of selecting the pin functions, see table 7.16.
When port B functions as an input/output port, a pin in port B becomes an output port if the
corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin
maintains its output state.
168
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data
for pins port B. When port B functions as an output port, the value of this register is output. When
a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned.
When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read.
Bit
Initial value
Read/Write
0
PB
0
R/W
0
1
PB
0
R/W
1
2
PB
0
R/W
2
3
PB
0
R/W
3
4
PB
0
R/W
4
5
PB
0
R/W
5
6
PB
0
R/W
6
7
PB
0
R/W
7
Port B data 7 to 0
These bits store data for port B pins
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
169
Table 7.16 Port B Pin Functions (Modes 1 to 4)
Pin Pin Functions and Selection Method
PB7/TP15 Bit NDER15 in NDERB and bit PB7DDR select the pin function as follows.
PB7DDR 0 1 1
NDER15 —01
Pin function PB7 input PB7 output TP15 output
PB6/TP14 Bit NDER14 in NDERB and bit PB6DDR select the pin function as follows.
PB6DDR 0 1 1
NDER14 —01
Pin function PB6 input PB6 output TP14 output
PB5/TP13 Bit NDER13 in NDERB and bit PB5DDR select the pin function as follows.
PB5DDR 0 1 1
NDER13 —01
Pin function PB5 input PB5 output TP13 output
PB4/TP12 Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows.
PB4DDR 0 1 1
NDER12 —01
Pin function PB4 input PB4 output TP12 output
PB3/TP11/
TMIO3/CS4
Bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1/0 in 8TCR3, bit CS4E in CSCR, bit
NDER11 in NDERB, and bit PB3DDR select the pin function as follows.
OIS3/2 and
OS1/0 All 0 Not all 0
CS4E 0 1 —
PB3DDR 0 1 1 ——
NDER11 —01——
Pin function PB3
input PB3
output TP11
output CS4
output TMIO3 output
TMIO3 input*
Note: * TMIO3 input when bit ICE = 1 in 8TCSR3.
170
Pin Pin Functions and Selection Method
PB2/TP10/
TMO2/CS5
Bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and
bit PB2DDR select the pin function as follows.
OIS3/2 and
OS1/0 All 0 Not all 0
CS5E 0 1 —
PB2DDR 0 1 1 ——
NDER10 —01——
Pin function PB2
input PB2
output TP10
output CS5
output TMIO2
output
PB1/TP9/
TMIO1/CS6
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1/0 in 8TCR1, bit CS6E in CSCR, bit
NDER9 in NDERB, and bit PB1DDR select the pin function as follows.
OIS3/2 and
OS1/0 All 0 Not all 0
CS6E 0 1 —
PB1DDR 0 1 1 ——
NDER9 —01——
Pin function PB1
input PB1
output TP9
output CS6
output TMIO1
output
TMIO1 input*
Note: * TMIO1 input when bit ICE = 1 in 8TCSR1.
PB0/TP8/
TMO0/CS7
Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and bit
PB0DDR select the pin function as follows.
OIS3/2 and
OS1/0 All 0 Not all 0
CS7E 0 1 —
PB0DDR 0 1 1 ——
NDER8 —01——
Pin function PB0
input PB0
output TP8
output CS7
output TMO0
output
171
Section 8 16-Bit Timer
8.1 Overview
The H8/3008 has built-in 16-bit timer module with three 16-bit counter channels.
8.1.1 Features
16-bit timer features are listed below.
• Capability to process up to 6 pulse outputs or 6 pulse inputs
• Six general registers (GRs, two per channel) with independently-assignable output compare or
input capture functions
• Selection of eight counter clock sources for each channel:
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• Five operating modes selectable in all channels:
Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
Input capture function
Rising edge, falling edge, or both edges (selectable)
Counter clearing function
Counters can be cleared by compare match or input capture
Synchronization
Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
three-phase PWM output is possible
• Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
• High-speed access via internal 16-bit bus
The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus.
• Any initial timer output value can be set
• Nine interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
172
• Output triggering of programmable timing pattern controller (TPC)
Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers.
Table 8.1 summarizes the 16-bit timer functions.
Table 8.1 16-bit timer Functions
Item Channel 0 Channel 1 Channel 2
Clock sources Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable
independently
General registers (output
compare/input
capture registers)
GRA0, GRB0 GRA1, GRB1 GRA2, GRB2
Input/output pins TIOCA0, TIOCB0TIOCA1, TIOCB1TIOCA2, TIOCB2
Counter clearing function GRA0/GRB0 compare
match or input capture GRA1/GRB1 compare
match or input capture GRA2/GRB2 compare
match or input capture
Initial output value setting function Available Available Available
Compare 0 Available Available Available
match output 1Available Available Available
Toggle Available Available Not available
Input capture function Available Available Available
Synchronization Available Available Available
PWM mode Available Available Available
Phase counting mode Not available Not available Available
Interrupt sources Three sources
• Compare match/input
capture A0
• Compare match/input
capture B0
• Overflow
Three sources
• Compare match/input
capture A1
• Compare match/input
capture B1
• Overflow
Three sources
• Compare match/input
capture A2
• Compare match/input
capture B2
• Overflow
173
8.1.2 Block Diagrams
16-bit timer Block Diagram (Overall): Figure 8.1 is a block diagram of the 16-bit timer.
16-bit timer channel 2
16-bit timer channel 1
16-bit timer channel 0
Module data bus
Bus interface
Internal data bus
IMIA0 to IMIA2
IMIB0 to IMIB2
OVI0 to OVI2
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8 Clock selector
Control logic
TIOCA0 to TIOCA2
TIOCB0 to TIOCB2
TSTR
TSNR
TMDR
TOLR
TISRA
TISRB
TISRC
Legend:
TSTR: Timer start register (8 bits)
TSNR: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TOLR: Timer output level setting register (8 bits)
TISRA: Timer interrupt status register A (8 bits)
TISRB: Timer interrupt status register B (8 bits)
TISRC: Timer interrupt status register C (8 bits)
Figure 8.1 16-bit timer Block Diagram (Overall)
174
Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical.
Both have the structure shown in figure 8.2.
Clock selector
Comparator
Control logic
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA0
TIOCB0
IMIA0
IMIB0
OVI0
16TCNT
GRA
GRB
16TCR
TIOR
Module data bus
Legend:
16TCNT:
GRA, GRB:
TCR:
TIOR:
Timer counter (16 bits)
General registers A and B (input capture/output compare registers) (16 bits 2)
Timer control register (8 bits)
Timer I/O control register (8 bits)
×
Figure 8.2 Block Diagram of Channels 0 and 1
175
Block Diagram of Channel 2: Figure 8.3 is a block diagram of channel 2
Clock selector
Comparator
Control logic
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA2
TIOCB2
IMIA2
IMIB2
OVI2
16TCNT2
GRA2
GRB2
16TCR2
TIOR2
Module data bus
Legend:
16TCNT2:
GRA2, GRB2:
TCR2:
TIOR2:
Timer counter 2 (16 bits)
General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
Timer control register 2 (8 bits)
Timer I/O control register 2 (8 bits)
Figure 8.3 Block Diagram of Channel 2
176
8.1.3 Pin Configuration
Table 8.2 summarizes the 16-bit timer pins.
Table 8.2 16-bit timer Pins
Channel Name Abbre-
viation Input/
Output Function
Common Clock input A TCLKA Input External clock A input pin
(phase-A input pin in phase counting mode)
Clock input B TCLKB Input External clock B input pin
(phase-B input pin in phase counting mode)
Clock input C TCLKC Input External clock C input pin
Clock input D TCLKD Input External clock D input pin
0 Input capture/output
compare A0 TIOCA0Input/
output GRA0 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B0 TIOCB0Input/
output GRB0 output compare or input capture pin
1 Input capture/output
compare A1 TIOCA1Input/
output GRA1 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B1 TIOCB1Input/
output GRB1 output compare or input capture pin
2 Input capture/output
compare A2 TIOCA2Input/
output GRA2 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B2 TIOCB2Input/
output GRB2 output compare or input capture pin
177
8.1.4 Register Configuration
Table 8.3 summarizes the 16-bit timer registers.
Table 8.3 16-bit timer Registers
Channel Address*1Name Abbre-
viation R/W Initial
Value
Common H'FFF60 Timer start register TSTR R/W H'F8
H'FFF61 Timer synchro register TSNC R/W H'F8
H'FFF62 Timer mode register TMDR R/W H'98
H'FFF63 Timer output level setting register TOLR W H'C0
H'FFF64 Timer interrupt status register A TISRA R/(W)*2H'88
H'FFF65 Timer interrupt status register B TISRB R/(W)*2H'88
H'FFF66 Timer interrupt status register C TISRC R/(W)*2H'88
0 H'FFF68 Timer control register 0 16TCR0 R/W H'80
H'FFF69 Timer I/O control register 0 TIOR0 R/W H'88
H'FFF6A Timer counter 0H 16TCNT0H R/W H'00
H'FFF6B Timer counter 0L 16TCNT0L R/W H'00
H'FFF6C General register A0H GRA0H R/W H'FF
H'FFF6D General register A0L GRA0L R/W H'FF
H'FFF6E General register B0H GRB0H R/W H'FF
H'FFF6F General register B0L GRB0L R/W H'FF
1 H'FFF70 Timer control register 1 16TCR1 R/W H'80
H'FFF71 Timer I/O control register 1 TIOR1 R/W H'88
H'FFF72 Timer counter 1H 16TCNT1H R/W H'00
H'FFF73 Timer counter 1L 16TCNT1L R/W H'00
H'FFF74 General register A1H GRA1H R/W H'FF
H'FFF75 General register A1L GRA1L R/W H'FF
H'FFF76 General register B1H GRB1H R/W H'FF
H'FFF77 General register B1L GRB1L R/W H'FF
178
Channel Address*1Name Abbre-
viation R/W Initial
Value
2 H'FFF78 Timer control register 2 16TCR2 R/W H'80
H'FFF79 Timer I/O control register 2 TIOR2 R/W H'88
H'FFF7A Timer counter 2H 16TCNT2H R/W H'00
H'FFF7B Timer counter 2L 16TCNT2L R/W H'00
H'FFF7C General register A2H GRA2H R/W H'FF
H'FFF7D General register A2L GRA2L R/W H'FF
H'FFF7E General register B2H GRB2H R/W H'FF
H'FFF7F General register B2L GRB2L R/W H'FF
Notes: 1. The lower 20 bits of the address in advanced mode are indicated.
2. Only 0 can be written in bits 3 to 0, to clear the flags.
8.2 Register Descriptions
8.2.1 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in
channels 0 to 2.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
STR2
0
R/W
1
STR1
0
R/W
0
STR0
0
R/W
Reserved bits Counter start 2 to 0
These bits start and
stop 16TCNT2 to 16TCNT0
TSTR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2).
Bit 2
STR2 Description
0 16TCNT2 is halted (Initial value)
1 16TCNT2 is counting
179
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1).
Bit 1
STR1 Description
0 16TCNT1 is halted (Initial value)
1 16TCNT1 is counting
Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0).
Bit 0
STR0 Description
0 16TCNT0 is halted (Initial value)
1 16TCNT0 is counting
8.2.2 Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate
independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
SYNC2
0
R/W
1
SYNC1
0
R/W
0
SYNC0
0
R/W
Reserved bits Timer sync 2 to 0
These bits synchronize
channels 2 to 0
TSNC is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or
synchronously.
Bit 2
SYNC2 Description
0 Channel 2’s timer counter (16TCNT2) operates independently (Initial value)
16TCNT2 is preset and cleared independently of other channels
1 Channel 2 operates synchronously
16TCNT2 can be synchronously preset and cleared
180
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1 Description
0 Channel 1’s timer counter (16TCNT1) operates independently (Initial value)
16TCNT1 is preset and cleared independently of other channels
1 Channel 1 operates synchronously
16TCNT1 can be synchronously preset and cleared
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0 Description
0 Channel 0’s timer counter (16TCNT0) operates independently (Initial value)
16TCNT0 is preset and cleared independently of other channels
1 Channel 0 operates synchronously
16TCNT0 can be synchronously preset and cleared
8.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
7
—
1
—
6
MDF
0
R/W
5
FDIR
0
R/W
4
—
1
—
3
—
1
—
0
PWM0
0
R/W
2
PWM2
0
R/W
1
PWM1
0
R/W
Reserved bit
Reserved bit PWM mode 2 to 0
These bits select PWM
mode for channels 2 to 0
Phase counting mode flag
Selects phase counting mode for channel 2
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
TMDR is initialized to H'98 by a reset and in standby mode.
181
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF Description
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in phase counting mode
When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter
and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and
falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting
Direction Down-Counting Up-Counting
TCLKA pin ↑High ↓Low Low ↑High ↓
TCLKB pin Low ↑High ↓↑High ↓Low
In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2
and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting
mode operations take precedence.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the
compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC
remain effective in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The
FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR Description
0 OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows (Initial value)
1 OVF is set to 1 in TISRC when 16TCNT2 overflows
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
182
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2 Description
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in PWM mode
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The
output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1 Description
0 Channel 1 operates normally (Initial value)
1 Channel 1 operates in PWM mode
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The
output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0 Description
0 Channel 0 operates normally (Initial value)
1 Channel 0 operates in PWM mode
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
183
8.2.4 Timer Interrupt Status Register A (TISRA)
TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture
and enables or disables GRA compare match and input capture interrupt requests.
7
—
1
—
Bit
Initial value
Read/Write
6
IMIEA2
0
R/W
5
IMIEA1
0
R/W
4
IMIEA0
0
R/W
3
—
1
—
2
IMFA2
0
R/(W)*
1
IMFA1
0
R/(W)*
0
IMFA0
0
R/(W)*
Reserved bit
Reserved bit
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
Note: * Only 0 can be written, to clear the flag.
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables
the interrupt requested by the IMFA2 when IMFA2 flag is set to 1.
Bit 6
IMIEA2 Description
0 IMIA2 interrupt requested by IMFA2 flag is disabled (Initial value)
1 IMIA2 interrupt requested by IMFA2 flag is enabled
184
Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables
the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Bit 5
IMIEA1 Description
0 IMIA1 interrupt requested by IMFA1 flag is disabled (Initial value)
1 IMIA1 interrupt requested by IMFA1 flag is enabled
Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables
the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 4
IMIEA0 Description
0 IMIA0 interrupt requested by IMFA0 flag is disabled (Initial value)
1 IMIA0 interrupt requested by IMFA0 flag is enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2
compare match or input capture events.
Bit 2
IMFA2 Description
0 [Clearing condition] (Initial value)
Read IMFA2 flag when IMFA2 =1, then write 0 in IMFA2 flag
1 [Setting conditions]
• 16TCNT2 = GRA2 when GRA2 functions as an output compare register
• 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2
functions as an input capture register
185
Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1
compare match or input capture events.
Bit 1
IMFA1 Description
0 [Clearing condition] (Initial value)
Read IMFA1 flag when IMFA1 =1, then write 0 in IMFA1 flag
1 [Setting conditions]
• 16TCNT1 = GRA1 when GRA1 functions as an output compare register
• 16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1
functions as an input capture register
Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0
compare match or input capture events.
Bit 0
IMFA0 Description
0 [Clearing condition] (Initial value)
Read IMFA0 flag when IMFA0 =1, then write 0 in IMFA0 flag
1 [Setting conditions]
• 16TCNT0 = GRA0 when GRA0 functions as an output compare register
• 16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0
functions as an input capture register
186
8.2.5 Timer Interrupt Status Register B (TISRB)
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables GRB compare match and input capture interrupt requests.
7
—
1
—
Bit
Initial value
Read/Write
6
IMIEB2
0
R/W
5
IMIEB1
0
R/W
4
IMIEB0
0
R/W
3
—
1
—
2
IMFB2
0
R/(W)*
1
IMFB1
0
R/(W)*
0
IMFB0
0
R/(W)*
Reserved bit
Reserved bit
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
Note: * Only 0 can be written, to clear the flag.
TISRB is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables
the interrupt requested by the IMFB2 when IMFB2 flag is set to 1.
Bit 6
IMIEB2 Description
0 IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value)
1 IMIB2 interrupt requested by IMFB2 flag is enabled
187
Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables
the interrupt requested by the IMFB1 when IMFB1 flag is set to 1.
Bit 5
IMIEB1 Description
0 IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value)
1 IMIB1 interrupt requested by IMFB1 flag is enabled
Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables
the interrupt requested by the IMFB0 when IMFB0 flag is set to 1.
Bit 4
IMIEB0 Description
0 IMIB0 interrupt requested by IMFB0 flag is disabled (Initial value)
1 IMIB0 interrupt requested by IMFB0 flag is enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2
compare match or input capture events.
Bit 2
IMFB2 Description
0 [Clearing condition] (Initial value)
Read IMFB2 flag when IMFB2 =1, then write 0 in IMFB2 flag
1 [Setting conditions]
• 16TCNT2 = GRB2 when GRB2 functions as an output compare register
• 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2
functions as an input capture register
188
Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1
compare match or input capture events.
Bit 1
IMFB1 Description
0 [Clearing condition] (Initial value)
Read IMFB1 flag when IMFB1 =1, then write 0 in IMFB1 flag
1 [Setting conditions]
• 16TCNT1 = GRB1 when GRB1 functions as an output compare register
• 16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1
functions as an input capture register
Bit 0—Input Capture/Compare Match Flag B0 (IMFB0): This status flag indicates GRB0
compare match or input capture events.
Bit 0
IMFB0 Description
0 [Clearing condition] (Initial value)
Read IMFB0 flag when IMFB0 =1, then write 0 in IMFB0 flag
1 [Setting conditions]
• 16TCNT0 = GRB0 when GRB0 functions as an output compare register
• 16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0
functions as an input capture register
189
8.2.6 Timer Interrupt Status Register C (TISRC)
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
7
—
1
—
Bit
Initial value
Read/Write
6
OVIE2
0
R/W
5
OVIE1
0
R/W
4
OVIE0
0
R/W
3
—
1
—
2
OVF2
0
R/(W)*
1
OVF1
0
R/(W)*
0
OVF0
0
R/(W)*
Reserved bit
Reserved bit
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
Note: * Only 0 can be written, to clear the flag.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 when OVF2 flag is set to 1.
Bit 6
OVIE2 Description
0 OVI2 interrupt requested by OVF2 flag is disabled (Initial value)
1 OVI2 interrupt requested by OVF2 flag is enabled
Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the
OVF1 when OVF1 flag is set to 1.
Bit 5
OVIE1 Description
0 OVI1 interrupt requested by OVF1 flag is disabled (Initial value)
1 OVI1 interrupt requested by OVF1 flag is enabled
190
Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the
OVF0 when OVF0 flag is set to 1.
Bit 4
OVIE0 Description
0 OVI0 interrupt requested by OVF0 flag is disabled (Initial value)
1 OVI0 interrupt requested by OVF0 flag is enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow.
Bit 2
OVF2 Description
0 [Clearing condition] (Initial value)
Read OVF2 flag when OVF2 =1, then write 0 in OVF2 flag
1 [Setting condition]
16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF
Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow
occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR).
Bit 1—Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow.
Bit 1
OVF1 Description
0 [Clearing condition] (Initial value)
Read OVF1 flag when OVF1 =1, then write 0 in OVF1 flag
1 [Setting condition]
16TCNT1 overflowed from H'FFFF to H'0000
Bit 0—Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow.
Bit 0
OVF0 Description
0 [Clearing condition] (Initial value)
Read OVF0 flag when OVF0 =1, then write 0 in OVF0 flag
1 [Setting condition]
16TCNT0 overflowed from H'FFFF to H'0000
191
8.2.7 Timer Counters (16TCNT)
16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel.
Channel Abbreviation Function
0 16TCNT0 Up-counter
1 16TCNT1
2 16TCNT2 Phase counting mode: up/down-counter
Other modes: up-counter
Bit
Initial value
Read/Write
14
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
6
0
R/W
0
0
R/W
4
0
R/W
2
0
R/W
15
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
7
0
R/W
1
0
R/W
5
0
R/W
3
0
R/W
Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source.
The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting
mode and an up-counter in other modes.
16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to
GRA or GRB (counter clearing function).
When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of
the corresponding channel.
When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC
of the corresponding channel.
The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each 16TCNT is initialized to H'0000 by a reset and in standby mode.
192
8.2.8 General Registers (GRA, GRB)
The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each
channel.
Channel Abbreviation Function
0 GRA0, GRB0 Output compare/input capture register
1 GRA1, GRB1
2 GRA2, GRB2
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is
set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR.
When a general register is used as an input capture register, an external input capture signal are
detected and the current 16TCNT value is stored in the general register. The corresponding IMFA
or IMFB flag in TISRA/TISRB is set to 1 at the same time. The edges of the input capture signal
are selected in TIOR.
TIOR settings are ignored in PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are set as output compare registers (with no pin output) and initialized to H'FFFF
by a reset and in standby mode.
193
8.2.9 Timer Control Registers (16TCR)
16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel.
Channel Abbreviation Function
0
1
2
16TCR0
16TCR1
16TCR2
16TCR controls the timer counter. The 16TCRs in all
channels are functionally identical. When phase counting
mode is selected in channel 2, the settings of bits CKEG1
and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
Bit
Initial value
Read/Write
7
—
1
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Timer prescaler 2 to 0
These bits select the timer
counter clock
Reserved bit
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Each 16TCR is an 8-bit readable/writable register that selects the timer counter clock source,
selects the edge or edges of external clock sources, and selects how the counter is cleared.
16TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
194
Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is
cleared.
Bit 6
CCLR1 Bit 5
CCLR0 Description
0 0 16TCNT is not cleared (Initial value)
1 16TCNT is cleared by GRA compare match or input capture*1
1 0 16TCNT is cleared by GRB compare match or input capture*1
1 Synchronous clear: 16TCNT is cleared in synchronization with other
synchronized timers*2
Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock source is used.
Bit 4
CKEG1 Bit 3
CKEG0 Description
0 0 Count rising edges (Initial value)
1 Count falling edges
1—Count both edges
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Function
0 0 0 Internal clock: φ(Initial value)
1 Internal clock: φ/2
1 0 Internal clock: φ/4
1 Internal clock: φ/8
1 0 0 External clock A: TCLKA input
1 External clock B: TCLKB input
1 0 External clock C: TCLKC input
1 External clock D: TCLKD input
195
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts
the edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in 16TCR2 are ignored. Phase counting takes precedence.
8.2.10 Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel.
Channel Abbreviation Function
0 TIOR0 TIOR controls the general registers. Some functions differ in PWM
1 TIOR1 mode.
2 TIOR2
Bit
Initial value
Read/Write
7
—
1
—
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
I/O control B2 to B0
These bits select GRB functions
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIORA and TIORB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
196
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Function
0 0 0 GRB is an output No output at compare match (Initial value)
1compare register 0 output at GRB compare match*1
1 0 1 output at GRB compare match*1
1 Output toggles at GRB compare match
(1 output in channel 2)*1, *2
1 0 0 GRB is an input GRB captures rising edge of input
1compare register GRB captures falling edge of input
1 0 GRB captures both edges of input
1
Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match.
2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1
output is selected automatically.
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Function
0 0 0 GRA is an output No output at compare match (Initial value)
1compare register 0 output at GRA compare match*1
1 0 1 output at GRA compare match*1
1 Output toggles at GRA compare match
(1 output in channel 2)*1, *2
1 0 0 GRA is an input GRA captures rising edge of input
1compare register GRA captures falling edge of input
1 0 GRA captures both edges of input
1
Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match.
2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1
output is selected automatically.
197
8.2.11 Timer Output Level Setting Register C (TOLR)
TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2.
7
—
1
—
Bit
Initial value
Read/Write
6
—
1
—
5
TOB2
0
W
4
TOA2
0
W
3
TOB1
0
W
2
TOA1
0
W
1
TOB0
0
W
0
TOA0
0
W
Reserved bits
Output level setting A2 to A0, B2 to B0
These bits set the levels of the timer outputs
(TIOCA2 to TIOCA0, and TIOCB2 to TIOCB0)
A TOLR setting can only be made when the corresponding bit in TSTR is 0.
TOLR is a write-only register, and cannot be read. If it is read, all bits will return a value of 1.
TOLR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6—Reserved: These bits cannot be modified.
Bit 5—Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB2.
Bit 5
TOB2 Description
0 TIOCB2 is 0 (Initial value)
1 TIOCB2 is 1
Bit 4—Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA2.
Bit 4
TOA2 Description
0 TIOCA2 is 0 (Initial value)
1 TIOCA2 is 1
198
Bit 3—Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB1.
Bit 3
TOB1 Description
0 TIOCB1 is 0 (Initial value)
1 TIOCB1 is 1
Bit 2—Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA1.
Bit 2
TOA1 Description
0 TIOCA1 is 0 (Initial value)
1 TIOCA1 is 1
Bit 1—Output Level Setting B0 (TOB0): Sets the value of timer output TIOCB0.
Bit 0
TOB0 Description
0 TIOCB0 is 0 (Initial value)
1 TIOCB0 is 1
Bit 0—Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA0.
Bit 0
TOA0 Description
0 TIOCA0 is 0 (Initial value)
1 TIOCA0 is 1
199
8.3 CPU Interface
8.3.1 16-Bit Accessible Registers
The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers,
and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a
word at a time, or a byte at a time.
Figures 8.4 and 8.5 show examples of word read/write access to a timer counter (16TCNT).
Figures 8.6 to 8.9 show examples of byte read/write access to 16TCNTH and 16TCNTL.
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCNTH 16TCNTL
Figure 8.4 16TCNT Access Operation [CPU → 16TCNT (Word)]
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCNTH 16TCNTL
Figure 8.5 Access to Timer Counter (CPU Reads 16TCNT, Word)
200
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCNTH 16TCNTL
Figure 8.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte)
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCNTH 16TCNTL
Figure 8.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte)
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCNTH 16TCNTL
Figure 8.8 Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte)
201
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCNTH 16TCNTL
Figure 8.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte)
8.3.2 8-Bit Accessible Registers
The registers other than the timer counters and general registers are 8-bit registers. These registers
are linked to the CPU by an internal 8-bit data bus.
Figures 8.10 and 8.11 show examples of byte read and write access to a 16TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCR
Figure 8.10 16TCR Access (CPU Writes to 16TCR)
On-chip data bus
CPU
H
L Bus interface
H
LModule
data bus
16TCR
Figure 8.11 16TCR Access (CPU Reads 16TCR)
202
8.4 Operation
8.4.1 Overview
A summary of operations in the various modes is given below.
Normal Operation: Each channel has a timer counter and general registers. The timer counter
counts up, and can operate as a free-running counter, periodic counter, or external event counter.
GRA and GRB can be used for input capture or output compare.
Synchronous Operation: The timer counters in designated channels are preset synchronously.
Data written to the timer counter in any one of these channels is simultaneously written to the
timer counters in the other channels as well. The timer counters can also be cleared synchronously
if so designated by the CCLR1 and CCLR0 bits in the TCRs.
PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare
match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending
on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB
automatically become output compare registers.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/down-
counter.
8.4.2 Basic Functions
Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR),
the timer counter (16TCNT) in the corresponding channel starts counting. The counting can be
free-running or periodic.
• Sample setup procedure for counter
Figure 8.12 shows a sample procedure for setting up a counter.
203
Counter setup
Select counter clock
Count operation
Periodic counting
Select counter clear source
Select output compare
register function
Set period
Start counter
Free-running counting
Start counter
Periodic counter Free-running counter
1
Yes
No
2
3
4
55
Figure 8.12 Counter Setup Procedure (Example)
1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock
source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the
external clock signal.
2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA
compare match or GRB compare match.
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
step 2.
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
204
• Free-running and periodic counter operation
A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 8.13 illustrates
free-running counting.
16TCNT value
H'FFFF
H'0000
STR0 to
STR2 bit
OVF
Time
Figure 8.13 Free-Running Counter Operation
When a channel is set to have its counter cleared by compare match, in that channel 16TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count
period in GRA or GRB. After these settings, the counter starts counting up as a periodic
counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or
GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to
H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU
interrupt is requested at this time. After the compare match, 16TCNT continues counting up
from H'0000. Figure 8.14 illustrates periodic counting.
16TCNT value
GR
H'0000
STR bit
IMF
Time
Counter cleared by general
register compare match
Figure 8.14 Periodic Counter Operation
205
• 16TCNT count timing
Internal clock source
Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock
sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Figure 8.15 shows the timing.
φ
Internal
clock
16TCNT input
clock
16TCNT N – 1 N N + 1
Figure 8.15 Count Timing for Internal Clock Sources
External clock source
The external clock pin (TCLKA to TCLKD) can be selected by bits TPSC2 to TPSC0 in
16TCR, and the detected edge by bits CKEG1 and CKEG0. The rising edge, falling edge,
or both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a
single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter
pulses will not be counted correctly.
Figure 8.16 shows the timing when both edges are detected.
φ
External
clock input
16TCNT input
clock
16TCNT N – 1 N N + 1
Figure 8.16 Count Timing for External Clock Sources (when Both Edges are Detected)
206
Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can
cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output
can only go to 0 or go to 1.
• Sample setup procedure for waveform output by compare match
Figure 8.17 shows an example of the setup procedure for waveform output by compare match.
Output setup
Select waveform
output mode
Set output timing
Start counter
Waveform output
Select the compare match output mode (0, 1, or
toggle) in TIOR. When a waveform output mode
is selected, the pin switches from its generic input/
output function to the output compare function
(TIOCA or TIOCB). An output compare pin outputs
the value set in TOLR until the first compare match
occurs.
Set a value in GRA or GRB to designate the
compare match timing.
Set the STR bit to 1 in TSTR to start the timer
counter.
1
2
3
1.
2.
3.
Figure 8.17 Setup Procedure for Waveform Output by Compare Match (Example)
207
• Examples of waveform output
Figure 8.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0
output is selected for compare match A, and 1 output is selected for compare match B. When
the pin is already at the selected output level, the pin level does not change.
Time
H'FFFF
GRB
TIOCB
TIOCA
GRA
No change
No change
No change
No change
1 output
0 output
16TCNT value
H'0000
Figure 8.18 0 and 1 Output (TOA = 1, TOB = 0)
Figure 8.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared
by compare match B. Toggle output is selected for both compare match A and B.
GRB
TIOCB
TIOCA
GRA
16TCNT value
Time
Counter cleared by compare match with GRB
Toggle
output
Toggle
output
H'0000
Figure 8.19 Toggle Output (TOA = 1, TOB = 0)
208
• Output compare output timing
The compare match signal is generated in the last state in which 16TCNT and the general
register match (when 16TCNT changes from the matching value to the next value). When the
compare match signal is generated, the output value selected in TIOR is output at the output
compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare
match signal is not generated until the next counter clock pulse.
Figure 8.20 shows the output compare timing.
N + 1N
N
φ
16TCNT input
clock
16TCNT
GR
Compare
match signal
TIOCA,
TIOCB
Figure 8.20 Output Compare Output Timing
Input Capture Function: The 16TCNT value can be transferred to a general register when an
input edge is detected at an input capture input/output compare pin (TIOCA or TIOCB). Rising-
edge, falling-edge, or both-edge detection can be selected. The input capture function can be used
to measure pulse width or period.
209
• Sample setup procedure for input capture
Figure 8.21 shows a sample procedure for setting up input capture.
Input selection
Select input-capture input
Start counter
Input capture
Set TIOR to select the input capture function of a
general register and the rising edge, falling edge,
or both edges of the input capture signal. Clear the
DDR bit to 0 before making these TIOR settings.
Set the STR bit to 1 in TSTR to start the timer
counter.
1
2
1.
2.
Figure 8.21 Setup Procedure for Input Capture (Example)
• Examples of input capture
Figure 8.22 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA
are selected as capture edges. 16TCNT is cleared by input capture into GRB.
H'0005
H'0180
H'0180
H'0160
H'0005
H'0000
TIOCB
TIOCA
GRA
GRB
16TCNT value
H'0160
Figure 8.22 Input Capture (Example)
210
• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 8.23 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
N
N
φ
Input-capture input
Input capture signal
16TCNT
GRA, GRB
Figure 8.23 Input Capture Signal Timing
8.4.3 Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two
or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 2).
Sample Setup Procedure for Synchronization: Figure 8.24 shows a sample procedure for
setting up synchronization.
211
Setup for synchronization
Synchronous preset
Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
When a value is written in 16TCNT in one of the synchronized channels, the same value is
simultaneously written in 16TCNT in the other channels.
Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture.
Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously.
Set the STR bits in TSTR to 1 to start the synchronized counters.
1.
2.
3.
4.
5.
2
3
1
5
4
5
Select synchronization
Synchronous preset
Write to 16TCNT
Synchronous clear
Clearing
synchronized to this
channel?
Select counter clear source
Start counter
Counter clear Synchronous clear
Start counter
Select counter clear source
Yes
No
Figure 8.24 Setup Procedure for Synchronization (Example)
Example of Synchronization: Figure 8.25 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1,
and TIOCA2. For further information on PWM mode, see section 8.4.4, PWM Mode.
212
TIOCA2
TIOCA1
TIOCA0
GRA2
GRA1
GRB2
GRA0
GRB1
GRB0
Value of 16TCNT0
to 16TCNT2 Cleared by compare match with GRB0
H'0000
Figure 8.25 Synchronization (Example)
8.4.4 PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB compare match is selected as the counter
clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
PWM mode can be selected in all channels (0 to 2).
Table 8.4 summarizes the PWM output pins and corresponding registers. If the same value is set in
GRA and GRB, the output does not change when compare match occurs.
Table 8.4 PWM Output Pins and Registers
Channel Output Pin 1 Output 0 Output
0 TIOCA0GRA0 GRB0
1 TIOCA1GRA1 GRB1
2 TIOCA2GRA2 GRB2
213
Sample Setup Procedure for PWM Mode: Figure 8.26 shows a sample procedure for setting up
PWM mode.
PWM mode 1.
2.
3.
4.
5.
6.
Set bits TPSC2 to TPSC0 in 16TCR to
select the counter clock source. If an
external clock source is selected, set
bits CKEG1 and CKEG0 in 16TCR to
select the desired edge(s) of the
external clock signal.
Set bits CCLR1 and CCLR0 in 16TCR
to select the counter clear source.
Set the time at which the PWM
waveform should go to 1 in GRA.
Set the time at which the PWM
waveform should go to 0 in GRB.
Set the PWM bit in TMDR to select
PWM mode. When PWM mode is
selected, regardless of the TIOR
contents, GRA and GRB become
output compare registers specifying
the times at which the PWM output
goes to 1 and 0. The TIOCA pin
automatically becomes the PWM
output pin. The TIOCB pin conforms
to the settings of bits IOB1 and IOB0
in TIOR. If TIOCB output is not
desired, clear both IOB1 and IOB0 to 0.
Set the STR bit to 1 in TSTR to start
the timer counter.
PWM mode
Select counter clock 1
Select counter clear source 2
Set GRA 3
Set GRB 4
Select PWM mode 5
Start counter 6
Figure 8.26 Setup Procedure for PWM Mode (Example)
214
Examples of PWM Mode: Figure 8.27 shows examples of operation in PWM mode. In PWM
mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0
at compare match with GRB.
In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized
operation and free-running counting are also possible.
16TCNT value Counter cleared by compare match A
Time
GRA
GRB
TIOCA
a. Counter cleared by GRA (TOA = 1)
16TCNT value Counter cleared by compare match B
Time
GRB
GRA
TIOCA
b. Counter cleared by GRB (TOA = 0)
H'0000
H'0000
Figure 8.27 PWM Mode (Example 1)
215
Figure 8.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a
higher value than GRA, the duty cycle is 100%.
16TCNT value Counter cleared by compare match B
Time
GRB
GRA
TIOCA
a. 0% duty cycle (TOA=0)
16TCNT value Counter cleared by compare match A
Time
GRA
GRB
TIOCA
b. 100% duty cycle (TOA=1)
Write to GRA Write to GRA
Write to GRB Write to GRB
H'0000
H'0000
Figure 8.28 PWM Mode (Example 2)
216
8.4.5 Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and
settings in TIOR2, TISRA, TISRB, TISRC, setting of STR2 bit in TSTR, GRA2, and GRB2 are
valid. The input capture and output compare functions can be used, and interrupts can be
generated.
Phase counting is available only in channel 2.
Sample Setup Procedure for Phase Counting Mode: Figure 8.29 shows a sample procedure for
setting up phase counting mode.
Phase counting mode
Select phase counting mode
Select flag setting condition
Start counter
1
2
3
Phase counting mode
1.
2.
3.
Set the MDF bit in TMDR to 1 to select
phase counting mode.
Select the flag setting condition with
the FDIR bit in TMDR.
Set the STR2 bit to 1 in TSTR to start
the timer counter.
Figure 8.29 Setup Procedure for Phase Counting Mode (Example)
217
Example of Phase Counting Mode: Figure 8.30 shows an example of operations in phase
counting mode. Table 8.5 lists the up-counting and down-counting conditions for 16TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The
phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must
also be at least 1.5 states, and the pulse width must be at least 2.5 states.
16TCNT2 value
Counting up Counting down
TCLKB
TCLKA
Figure 8.30 Operation in Phase Counting Mode (Example)
Table 8.5 Up/Down Counting Conditions
Counting
Direction Up-Counting Down-Counting
TCLKB pin ↑High ↓Low HIgh ↓Low ↑
TCLKA pin Low ↑High ↓↓Low ↑HIgh
TCLKA
TCLKB
Phase
difference Phase
difference Pulse width Pulse width
Overlap Overlap
Phase difference and o v erlap:
Pulse width: at least 1.5 states
at least 2.5 states
Figure 8.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
218
8.4.6 16-Bit Timer Output Timing
The initial value of 16-bit timer output when a timer count operation begins can be specified
arbitrarily by making a setting in TOLR.
Figure 8.32 shows the timing for setting the initial value with TOLR.
Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
T1
TOLR address
N
N
T2T3
Address bus
φ
TOLR
16-bit timer output pin
Figure 8.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR
219
8.5 Interrupts
The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when 16TCNT matches a general register (GR). The compare
match signal is generated in the last state in which the values match (when 16TCNT is updated
from the matching count to the next count). Therefore, when 16TCNT matches a general register,
the compare match signal is not generated until the next 16TCNT clock input. Figure 8.33 shows
the timing of the setting of IMFA and IMFB.
φ
16TCNT
GR
IMF
IMI
16TCNT input
clock
Compare
match signal
N N + 1
N
Figure 8.33 Timing of Setting of IMFA and IMFB by Compare Match
220
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an
input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding
general register. Figure 8.34 shows the timing.
Input capture
signal
N
N
φ
IMF
16TCNT
GR
IMI
Figure 8.34 Timing of Setting of IMFA and IMFB by Input Capture
221
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.35 shows the timing.
Overflow
signal
φ
16TCNT
OVF
OVI
Figure 8.35 Timing of Setting of OVF
8.5.2 Timing of Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8.36 shows the timing.
φ
Address
IMF, OVF
TISR write cycle
TISR address
T1T2T3
Figure 8.36 Timing of Clearing of Status Flags
222
8.5.3 Interrupt Sources
Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare
match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources
of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag
are set to 1.
The priority order of the channels can be modified in interrupt priority registers A (IPRA). For
details see section 5, Interrupt Controller.
Table 8.6 lists the interrupt sources.
Table 8.6 16-bit timer Interrupt Sources
Channel Interrupt
Source Description Priority*
0 IMIA0
IMIB0
OVI0
Compare match/input capture A0
Compare match/input capture B0
Overflow 0
High
1 IMIA1
IMIB1
OVI1
Compare match/input capture A1
Compare match/input capture B1
Overflow 1
2 IMIA2
IMIB2
OVI2
Compare match/input capture A2
Compare match/input capture B2
Overflow 2 Low
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed
by settings in IPRA.
223
8.6 Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state of
a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 8.37.
φ
Address bus
Internal write signal
Counter clear signal
16TCNT
16TCNT write cycle
16TCNT address
N H'0000
T1T2T3
Figure 8.37 Contention between 16TCNT Write and Clear
224
Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the
T3 state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented.
Figure 8.38 shows the timing in this case.
φ
Address bus
Internal write signal
16TCNT input clock
16TCNT N
16TCNT address
M
16TCNT write data
16TCNT word write cycle
T1T2T3
Figure 8.38 Contention between 16TCNT Word Write and Increment
225
Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the
T2 or T3 state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not
incremented. The byte data for which a write was not performed is not incremented, and retains its
pre-write value. See figure 8.39, which shows an increment pulse occurring in the T2 state of a
byte write to 16TCNTH.
φ
Address bus
Internal write signal
16TCNT input clock
16TCNTH
16TCNTL
16TCNTH byte write cycle
T1T2T3
N
16TCNTH address
M
16TCNT write data
XXX + 1
Figure 8.39 Contention between 16TCNT Byte Write and Increment
226
Contention between General Register Write and Compare Match: If a compare match occurs
in the T3 state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 8.40.
φ
Address bus
Internal write signal
16TCNT
GR
Compare match signal
General register write cycle
T1T2T3
N
GR address
M
N N + 1
General register write data
Inhibited
Figure 8.40 Contention between General Register Write and Compare Match
227
Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the
T3 state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF
is
set to 1.The same holds for underflow. See figure 8.41.
φ
Address bus
Internal write signal
16TCNT input clock
Overflow signal
16TCNT
OVF
H'FFFF
16TCNT address
M
16TCNT write data
16TCNT write cycle
T1T2T3
Figure 8.41 Contention between 16TCNT Write and Overflow
228
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T3 state of a general register read cycle, the value before input capture is read.
See figure 8.42.
φ
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
GR address
X
General register read cycle
T1T2T3
XM
Figure 8.42 Contention between General Register Read and Input Capture
229
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 8.43.
φ
Input capture signal
Counter clear signal
16TCNT input clock
16TCNT
GR N
N H'0000
Figure 8.43 Contention between Counter Clearing by Input Capture and Counter
Increment
230
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T3 state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 8.44.
φ
Address bus
Internal write signal
Input capture signal
16TCNT
GR M
GR address
General register write cycle
T1T2T3
M
Figure 8.44 Contention between General Register Write and Input Capture
231
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the 16TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
f = φ
(N+1)
(f: counter frequency. φ: system clock frequency. N: value set in general register.)
Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT
value is modified by byte write access, all 16 bits of all synchronized counters assume the same
value as the counter that was addressed.
(Example) When channels 1 and 2 are synchronized
• Byte write to channel 1 or byte write to channel 2
16TCNT1
16TCNT2
W
Y
X
Z
16TCNT1
16TCNT2
A
A
X
X
16TCNT1
16TCNT2
Y
Y
A
A
16TCNT1
16TCNT2
W
Y
X
Z
16TCNT1
16TCNT2
A
A
B
B
• Word write to channel 1 or word write to channel 2
Upper byte Lower byte
Upper byte Lower byte
Upper byte Lower byte
Upper byte Lower byte
Upper byte Lower byte
Write A to upper byte
of channel 1
Write A to lower byte
of channel 2
Write AB word to
channel 1 or 2
232
16-bit timer Operating Modes
Table 8.7 (a) 16-bit timer Operating Modes (Channel 0)
Register Settings
TSNC TMDR TIOR0 16TCR0
Synchro- Clear Clock
Operating Mode nization MDF FDIR PWM IOA IOB Select Select
Synchronous preset SYNC0 = 1 ——
PWM mode ——PWM0 = 1 —*
Output compare A ——PWM0 = 0 IOA2 = 0
Other bits
unrestricted
Output compare B —— IOB2 = 0
Other bits
unrestricted
Input capture A ——PWM0 = 0 IOA2 = 1
Other bits
unrestricted
Input capture B ——PWM0 = 0 IOB2 = 1
Other bits
unrestricted
Counter By compare —— CCLR1 = 0
clearing match/input CCLR0 = 1
capture A
By compare —— CCLR1 = 1
match/input CCLR0 = 0
capture B
Syn- SYNC0 = 1 —— CCLR1 = 1
chronous CCLR0 = 1
clear
Legend: Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
233
Table 8.7 (b) 16-bit timer Operating Modes (Channel 1)
Register Settings
TSNC TMDR TIOR1 16TCR1
Synchro- Clear Clock
Operating Mode nization MDF FDIR PWM IOA IOB Select Select
Synchronous preset SYNC1 = 1 ——
PWM mode ——PWM1 = 1 —
Output compare A ——PWM1 = 0 IOA2 = 0
Other bits
unrestricted
Output compare B —— IOB2 = 0
Other bits
unrestricted
Input capture A ——PWM1 = 0 IOA2 = 1
Other bits
unrestricted
Input capture B ——PWM1 = 0 IOB2 = 1
Other bits
unrestricted
Counter By compare —— CCLR1 = 0
clearing match/input CCLR0 = 1
capture A
By compare —— CCLR1 = 1
match/input CCLR0 = 0
capture B
Syn- SYNC1 = 1 —— CCLR1 = 1
chronous CCLR0 = 1
clear
Legend: Setting available (valid). — Setting does not affect this mode.
Note: The input capture function cannot be used in PWM mode. If compare match A and compare match B
occur simultaneously, the compare match signal is inhibited.
*
*
234
Table 8.7 (c) 16-bit timer Operating Modes (Channel 2)
Register Settings
TSNC TMDR TIOR2 16TCR2
Synchro- Clear Clock
Operating Mode nization MDF FDIR PWM IOA IOB Select Select
Synchronous preset SYNC2 = 1 —
PWM mode —PWM2 = 1 —*
Output compare A —PWM2 = 0 IOA2 = 0
Other bits
unrestricted
Output compare B —IOB2 = 0
Other bits
unrestricted
Input capture A —PWM2 = 0 IOA2 = 1
Other bits
unrestricted
Input capture B —PWM2 = 0 IOB2 = 1
Other bits
unrestricted
Counter By compare —CCLR1 = 0
clearing match/input CCLR0 = 1
capture A
By compare —CCLR1 = 1
match/input CCLR0 = 0
capture B
Syn- SYNC2 = 1 —CCLR1 = 1
chronous CCLR0 = 1
clear
Phase counting MDF = 1 —
mode
Legend: Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
235
Section 9 8-Bit Timers
9.1 Overview
The H8/3008 has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and
TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit
time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT
value to detect compare match events. The timers can be used as multifunctional timers in a
variety of applications, including the generation of a rectangular-wave output with an arbitrary
duty cycle.
9.1.1 Features
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input (enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or input capture B.
• Timer output controlled by two compare match signals
The timer output signal in each channel is controlled by two independent compare match
signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM
output.
• A/D converter can be activated by a compare match
• Two channels can be cascaded
Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
Channel 1 can count channel 0 compare match events (compare match count mode).
Channel 3 can count channel 2 compare match events (compare match count mode).
• Input capture function can be set
8-bit or 16-bit input capture operation is available.
236
• Twelve interrupt sources
There are twelve interrupt sources: four compare match sources, four compare match/input
capture sources, four overflow sources.
Two of the compare match sources and two of the combined compare match/input capture
sources each have an independent interrupt vector. The remaining compare match interrupts,
combined compare match/input capture interrupts, and overflow interrupts have one interrupt
vector for two sources.
237
9.1.2 Block Diagram
The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0
and 1, and group 1 comprising channels 2 and 3. Figure 9.1 shows a block diagram of 8-bit timer
group 0.
φ/8
φ/64
φ/8192
CMIA0
CMIB0
CMIA1/CMIB1
OVI0/OVI1
Interrupt signals
TMO0
TMIO1
TCORA0
TCORB0
8TCSR0
8TCR0
TCORA1
8TCNT1
TCORB1
8TCSR1
8TCR1
TCLKA
TCLKC
8TCNT0
Legend:
TCORA: Time constant register A
TCORB: Time constant register B
8TCNT: Timer counter
8TCSR: Timer control/status register
8TCR: Timer control register
External clock
sources Internal clock
sources
Clock select
Control logic
Clock 1
Clock 0
Compare match A1
Compare match A0
Overflow 1
Overflow 0
Compare match B1
Compare match B0
Input capture B1
Comparator A0 Comparator A1
Comparator B0 Comparator B1
Internal bus
Figure 9.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)
238
9.1.3 Pin Configuration
Table 9.1 summarizes the input/output pins of the 8-bit timer module.
Table 9.1 8-Bit Timer Pins
Group Channel Name Abbreviation I/O Function
0 0 Timer output TMO0Output Compare match output
Timer clock input TCLKC Input Counter external clock input
1 Timer input/output TMIO1I/O Compare match output/input
capture input
Timer clock input TCLKA Input Counter external clock input
1 2 Timer output TMO2Output Compare match output
Timer clock input TCLKD Input Counter external clock input
3 Timer input/output TMIO3I/O Compare match output/input
capture input
Timer clock input TCLKB Input Counter external clock input
239
9.1.4 Register Configuration
Table 9.2 summarizes the registers of the 8-bit timer module.
Table 9.2 8-Bit Timer Registers
Channel Address*1Name Abbreviation R/W Initial value
0 H'FFF80 Timer control register 0 8TCR0 R/W H'00
H'FFF82 Timer control/status register 0 8TCSR0 R/(W)*2H'00
H'FFF84 Time constant register A0 TCORA0 R/W H'FF
H'FFF86 Time constant register B0 TCORB0 R/W H'FF
H'FFF88 Timer counter 0 8TCNT0 R/W H'00
1 H'FFF81 Timer control register 1 8TCR1 R/W H'00
H'FFF83 Timer control/status register 1 8TCSR1 R/(W)*2H'00
H'FFF85 Time constant register A1 TCORA1 R/W H'FF
H'FFF87 Time constant register B1 TCORB1 R/W H'FF
H'FFF89 Timer counter 1 8TCNT1 R/W H'00
2 H'FFF90 Timer control register 2 8TCR2 R/W H'00
H'FFF92 Timer control/status register 2 8TCSR2 R/(W)*2H'10
H'FFF94 Time constant register A2 TCORA2 R/W H'FF
H'FFF96 Time constant register B2 TCORB2 R/W H'FF
H'FFF98 Timer counter 2 8TCNT2 R/W H'00
3 H'FFF91 Timer control register 3 8TCR3 R/W H'00
H'FFF93 Timer control/status register 3 8TCSR3 R/(W)*2H'00
H'FFF95 Time constant register A3 TCORA3 R/W H'FF
H'FFF97 Time constant register B3 TCORB3 R/W H'FF
H'FFF99 Timer counter 3 8TCNT3 R/W H'00
Notes: 1. Indicates the lower 20 bits of the address in advanced mode.
2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0
register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed
together by word access.
Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the
channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be
accessed together by word access.
240
9.2 Register Descriptions
9.2.1 Timer Counters (8TCNT)
15
0
R/W
Bit
Initial value
Read/Write
14
0
R/W
Bit
Initial value
Read/Write
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
8TCNT0 8TCNT1
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
8TCNT2 8TCNT3
The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses
generated from an internal or external clock source. The clock source is selected by clock select
bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or
write to the timer counters.
The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a
16-bit register by word access.
8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1
and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing.
When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status
register (8TCSR) is set to 1.
Each 8TCNT is initialized to H'00 by a reset and in standby mode.
241
9.2.2 Time Constant Registers A (TCORA)
TCORA0 to TCORA3 are 8-bit readable/writable registers.
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TCORA0 TCORA1
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TCORA2 TCORA3
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a
16-bit register by word access.
The TCORA value is constantly compared with the 8TCNT value. When a match is detected, the
corresponding compare match flag A (CMFA) is set to 1 in 8TCSR.
The timer output can be freely controlled by these compare match signals and the settings of
output select bits 1 and 0 (OS1, OS0) in 8TCSR.
Each TCORA register is initialized to H'FF by a reset and in standby mode.
242
9.2.3 Time Constant Registers B (TCORB)
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TCORB0 TCORB1
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TCORB2 TCORB3
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and
the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access.
The TCORB value is constantly compared with the 8TCNT value. When a match is detected, the
corresponding compare match flag B (CMFB) is set to 1 in 8TCSR*.
The timer output can be freely controlled by these compare match signals and the settings of
output/input capture edge select bits 3 and 2 (OIS3, OIS2) in 8TCSR.
When TCORB is used for input capture, it stores the 8TCNT value on detection of an external
input capture signal. At this time, the CMFB flag is set to 1 in the corresponding 8TCSR register.
The detected edge of the input capture signal is set in 8TCSR.
Each TCORB register is initialized to H'FF by a reset and in standby mode.
Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB flag is
not set by a channel 0 or channel 2 compare match B.
243
9.2.4 Timer Control Register (8TCR)
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT
clearing specification, and enables interrupt requests.
8TCR is initialized to H'00 by a reset and in standby mode.
For the timing, see section 9.4, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB Description
0 CMIB interrupt requested by CMFB is disabled (Initial value)
1 CMIB interrupt requested by CMFB is enabled
Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA Description
0 CMIA interrupt requested by CMFA is disabled (Initial value)
1 CMIA interrupt requested by CMFA is enabled
Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt request
when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE Description
0 OVI interrupt requested by OVF is disabled (Initial value)
1 OVI interrupt requested by OVF is enabled
244
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT
clearing source. Compare match A or B, or input capture B, can be selected as the clearing source.
Bit 4
CCLR1 Bit 3
CCLR0 Description
0 0 Clearing is disabled (Initial value)
1 Cleared by compare match A
1 0 Cleared by compare match B/input capture B
1 Cleared by input capture B
Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0
and 8TCNT2 are not cleared by compare match B.
Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to
8TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192.
The rising edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded.
The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and
8TCR3 are set.
245
Bit 2
CSK2 Bit 1
CSK1 Bit 0
CSK0 Description
0 0 0 Clock input disabled (Initial value)
1 Internal clock, counted on falling edge of φ/8
1 0 Internal clock, counted on falling edge of φ/64
1 Internal clock, counted on falling edge of φ/8192
1 0 0 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow
signal*1
Channel 1 (compare match count mode): Count on 8TCNT0
compare match A*1
Channel 2 (16-bit count mode): Count on 8TCNT3 overflow
signal*2
Channel 3 (compare match count mode): Count on 8TCNT2
compare match A*2
1 External clock, counted on rising edge
1 0 External clock, counted on falling edge
1 External clock, counted on both rising and falling edges
Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the
8TCNT2 compare match signal, no incrementing clock is generated. Do not use this
setting.
246
9.2.5 Timer Control/Status Registers (8TCSR)
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
1
—
3
OIS3
0
R/W
0
OS0
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
8TCSR2
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
0
R/W
3
OIS3
0
R/W
0
OS0
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
8TCSR0
ADTE
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ICE
0
R/W
3
OIS3
0
R/W
0
OS0
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
8TCSR1, 8TCSR3
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Bit
Initial value
Read/Write
The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input
capture and overflow statuses, and control compare match output/input capture edge selection.
8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in
standby mode.
247
Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the
occurrence of a TCORB compare match or input capture.
Bit 7
CMFB Description
0 [Clearing condition] (Initial value)
Read CMFB when CMFB = 1, then write 0 in CMFB
1 [Setting conditions]
• 8TCNT = TCORB*
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register
Note: * When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when 8TCNT0 =
TCORB0 or 8TCNT2 = TCORB2.
Bit 6—Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA
compare match.
Bit 6
CMFA Description
0 [Clearing condition] (Initial value)
Read CMFA when CMFA = 1, then write 0 in CMFA
1 [Setting condition]
8TCNT = TCORA
Bit 5—Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed
from H'FF to H'00.
Bit 5
OVF Description
0 [Clearing condition] (Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
8TCNT overflows from H'FF to H'00
248
Bit 4—A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D
control register (ADCR), enables or disables A/D converter start requests by compare match A or
an external trigger.
TRGE* Bit 4
ADTE Description
0 0 A/D converter start requests by compare match A or external trigger pin
(ADTRG) input are disabled (Initial value)
1 A/D converter start requests by compare match A or external trigger pin
(ADTRG) input are disabled
1 0 A/D converter start requests by external trigger pin (ADTRG) input are
enabled, and A/D converter start requests by compare match A are disabled
1 A/D converter start requests by compare match A are enabled, and A/D
converter start requests by external trigger pin (ADTRG) input are disabled
Note: * TRGE is bit 7 of the A/D control register (ADCR).
Bit 4—Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written.
Bit 4—Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of
TCORB1 and TCORB3.
Bit 4
ICE Description
0 TCORB1 and TCORB3 are compare match registers (Initial value)
1 TCORB1 and TCORB3 are input capture registers
When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB
registers in channels 0 to 3 is as shown in the tables below.
249
Table 9.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register
Register Register
Function Status Flag Change Timer Output
Capture Input Interrupt Request
TCORA0 Compare match
operation CMFA changed from 0
to 1 in 8TCSR0 by
compare match
TMO0 output
controllable CMIA0 interrupt request
generated by compare
match
TCORB0 Compare match
operation CMFB not changed
from 0 to 1 in 8TCSR0
by compare match
No output from
TMO0
CMIB0 interrupt request
not generated by compare
match
TCORA1 Compare match
operation CMFA changed from 0
to 1 in 8TCSR1 by
compare match
TMIO1 is dedicated
input capture pin CMIA1 interrupt request
generated by compare
match
TCORB1 Input capture
operation CMFB changed from 0
to 1 in 8TCSR1 by
input capture
TMIO1 is dedicated
input capture pin CMIB1 interrupt request
generated by input
capture
Table 9.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register
Register Register
Function Status Flag Change Timer Output
Capture Input Interrupt Request
TCORA2 Compare match
operation CMFA changed from 0
to 1 in 8TCSR2 by
compare match
TMO2 output
controllable CMIA2 interrupt request
generated by compare
match
TCORB2 Compare match
operation CMFB not changed
from 0 to 1 in 8TCSR2
by compare match
No output from
TMO2
CMIB2 interrupt request
not generated by compare
match
TCORA3 Compare match
operation CMFA changed from 0
to 1 in 8TCSR3 by
compare match
TMIO3 is dedicated
input capture pin CMIA3 interrupt request
generated by compare
match
TCORB3 Input capture
operation CMFB changed from 0
to 1 in 8TCSR3 by
input capture
TMIO3 is dedicated
input capture pin CMIB3 interrupt request
generated by input
capture
250
Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination
with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the
input capture input detected edge.
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
ICE Bit in
8TCSR1
(8TCSR3) Bit 3
OIS3 Bit 2
OIS2 Description
0 0 0 No change when compare match B occurs (Initial value)
1 0 is output when compare match B occurs
1 0 1 is output when compare match B occurs
1 Output is inverted when compare match B occurs (toggle output)
1 0 0 TCORB input capture on rising edge
1 TCORB input capture on falling edge
1 0 TCORB input capture on both rising and falling edges
1
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1 Bit 0
OS0 Description
0 0 No change when compare match A occurs (Initial value)
1 0 is output when compare match A occurs
1 0 1 is output when compare match A occurs
1 Output is inverted when compare match A occurs (toggle output)
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
251
9.3 CPU Interface
9.3.1 8-Bit Registers
8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected
to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at
a time.
Figures 9.2 and 9.3 show the operation in word read and write accesses to 8TCNT.
Figures 9.4 to 9.7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1.
8TCNT0 8TCNT1
H
L
H
L
C
P
U
Internal data bus
Bus
interface Module data bus
Figure 9.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word)
8TCNT0 8TCNT1
H
L
H
L
C
P
U
Internal data bus
Bus
interface Module data bus
Figure 9.3 8TCNT Access Operation (CPU Reads 8TCNT, Word)
8TCNTH0 8TCNTL1
H
L
H
L
C
P
U
Internal data bus
Bus
interface Module data bus
Figure 9.4 8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte)
252
8TCNTH0 8TCNTL1
H
L
H
L
C
P
U
Internal data bus
Bus
interface Module data bus
Figure 9.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)
8TCNT0 8TCNT1
H
L
H
L
C
P
U
Internal data bus
Bus
interface Module data bus
Figure 9.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)
8TCNT0 8TCNT1
H
L
H
L
C
P
U
Internal data bus
Bus
interface Module data bus
Figure 9.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte)
253
9.4 Operation
9.4.1 8TCNT Count Timing
8TCNT is incremented by input clock pulses (either internal or external).
Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the
system clock (φ) can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 9.8 shows the
count timing.
φ
8TCNT N–1 N N+1
Internal clock
8TCNT input clock
Note: Even if the same internal clock is selected for the 16-bit timer and the 8-bit timer, the same operation
will not be performed since the incrementing edge is different in each case.
Figure 9.8 Count Timing for Internal Clock Input
External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in
8TCR: on the rising edge, the falling edge, and both rising and falling edges.
The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge
is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be
counted correctly.
Figure 9.9 shows the timing for incrementation on both edges of the external clock signal.
254
φ
8TCNT N–1 N N+1
External clock input
8TCNT input clock
Figure 9.9 Count Timing for External Clock Input (Both-Edge Detection)
9.4.2 Compare Match Timing
Timer Output Timing: When compare match A or B occurs, the timer output is as specified by
the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Figure 9.10 shows the timing when the output is set to toggle on compare match A.
φ
Compare match A
signal
Timer output
Figure 9.10 Timing of Timer Output
255
Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when compare match A or B occurs, Figure 9.11 shows the timing of this
operation.
φ
N H'008TCNT
Compare match signal
Figure 9.11 Timing of Clear by Compare Match
Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when input capture B occurs. Figure 9.12 shows the timing of this
operation.
φ
Input capture signal
Input capture input
8TCNT NH
'00
Figure 9.12 Timing of Clear by Input Capture
9.4.3 Input Capture Signal Timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR.
Figure 9.13 shows the timing when the rising edge is selected.
The pulse width of the input capture input signal must be at least 1.5 system clocks when a single
edge is selected, and at least 2.5 system clocks when both edges are selected.
256
φ
Input capture signal
Input capture input
8TCNT N
TCORB N
Figure 9.13 Timing of Input Capture Input Signal
9.4.4 Timing of Status Flag Setting
Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB
flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and
8TCNT values match. The compare match signal is generated in the last state of the match (when
the matched 8TCNT count value is updated). Therefore, after the 8TCNT and TCORA or
TCORB values match, the compare match signal is not generated until an incrementing clock
pulse signal is generated. Figure 9.14 shows the timing in this case.
φ
CMF
Compare match signal
8TCNT N N+1
N
TCOR
Figure 9.14 CMF Flag Setting Timing when Compare Match Occurs
Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.
Figure 9.15 shows the timing in this case.
257
φ
CMFB
Input capture signal
8TCNT
N
N
TCORB
Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs
Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow
signal generated when 8TCNT overflows (from H'FF to H'00). Figure 9.16 shows the timing in
this case.
φ
OVF
Overflow signal
8TCNT H'FF H'00
Figure 9.16 Timing of OVF Setting
9.4.5 Operation with Cascaded Connection
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0
and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer
(16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1
(compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 or
8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two timers
can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare matches
can be counted in channel 3 (compare match count mode). In this case, the timer operates as
below.
258
16-Bit Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
Setting when Compare Match Occurs
• The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match
occurs.
• TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
accordance with the 16-bit compare match conditions.
• TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
accordance with the lower 8-bit compare match conditions.
Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1
and input capture occurs.
• TMIO1 pin input capture input signal edge detection is selected by bits OIS3 and OIS2
in 8TCSR0.
Counter Clear Specification
• If counter clear on compare match or input capture has been selected by the CCLR1 and
CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits
cannot be cleared independently.
OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from
H'FF to H'00).
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit
timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits.
Setting when Compare Match Occurs
• The CMFA or CMFB flag is set to 1 in 8TCSR2 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR3 when a lower 8-bit compare match
occurs.
• TMO2 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in
accordance with the 16-bit compare match conditions.
• TMIO3 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in
accordance with the lower 8-bit compare match conditions.
259
Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3
and input capture occurs.
• TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2
in 8TCSR2.
Counter Clear Specification
• If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in
8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits
cannot be cleared independently.
OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
H'FF to H'00).
Compare Match Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in
channel 0 cannot be used.
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR3, the compare match register function of TCORB2 in
channel 2 cannot be used.
Caution
Do not set 16-bit counter mode and compare match count mode simultaneously within the same
group, as the 8TCNT input clock will not be generated and the counters will not operate.
260
9.4.6 Input Capture Setting
The 8TCNT value can be transferred to TCORB on detection of an input edge on the input
capture/output compare pin (TMIO1 or TMIO3). Rising edge, falling edge, or both edge detection
can be selected. In 16-bit count mode, 16-bit input capture can be used.
Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation)
• Channel 1:
Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1.
Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR1.
Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
• Channel 3:
Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3.
Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR3.
Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.
Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be
used as a compare match register.
Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2
cannot be used as a compare match register.
Setting Input Capture Operation in 16-Bit Count Mode
• Channels 0 and 1:
In 16-bit count mode, TCORB0 and TCORB1 function as a 16-bit input capture register
when the ICE bit is set to 1 in 8TCSR1.
Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR0. (In 16-bit count mode, the settings of
bits OIS3 and OIS2 in 8TCSR1 are ignored.)
Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
• Channels 2 and 3:
In 16-bit count mode, TCORB2 and TCORB3 function as a 16-bit input capture register
when the ICE bit is set to 1 in 8TCSR3.
Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings of
bits OIS3 and OIS2 in 8TCSR3 are ignored.)
Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.
261
9.5 Interrupt
9.5.1 Interrupt Sources
The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and
CMIB) and overflow (TOVI). Table 9.5 shows the interrupt sources and their priority order. Each
interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A
separate interrupt request signal is sent to the interrupt controller by each interrupt source.
Table 9.5 Types of 8-Bit Timer Interrupt Sources and Priority Order
PriorityInterrupt Source Description
HighCMIA Interrupt by CMFA
CMIB Interrupt by CMFB
TOVI Interrupt by OVF Low
For compare match interrupts CMIA1/CMIB1 and CMIA3/CMIB3 and the overflow interrupts
(TOVI0/TOVI1 and TOVI2/TOVI3),
one vector is shared by two interrupts.
Table 9.6 lists the interrupt sources.
Table 9.6 8-Bit Timer Interrupt Sources
Channel Interrupt Source Description
0 CMIA0 TCORA0 compare match
CMIB0 TCORB0 compare match/input capture
1 CMIA1/CMIB1 TCORA1 compare match, or TCORB1 compare match/input
capture
0, 1 TOVI0/TOVI1 Counter 0 or counter 1 overflow
2 CMIA2 TCORA2 compare match
CMIB2 TCORB2 compare match/input capture
3 CMIA3/CMIB3 TCORA3 compare match, or TCORB3 compare match/input
capture
2, 3 TOVI2/TOVI3 Counter 2 or counter 3 overflow
262
9.5.2 A/D Converter Activation
The A/D converter can only be activated by channel 0 compare match A.
If the ADTE bit setting is 1 when the CMFA flag in 8TCSR0 is set to 1 by generation of channel 0
compare match A, an A/D conversion start request will be issued to the A/D converter. If the
TRGE bit in ADCR is 1 at this time, the A/D converter will be started. If the ADTE bit in
8TCSR0 is 1, A/D converter external trigger pin (ADTRG) input is disabled.
9.6 8-Bit Timer Application Example
Figure 9.17 shows how the 8-bit timer module can be used to output pulses with any desired duty
cycle. The settings for this example are as follows:
• Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a
TCORA compare match.
• Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA
compare match and 0 is output on a TCORB compare match.
The above settings enable a waveform with the cycle determined by TCORA and the pulse width
detected by TCORB to be output without software intervention.
8TCNT
H'FF Counter clear
TCORA
TCORB
H'00
TMO
Figure 9.17 Example of Pulse Output
263
9.7 Usage Notes
Note that the following kinds of contention can occur in 8-bit timer operation.
9.7.1 Contention between 8TCNT Write and Clear
If a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle, clearing of the
counter takes priority and the write is not performed. Figure 9.18 shows the timing in this case.
φ
Address bus 8TCNT address
Internal write signal
Counter clear signal
8TCNT N H'00
T1T3T2
8TCNT write cycle
Figure 9.18 Contention between 8TCNT Write and Clear
264
9.7.2 Contention between 8TCNT Write and Increment
If an increment pulse occurs in the T3 state of a 8TCNT write cycle, writing takes priority and
8TCNT is not incremented. Figure 9.19 shows the timing in this case.
φ
Address bus 8 TCNT address
Internal write signal
8TCNT input clock
8TCNT NM
T1T3T2
8TCNT write cycle
8TCNT write data
Figure 9.19 Contention between 8TCNT Write and Increment
265
9.7.3 Contention between TCOR Write and Compare Match
If a compare match occurs in the T3 state of a TCOR write cycle, writing takes priority and the
compare match signal is inhibited. Figure 9.20 shows the timing in this case.
φ
Address bus TCOR address
Internal write signal
8TCNT
TCOR NM
T1T3T2
TCOR write cycle
TCOR write data
N N+1
Compare match signal Inhibited
Figure 9.20 Contention between TCOR Write and Compare Match
266
9.7.4 Contention between TCOR Read and Input Capture
If an input capture signal occurs in the T3 state of a TCOR read cycle, the value before input
capture is read. Figure 9.21 shows the timing in this case.
φ
Address bus TCORB address
Internal read signal
Input capture signal
TCORB NM
T1T3T2
TCORB read cycle
Internal data bus N
Figure 9.21 Contention between TCOR Read and Input Capture
267
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, counter clearing by
the input capture signal takes priority and the counter is not incremented. The value before the
counter is cleared is transferred to TCORB. Figure 9.22 shows the timing in this case.
φ
Counter clear signal
8TCNT internal clock
8TCNT N
X
H'00
T1T3T2
Input capture signal
TCORB N
Figure 9.22 Contention between Counter Clearing by Input Capture and Counter
Increment
268
9.7.6 Contention between TCOR Write and Input Capture
If an input capture signal occurs in the T3 state of a TCOR write cycle, input capture takes priority
and the write to TCOR is not performed. Figure 9.23 shows the timing in this case.
φ
Address bus TCOR address
Internal write signal
Input capture signal
8TCNT M
T1T3T2
TCOR write cycle
TCOR MX
Figure 9.23 Contention between TCOR Write and Input Capture
269
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)
If an increment pulse occurs in the T3 state of an 8TCNT byte write cycle in 16-bit count mode,
the counter write takes priority and the byte data for which the write was performed is not
incremented. The byte data for which a write was not performed is incremented. Figure 9.24
shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNT (upper
byte). If an increment pulse occurs in the T2 state, on the other hand, the increment takes priority.
φ
Address bus 8TCNTH address
Internal write signal
8TCNT input clock
8TCNT (upper byte) N N+1 8TCNT write data
T1T3T2
8TCNT (upper byte) byte write cycle
8TCNT (lower byte) X+1X
Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
270
9.7.8 Contention between Compare Matches A and B
If compare matches A and B occur at the same time, the 8-bit timer operates according to the
relative priority of the output states set for compare match A and compare match B, as shown in
Table 9.7.
Table 9.7 Timer Output Priority Order
PriorityOutput Setting
HighToggle output
1 output
0 output
No change Low
9.7.9 8TCNT Operation and Internal Clock Source Switchover
Switching internal clock sources may cause 8TCNT to increment, depending on the switchover
timing. Table 9.8 shows the relation between the time of the switchover (by writing to bits CKS1
and CKS0) and the operation of 8TCNT.
The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of
the internal clock. If a switchover is made from a low clock source to a high clock source, as in
case No. 3 in Table 9.8, the switchover will be regarded as a falling edge, a 8TCNT clock pulse
will be generated, and 8TCNT will be incremented.
8TCNT may also be incremented when switching between internal and external clocks.
271
Table 9.8 Internal Clock Switchover and 8TCNT Operation
No. CKS1 and CKS0 Write
Timing 8TCNT Operation
1 High → high switchover*1Old clock
source
New clock
source
8TCNT clock
8TCNT
CKS bits rewritten
N N+1
2 High → low switchover*2Old clock
source
New clock
source
8TCNT clock
8TCNT
CKS bits rewritten
N N+1 N+2
3 Low → high switchover*3Old clock
source
New clock
source
8TCNT clock
8TCNT
CKS bits rewritten
N N+1 N+2
*4
272
No. CKS1 and CKS0 Write
Timing 8TCNT Operation
4 Low → low switchover*4Old clock
source
New clock
source
8TCNT clock
8TCNT
CKS bits rewritten
N N+1 N+2
Notes: 1. Including switchovers from the high level to the halted state, and from the halted state
to the high level.
2. Including switchover from the halted state to the low level.
3. Including switchover from the low level to the halted state.
4. The switchover is regarded as a rising edge, causing 8TCNT to increment.
273
Section 10 Programmable Timing Pattern Controller (TPC)
10.1 Overview
The H8/3008 has a built-in programmable timing pattern controller (TPC) that provides pulse
outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit
groups (group 3 to group 0) that can operate simultaneously and independently.
10.1.1 Features
TPC features are listed below.
• 16-bit output data
Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis.
• Four output groups
Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
outputs.
• Selectable output trigger signals
• Output trigger signals can be selected for each group from the compare match signals of three
16-bit timer channels.
• Non-overlap mode
A non-overlap margin can be provided between pulse outputs.
274
10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the TPC.
PADDR
NDERA
TPMR
PBDDR
NDERB
TPCR
Internal
data bus
TP
TP
TP
TP
TP
TP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Control logic
16-bit timer compare match signals
Pulse output
pins, group 3
PBDR
PADR
Legend:
TPMR:
TPCR:
NDERB:
NDERA:
PBDDR:
PADDR:
NDRB:
NDRA:
PBDR:
PADR:
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Port B data direction register
Port A data direction register
Next data register B
Next data register A
Port B data register
Port A data register
NDRB
NDRA
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
Figure 10.1 TPC Block Diagram
275
10.1.3 Pin Configuration
Table 10.1 summarizes the TPC output pins.
Table 10.1 TPC Pins
Name Symbol I/O Function
TPC output 0 TP0Output Group 0 pulse output
TPC output 1 TP1Output
TPC output 2 TP2Output
TPC output 3 TP3Output
TPC output 4 TP4Output Group 1 pulse output
TPC output 5 TP5Output
TPC output 6 TP6Output
TPC output 7 TP7Output
TPC output 8 TP8Output Group 2 pulse output
TPC output 9 TP9Output
TPC output 10 TP10 Output
TPC output 11 TP11 Output
TPC output 12 TP12 Output Group 3 pulse output
TPC output 13 TP13 Output
TPC output 14 TP14 Output
TPC output 15 TP15 Output
276
10.1.4 Register Configuration
Table 10.2 summarizes the TPC registers.
Table 10.2 TPC Registers
Address*1Name Abbreviation R/W Initial Value
H'EE009 Port A data direction register PADDR W H'00
H'FFFD9 Port A data register PADR R/(W)*2H'00
H'EE00A Port B data direction register PBDDR W H'00
H'FFFDA Port B data register PBDR R/(W)*2H'00
H'FFFA0 TPC output mode register TPMR R/W H'F0
H'FFFA1 TPC output control register TPCR R/W H'FF
H'FFFA2 Next data enable register B NDERB R/W H'00
H'FFFA3 Next data enable register A NDERA R/W H'00
H'FFFA5/
H'FFFA7*3Next data register A NDRA R/W H'00
H'FFFA4/
H'FFFA6*3Next data register B NDRB R/W H'00
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC
output groups 0 and 1 by settings in TPCR. When the output triggers are different, the
NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address
of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2
and 3 by settings in TPCR. When the output triggers are different, the NDRB address is
H'FFFA6 for group 2 and H'FFFA4 for group 3.
277
10.2 Register Descriptions
10.2.1 Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
Initial value
Read/Write
7
PA DDR
0
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
7
6
PA DDR
0
W
6
5
PA DDR
0
W
5
4
PA DDR
0
W
4
3
PA DDR
0
W
3
2
PA DDR
0
W
2
1
PA DDR
0
W
1
0
PA DDR
0
W
0
Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PADDR, see section 7.11, Port A.
10.2.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
Initial value
Read/Write
0
PA
0
R/(W)
0
1
PA
0
R/(W)
1
2
PA
0
R/(W)
2
3
PA
0
R/(W)
3
4
PA
0
R/(W)
4
5
PA
0
R/(W)
5
6
PA
0
R/(W)
6
7
PA
0
R/(W)
7
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
********
Note: Bits selected for TPC output by NDERA settings become read-only bits.*
For further information about PADR, see section 7.11, Port A.
278
10.2.3 Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
Initial value
Read/Write
7
PB DDR
0
W
Port B data direction 7 to 0
These bits select input or
output for port B pins
7
6
PB DDR
0
W
6
5
PB DDR
0
W
5
4
PB DDR
0
W
4
3
PB DDR
0
W
3
2
PB DDR
0
W
2
1
PB DDR
0
W
1
0
PB DDR
0
W
0
Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PBDDR, see section 7.12, Port B.
10.2.4 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
Initial value
Read/Write
0
PB
0
R/(W)
0
1
PB
0
R/(W)
1
2
PB
0
R/(W)
2
3
PB
0
R/(W)
3
4
PB
0
R/(W)
4
5
PB
0
R/(W)
5
6
PB
0
R/(W)
6
7
PB
0
R/(W)
7
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
********
Note: Bits selected for TPC output by NDERB settings become read-only bits.*
For further information about PBDR, see section 7.12, Port B.
279
10.2.5 Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event
specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The
address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output
trigger or different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group
1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA5
Bit
Initial value
Read/Write
0
NDR0
0
R/W
1
NDR1
0
R/W
2
NDR2
0
R/W
3
NDR3
0
R/W
4
NDR4
0
R/W
5
NDR5
0
R/W
6
NDR6
0
R/W
7
NDR7
0
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Address H'FFFA7
Bit
Initial value
Read/Write
0
—
1
—
1
—
1
—
2
—
1
—
3
—
1
—
4
—
1
—
5
—
1
—
6
—
1
—
7
—
1
—
Reserved bits
280
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Bit
Initial value
Read/Write
0
—
1
—
1
—
1
—
2
—
1
—
3
—
1
—
4
NDR4
0
R/W
5
NDR5
0
R/W
6
NDR6
0
R/W
7
NDR7
0
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Reserved bits
Address H'FFFA7
Bit
Initial value
Read/Write
0
NDR0
0
R/W
1
NDR1
0
R/W
2
NDR2
0
R/W
3
NDR3
0
R/W
4
—
1
—
5
—
1
—
6
—
1
—
7
—
1
—
Reserved bits Next data 3 to 0
These bits store the next output
data for TPC output group 0
281
10.2.6 Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP15 to TP8). During TPC output, when an 16-bit timer compare match event
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group
3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA4
Bit
Initial value
Read/Write
0
NDR8
0
R/W
1
NDR9
0
R/W
2
NDR10
0
R/W
3
NDR11
0
R/W
4
NDR12
0
R/W
5
NDR13
0
R/W
6
NDR14
0
R/W
7
NDR15
0
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Address H'FFFA6
Bit
Initial value
Read/Write
0
—
1
—
1
—
1
—
2
—
1
—
3
—
1
—
4
—
1
—
5
—
1
—
6
—
1
—
7
—
1
—
Reserved bits
282
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4
and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits
7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFFA4
Bit
Initial value
Read/Write
0
—
1
—
1
—
1
—
2
—
1
—
3
—
1
—
4
NDR12
0
R/W
5
NDR13
0
R/W
6
NDR14
0
R/W
7
NDR15
0
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Reserved bits
Address H'FFFA6
Bit
Initial value
Read/Write
0
NDR8
0
R/W
1
NDR9
0
R/W
2
NDR10
0
R/W
3
NDR11
0
R/W
4
—
1
—
5
—
1
—
6
—
1
—
7
—
1
—
Reserved bits Next data 11 to 8
These bits store the next output
data for TPC output group 2
283
10.2.7 Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP7 to TP0) on a bit-by-bit basis.
Bit
Initial value
Read/Write
0
NDER0
0
R/W
1
NDER1
0
R/W
2
NDER2
0
R/W
3
NDER3
0
R/W
4
NDER4
0
R/W
5
NDER5
0
R/W
6
NDER6
0
R/W
7
NDER7
0
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically
transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0 Description
0 TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0)(Initial value)
1 TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
284
10.2.8 Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP15 to TP8) on a bit-by-bit basis.
Bit
Initial value
Read/Write
0
NDER8
0
R/W
1
NDER9
0
R/W
2
NDER10
0
R/W
3
NDER11
0
R/W
4
NDER12
0
R/W
5
NDER13
0
R/W
6
NDER14
0
R/W
7
NDER15
0
R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically
transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8 Description
0 TPC outputs TP15 to TP8 are disabled
(NDR15 to NDR8 are not transferred to PB7 to PB0)(Initial value)
1 TPC outputs TP15 to TP8 are enabled
(NDR15 to NDR8 are transferred to PB7 to PB0)
285
10.2.9 TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
Initial value
Read/Write
0
G0CMS0
1
R/W
1
G0CMS1
1
R/W
2
G1CMS0
1
R/W
3
G1CMS1
1
R/W
4
G2CMS0
1
R/W
5
G2CMS1
1
R/W
6
G3CMS0
1
R/W
7
G3CMS1
1
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP15 to TP12)
Group 2 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 2
(TP11 to TP8)
Group 1 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 1
(TP7 to TP4)
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP3 to TP0)
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP15 to TP12).
Bit 7
G3CMS1 Bit 6
G3CMS0 Description
0 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 0
1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 1
1 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 2
1 TPC output group 3 (TP15 to TP12) is triggered by
compare match in 16-bit timer channel 2 (Initial value)
286
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP11 to TP8).
Bit 5
G2CMS1 Bit 4
G2CMS0 Description
0 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 0
1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 1
1 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 2
1 TPC output group 2 (TP11 to TP8) is triggered by
compare match in 16-bit timer channel 2 (Initial value)
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP7 to TP4).
Bit 3
G1CMS1 Bit 2
G1CMS0 Description
0 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 0
1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 1
1 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 2
1 TPC output group 1 (TP7 to TP4) is triggered by
compare match in 16-bit timer channel 2 (Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP3 to TP0).
Bit 1
G0CMS1 Bit 0
G0CMS0 Description
0 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 0
1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 1
1 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 2
1 TPC output group 0 (TP3 to TP0) is triggered by
compare match in 16-bit timer channel 2 (Initial value)
287
10.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
G3NOV
0
R/W
0
G0NOV
0
R/W
2
G2NOV
0
R/W
1
G1NOV
0
R/W
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP to TP )
Reserved bits
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP to TP )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP to TP )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP to TP )
15 12
11 8
74
30
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in
general register A (GRA). The output values change at compare match A and B.
For details see section 10.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
288
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for
group 3 (TP15 to TP12).
Bit 3
G3NOV Description
0 Normal TPC output in group 3 (output values change at
compare match A in the selected 16-bit timer channel) (Initial value)
1 Non-overlapping TPC output in group 3 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP11 to TP8).
Bit 2
G2NOV Description
0 Normal TPC output in group 2 (output values change at
compare match A in the selected 16-bit timer channel) (Initial value)
1 Non-overlapping TPC output in group 2 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP7 to TP4).
Bit 1
G1NOV Description
0 Normal TPC output in group 1 (output values change at
compare match A in the selected 16-bit timer channel) (Initial value)
1 Non-overlapping TPC output in group 1 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP3 to TP0).
Bit 0
G0NOV Description
0 Normal TPC output in group 0 (output values change at
compare match A in the selected 16-bit timer channel) (Initial value)
1 Non-overlapping TPC output in group 0 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
289
10.3 Operation
10.3.1 Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 10.2 illustrates the TPC output operation. Table 10.3 summarizes the TPC operating
conditions.
DDR NDER
QQ
TPC output pin
DR NDR
C
QD QDInternal
data bus
Output trigger signal
Figure 10.2 TPC Output Operation
Table 10.3 TPC Operating Conditions
NDER DDR Pin Function
0 0 Generic input port
1 Generic output port
1 0 Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
1 TPC pulse output
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 10.3.4, Non-Overlapping TPC Output.
290
10.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 10.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
T
CNT
G
RA
C
ompare
m
atch A signal
N
DRB
P
BDR
T
P to TP
815
N
N
n
m
m
N + 1
n
n
Figure 10.3 Timing of Transfer of Next Data Register Contents and Output (Example)
291
10.3.3 Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 10.4 shows a sample procedure for
setting up normal TPC output.
Normal TPC output
Set next TPC output data
Compare match? No
Yes
Set next TPC output data
16-bit timer
setup
16-bit timer
setup
Port and
TPC setup
10
11
9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Set TIOR to make GRA an output compare
register (with output inhibited).
Set the TPC output trigger period.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the
counter clear source with bits CCLR1 and
CCLR0.
Enable the IMFA interrupt in TISRA.
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
Set the NDER bits of the pins to be used
for TPC output to 1.
Select the 16-bit timer compare match
event to be used as the TPC output trigger
in TPCR.
Set the next TPC output values in the NDR
bits.
Set the STR bit to 1 in TSTR to start the
timer counter.
At each IMFA interrupt, set the next output
values in the NDR bits.
1
2
3
4
5
6
7
8
Select GR functions
Set GRA value
Select counting operation
Select interrupt request
Start counter
Set initial output data
Select port output
Enable TPC output
Select TPC output trigger
Figure 10.4 Setup Procedure for Normal TPC Output (Example)
292
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 10.5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
GRA
H'0000
NDRB
PBDR
TP15
TP14
TP13
TP12
TP11
1.
2.
3.
4.
Time
80
TCNT
TCNT value
C0 40 60 20 30 10 18 08 88 80 C0
Compare match
The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output
compare register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TISRA to enable the compare match A interrupt.
H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB
contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt
service routine writes the next output data (H'C0) in NDRB.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts.
00
80 C0 40 60 20 30 10 18 08 88 80 C0 40
Figure 10.5 Normal TPC Output Example (Five-Phase Pulse Output)
293
10.3.4 Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 10.6 shows a sample
procedure for setting up non-overlapping TPC output.
Non-overlapping
TPC output
Set next TPC output data
Compare match A? No
Yes
Set next TPC output data
Start counter
16-bit timer
setup
16-bit timer
setup
Port and
TPC setup
Set initial output data
Set up TPC output
Enable TPC transfer
Select TPC transfer trigger
Select non-overlapping groups
1
2
3
4
12
10
11
5
6
7
8
9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
Enable the IMFA interrupt in TISRA.
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
Set the NDER bits of the pins to be used for
TPC output to 1.
In TPCR, select the 16-bit timer compare
match event to be used as the TPC output
trigger.
In TPMR, select the groups that will operate
in non-overlap mode.
Set the next TPC output values in the NDR
bits.
Set the STR bit to 1 in TSTR to start the timer
counter.
At each IMFA interrupt, write the next output
value in the NDR bits.
Select GR functions
Set GR values
Select counting operation
Select interrupt requests
Figure 10.6 Setup Procedure for Non-Overlapping TPC Output (Example)
294
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-
Overlapping Output): Figure 10.7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
GRB
H'0000
NDRB
PBDR
TP
15
TP
14
TP
13
TP
12
TP
11
TP
10
TP
9
TP
8
Time
95
00
65
95
59 56 95 65
05 65 41 59 50 56 14 95 05 65
TCNT
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable
IMFA interrupts.
H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits
G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in
NDRB.
TCNT value
Non-overlap margin
The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are
output compare registers and the counter will be cleared by compare match B. The TPC output trigger
1.
2.
3.
4.
The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change
from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts.
GRA
Figure 10.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)
295
10.3.5 TPC Output Triggering by Input Capture
TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA
functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output
will be triggered by the input capture signal. Figure 10.8 shows the timing.
φ
TIOC pin
Input capture
signal
NDR
DR N
N
M
Figure 10.8 TPC Output Triggering by Input Capture (Example)
296
10.4 Usage Notes
10.4.1 Operation of TPC Output Pins
TP0 to TP15 are multiplexed with 16-bit timer, address bus, and other pin functions. When 16-bit
timer, or address bus output is enabled, the corresponding pins cannot be used for TPC output. The
data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
10.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 10.9 illustrates the non-overlapping TPC output operation.
DDR NDER
QQ
TPC output pin
DR NDR
C
QD QD
Compare match A
Compare match B
Figure 10.9 Non-Overlapping TPC Output
297
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR. The next data must be written before the next compare match B occurs.
Figure 10.10 shows the timing relationships.
Compare
match A
Compare
match B
NDR write
NDR
NDR write
DR
0/1 output 0/1 output0 output 0 output
Do not write
to NDR in this
interval
Do not write
to NDR in this
interval
Write to NDR
in this interval
Write to NDR
in this interval
Figure 10.10 Non-Overlapping Operation and NDR Write Timing
298
299
Section 11 Watchdog Timer
11.1 Overview
The H8/3008 has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it
can operate as a watchdog timer to supervise system operation, or it can operate as an interval
timer. As a watchdog timer, it generates a reset signal for the H8/3008 chip if a system crash
allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation,
an interval timer interrupt is requested at each TCNT overflow.
11.1.1 Features
WDT features are listed below.
• Selection of eight counter clock sources
φ/2, φ /32, φ /64, φ /128, φ /256, φ /512, φ /2048, or φ /4096
• Interval timer option
• Timer counter overflow generates a reset signal or interrupt.
The reset signal is generated in watchdog timer operation. An interval timer interrupt is
generated in interval timer operation.
• Watchdog timer reset signal resets the entire H8/3008 internally, and can also be output
externally.
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire H8/3008 internally. An external reset signal can be output from the RESO pin to
reset other system devices simultaneously.
300
11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the WDT.
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
TCNT
TCSR
RSTCSR
Reset control
Interrupt signal
Reset
(internal, external)
(interval timer) Interrupt
control
Overflow
Clock Clock
selector
Read/
write
control
Internal
data bus
Internal clock sources
Legend:
TCNT:
TCSR:
RSTCSR:
Timer counter
Timer control/status register
Reset control/status register
Figure 11.1 WDT Block Diagram
11.1.3 Pin Configuration
Table 11.1 describes the WDT output pin.
Table 11.1 WDT Pin
Name Abbreviation I/O Function
Reset output RESO Output* External output of the watchdog timer reset signal
Note: * Open-drain output.
301
11.1.4 Register Configuration
Table 11.2 summarizes the WDT registers.
Table 11.2 WDT Registers
Address*1
Write*2Read Name Abbreviation R/W Initial Value
H'FFF8C H'FFF8C Timer control/status register TCSR R/(W)*3H'18
H'FFF8D Timer counter TCNT R/W H'00
H'FFF8E H'FFF8F Reset control/status register RSTCSR R/(W)*3H'3F
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable and writable up-counter.
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Note: The method for writing to TCNT is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
302
11.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and
clock source.
Bit
Initial value
Read/Write
7
OVF
0
R/(W)
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Overflow flag
Status flag indicating overflow
Clock select
These bits select the
TCNT clock source
Timer mode select
Selects the mode
Timer enable
Selects whether TCNT runs or halts
Reserved bits
*
Notes: The method for writing to TCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
* Only 0 can be written, to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7
OVF Description
0 [Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value)
1 [Setting condition]
Set when TCNT changes from H'FF to H'00
303
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6
WT/IT Description
0 Interval timer: requests interval timer interrupts (Initial value)
1 Watchdog timer: generates a reset signal
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/IT = 1, clear
the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1,
TME should be cleared to 0.
Bit 5
TME Description
0 TCNT is initialized to H'00 and halted (Initial value)
1 TCNT is counting
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0 Description
000φ/2 (Initial value)
1φ /32
10φ /64
1φ /128
100φ /256
1φ /512
10φ /2048
1φ /4096
304
11.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
Initial value
Read/Write
7
WRST
0
R/(W)
6
RSTOE
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
*
Watchdog timer reset
Indicates that a reset signal has been generated
Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Notes: The method for writing to RSTCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
* Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3008 chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices. Note that there is no RESO pin in the versions with on-chip
flash memory.
Bit 7
WRST Description
0 [Clearing conditions]
• Reset signal at RES pin.
• Read WRST when WRST =1, then write 0 in WRST. (Initial value)
1 [Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
305
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is
no RESO pin in the versions with on-chip flash memory.
Bit 6
RSTOE Description
0 Reset signal is not output externally (Initial value)
1 Reset signal is output externally
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
11.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 11.2 shows the format of data written to TCNT
and TCSR. TCNT and TCSR both have the same write address. The write data must be contained
in the lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or
H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR.
15 8 7 0
H'5A Write dataAddress H'FFF8C*
15 8 7 0
H'A5 Write dataAddress H'FFF8C*
TCNT write
TCSR write
Note: Lower 20 bits of the address in advanced mode.*
Figure 11.2 Format of Data Written to TCNT and TCSR
306
Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be
written by byte transfer instructions. Figure 11.3 shows the format of data written to RSTCSR. To
write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower
byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. To
write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the
write data. Writing this word transfers a write data value into the RSTOE bit.
15 8 7 0
H'A5 H'00Address H'FFF8E*
15 8 7 0
H'5A Write dataAddress H'FFF8E*
Writing 0 in WRST bit
Writing to RSTOE bit
Note: Lower 20 bits of the address in advanced mode.*
Figure 11.3 Format of Data Written to RSTCSR
Reading TCNT, TCSR, and RSTCSR: For reads of TCNT, TCSR, and RSTCSR, address
H'FFF8C is assigned to TCSR, address H'FFF8D to TCNT, and address H'FFF8F to RSTCSR.
These registers are therefore read like other registers. Byte transfer instructions can be used for
reading. Table 11.3 lists the read addresses of TCNT, TCSR, and RSTCSR.
Table 11.3 Read Addresses of TCNT, TCSR, and RSTCSR
Address* Register
H'FFF8C TCSR
H'FFF8D TCNT
H'FFF8F RSTCSR
Note: * Lower 20 bits of the address in advanced mode.
307
11.3 Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
11.3.1 Watchdog Timer Operation
Figure 11.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3008 is internally reset for a duration of 518 states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
H
'FF
H
'00
R
ESO
WDT overflow
Start H'00 written
in TCNT Reset
TME set to 1
H'00 written
in TCNT
I
nternal
r
eset signal
518 states
132 states
T
CNT count
v
alue
OVF = 1
Figure 11.4 Operation in Watchdog Timer Mode
308
11.3.2 Interval Timer Operation
Figure 11.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit
WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each
TCNT overflow. This function can be used to generate interval timer interrupts at regular
intervals.
TCNT
count value
Time t
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
WT/ = 0
TME = 1
IT
H'FF
H'00
Figure 11.5 Interval Timer Operation
11.3.3 Timing of Setting of Overflow Flag (OVF)
Figure 11.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT
overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval
timer interrupt is generated in interval timer operation.
φ
TCNT
Overflow signal
OVF
H'FF H'00
Figure 11.6 Timing of Setting of OVF
309
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 11.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3008 chip. This internal reset signal clears OVF to 0, but the WRST bit
remains set to 1. The reset routine must therefore clear the WRST bit.
φ
TCNT
Overflow signal
OVF
WRST
H'FF H'00
WDT internal
reset
Figure 11.7 Timing of Setting of WRST Bit and Internal Reset
310
11.4 Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
11.5 Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not
incremented. See figure 11.8.
φ
TCNT
TCNT NM
Counter write data
T
3
T
2
T
1
CPU: TCNT write cycle
Internal write
signal
TCNT input
clock
Figure 11.8 Contention between TCNT Write and Count up
Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
311
Section 12 Serial Communication Interface
12.1 Overview
The H8/3008 has a serial communication interface (SCI) with two independent channels. The two
channels have identical functions. The SCI can communicate in both asynchronous and
synchronous mode. It also has a multiprocessor communication function for serial communication
among two or more processors.
When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted
independently. For details, see section 18.6, Module Standby Function.
The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3 (Identification
Card) standard. This function supports serial communication with a smart card. Switching
between the normal serial communication interface and the smart card interface is carried out by
means of a register setting.
12.1.1 Features
SCI features are listed below.
• Selection of synchronous or asynchronous mode for serial communication
Asynchronous mode
Serial data communication is synchronized one character at a time. The SCI can communicate
with a universal asynchronous receiver/transmitter (UART), asynchronous communication
interface adapter (ACIA), or other chip that employs standard asynchronous communication.
It can also communicate with two or more other processors using the multiprocessor
communication function. There are twelve selectable serial data transfer formats.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: even/odd/none
Multiprocessor bit: 1 or 0
Receive error detection: parity, overrun, and framing errors
Break detection: by reading the RxD level directly when a framing error occurs
Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a synchronous communication function.
There is a single serial data communication format.
Data length: 8 bits
Receive error detection: overrun errors
312
• Full-duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
• The following settings can be made for the serial data to be transferred:
LSB-first or MSB-first transfer
Inversion of data logic level
• Built-in baud rate generator with selectable bit rates
• Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
clock from the SCK pin
• Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently.
Features of the smart card interface are listed below.
• Asynchronous communication
Data length: 8 bits
Parity bits generated and checked
Error signal output in receive mode (parity error)
Error signal detect and automatic data retransmit in transmit mode
Supports both direct convention and inverse convention
• Built-in baud rate generator with selectable bit rates
• Three types of interrupts
Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested
independently.
313
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the SCI.
RDR
RSR
TDR
TSR
SSR
SCR
SMR
SCMR
BRR
φ/ 4
φ/16
φ/64
RxD
TxD
SCK TEI
TXI
RXI
ERI
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
SCMR: Smart card mode register
Module data bus
Bus interface
Internal data bus
Parity generate
Parity check
Transmit/receive
control
Baud rate
generator
Clock
External clock
φ
Figure 12.1 SCI Block Diagram
314
12.1.3 Pin Configuration
The SCI has serial pins for each channel as listed in table 12.1.
Table 12.1 SCI Pins
Channel Name Abbreviation I/O Function
0 Serial clock pin SCK0Input/output SCI0 clock input/output
Receive data pin RxD0Input SCI0 receive data input
Transmit data pin TxD0Output SCI0 transmit data output
1 Serial clock pin SCK1Input/output SCI1 clock input/output
Receive data pin RxD1Input SCI1 receive data input
Transmit data pin TxD1Output SCI1 transmit data output
315
12.1.4 Register Configuration
The SCI has internal registers as listed in table 12.2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, control the transmitter and receiver
sections, and specify switching between the serial communication interface and smart card
interface.
Table 12.2 SCI Registers
Channel Address*1Name Abbreviation R/W Initial Value
0 H’FFFB0 Serial mode register SMR R/W H'00
H’FFFB1 Bit rate register BRR R/W H'FF
H’FFFB2 Serial control register SCR R/W H'00
H’FFFB3 Transmit data register TDR R/W H'FF
H’FFFB4 Serial status register SSR R/(W)*2H'84
H’FFFB5 Receive data register RDR R H'00
H’FFFB6 Smart card mode register SCMR R/W H'F2
1 H’FFFB8 Serial mode register SMR R/W H'00
H’FFFB9 Bit rate register BRR R/W H'FF
H’FFFBA Serial control register SCR R/W H'00
H’FFFBB Transmit data register TDR R/W H'FF
H’FFFBC Serial status register SSR R/(W)*2H'84
H’FFFBD Receive data register RDR R H'00
H’FFFBE Smart card mode register SCMR R/W H'F2
Notes: 1. Indicates the lower 20 bits of the address in advanced mode.
2. Only 0 can be written, to clear flags.
316
12.2 Register Descriptions
12.2.1 Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit 7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
—
Read/Write
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When one byte of data has been received, it is
automatically transferred to RDR. The CPU cannot read or write RSR directly.
12.2.2 Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit 76543210
Initial value
Read/Write R
00000000
R
RRRR
R
R
When the SCI has received one byte of serial data, it transfers the received data from RSR into
RDR for storage, completing the receive operation. RSR is then ready to receive the next data.
This double-buffering allows data to be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
317
12.2.3 Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit 7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
—
Read/Write
The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit
data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however,
the SCI does not load the TDR contents into TSR. The CPU cannot read or write RSR directly.
12.2.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit 76543210
Initial value
Read/Write R/W
11111111
R/WR/WR/WR/WR/WR/W
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
318
12.2.5 Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock
source for the baud rate generator.
C/ACHR PE O/ESTOP MP CKS1 CKS0
R/W
00000000
R/WR/WR/WR/WR/WR/WR/W
Initial value
Read/Write
Bit 76543210
Clock select 1/0
These bits select the
baud rate generator's
clock source
Communication mode
Selects asynchronous or synchronous mode
Character length
Selects character length in asynchronous mode
Parity enable
Selects whether a parity bit is added
Parity mode
Selects even or odd parity
Stop bit length
Selects the stop bit length
Multiprocessor mode
Selects the multiprocessor
function
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Communication Mode (C/A)/GSM Mode (GM): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0): Selects whether the
SCI operates in asynchronous or synchronous mode.
319
Bit 7
C/ADescription
0 Asynchronous mode (Initial value)
1 Synchronous mode
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Selects GSM mode for the smart card
interface.
Bit 7
GM Description
0 The TEND flag is set 12.5 etu after the start bit (Initial value)
1 The TEND flag is set 11.0 etu after the start bit
Note: etu: Elementary time unit (time required to transmit one bit)
Bit 6—Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In
synchronous mode, the data length is 8 bits regardless of the CHR setting,
Bit 6
CHR Description
0 8-bit data (Initial value)
1 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode,
the parity bit is neither added nor checked, regardless of the PE bit setting.
Bit 5
PE Description
0 Parity bit not added or checked (Initial value)
1 Parity bit added and checked*
Note: * When PE bit is set to 1, an even or odd parity bit is added to transmit data according to the
even or odd parity mode selection by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
Bit 4—Parity Mode (O/E): Specifies whether even parity or odd parity is used for parity addition
and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit
addition and checking, in asynchronous mode. The O/E bit setting is ignored in synchronous
mode, or when parity addition and checking is disabled in asynchronous mode.
320
Bit 4
O/EDescription
0 Even parity*1(Initial value)
1 Odd parity*2
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mod no stop bit is added, so the STOP bit
setting is ignored.
Bit 3
STOP Description
0 1 stop bit*1(Initial value)
1 2 stop bits*2
Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character.
2. Two stop bits (with value 1) are added to the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the
next incoming character.
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is
valid only in asynchronous mode. It is ignored in synchronous mode.
For further information on the multiprocessor communication function, see section 12.3.3,
Multiprocessor Communication.
Bit 2
MP Description
0 Multiprocessor function disabled (Initial value)
1 Multiprocessor format selected
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. Four clock sources can be selected by the CKS1 and CKS0 bits: ø, ø/4,
ø/16, and ø/64.
321
For the relationship between the clock source, bit rate register setting, and baud rate, see section
12.2.8, Bit Rate Register (BRR).
Bit 1
CKS1 Bit 0
CKS0 Description
00φ(Initial value)
01φ/4
10φ/16
11φ/64
12.2.6 Serial Control Register (SCR)
SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock
output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock
source.
Bit 7 6 5 43210
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Initial value
Read/Write R/W
00000000
R/W
R/W
R/W
R/WR/WR/WR/W
Transmit-end interrupt enable
Enables or disables transmit-end
interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RxI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TxI)
Clock enable 1/0
These bits select the
SCI clock source
322
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from
TDR to TSR.
Bit 7
TIE Description
0 Transmit-data-empty interrupt request (TXI) is disabled* (Initial value)
1 Transmit-data-empty interrupt request (TXI) is enabled
Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the RDRF flag in SSR is set to 1 due to transfer of serial receive data from RSR to
RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6
RIE Description
0 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled*
(Initial value)
1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER,
PER, or ORER flag, then clearing the flag to 0; or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.
Bit 5
TE Description
0 Transmitting disabled*1(Initial value)
1 Transmitting enabled*2
Notes: 1. The TDRE flag is fixed at 1 in SSR.
2. In the enabled state, serial transmission starts when the TDRE flag in SSR is cleared to
0 after writing of transmit data into TDR. Select the transmit format in SMR before
setting the TE bit to 1.
Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
323
Bit 4
RE Description
0 Receiving disabled*1(Initial value)
1 Receiving enabled*2
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
flags retain their previous values.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in
SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0 Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clearing conditions]
• The MPIE bit is cleared to 0
• MPB = 1 in received data
1 Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of
the RDRF, FER, and ORER status flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which
MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,
enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the
FER and ORER flags to be set.
Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2
TEIE Description
0 Transmit-end interrupt requests (TEI) are disabled* (Initial value)
1 Transmit-end interrupt requests (TEI) are enabled*
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): The function of these bits differs for the
normal serial communication interface and for the smart card interface. Their function is switched
with the SMIF bit in SCMR.
324
For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the
SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings
of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or
serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits . For further details on selection of the SCI clock source, see table 12.9 in
section 12.3, Operation.
Bit 1
CKE1 Bit 0
CKE0 Description
0 0 Asynchronous mode Internal clock, SCK pin available for generic input/output*1
Synchronous mode Internal clock, SCK pin used for serial clock output*1
0 1 Asynchronous mode Internal clock, SCK pin used for clock output*2
Synchronous mode Internal clock, SCK pin used for serial clock output
1 0 Asynchronous mode External clock, SCK pin used for clock input*3
Synchronous mode External clock, SCK pin used for serial clock input
1 1 Asynchronous mode External clock, SCK pin used for clock input*3
Synchronous mode External clock, SCK pin used for serial clock input
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in
SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output
pin.
SMR
GM Bit 1
CKE1 Bit 0
CKE0 Description
0 0 0 SCK pin available for generic input/output (Initial value)
0 0 1 SCK pin used for clock output
1 0 0 SCK pin output fixed low
1 0 1 SCK pin used for clock output
1 1 0 SCK pin output fixed high
1 1 1 SCK pin used for clock output
325
12.2.7 Serial Status Register (SSR)
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the
operating status of the SCI.
Initial value
Read/Write R R/W
01000100
Bit 76543210
Multiprocessor bit transfer
Value of multiprocessor bit
to be transmitted
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R
TDRE RDRF ORER FER/ERS PER TEND MPB MPBT
Multiprocessor bit
Stores the received
multiprocessor bit value
Transmit end*
2
Status flag indicating end of transmission
Parity error
Status flag indicating detection of a receive parity
error
Framing error (FER)/Error signal status (ERS)*
2
Status flag indicating detection of a receive framing error,
or flag indicating detection of an error signal
Overrun error
Status flag indicating detection of a receive overrun error
Receive data register full
Status flag indicating that data has been received and stored in RDR
Transmit data register empty
Status flag indicating that transmit data has been transferred from
TDR into TSR and new data can be written in TDR
Notes: 1. Only 0 can be written, to clear the flag.
2. Function differs between the normal serial communication interface and the smart card interface.
326
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1.
The TEND and MPB flags are read-only bits that cannot be written.
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial data can be written in TDR.
Bit 7
TDRE Description
0 TDR contains valid transmit data
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
1 TDR does not contain valid transmit data (Initial value)
[Setting conditions]
• The chip is reset or enters standby mode
• The TE bit in SCR is cleared to 0
• TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF Description
0 RDR does not contain new receive data (Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode
• Read RDRF when RDRF = 1, then write 0 in RDRF
1 RDR contains new receive data
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
Note: The RDR contents and the RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is
still set to 1 when reception of the next data ends, an overrun error will occur and the
receive data will be lost.
327
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5
ORER Description
0 Receiving is in progress or has ended normally*1(Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode
• Read ORER when ORER = 1, then write 0 in ORER
1 A receive overrun error occurred*2
[Setting condition]
Reception of the next serial data ends when RDRF = 1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data prior to the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data
reception ended abnormally due to a framing error in asynchronous mode.
Bit 4
FER Description
0 Receiving is in progress or has ended normally*1(Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode
• Read FER when FER = 1, then write 0 in FER
1 A receive framing error occurred
[Setting condition]
The stop bit at the end of the receive data is checked for a value of 1, and is
found to be 0.*2
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked for a value of 1. The
second stop bit is not checked. When a framing error occurs the SCI transfers the
receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue
while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled.
328
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates the status of the error signal
sent back from the receiving side during transmission. Framing errors are not detected in smart
card interface mode.
Bit 4
ERS Description
0 Normal reception, no error signal* (Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode
• Read ERS when ERS = 1, then write 0 in ERS
1 An error signal has been sent from the receiving side indicating detection of a
parity error
[Setting condition]
The error signal is low when sampled
Note: * Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
Bit 3—Parity Error (PER): Indicates that reception of data with parity added ended abnormally
due to a parity error in asynchronous mode.
Bit 3
PER Description
0 Receiving is in progress or has ended normally*1(Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode
• Read PER when PER = 1, then write 0 in PER
1 A receive parity error occurred*2
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/E in SMR
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): The function of this bit differs for the normal serial
communication interface and for the smart card interface. Its function is switched with the SMIF
bit in SCMR.
For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0): Indicates that when
the last bit of a serial character was transmitted TDR did not contain valid transmit data, so
transmission has ended. The TEND flag is a read-only bit and cannot be written.
329
Bit 2
TEND Description
0 Transmission is in progress
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
1 End of transmission (Initial value)
[Setting conditions]
• The chip is reset or enters standby mode
• The TE bit in SCR is cleared to 0
• TDRE is 1 when the last bit of a 1-byte serial transmit character is
transmitted
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates that when the last bit of a
serial character was transmitted TDR did not contain valid transmit data, so transmission has
ended. The TEND flag is a read-only bit and cannot be written.
Bit 2
TEND Description
0 Transmission is in progress
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
1 End of transmission (Initial value)
[Setting conditions]
• The chip is reset or enters standby mode
• The TE bit is cleared to 0 in SCR and the FER/ERS bit is also cleared to 0
• TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0)
or 1.0 etu (when GM = 1) after a 1-byte serial character is transmitted
Note: etu: Elementary time unit (time required to transmit one bit)
Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot
be written.
Bit 1
MPB Description
0 Multiprocessor bit value in receive data is 0* (Initial value)
1 Multiprocessor bit value in receive data is 1
Note: * If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB retains
its previous value.
330
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format in selected for transmitting in asynchronous mode.
The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not
selected, or when the SCI cannot transmit.
Bit 0
MPBT Description
0 Multiprocessor bit value in transmit data is 0 (Initial value)
1 Multiprocessor bit value in transmit data is 1
12.2.8 Bit Rate Register (BRR)
BRR is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS0 and CKS1 in SMR.
Bit
Initial value
Read/Write
7
R/W R/W R/W R/W R/W R/W R/W R/W
6
11111111
543210
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in standby mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 12.3 shows examples of BRR settings in asynchronous mode. Table 12.4 shows examples
of BRR settings in synchronous mode.
331
Table 12.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
φ (MHz)
Bit Rate 2 2.097152 2.4576 3
(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
110 1 141 0.03 1 148 -0.04 1 174 -0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16
1200 0 51 0.16 0 54 -0.70 0 63 0.00 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16
4800 0 12 0.16 0 13 -2.48 0 15 0.00 0 19 -2.34
9600 0 6 -6.99 0 6 -2.48 0 7 0.00 0 9 -2.34
19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 -2.34
31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00
38400 0 1 -18.62 0 1 -14.67 0 1 0.00 ———
φ (MHz)
Bit Rate 3.6864 4 4.9152 5
(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 -0.25
150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16
300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16
600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 -1.36
9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
19200 0 5 0.00 0 6 -6.99 0 7 0.00 0 7 1.73
31250 ——— 0 3 0.00 0 4 -1.70 0 4 0.00
38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73
332
φ (MHz)
Bit Rate 6 6.144 7.3728 8
(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
110 2 106 -0.44 2 108 0.08 2 130 -0.07 2 141 0.03
150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16
300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16
600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16
1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16
2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16
4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16
9600 0 19 -2.34 0 19 0.00 0 23 0.00 0 25 0.16
19200 0 9 -2.34 0 9 0.00 0 11 0.00 0 12 0.16
31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00
38400 0 4 -2.34 0 4 0.00 0 5 0.00 0 6 -6.99
φ (MHz)
Bit Rate 9.8304 10 12 12.288
(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
110 2 174 -0.26 2 177 -0.25 2 212 0.03 2 217 0.08
150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00
300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00
600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00
1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00
2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00
4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00
9600 0 31 0.00 0 32 -1.36 0 38 0.16 0 39 0.00
19200 0 15 0.00 0 15 1.73 0 19 -2.34 0 19 0.00
31250 0 9 -1.70 0 9 0.00 0 11 0.00 0 11 2.40
38400 0 7 0.00 0 7 1.73 0 9 -2.34 0 9 0.00
333
φ (MHz)
Bit Rate 13 14 14.7456 16
(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
110 2 230 -0.08 2 248 -0.17 3 64 0.70 3 70 0.03
150 2 168 0.16 2 181 0.16 2 191 0.00 2 207 0.16
300 2 84 -0.43 2 90 0.16 2 95 0.00 2 103 0.16
600 1 168 0.16 1 181 0.16 1 191 0.00 1 207 0.16
1200 1 84 -0.43 1 90 0.16 1 95 0.00 1 103 0.16
2400 0 168 0.16 0 181 0.16 0 191 0.00 0 207 0.16
4800 0 84 -0.43 0 90 0.16 0 95 0.00 0 103 0.16
9600 0 41 0.76 0 45 -0.93 0 47 0.00 0 51 0.16
19200 0 20 0.76 0 22 -0.93 0 23 0.00 0 25 0.16
31250 0 12 0.00 0 13 0.00 0 14 -1.70 0 15 0.00
38400 0 10 -3.82 0 10 3.57 0 11 0.00 0 12 0.16
φ (MHz)
Bit Rate 18 20 25
(bit/s) n N Error (%) n N Error (%) n N Error (%)
110 3 79 -0.12 3 88 -0.25 3 110 -0.02
150 2 233 0.16 3 64 0.16 3 80 -0.47
300 2 116 0.16 2 129 0.16 2 162 0.15
600 1 233 0.16 2 64 0.16 2 80 -0.47
1200 1 116 0.16 1 129 0.16 1 162 0.15
2400 0 233 0.16 1 64 0.16 1 80 -0.47
4800 0 116 0.16 0 129 0.16 0 162 0.15
9600 0 58 -0.69 0 64 0.16 0 80 -0.47
19200 0 28 1.02 0 32 -1.36 0 40 -0.76
31250 0 17 0.00 0 19 0.00 0 24 0.00
38400 0 14 -2.34 0 15 1.73 0 19 1.73
334
Table 12.4 Examples of Bit Rates and BRR Settings in Synchronous Mode
Bit φ (MHz)
Rate 2 4 8 10 13 16 18 20 25
(bit/s) n N n N n N n N n N n N n N n N n N
110 3 70 —— —— —— —— —— —— —— — —
250 2 124 2 249 3 124 —— 3 202 3 249 —— —— — —
500 1 249 2 124 2 249 —— 3 101 3 124 3 140 3 155 ——
1k 1 124 1 249 2 124 —— 2 202 2 249 3 69 3 77 3 97
2.5k 0 199 1 99 1 199 1 249 2 80 2 99 2 112 2 124 2 155
5k 0 99 0 199 1 99 1 124 1 162 1 199 1 224 1 249 2 77
10k 0 49 0 99 0 199 0 249 1 80 1 99 1 112 1 124 1 155
25k 0 19 0 39 0 79 0 99 0 129 0 159 0 179 0 199 0 249
50k 0 9 0 19 0 39 0 49 0 64 0 79 0 89 0 99 0 124
100k 0 4 0 9 0 19 0 24 —— 0390440490 62
250k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 0 19 0 24
500k 0 0* 0 1 0 3 0 4 —— 07 08 09 ——
1M 0 0* 0 1 —— —— 03 04 04 ——
2M 0 0* —— —— 01 —— —— — —
2.5M —— 00*—— —— —— —— — —
4M 0 0* —— —— — —
Note: Settings with an error of 1% or less are recommended.
Legend
Blank: No setting available
—: Setting possible, but error occurs
*: Continuous transmission/reception not possible
335
The BRR setting is calculated as follows:
Asynchronous mode:
N = 64 × 22n–1 × B× 106 – 1
φ
Synchronous mode:
N = 8 × 22n–1 × B× 106 – 1
φ
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clock frequency (MHz)
n: Baud rate generator input clock (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n Clock Source CKS1 CKS0
0φ00
1φ/4 0 1
2φ/16 1 0
3φ/64 1 1
The bit rate error in asynchronous mode is calculated as follows:
Error (%) = (N + 1) × B × 64 × 22n–1 – 1 × 100
φ × 106
336
Table 12.5 shows the maximum bit rates in asynchronous mode for various system clock
frequencies. Tables 12.6 and 12.7 show the maximum bit rates with external clock input.
Table 12.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings
φ (MHz) Maximum Bit Rate (bit/s) n N
2 62500 0 0
2.097152 65536 0 0
2.4576 76800 0 0
3 93750 0 0
3.6864 115200 0 0
4 125000 0 0
4.9152 153600 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
12 375000 0 0
12.288 384000 0 0
14 437500 0 0
14.7456 460800 0 0
16 500000 0 0
17.2032 537600 0 0
18 562500 0 0
20 625000 0 0
25 781250 0 0
337
Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)
2 0.5000 31250
2.097152 0.5243 32768
2.4576 0.6144 38400
3 0.7500 46875
3.6864 0.9216 57600
4 1.0000 62500
4.9152 1.2288 76800
5 1.2500 78125
6 1.5000 93750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
12 3.0000 187500
12.288 3.0720 192000
14 3.5000 218750
14.7456 3.6864 230400
16 4.0000 250000
17.2032 4.3008 268800
18 4.5000 281250
20 5.0000 312500
25 6.2500 390625
338
Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)
2 0.3333 333333.3
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
12 2.0000 2000000.0
14 2.3333 2333333.3
16 2.6667 2666666.7
18 3.0000 3000000.0
20 3.3333 3333333.3
25 4.1667 4166666.7
12.3 Operation
12.3.1 Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses. A smart card interface is also supported as a serial
communication function for an IC card interface.
Selection of asynchronous or synchronous mode and the transmission format for the normal serial
communication interface is made in SMR, as shown in table 12.8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 12.9.
For details of the procedures for switching between LSB-first and MSB-first mode and inverting
the data logic level, see section 13.2.1, Smart Card Mode Register (SCMR).
For selection of the smart card interface format, see section 13.3.3, Data Format.
339
Asynchronous Mode
• Data length is selectable: 7 or 8 bits
• Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These
selections determine the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break
state.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Synchronous Mode
• The communication format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal to external devices.
When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
Smart Card Interface
• One frame consists of 8-bit data and a parity bit.
• In transmitting, a guard time of at least two elementary time units (2 etu) is provided between
the end of the parity bit and the start of he next frame. (An elementary time unit is the time
required to transmit one bit.)
• In receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning
10.5 etu after the start bit..
• In transmitting, if an error signal is received, the same data is automatically transmitted again
after at least 2 etu.
• Only asynchronous communication is supported. There is no synchronous communication
function.
For details of smart card interface operation, see section 13, Smart Card Interface.
340
Table 12.8 SMR Settings and Serial Communication Formats
SMR Settings SCI Communication Format
Bit 7
C/ABit 6
CHR Bit 2
MP Bit 5
PE Bit 3
STOP Mode Data
Length
Multi-
pro-
cessor
Bit Parity
Bit Stop Bit
Length
0 0 0 0 0 Asyn- 8-bit data Absent Absent 1 bit
1chronous 2 bits
10 mode Present 1 bit
1 2 bits
1 0 0 7-bit data Absent 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
01—0 Asyn-
chronous 8-bit data Present Absent 1 bit
—1mode (multi- 2 bits
1—0processor 7-bit data 1 bit
—1format) 2 bits
1———— Syn-
chronous
mode
8-bit data Absent None
Table 12.9 SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Setting SCI Transmit/Receive clock
Bit 7
C/ABit 1
CKE1 Bit 0
CKE0 Mode Clock Source SCK Pin Function
0 0 0 Asynchronous Internal SCI does not use the SCK pin
1mode Outputs clock with frequency matching the
bit rate
1 0 External Inputs clock with frequency 16 times the bit
1rate
1 0 0 Synchronous Internal Outputs the serial clock
1mode
1 0 External Inputs the serial clock
1
341
12.3.2 Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
one or two stop bits. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full-duplex communication
is possible. The transmitter and the receiver are both double-buffered, so data can be written and
read while transmitting and receiving are in progress, enabling continuous transmitting and
receiving.
Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and one or two stop bits (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
1D0 D1 D2 D3 D4 D5 D6 D7 0/1 1
Idle (mark) state
1
(MSB)(LSB)
0
1
Serial
data Start
bit
1 bit
Transmit or receive data
7 or 8 bits
One unit of data (character or frame)
1 bit,
or
none
Parity
bit
1 or 2 bits
Stop bit(s)
Figure 12.2 Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits)
Communication Formats: Table 12.10 shows the 12 communication formats that can be selected
in asynchronous mode. The format is selected by settings in SMR.
342
Table 12.10 Serial Communication Formats (Asynchronous Mode)
7-bit data
STOP STOP
MPB
STOPMPB
STOP
P
STOP
STOP
P
STOP STOP
SMR Settings
CHR PE MP STOP
00 0 0
00 0 1
01 0 0
01 0 1
10 0 0
10 0 1
11 0 0
11 0 1
0—10
0—11
1—10
1—11
Serial Communication Format and Frame Length
123456789101112
STOP
8-bit data
S
8-bit data
S
STOP
P
8-bit data
S
8-bit data
S
STOP
7-bit data
S
7-bit data
S
7-bit data
S
S
8-bit data
S
STOP STOP
MPB
8-bit data
S
7-bit data
S
7-bit data
S
P
STOPSTOP
STOP
STOP
STOPMPB
Legend:
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
343
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source
selection, see table 12.9.
When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit
rate.
When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 12.3
so that the rising edge of the clock occurs at the center of each transmit data bit.
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
0
1frame
Figure 12.3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
Transmitting and Receiving Data:
• SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE
and RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags, or RDR, which retain their previous contents.
When an external clock is used the clock should not be stopped during initialization or
subsequent operation, since operation will be unreliable in this case.
344
Figure 12.4 shows a sample flowchart for initializing the SCI.
Start of initialization
Set value in BRR
Select communication format
in SMR
1-bit interval elapsed?
Wait
(4)
(3)
(2)
(1)
Yes
No
<End of initialization>
Set TE or RE bit to 1 in SCR
Set the RIE, TIE, TEIE, and
MPIE bits
Set CKE1 and CKE0 bits in SCR
(leaving TE and RE bits
cleared to 0)
Clear TE and RE bits
to 0 in SCR
(1)
(2)
(3)
(4)
Set the clock source in SCR. Clear the
RIE, TIE, TEIE, MPIE, TE, and RE bits to
0. If clock output is selected in
asynchronous mode, clock output starts
immediately after the setting is made in
SCR.
Select the communication format in SMR.
Write the value corresponding to the bit
rate in BRR.
This step is not necessary when an
external clock is used.
Wait for at least the interval required to
transmit or receive one bit, then set the
TE or RE bit to 1 in SCR. Set the RIE,
TIE, TEIE, and MPIE bits as necessary.
Setting the TE or RE bit enables the SCI
to use the TxD or RxD pin.
Figure 12.4 Sample Flowchart for SCI Initialization
345
• Transmitting Serial Data (Asynchronous Mode): Figure 12.5 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
Yes
Yes
<End>
Clear TE bit to 0 in SCR
Clear DR bit to 0 and set
DDR bit to 1
TEND= 1 No
Output break signal? No
Read TEND flag in SSR
All data transmitted? No
TDRE= 1
Yes
No
Read TDRE flag in SSR
(3)
Initialize
(4)
Write transmit data in TDR
and clear TDRE flag to 0 in SSR
(1)
(2)
(3)
(4)
Start transmitting
(1)
(2)
Yes
SCI initialization:
the transmit data output function of
the TxD pin is selected automatically.
After the TE bit is set to 1, one frame
of 1s is output, then transmission is
possible.
SCI status check and transmit data
write:
read SSR and check that the TDRE
flag is set to 1, then write transmit data
in TDR and clear the TDRE flag to 0.
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written,
write data in TDR, then clear the
TDRE flag to 0.
To output a break signal at the end of
serial transmission:
set the DDR bit to 1 and clear the DR
bit to 0, then clear the TE bit to 0 in
SCR.
Figure 12.5 Sample Flowchart for Transmitting Serial Data
346
In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
Start bit: One 0 bit is output.
Transmit data: 7 or 8 bits are output, LSB first.
Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
Stop bit(s): One or two 1 bits (stop bits) are output.
Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time
Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
0/1D0 D1 D7 0/1 1
1
0
Start bit
0D0D1 D7 1
1
Data Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
TDRE
TEND
Idle state
(mark state)
TEI interrupt
request
TXI interrupt
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI interrupt
request
1 frame
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit)
347
• Receiving Serial Data (Asynchronous Mode): Figure 12.7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
Yes
Yes
No
No
<End>
All data received?
(2)
(1)
Initialize
(4)
(5)
(1)
(2)(3)
(4)
(5)
Start receiving
Error handling
Read ORER, PER, and FER
flags in SSR
PER∨FER∨OPER= 1
RDRF= 1
Read RDRF flag in SSR
(continued on next page)
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
Yes
(3)
No
SCI initialization:
the receive data input function of the RxD
pin is selected automatically.
Receive error handling and break detection:
if a receive error occurs, read the ORER,
PER, and FER flags in SSR to identify the
error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if
any of these flags remains set to 1. When a
framing error occurs, the RxD pin can be
read to detect the break state.
SCI status check and receive data read:
read SSR, check that the RDRF flag is set
to 1, then read receive data from RDR and
clear the RDRF flag to 0. Notification that
the RDRF flag has changed from 0 to 1 can
also be given by the RXI interrupt.
To continue receiving serial data:
check the RDRF flag, read RDR, and clear
the RDRF flag to 0 before the stop bit of the
current frame is received.
Clear RE bit to 0 in SCR
Figure 12.7 Sample Flowchart for Receiving Serial Data
348
Yes
<End>
Error handling
Yes
No
Yes
Yes
No
No
No
ORER= 1
Overrun error handling
FER= 1
Break?
Framing error handling Clear RE bit to 0 in SCR
PER= 1
Parity error handling
Clear ORER, PER, and FER flags
to 0 in SSR
(3)
Figure 12.7 Sample Flowchart for Receiving Serial Data (cont)
349
In receiving, the SCI operates as follows:
• The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI
synchronizes internally and starts receiving.
• Receive data is stored in RSR in order from LSB to MSB.
• The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks:
Parity check: The number of 1s in the receive data must match the even or odd parity
setting of in the O/E bit in SMR.
Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is
checked.
Status check: The RDRF flag must be 0, indicating that the receive data can be transferred
from RSR into RDR.
If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If
one of the checks fails (receive error*), the SCI operates as shown in table 12.11.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
is not set to 1. Be sure to clear the error flags to 0.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 12.11 Receive Error Conditions
Receive Error Abbreviation Condition Data Transfer
Overrun error ORER Receiving of next data ends while
RDRF flag is still set to 1 in SSR Receive data is not transferred
from RSR to RDR
Framing error FER Stop bit is 0 Receive data is transferred from
RSR to RDR
Parity error PER Parity of received data differs from
even/odd parity setting in SMR Receive data is transferred from
RSR to RDR
350
Figure 12.8 shows an example of SCI receive operation in asynchronous mode.
0/1D0 D1 D7 0/1 1
1
0
Start
bit
0D0D1 D7 1
1
Data Data
Parity
bit Parity
bit
Stop
bit Stop
bit
Start
bit
RDRF
FER
Idle (mark) state
Framing error,
ERI interrupt
request
RXI interrupt
request RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
1 frame
Figure 12.8 Example of SCI Receive Operation
(8-Bit Data with Parity and One Stop Bit)
12.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 12.9 shows an example of communication among different processors using a
multiprocessor format.
351
Communication Formats: Four formats are available. Parity bit settings are ignored when a
multiprocessor format is selected. For details see table 12.10.
Clock: See the description of asynchronous mode.
(ID=04)(ID=01) (ID=02) (ID=03)
Transmitting
processor
Receiving
processor B
Receiving
processor A Receiving
processor C Receiving
processor D
H'01 (MPB=1)
Serial data H'AA (MPB=0)
Serial communication line
ID-sending cycle:
receiving processor address Data-sending cycle:
data sent to receiving processor
specified by ID
Legend
MPB : Multiprocessor bit
Figure 12.9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Transmitting and Receiving Data:
• Transmitting Multiprocessor Serial Data: Figure 12.10 shows a sample flowchart for
transmitting multiprocessor serial data and indicates the procedure to follow.
352
TEND= 1 No
No
Read TEND flag in SSR
Yes
Yes
Yes
Yes
No
No
<End>
Clear TE bit to 0 in SCR
Clear DR bit to 0 and set DDR to 1
(2)
(1)
Initialize
(3)
(4)
(1)
(2)
(3)
(4)
TDRE= 1
All data transmitted?
Read TDRE flag in SSR
Start transmitting
Write transmit data in TDR
and set MPBT bit in SSR
Clear TDRE flag to 0
Output break signal?
SCI initialization:
the transmit data output function of
the TxD pin is selected automatically.
SCI status check and transmit data
write:
read SSR, check that the TDRE flag is
1, then write transmit data in TDR.
Also set the MPBT flag to 0 or 1 in
SSR. Finally, clear the TDRE flag to 0.
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written, write
data in TDR, then clear the TDRE flag
to 0.
To output a break signal at the end of
serial transmission:
set the DDR bit to 1 and clear the DR
bit to 0, then clear the TE bit to 0 in
SCR.
Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
353
In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
Start bit: One 0 bit is output.
Transmit data: 7 or 8 bits are output, LSB first.
Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
Stop bit(s): One or two 1 bits (stop bits) are output.
Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time
Figure 12.11 shows an example of SCI transmit operation using a multiprocessor format.
D0 D1 D7 0/1 1
1
0
Start
bit
0D0 D1 D7 0/1 1
Data Multi-
processor
bit Stop
bit Start
bit Data Multi-
processor
bit Stop
bit
TDRE
TEND
Idle (mark)
state
TEI interrupt
request
TXI interrupt
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI interrupt
request
1 frame
Figure 12.11 Example of SCI Transmit Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
• Receiving Multiprocessor Serial Data: Figure 12.12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
354
Read RDRF flag in SSR
No
Yes
Yes
Yes
No
Yes
Yes
No
No
No
Read ORER and FER flags
in SSR
(3)
(1)
(2)
(4)
(1)
(2)
(3)
(4)
(5)
RDRF= 1
FER∨ORER= 1
FER∨ORER= 1
Start receiving
Own ID?
<End>
RDRF= 1
Read RDRF flag in SSR
Finished receiving?
Read receive data from RDR
Yes
Clear RE bit to 0 in SCR
(5)
Error handling
(continued on next page)
SCI initialization:
the receive data input function of the
RxD pin is selected automatically.
ID receive cycle:
set the MPIE bit to 1 in SCR.
SCI status check and ID check:
read SSR, check that the RDRF flag
is set to 1, then read data from RDR
and compare it with the processor's
own ID. If the ID does not match, set
the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches,
clear the RDRF flag to 0.
SCI status check and data receiving:
read SSR, check that the RDRF flag
is set to 1, then read data from RDR.
Receive error handling and break
detection:
if a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After executing the
necessary error handling, clear the
ORER and FER flags both to 0.
Receiving cannot resume while either
the ORER or FER flag remains set to
1. When a framing error occurs, the
RxD pin can be read to detect the
break state.
No
Set MPIE bit to 1 in SCR
Read ORER and FER flags
in SSR
Read RDRF flag in SSR
Initialize
Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data
355
Yes
Yes
No
No
<End>
Clear ORER, PER, and FER
flags to 0 in SSR
Clear RE bit to 0 in SCR
(5)
Error handling
ORER= 1
FER= 1
No
Break?
Overrun error handling
Framing error handling
Yes
Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
356
Figure 12.13 shows an example of SCI receive operation using a multiprocessor format.
ID2 Data2
Idle (mark)
state
Not own ID, so MPIE
bit is set to 1 again
a. Own ID does not match data
b. Own ID matches data
D0 D1 D7 1
10
Start
bit Start
bit
Stop
bit Stop
bit
0D0 D1 D7 011
Data (ID1) Data (data1)
Start
bit
Stop
bit Stop
bit
Data (data2)
MPIE
Idle (mark)
state
1
MPB
RDRF
RDR value
RDR value
RXI interrupt request
(multiprocessor interrupt) RXI interrupt handler reads
RDR data and clears
RDRF flag to 0
No RXI interrupt
request, RDR not
updated
ID1
MPB
D0 D1 D7 1
10
Start
bit 0D0 D1 D7 011
Data (ID2)
MPIE
1
MPB
RDRF
RXI interrupt request
(multiprocessor interrupt)
MPB detection
MPIE = 0
RXI interrupt handler
reads RDR data and
clears RDRF flag to 0
Own ID, so receiving
continues, with data
received by RXI
interrupt handler
MPB
ID1
MPIE bit is set to
1 again
MPB detection
MPIE = 0
Figure 12.13 Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
357
12.3.4 Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full-
duplex communication is possible. The transmitter and the receiver are also double-buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 12.14 shows the general format in synchronous serial communication.
Don't care
One unit (character or frame) of transfer data
MSB
Bit 0 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 6 Bit 7
LSB
Don't care
Serial clock
Serial data
**
Note: * High except in continuous transmitting or receiving
Figure 12.14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transferred in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous
mode the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit
can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by means of the C/A bit in SMR and the CKE1 and CKE0 bits
in SCR. See table 12.6 for details of SCI clock source selection.
When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. If receiving in single-character units is
required, an external clock should be selected.
358
Transmitting and Receiving Data:
• SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and
RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags, or RDR, which retain their previous contents.
Figure 12.15 shows a sample flowchart for initializing the SCI.
<Start transmitting or receiving>
Note: *In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0
or set to 1 simultaneously.
(4)
(3)
(2)
(1)
Start of initialization
Yes
Wait
Yes
1-bit interval elapsed?
Set value in BRR
Clear TE and RE bits to 0 in SCR
Select communication format
in SMR
Set RIE, TIE, MPIE, CKE1 and
CKE0 bits in SCR (leaving TE and
RE bits cleared to 0)
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and MPIE
bits as necessary
(1)
(2)
(3)
(4)
Set the clock source in SCR. Clear the
RIE, TIE, TEIE, MPIE, TE, and RE bits to
0.*
Set the communication format in SMR.
Write the value corresponding to the bit rate
in BRR.
This step is not necessary when an
external clock is used.
Wait for at least the interval required to
transmit or receive one bit, then set the TE
or RE bit to 1 in SCR.* Set the RIE, TIE,
TEIE, and MPIE bits as necessary.
Setting the TE or RE bit enables the SCI to
use the TxD or RxD pin.
Figure 12.15 Sample Flowchart for SCI Initialization
359
• Transmitting Serial Data (Synchronous Mode): Figure 12.16 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
<End>
Yes
Yes
Clear TE bit to 0 in SCR
Yes
No
No
(2)
(1)
Initialize
(3)
(1)
(2)
(3)
Start transmitting
TDRE= 1
All data transmitted?
Read TEND flag in SSR
Read TDRE flag in SSR
Write transmit data in TDR
and clear TDRE flag to 0 in SSR
TEND= 1
No
SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit data in
TDR and clear the TDRE flag to 0.
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written,
write data in TDR, then clear the TDRE
flag to 0.
Figure 12.16 Sample Flowchart for Serial Transmitting
360
In transmitting serial data, the SCI operates as follows.
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
is selected, the SCI outputs data in synchronization with the input clock. Data is output from
the TxD pin in order from LSB (bit 0) to MSB (bit 7).
• The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI
loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE
flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds the
TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is
requested at this time
• After the end of serial transmission, the SCK pin is held in a constant state.
Figure 12.17 shows an example of SCI transmit operation.
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Serial clock
Serial data
1 frame
TXI interrupt
request TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
TXI interrupt
request TEI interrupt
request
Transmit direction
TEND
TDRE
Figure 12.17 Example of SCI Transmit Operation
• Receiving Serial Data (Synchronous Mode): Figure 12.18 shows a sample flowchart for
receiving serial data and indicates the procedure to follow. When switching from
asynchronous to synchronous mode. make sure that the ORER, PER, and FER flags are cleared
to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and
receiving will be disabled.
361
Yes
Yes
No
No
<End>
Clear RE bit to 0 in SCR
Finished receiving?
(2)
(1)
Initialize
(4)
(3)
(5)
(1)
(2)(3)
(4)
(5)
Start receiving
Error handling
ORER= 1
RDRF= 1
Read RDRF flag in SSR
Read ORER flag in SSR
(continued on next page)
Read receive data from
RDR, and clear RDRF
flag to 0 in SSR
No
Yes
SCI initialization: the receive data
input function of the RxD pin is
selected automatically.
Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the
necessary error handling, clear the
ORER flag to 0. Neither transmitting
nor receiving can resume while the
ORER flag remains set to 1.
SCI status check and receive data
read: read SSR, check that the RDRF
flag is set to 1, then read receive data
from RDR and clear the RDRF flag to
0. Notification that the RDRF flag
has changed from 0 to 1 can also be
given by the RXI interrupt.
To continue receiving serial data:
check the RDRF flag, read RDR, and
clear the RDRF flag to 0 before the
MSB (bit 7) of the current frame is
received.
Figure 12.18 Sample Flowchart for Serial Receiving
362
<End>
(3)
Error handling
Overrun error handling
Clear ORER flag to 0 in SSR
Figure 12.18 Sample Flowchart for Serial Receiving (cont)
In receiving, the SCI operates as follows:
• The SCI synchronizes with serial clock input or output and synchronizes internally.
• Receive data is stored in RSR in order from LSB to MSB.
After receiving the data, the SCI checks that the RDRF flag is 0, so that receive data can be
transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received
data is stored in RDR. If the checks fails (receive error), the SCI operates as shown in table
12.11.
When a receive error has been identified in the error check, subsequent transmit and receive
operations are disabled.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, a
receive-error interrupt (ERI) is requested.
363
Figure 12.19 shows an example of SCI receive operation.
Serial clock
Serial data
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
RXI interrupt
request
RXI interrupt
request Overrun error,
ERI interrupt
request
ORER
RDRF
Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
1 frame
Figure 12.19 Example of SCI Receive Operation
364
• Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 12.20 shows a
sample flowchart for transmitting and receiving serial data simultaneously and indicates the
procedure to follow.
Yes
No
No
<End>
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
Yes
No
No
(2)
(1)
Initialize
(3)
(5)
(4)
(1)
(2)
(3)
(4)
(5)
Start of transmitting and receiving
Error handling
TDRE= 1
ORER= 1
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Yes
End of transmitting
and receiving?
Clear TE and RE bits to 0 in SCR
RDRF= 1
Yes
SCI initialization: the transmit data output function of
the TxD pin and the read data input function of the
TxD pin are selected, enabling simultaneous
transmitting and receiving.
SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit
data in TDR and clear the TDRE flag to 0.
Notification that the TDRE flag has changed from 0
to 1 can also be given by the TXI interrupt.
Receive error handling: if a receive error occurs,
read the ORER flag in SSR, then after executing the
necessary error handling, clear the ORER flag to 0.
Neither transmitting nor receiving can resume while
the ORER flag remains set to 1.
SCI status check and receive data read: read SSR,
check that the RDRF flag is 1, then read receive
data from RDR and clear the RDRF flag to 0.
Notification that the RDRF flag has changed from 0
to 1 can also be given by the RXI interrupt.
To continue transmitting and receiving serial data:
check the RDRF flag, read RDR, and clear the
RDRF flag to 0 before the MSB (bit 7) of the current
frame is received. Also check that the TDRE flag is
set to 1, indicating that data can be written, write
data in TDR, then clear the TDRE flag to 0 before
the MSB (bit 7) of the current frame is transmitted.
Note: When switching from transmitting or receiving to simultaneous transmitting and receiving,
clear both the TE bit and the RE bit to 0, then set both bits to 1 simultaneously.
Figure 12.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving
365
12.4 SCI Interrupts
The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 12.12 lists the interrupt
sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE,
and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller.
A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested
when the TEND flag is set to 1 in SSR.
An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR.
Table 12.12 SCI Interrupt Sources
PriorityInterrupt Source Description
HighERI Receive error (ORER, FER, or PER)
RXI Receive data register full (RDRF)
TXI Transmit data register empty (TDRE)
Low
Transmit end (TEND)
TEI
366
12.5 Usage Notes
12.5.1 Notes on Use of SCI
Note the following points when using the SCI.
TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of
transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from
TDR to TSR.
Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not
yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE
flag is set to 1.
Simultaneous Multiple Receive Errors: Table 12.13 shows the state of the SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs the RSR
contents are not transferred to RDR, so receive data is lost.
Table 12.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags Receive Data
Transfer
RDRF ORER FER PER RSR → RDR Receive Errors
11 0 0 × Overrun error
00 1 0 Framing error
00 0 1 Parity error
11 1 0 × Overrun error +
framing error
11 0 1 × Overrun error +
parity error
00 1 1 Framing error +
parity error
11 1 1 × Overrun error +
framing error +
parity error
Note: :Receive data is transferred from RSR to RDR.
× :Receive data is not transferred from RSR to RDR.
367
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the
SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Sending a Break Signal: The input/output condition and level of the TxD pin are determined by
DR and DDR bits. This feature can be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE bit
is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR bits
should therefore be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0.
When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the
TxD pin becomes an input/output outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note
that clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 12.21.
15 0
Internal base clock
8 clocks 70
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
15 0
D
0
D
1
Start bit
16 clocks
7
Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode
368
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 – 1
2N D – 0.5
N
) – (L – 0.5) F –(1 + F) × 100% . . . . . . . . (1)
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 –2 × 16 ) × 100%
1
= 46.875% . . . . . . . . (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of an External Clock Source:
• When an external clock source is used for the serial clock, after updates TDR, allow an
inversion of at least five system clock (φ) cycles before input of the serial clock to start
transmitting. If the serial clock is input within four states of the TDR update, a malfunction
may occur. (See figure 12.22)
SCK
D0 D1 D2 D3 D4 D5 D6 D7
TDRE
t
Note: In operation with an external clock source, be sure that t >4 states.
Figure 12.22 Example of Synchronous Transmission
369
Switching from SCK Pin Function to Port Pin Function:
• Problem in Operation: When switching the SCK pin function to the output port function (high-
level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0,
CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 12.23)
SCK/port
Data
TE
C/A
CKE1
CKE0
Bit 7Bit 6
1. End of transmission 4. Low-level output
3.C/A= 0
2.TE= 0
Half-cycle low-level output
Figure 12.23 Operation when Switching from SCK Pin Function to Port Pin Function
370
• Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily
places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an
external circuit.
With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following
settings in the order shown.
1. End of serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 ... switchover to port output
5. CKE1 bit = 0
SCK/port
Data
TE
C/A
CKE1
CKE0
Bit 7Bit 6
1. End of transmission
3.CKE1= 1 5.CKE1= 0
4.C/A= 0
2.TE= 0
High-level outputTE
Figure 12.24 Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output)
371
Section 13 Smart Card Interface
13.1 Overview
The SCI supports an IC card (smart card) interface handling ISO/IEC7816-3 (Identification Card)
character transmission as a serial communication interface expansion function.
Switchover between the normal serial communication interface and the smart card interface is
controlled by a register setting.
13.1.1 Features
Features of the smart card interface supported by the H8/3008 are listed below.
• Asynchronous communication
Data length: 8 bits
Parity bit generation and checking
Transmission of error signal (parity error) in receive mode
Error signal detection and automatic data retransmission in transmit mode
Direct convention and inverse convention both supported
• Built-in baud rate generator allows any bit rate to be selected
• Three interrupt sources
There are three interrupt sources—transmit-data-empty, receive-data-full, and
transmit/receive error—that can issue requests independently.
372
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the smart card interface.
Bus interface
TDR
RSR
RDR
Module data bus
TSR
SCMR
SSR
SCR
Transmission/
reception
control
BRR
Baud rate
generator
Internal
data bus
RxD
TxD
SCK
Parity generation
Parity check
Clock
External clock
φ
φ/4
φ/16
φ/64
TXI
RXI
ERI
SMR
Legend
SCMR: Smart card mode register
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Figure 13.1 Block Diagram of Smart Card Interface
13.1.3 Pin Configuration
Table 13.1 shows the smart card interface pins.
Table 13.1 Smart Card Interface Pins
Pin Name Abbreviation I/O Function
Serial clock pin SCK I/O Clock input/output
Receive data pin RxD Input Receive data input
Transmit data pin TxD Output Transmit data output
373
13.1.4 Register Configuration
The smart card interface has the internal registers listed in table 13.2. The BRR, TDR, and RDR
registers have their normal serial communication interface functions, as described in section 12,
Serial Communication Interface.
Table 13.2 Smart Card Interface Registers
Channel Address*1Name Abbreviation R/W Initial Value
0 H'FFFB0 Serial mode register SMR R/W H'00
H'FFFB1 Bit rate register BRR R/W H'FF
H'FFFB2 Serial control register SCR R/W H'00
H'FFFB3 Transmit data register TDR R/W H'FF
H'FFFB4 Serial status register SSR R/(W)*2H'84
H'FFFB5 Receive data register RDR R H'00
H'FFFB6 Smart card mode register SCMR R/W H'F2
1 H'FFFB8 Serial mode register SMR R/W H'00
H'FFFB9 Bit rate register BRR R/W H'FF
H'FFFBA Serial control register SCR R/W H'00
H'FFFBB Transmit data register TDR R/W H'FF
H'FFFBC Serial status register SSR R/(W)*2H'84
H'FFFBD Receive data register RDR R H'00
H'FFFBE Smart card mode register SCMR R/W H'F2
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written in bits 7 to 3, to clear the flags.
374
13.2 Register Descriptions
This section describes the new or modified registers and bit functions in the smart card interface.
13.2.1 Smart Card Mode Register (SCMR)
SCMR is an 8-bit readable/writable register that selects smart card interface functions.
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Bit
Initial value
Read/Write
Reserved bits Reserved bit
Smart card interface
mode select
Enables or disables
the smart card interface
function
Smart card data invert
Inverts data logic levels
Smart card data transfer direction
Selects the serial/parallel conversion format
SCMR is initialized to H'F2 by a reset and in standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.*1
Bit 3
SDIR Description
0 TDR contents are transmitted LSB-first (Initial value)
Receive data is stored LSB-first in RDR
1 TDR contents are transmitted MSB-first
Receive data is stored MSB-first in RDR
375
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used in combination with the SDIR bit to communicate with inverse-convention
cards.*2 The SINV bit does not affect the logic level of the parity bit. For parity settings, see
section 13.3.4, Register Settings.
Bit 2
SINV Description
0 Unmodified TDR contents are transmitted (Initial value)
Receive data is stored unmodified in RDR
1 Inverted TDR contents are transmitted
Receive data is inverted before storage in RDR
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0
SMIF Description
0 Smart card interface function is disabled (Initial value)
1 Smart card interface function is enabled
Notes: 1. The function for switching between LSB-first and MSB-first mode can also be used
with the normal serial communication interface. Note that when the communication
format data length is set to 7 bits and MSB-first mode is selected for the serial data to
be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data
are valid.
2. The data logic level inversion function can also be used with the normal serial
communication interface. Note that, when inverting the serial data to be transferred,
parity transmission and parity checking is based on the number of high-level periods at
the serial data I/O pin, and not on the register value.
376
13.2.2 Serial Status Register (SSR)
The function of SSR bit 4 is modified in smart card interface mode. This change also causes a
modification to the setting conditions for bit 2 (TEND).
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Bit
Initial value
Read/Write
Transmit end
Status flag indicating end
of transmission
Error signal status (ERS)
Status flag indicating that an error
signal has been received
Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 12.2.7,
Serial Status Register (SSR).
Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of
the error signal sent from the receiving device to the transmitting device. The smart card interface
does not detection framing errors.
Bit 4
ERS Description
0 Indicates normal transmission, with no error signal returned (Initial value)
[Clearing conditions]
• The chip is reset, or enters standby mode or module stop mode
• Software reads ERS while it is set to 1, then writes 0.
1 Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
A low error signal was sampled.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
377
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 12.2.7,
Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are
modified as follows.
Bit 2
TEND Description
0 Transmission is in progress
[Clearing condition]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
1 End of transmission
[Setting conditions] (Initial value)
• The chip is reset or enters standby mode.
• The TE bit and FER/ERS bit are both cleared to 0 in SCR.
• TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial
character is transmitted (normal transmission).
Note: An etu (elementary time unit) is the time needed to transmit one bit.
13.2.3 Serial Mode Register (SMR)
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a
modification to the function of bits 1 and 0 in the serial control register (SCR).
7
GM
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Bit 7—GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting
this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the
TEND flag that indicates completion of transmission, and the type of clock output used. The
details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in
the serial control register (SCR).
378
Bit 7
GM Description
0 Normal smart card interface mode operation
• The TEND flag is set 12.5 etu after the beginning of the start bit.
• Clock output on/off control only. (Initial value)
1 GSM mode smart card interface mode operation
• The TEND flag is set 11.0 etu after the beginning of the start bit.
• Clock output on/off and fixed-high/fixed-low control.
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 12.2.5,
Serial Mode Register (SMR).
13.2.4 Serial Control Register (SCR)
The function of SCR bits 1 and 0 is modified in smart card interface mode.
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit
Initial value
Read/Write
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 12.2.6,
Serial Control Register (SCR).
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM Bit 1
CKE1 Bit 0
CKE0 Description
0 0 0 Internal clock/SCK pin is I/O port (Initial value)
1 Internal clock/SCK pin is clock output
1 0 Internal clock/SCK pin is fixed at low output
1 Internal clock/SCK pin is clock output
1 0 Internal clock/SCK pin is fixed at high output
1 Internal clock/SCK pin is clock output
379
13.3 Operation
13.3.1 Overview
The main features of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of
one bit) is provided between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for 1 etu period
10.5 etu after the start bit.
• If an error signal is detected during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no synchronous communication
function.
13.3.2 Pin Connections
Figure 13.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should both be connected to this line. The
data transmission line should be pulled up to VCC with a resistor.
When the smart card uses the clock generated on the smart card interface, the SCK pin output is
input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is
unnecessary.
The reset signal should be output from one of the H8/3008’s generic ports.
In addition to these pin connections. power and ground connections will normally also be
necessary.
380
TxD
RxD
SCK
Px (port)
H8/3008
chip
VCC
I/O
Data line
Clock line
Reset line
CLK
RST
Card-processing device
Smart card
Figure 13.2 Smart Card Interface Connection Diagram
Note: Setting both TE and RE to 1 without connecting a smart card enables closed
transmission/reception, allowing self-diagnosis to be carried out.
13.3.3 Data Format
Figure 13.3 shows the smart card interface data format. In reception in this mode, a parity check is
carried out on each frame, and if an error is detected an error signal is sent back to the transmitting
device to request retransmission of the data. In transmission, the error signal is sampled and the
same data is retransmitted.
381
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
No parity error
Output from transmitting device
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Parity error
Output from transmitting device
DE
Output from
receiving
device
Legend
Ds: Start bit
D0 to D7: Data bits
Dp: Parity bit
DE: Error signal
Figure 13.3 Smart Card Interface Data Format
The operating sequence is as follows.
1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
up resistor.
2. The transmitting device starts transfer of one frame of data. The data frame starts with a start
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
3. With the smart card interface, the data line then returns to the high-impedance state. The data
line is pulled high with a pull-up resistor.
4. The receiving device carries out a parity check. If there is no parity error and the data is
received normally, the receiving device waits for reception of the next data. If a parity error
occurs, however, the receiving device outputs an error signal (DE, low-level) to request
retransmission of the data. After outputting the error signal for the prescribed length of time,
the receiving device places the signal line in the high-impedance state again. The signal line is
pulled high again by a pull-up resistor.
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data
frame. If it receives an error signal, however, it returns to step 2 and transmits the same data
again.
382
13.3.4 Register Settings
Table 13.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 must be set to the value shown. The setting of other bits is described in this section.
Table 13.3 Smart Card Interface Register Settings
Bit
Register Address*1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SMR H'FFFB0 GM 0 1 O/E1 0 CKS1 CKS0
BRR H'FFFB1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR H'FFFB2 TIE RIE TE RE 0 0 CKE1*2CKE0
TDR H'FFFB3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0
SSR H'FFFB4 TDRE RDRF ORER ERS PER TEND 0 0
RDR H'FFFB5 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
SCMR H'FFFB6 ————SDIR SINV —SMIF
Notes: —Unused bit.
1. Lower 20 bits of the address in advanced mode.
2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.
Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card
interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the
direct convention type, or set to 1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section
13.3.5, Clock.
Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 13.3.5, Clock, for
the method of calculating the value to be set.
Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial
communication functions. See section 12, Serial Communication Interface, for details. The CKE1
and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock
output, set these bits to 01. Clock output is performed when the GM bit is set to 1 in SMR. Clock
output can also be fixed low or high.
Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to
0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention
type. To use the smart card interface, set the SMIF bit to 1.
383
The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
1. Direct Convention (SDIR = SINV = O/E = 0)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
AZZAZZZAAZ(Z) (Z) State
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to
state A, and transfer is performed in LSB-first order. In the example above, the first character
data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
2. Inverse Convention (SDIR = SINV = O/E = 1)
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
AZZAAAAAAZ(Z) (Z) State
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. In the example above, the first
character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity
rule designated for smart cards.
In the H8/3008, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For
parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies to both
transmission and reception.
384
13.3.5 Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for
calculating the bit rate is shown below. Table 13.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
B = 1488 × 22n–1 × (N + 1) × 106
φ
where, N: BRR setting (0 ≤ N ≤ 255)
B: Bit rate (bit/s)
φ: Operating frequency (MHz)
n: See table 13.4
Table 13.4 n-Values of CKS1 and CKS0 Settings
n CKS1 CKS0
00 0
11
21 0
31
Note:* If the gear function is used to divide the clock frequency, use the divided frequency to
calculate the bit rate. The equation above applies directly to 1/1 frequency division.
Table 13.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
φ (MHz)
N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 25.00
0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 33602.2
1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 16801.1
2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 11200.7
Note: Bit rates are rounded off to two decimal places.
385
The following equation calculates the bit rate register (BRR) setting from the operating frequency
and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
N = 1488 × 22n–1 × B× 106 – 1
φ
Table 13.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0)
φ (MHz)
7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 25.0
bit/s N Error N Error N Error N Error N Error N Error N Error N Error
9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 3 12.49
Table 13.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode)
φ (MHz) Maximum Bit Rate (bits/s) N n
7.1424 9600 0 0
10.00 13441 0 0
10.7136 14400 0 0
13.00 17473 0 0
14.2848 19200 0 0
16.00 21505 0 0
18.00 24194 0 0
20.00 26882 0 0
25.00 33602 0 0
The bit rate error is given by the following equation:
Error (%) = 1488 × 22n-1 × B × (N + 1) × 106 – 1 × 100
φ
386
13.3.6 Transmitting and Receiving Data
Initialization: Before transmitting or receiving data, the smart card interface must be initialized as
described below. Initialization is also necessary when switching from transmit mode to receive
mode, or vice versa.
1. Clear the TE and RE bits to 0 in the serial control register (SCR).
2. Clear error flags ERS, PER, and ORER to 0 in the serial status register (SSR).
3. Set the parity bit (O/E) and baud rate generator select bits (CKS1 and CKS0) in the serial mode
register (SMR). Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1.
4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR).
When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI
pin functions and go to the high-impedance state.
5. Set a value corresponding to the desired bit rate in the bit rate register (BRR).
6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the
CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
Transmitting Serial Data: As data transmission in smart card mode involves error signal
sampling and retransmission processing, the processing procedure is different from that for the
normal SCI. Figure 13.5 shows a sample transmission processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ERS error flag is cleared to 0 in SSR.
3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR.
4. Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation.
The TEND flag is cleared to 0.
5. To continue transmitting data, go back to step 2.
6. To end transmission, clear the TE bit to 0.
The above processing may include interrupt handling.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt
requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in
transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are
enabled, a transmit/receive-error interrupt (ERI) will be requested.
The timing of TEND flag setting depends on the GM bit in SMR.
Figure 13.4 shows timing of TEND flag setting.
387
For details, see Interrupt Operations in this section.
Serial data
(1) GM = 0
TEND
(2) GM = 1
TEND
Ds Dp DE
Guard time
11.0 etu
12.5 etu
Figure 13.4 Timing of TEND Flag Setting
388
Initialization
No
Yes
Clear TE bit to 0
Start transmitting
Start
No
No
No
Yes
Yes
Yes
Yes
No
End
Write transmit data in TDR,
and clear TDRE flag
to 0 in SSR
Error handling
Error handling
TEND = 1?
All data transmitted?
TEND = 1?
FER/ERS = 0?
FER/ERS = 0?
Figure 13.5 Sample Transmission Processing Flowchart
389
1. Data write
TDR TSR
(shift register)
Data 1
2. Transfer from TDR to TSR Data 1 Data 1 Data remains in TDR
Data 1
3. Serial data output
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has
been completed.
In case of normal transmission: TEND flag is set
In case of transmit error: ERS flag is set
Steps 2 and 3 above are repeated until the
TEND flag is set.
I/O signal
output
Data 1
Figure 13.6 Relation Between Transmit Operation and Internal Registers
I/O data
When GM = 0
Guard time
DEDs Da Db Dc Dd De Df Dg Dh Dp
12.5 etu
11.0 etu When GM = 1
TXI (TEND
interrupt)
Figure 13.7 Timing of TEND Flag Setting
Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as
for the normal SCI. Figure 13.8 shows a sample reception processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the
appropriate receive error handling, then clear both the ORER and the PER flag to 0.
3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.
4. Read the receive data from RDR.
5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.
6. To end reception, clear the RE bit to 0.
390
Initialization
Read RDR and clear
RDRF flag to 0 in SSR
Clear RE bit to 0
Start receiving
Start
Error handling
No
No
No
Yes
Yes
ORER = 0
and PER = 0?
RDRF = 1?
All data received?
Yes
Figure 13.8 Sample Reception Processing Flowchart
The above procedure may include interrupt handling.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception
and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will
be requested.
For details, see Interrupt Operations in this section.
If a parity error occurs during reception and the PER flag is set to 1, the received data is
transferred to RDR, so the erroneous data can be read.
Switching Modes: When switching from receive mode to transmit mode, first confirm that the
receive operation has been completed, then start from initialization, clearing RE to 0 and setting
TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been
completed.
391
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND
flag can be used to check that the transmit operation has been completed.
Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means
of the CKE1 and CKE0 bits in SCR. The minimum clock pulse width can be set to the specified
width in this case.
Figure 13.9 shows the timing for fixing clock output. In this example, GM = 1, CKE1 = 0, and the
CKE0 bit is controlled.
Specified pulse
width
CKE1 value
SCK
Specified pulse
width
SCR write
(CKE0 = 1)
SCR write
(CKE0 = 0)
Figure 13.9 Timing for Fixing Cock Output
Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty
(TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt
request (TEI) is not available in smart card mode.
A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested
when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or
ERS flag is set to 1 in SSR. These relationships are shown in table 13.8.
Table 13.8 Smart Card Interface Mode Operating States and Interrupt Sources
Operating State Flag Enable Bit Interrupt Source
Transmit Mode Normal operation TEND TIE TXI
Error ERS RIE ERI
Receive Mode Normal operation RDRF RIE RXI
Error PER, ORER RIE ERI
392
Examples of Operation in GSM Mode: When switching between smart card interface mode and
software standby mode, use the following procedures to maintain the clock duty cycle.
• Switching from smart card interface mode to software standby mode
1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed
output state in software standby mode.
2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive
operations. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
3. Write 0 in the CKE0 bit in SCR to stop the clock.
4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output
is fixed at the specified level.
5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR).
6. Make the transition to the software standby state.
• Returning from software standby mode to smart card interface mode
1'. Clear the software standby state.
2'. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby
(the current P94 pin state).
3'. Set smart card interface mode and output the clock. Clock signal generation is started with the
normal duty cycle.
Software
standby Normal operation
Normal operation
1 2 3 4 5 6 1' 2' 3'
Figure 13.10 Procedure for Stopping and Restarting the Clock
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
potential.
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit to 1 in SCR to start clock output.
393
13.4 Usage Notes
The following points should be noted when using the SCI as a smart card interface.
Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart
card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer
rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing
is shown in figure 13.11.
Internal base
clock
372 clocks
186 clocks
Receive data
(RxD)
Synchronization
sampling timing
D0 D1
Data sampling
timing
185 371 0
371
185 0
0
Start bit
Figure 13.11 Receive Data Sampling Timing in Smart Card Interface Mode
394
The receive margin can therefore be expressed as follows.
Receive margin in smart card interface mode:
M = (0.5 – 1
2N D – 0.5
N
) – (L – 0.5) F –(1 + F) × 100%
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (L = 0 to 1.0)
L: Frame length (L =10)
F: Absolute deviation of clock frequency
From the above equation, if F = 0 and D = 0.5, the receive margin is as follows.
When D = 0.5 and F = 0:
M= (0.5 – 1/2 × 372) × 100%
= 49.866%
Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as
described below.
• Retransmission when SCI is in Receive Mode
Figure 13.12 illustrates retransmission when the SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit is automatically set to
1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit
should be cleared to 0 in SSR before the next parity bit sampling timing.
2. The RDRF bit in SSR is not set for the frame in which the error has occurred.
3. If an error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR.
4. If no error is found when the received parity bit is checked, the receive operation is assumed to
have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE
bit in SCR is set to the enable state, an RXI interrupt is requested.
5. When a normal frame is received, the data pin is held in three-state at the error signal
transmission timing.
395
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp(DE) Ds D0 D1 D2 D3 D4Ds
Frame n+1
Retransmitted frameFrame n
RDRF
[1]
PER [2]
[3]
[4]
Figure 13.12 Retransmission in SCI Receive Mode
• Retransmission when SCI is in Transmit Mode
Figure 13.13 illustrates retransmission when the SCI is in transmit mode.
6. If an error signal is sent back from the receiving device after transmission of one frame is
completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an
ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit
sampling timing.
7. The TEND bit in SSR is not set for the frame for which the error signal was received.
8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.
9. If an error signal is not sent back from the receiving device, transmission of one frame,
including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in
SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested.
D0D1D2D3D4D5D6D7Dp DE Ds D0D1D2D3D4D5D6D7Dp (DE) Ds D0D1D2D3D4Ds
Frame n+1
Retransmitted frameFrame n
TDRE
TEND
[6]
ERS
Transfer from TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR
[7] [9]
[8]
Figure 13.13 Retransmission in SCI Transmit Mode
Note on Block Transfer Mode Support: The smart card interface installed in the H8/3008
supports an IC card (smart card) interface with provision for ISO/IEC7816-3 T=0 (character
transmission). Therefore, block transfer operations are not supported (error signal transmission,
detection, and automatic data retransmission are not performed).
396
397
Section 14 A/D Converter
14.1 Overview
The H8/3008 includes a 10-bit successive-approximations A/D converter with a selection of up to
eight analog input channels.
When the A/D converter is not used, it can be halted independently to conserve power. For details
see section 18.6, Module Standby Function.
The H8/3008 supports 70/134-state conversion as a high-speed conversion mode. Note that it
differs in this respect from the H8/3048 Series, which supports 134/266-state conversion.
14.1.1 Features
A/D converter features are listed below.
• 10-bit resolution
• Eight input channels
• Selectable analog conversion voltage range
The analog voltage conversion range can be programmed by input of an analog reference
voltage at the VREF pin.
• High-speed conversion
Conversion time: minimum 3.5 µs per channel (with 20 MHz system clock)
minimum 2.8 µs per channel (with 25 MHz system clock)
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous A/D conversion on one to four channels
• Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Sample-and-hold function
• Three conversion start sources
The A/D converter can be activated by software, an external trigger, or an 8-bit timer compare
match.
• A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
398
14.1.2 Block Diagram
Figure 14.1 shows a block diagram of the A/D converter.
Module data bus
Bus interface
Internal
data bus
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
Successive-
approximations register
10-bit D/A
Analog
multi-
plexer Sample-and-
hold circuit
Comparator
+
–
Control circuit
ø/4
ø/8
ADI
interrupt signal
AV
V
AV
CC
REF
SS
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Legend:
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
ADTRG
ADTE
Compare match A0
8TCSR0
8-bit timer
Figure 14.1 A/D Converter Block Diagram
399
14.1.3 Pin Configuration
Table 14.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided
into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power
supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage.
Table 14.1 A/D Converter Pins
Pin Name Abbrevi-
ation I/O Function
Analog power supply pin AVCC Input Analog power supply
Analog ground pin AVSS Input Analog ground and reference voltage
Reference voltage pin VREF Input Analog reference voltage
Analog input pin 0 AN0Input Group 0 analog inputs
Analog input pin 1 AN1Input
Analog input pin 2 AN2Input
Analog input pin 3 AN3Input
Analog input pin 4 AN4Input Group 1 analog inputs
Analog input pin 5 AN5Input
Analog input pin 6 AN6Input
Analog input pin 7 AN7Input
A/D external trigger input pin ADTRG Input External trigger input for starting A/D conversion
400
14.1.4 Register Configuration
Table 14.2 summarizes the A/D converter’s registers.
Table 14.2 A/D Converter Registers
Address*1Name Abbreviation R/W Initial Value
H'FFFE0 A/D data register A H ADDRAH R H'00
H'FFFE1 A/D data register A L ADDRAL R H'00
H'FFFE2 A/D data register B H ADDRBH R H'00
H'FFFE3 A/D data register B L ADDRBL R H'00
H'FFFE4 A/D data register C H ADDRCH R H'00
H'FFFE5 A/D data register C L ADDRCL R H'00
H'FFFE6 A/D data register D H ADDRDH R H'00
H'FFFE7 A/D data register D L ADDRDL R H'00
H'FFFE8 A/D control/status register ADCSR R/(W)*2H'00
H'FFFE9 A/D control register ADCR R/W H'7E
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written in bit 7, to clear the flag.
14.2 Register Descriptions
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
ADDRn
Initial value
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
Read/Write
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
401
data register are reserved bits that are always read as 0. Table 14.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 14.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 14.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD)
Analog Input Channel
Group 0 Group 1 A/D Data Register
AN0AN4ADDRA
AN1AN5ADDRB
AN2AN6ADDRC
AN3AN7ADDRD
14.2.2 A/D Control/Status Register (ADCSR)
Bit
Initial value
Read/Write
7
ADF
0
R/(W)
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
*
Note: Only 0 can be written, to clear the flag.*
A/D end flag
Indicates end of A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
A/D start
Starts or stops A/D conversion
Scan mode
Selects single mode or scan mode
Clock select
Selects the A/D conversion time
Channel select 2 to 0
These bits select analog
input channels
402
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing condition]
Read ADF when ADF =1, then write 0 in ADF. (Initial value)
1 [Setting conditions]
• Single mode: A/D conversion ends
• Scan mode: A/D conversion ends in all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE Description
0 A/D end interrupt request (ADI) is disabled (Initial value)
1 A/D end interrupt request (ADI) is enabled
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit
timer compare match.
Bit 5
ADST Description
0 A/D conversion is stopped (Initial value)
1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends.
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode.
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 14.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN Description
0 Single mode (Initial value)
1 Scan mode
403
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3
CKS Description
0 Conversion time = 134 states (maximum) (Initial value)
1 Conversion time = 70 states (maximum)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection Channel Selection Description
CH2 CH1 CH0 Single Mode Scan Mode
000 AN
0 (Initial value) AN0
1AN
1AN0, AN1
10 AN
2AN0 to AN2
1AN
3AN0 to AN3
100 AN
4AN4
1AN
5AN4, AN5
10 AN
6AN4 to AN6
1AN
7AN4 to AN7
14.2.3 A/D Control Register (ADCR)
Bit
Initial value
Read/Write
7
TRGE
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
0
R/W
2
—
1
—
1
—
1
—
Trigger enable
Enables or disables starting of A/D conversion
by an external trigger or 8-bit timer compare match
Reserved bits
ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by
external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a
reset and in standby mode.
404
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external
trigger or 8-bit timer compare match.
Bit 7
TRGE Description
0 Starting of A/D conversion by an external trigger or 8-bit timer
compare match is disabled (Initial value)
1 A/D conversion is started at the falling edge of the external trigger
signal (ADTRG) or by an 8-bit timer compare match
External trigger pin and 8-bit timer selection is performed by the 8-bit timer. For details, see
section 9, 8-Bit Timers.
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Reserved: This bit can be read or written, but must not be set to 1.
14.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 14.2 shows the data flow for access to an A/D data register.
405
Upper-byte read
Bus interface Module data bus
CPU
(H'AA)
ADDRnH
(H'AA) ADDRnL
(H'40)
Lower-byte read
Bus interface Module data bus
CPU
(H'40)
ADDRnH
(H'AA) ADDRnL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
(n = A to D)
(n = A to D)
Figure 14.2 A/D Data Register Access Operation (Reading H'AA40)
406
14.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
14.4.1 Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF flag is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 14.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0,
CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started
(ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
407
ADIE
ADST
ADF
State of channel 0
(AN )
Set
Set Set
Clear Clear
Idle
Idle
Idle
Idle
A/D conversion (1)
A/D conversion (2)
Idle
Read conversion result
A/D conversion result (1) Read conversion result
A/D conversion result (2)
Note: Vertical arrows ( ) indicate instructions executed by software.
0
1
2
3
A/D conversion
starts
*
*
*
*
*
*
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Idle
Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
408
14.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are
selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data
registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 14.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested when A/D conversion ends.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
409
ADST
ADF
State of channel 0
(AN )
0
1
2
3
Continuous A/D conversion
Set Clear*1
Clear*1
Idle
A/D conversion (1)
Idle
Idle
Idle
A/D conversion (4) Idle
A/D conversion (2)
Idle
A/D conversion (5)
Idle
A/D conversion (3)
Idle
Idle
Transfer A/D conversion result (1) A/D conversion result (4)
A/D conversion result (2)
A/D conversion result (3)
1.
2.
A/D conversion time
Notes:
*2
*1
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Vertical arrows ( ) indicate instructions executed by software.
Data currently being converted is ignored.
Figure 14.4 Example of A/D Converter Operation (Scan Mode,
Channels AN0 to AN2 Selected)
410
14.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D
conversion timing. Table 14.4 indicates the A/D conversion time.
As indicated in figure 14.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 14.4.
In scan mode, the values given in table 14.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when
CKS = 1.
φ
Address bus
Write signal
Input sampling
timing
ADF
(1)
(2)
tDtSPL
tCONV
Legend:
(1):
(2):
t :
t :
t :
D
SPL
CONV
ADCSR write cycle
ADCSR address
Synchronization delay
Input sampling time
A/D conversion time
Figure 14.5 A/D Conversion Timing
411
Table 14.4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Symbol Min Typ Max Min Typ Max
Synchronization delay tD6—94 —5
Input sampling time tSPL —31 —— 15 —
A/D conversion time tCONV 131 —134 69 —70
Note: Values in the table are numbers of states.
14.4.4 External Trigger Input Timing
A/D conversion can be externally triggered When the TRGE bit is set to 1 in ADCR and the 8-bit
timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A high-to-
low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1
by software. Figure 14.6 shows the timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 14.6 External Trigger Input Timing
412
14.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
14.6 Usage Notes
When using the A/D converter, note the following points:
1. Analog Input Voltage Range
During A/D conversion, the voltages input to the analog input pins ANn should be in the range
AVSS ≤ ANn ≤ VREF.
2. Relationships of AVCC and AVSS to VCC and VSS
AVCC, AVSS, VCC, and VSS should be related as follows: AVSS = VSS. AVCC and AVSS must not
be left open, even if the A/D converter is not used.
3. VREF Programming Range
The reference voltage input at the VREF pin should be in the range VREF ≤ AVCC.
4. Note on Board Design
In board layout, separate the digital circuits from the analog circuits as much as possible.
Particularly avoid layouts in which the signal lines of digital circuits cross or closely approach
the signal lines of analog circuits. Induction and other effects may cause the analog circuits to
operate incorrectly, or may adversely affect the accuracy of A/D conversion.
The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply
voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The
analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the
board.
5. Note on Noise
To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to
AN7) and analog reference voltage pin (VREF), connect a protection circuit like the one in figure
14.7 between AVCC and AVSS. The bypass capacitors connected to AVCC and VREF and the filter
capacitors connected to AN0 to AN7 must be connected to AVSS. If filter capacitors like the
ones in figure 14.7 are connected, the voltage values input to the analog input pins (AN0 to
AN7) will be smoothed, which may give rise to error. Error can also occur if A/D conversion is
frequently performed in scan mode so that the current that charges and discharges the capacitor
in the sample-and-hold circuit of the A/D converter becomes greater than that input to the
analog input pins via input impedance (Rin). The circuit constants should therefore be selected
carefully.
413
AVCC
*1 *1
VREF
AN0 to AN7
AVSS
Notes: 1.
2. Rin: input impedance
Rin*2 100 Ω
0.1 µF
0.01 µF10 µF
Figure 14.7 Example of Analog Input Protection Circuit
Table 14.5 Analog Input Pin Ratings
Item Min Max Unit
Analog input capacitance —20 pF
Allowable signal-source impedance —10* kΩ
Note: * When conversion time = 134 states, VCC = 4.0 V to 5.5 V, and φ ≤ 13 MHz. For details, see
section 19. Electrical Characteristics.
20 pF
To A/D converterAN0 to AN7
10 kΩ
Figure 14.8 Analog Input Pin Equivalent Circuit
Note: Numeric values are approximate, except in table 14.5
414
6. A/D Conversion Accuracy Definitions
A/D conversion accuracy in the H8/3008 is defined as follows:
•Resolution
Digital output code length of A/D converter
•Offset error
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from minimum voltage value 0000000000 to 0000000001 (figure
14.10)
•Full-scale error
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from 1111111110 to 1111111111 (figure 14.10)
•Quantization error
Intrinsic error of the A/D converter; 1/2 LSB (figure 14.9)
•Nonlinearity error
Deviation from ideal A/D conversion characteristic in range from zero volts to full scale,
exclusive of offset error, full-scale error, and quantization error.
•Absolute accuracy
Deviation of digital value from analog input value, including offset error, full-scale error,
quantization error, and nonlinearity error.
111
110
101
100
011
010
001
000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
Quantization error
Analog input
voltage
Digital
output
Ideal A/D conversion
characteristic
Figure 14.9 A/D Converter Accuracy Definitions (1)
415
FS
Offset error
Nonlinearity
error
Actual A/D conversion
characteristic
Analog input
voltage
Digital
output
Ideal A/D
conversion
characteristic
Full-scale
error
Figure 14.10 A/D Converter Accuracy Definitions (2)
7. Allowable Signal-Source Impedance
The analog inputs of the H8/3008 are designed to assure accurate conversion of input signals
with a signal-source impedance not exceeding 10 kΩ. The reason for this rating is that it
enables the input capacitor in the sample-and-hold circuit in the A/D converter to charge
within the sampling time. If the sensor output impedance exceeds 10 kΩ, charging may be
inadequate and the accuracy of A/D conversion cannot be guaranteed.
If a large external capacitor is provided in single mode, then the internal 10-kΩ input resistance
becomes the only significant load on the input. In this case the impedance of the signal source
is not a problem.
A large external capacitor, however, acts as a low-pass filter. This may make it impossible to
track analog signals with high dv/dt (e.g. a variation of 5 mV/µs) (figure 14.11). To convert
high-speed analog signals or to use scan mode, insert a low-impedance buffer.
8. Effect on Absolute Accuracy
Attaching an external capacitor creates a coupling with ground, so if there is noise on the
ground line, it may degrade absolute accuracy. The capacitor must be connected to an
electrically stable ground, such as AVSS.
If a filter circuit is used, be careful of interference with digital signals on the same board, and
make sure the circuit does not act as an antenna.
416
Equivalent circuit of
A/D converter
H8/3008
20 pF
Cin =
15 pF
10 kΩ
Up to 10 kΩ
Low-pass
filter
C up to 0.1 µF
Sensor output impedance
Sensor
input
Figure 14.11 Analog Input Circuit (Example)
417
Section 15 D/A Converter
15.1 Overview
The H8/3008 includes a D/A converter with two channels.
15.1.1 Features
D/A converter features are listed below.
• Eight-bit resolution
• Two output channels
• Conversion time: maximum 10 µs (with 20-pF capacitive load)
• Output voltage: 0 V to VREF
• D/A outputs can be sustained in software standby mode
418
15.1.2 Block Diagram
Figure 15.1 shows a block diagram of the D/A converter.
DADR0
DADR1
DACR
DASTCR
V
AV
DA
DA
AV
REF
CC
SS
0
1
Legend:
DACR:
DADR0:
DADR1:
DASTCR:
8-bit D/A
Module data bus
Bus interface
Internal
data bus
Control circuit
D/A control register
D/A data register 0
D/A data register 1
D/A standby control register
Figure 15.1 D/A Converter Block Diagram
419
15.1.3 Pin Configuration
Table 15.1 summarizes the D/A converter's input and output pins.
Table 15.1 D/A Converter Pins
Pin Name Abbreviation I/O Function
Analog power supply pin AVSS Input Analog power supply and reference voltage
Analog ground pin AVSS Input Analog ground and reference voltage
Analog output pin 0 DA0Output Analog output, channel 0
Analog output pin 1 DA1Output Analog output, channel 1
Reference voltage input pin VREF Input Analog reference voltage
15.1.4 Register Configuration
Table 15.2 summarizes the D/A converter's registers.
Table 15.2 D/A Converter Registers
Address* Name Abbreviation R/W Initial Value
H'FFF9C D/A data register 0 DADR0 R/W H'00
H'FFF9D D/A data register 1 DADR1 R/W H'00
H'FFF9E D/A control register DACR R/W H'1F
H'EE01A D/A standby control register DASTCR R/W H'FE
Note: * Lower 20 bits of the address in advanced mode.
420
15.2 Register Descriptions
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the
data to be converted. When analog output is enabled, the D/A data register values are constantly
converted and output at the analog output pins.
The D/A data registers are initialized to H'00 by a reset and in standby mode.
When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers
are not initialized in software standby mode.
15.2.2 D/A Control Register (DACR)
Bit
Initial value
Read/Write
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
0
R/W
4
—
1
—
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
D/A output enable 1
D/A output enable 0
D/A enable
Controls D/A conversion and analog output
Controls D/A conversion and analog output
Controls D/A conversion
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a reset and in standby mode.
When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers
are not initialized in software standby mode.
421
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7
DAOE1 Description
0DA
1 analog output is disabled
1 Channel-1 D/A conversion and DA1 analog output are enabled
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6
DAOE0 Description
0DA
0 analog output is disabled
1 Channel-0 D/A conversion and DA0 analog output are enabled
Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.
When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0
and 1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1.
Output of the conversion results is always controlled independently by DAOE0 and DAOE1.
Bit 7
DAOE1 Bit 6
DAOE0 Bit 5
DAE Description
0 0 — D/A conversion is disabled in channels 0 and 1
0 1 0 D/A conversion is enabled in channel 0
D/A conversion is disabled in channel 1
0 1 1 D/A conversion is enabled in channels 0 and 1
1 0 0 D/A conversion is disabled in channel 0
D/A conversion is enabled in channel 1
1 0 1 D/A conversion is enabled in channels 0 and 1
1 1 — D/A conversion is enabled in channels 0 and 1
When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in
ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D
and D/A conversion.
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
422
15.2.3 D/A Standby Control Register (DASTCR)
DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software
standby mode.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
DASTE
0
R/W
2
—
1
—
1
—
1
—
Reserved bits D/A standby enable
Enables or disables D/A output
in software standby mode
DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—D/A Standby Enable (DASTE): Enables or disables D/A output in software standby
mode.
Bit 0
DASTE Description
0 D/A output is disabled in software standby mode (Initial value)
1 D/A output is enabled in software standby mode
15.3 Operation
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
423
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 15.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The
converted result is output after the conversion time.
× VREF
The output value is DADR contents
256
Output of this conversion result continues until the value in DADR0 is modified or the DAOE0
bit is cleared to 0.
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
the conversion time.
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
DADR0
write cycle DACR
write cycle DADR0
write cycle DACR
write cycle
Address
DADR0
DAOE0
DA
φ
0
Conversion data 1 Conversion data 2
High-impedance state Conversion
result 1
Conversion
result 2
tDCONV tDCONV
Legend:
t : D/A conversion time
DCONV
Figure 15.2 Example of D/A Converter Operation
424
15.4 D/A Output Control
In the H8/3008, D/A converter output can be enabled or disabled in software standby mode.
When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby
mode. The D/A converter registers retain the values they held prior to the transition to software
standby mode.
When D/A output is enabled in software standby mode, the reference supply current is the same as
during normal operation.
425
Section 16 RAM
16.1 Overview
The H8/3008 has high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit
data bus. The CPU accesses both byte data and word data in two states, making the RAM useful
for rapid data transfer.
The on-chip RAM can be enabled or disabled with the RAM enable bit (RAME) in the system
control register (SYSCR). When the on-chip RAM is disabled, that area is assigned to external
space in the expanded modes. The on-chip RAM specifications for the H8/3008 are shown in table
16.1.
Table 16.1 H8/3008 On-Chip RAM Specifications
RAM size 4 kbytes
Address assignment Modes 1, 2 H'FEF20 to H'FFF1F
Modes 3, 4 H'FFEF20 to H'FFFF1F
426
16.1.1 Block Diagram
Figure 16.1 shows a block diagram of the on-chip RAM.
H'FEF20*
H'FEF22*
H'FFF1E*
H'FEF21*
H'FEF23*
H'FFF1F*
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface SYSCR
On-chip RAM
Even addresses Odd addresses
Legend:
SYSCR: System control register
Note: * The lower 20 bits of the address are shown.
Figure 16.1 RAM Block Diagram
16.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 16.2 gives the address and initial value of
SYSCR.
Table 16.2 System Control Register
Address* Name Abbreviation R/W Initial Value
H'EE012 System control register SYSCR R/W H'09
Note: * Lower 20 bits of the address in advanced mode.
427
16.2 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
2
NMIEG
0
R/W
1
SSOE
0
R/W
0
RAME
1
R/W
Software standby Standby timer select 2 to 0
User bit enable
NMI edge select
Software standby
output port enable
RAM enable bit
Enables or
disables
on-chip RAM
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
428
16.3 Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to the addresses shown in
table 16.1 are directed to the on-chip RAM. In modes 1 to 4 (expanded modes), when the RAME
bit is cleared to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
429
Section 17 Clock Pulse Generator
17.1 Overview
The H8/3008 has a built-in clock pulse generator (CPG) that generates the system clock (φ) and
other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the
clock frequency to generate the system clock (φ). The system clock is output at the φ pin*
1 and
furnished as a master clock to prescalers that supply clock signals to the on-chip supporting
modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency
divider by settings in a division control register (DIVCR)*2. Power consumption in the chip is
reduced in almost direct proportion to the frequency division ratio.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby control register (MSTCR). For details, see section 18.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
φ = EXTAL × n
where, EXTAL: Frequency of crystal resonator or external clock signal
n: Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
17.1.1 Block Diagram
Figure 17.1 shows a block diagram of the clock pulse generator.
XTAL
EXTAL
CPG
φ pin φ/2 to φ/4096
Oscillator Duty
adjustment
circuit Frequency
divider
Division
control
register
Prescalers
Data bus
φ
Figure 17.1 Block Diagram of Clock Pulse Generator
430
17.2 Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock
signal.
17.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as in the example in figure 17.2.
Damping resistance Rd should be selected according to table 17.1 (1), and external capacitances
CL1 and CL2 according to table 17.1 (2). An AT-cut parallel-resonance crystal should be used.
EXTAL
XTAL
CL1
CL2
Rd
Figure 17.2 Connection of Crystal Resonator (Example)
If a crystal resonator with a frequency higher than 20 MHz is connected, the external load
capacitance values in table 17.1 (2) should not exceed 10 [pF]. Also, in order to improve the
accuracy of the oscillation frequency, a thorough study of oscillation matching evaluation, etc.,
should be carried out when deciding the circuit constants.
Table 17.1 (1) Damping Resistance Value
Damping
Resistance Frequency f (MHz)
Value 22 < f ≤ 44 < f ≤88 < f ≤ 10 10 < f ≤ 13 13 < f ≤ 16 16 < f ≤ 18 18 < f ≤ 25
Rd (Ω)1 k50020000000
Note: A crystal resonator between 2 MHz and 25 MHz can be used. If the chip is to be operated
at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of
less than 2 MHz cannot be used.)
Table 17.1 (2) External Capacitance Values
External Capacitance Value 5 V Version Low-Voltage Version
Frequency f (MHz) 20 < f ≤ 25 2 ≤ f ≤ 20 2 ≤ f ≤ 13 2 ≤ f ≤ TBD
CL1 = CL2 (pF) 10 10 to 22 10 to 22 10
431
Crystal Resonator: Figure 17.3 shows an equivalent circuit of the crystal resonator. The crystal
resonator should have the characteristics listed in table 17.2.
XTAL
LRs
C
L
C
0
EXTAL
AT-cut parallel-resonance type
Figure 17.3 Crystal Resonator Equivalent Circuit
Table 17.2 Crystal Resonator Parameters
Frequency (MHz) 248101216182025
Rs max (Ω) 500 120 80 70 60 50 40 40 TBD
Co (pF) 7 pF max
Use a crystal resonator with a frequency equal to the system clock frequency (φ).
Notes on Board Design: When a crystal resonator is connected, the following points should be
noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 17.4.
When the board is designed, the crystal resonator and its load capacitors should be placed as close
as possible to the XTAL and EXTAL pins.
XTAL
EXTAL
C
L2
C
L1
H8/3008
Avoid Signal A Signal B
Figure 17.4 Oscillator Circuit Block Board Design Precautions
432
17.2.2 External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
17.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray
capacitance at the XTAL pin exceeds 10 pF in configuration a, use the connection shown in
configuration b instead, and hold the external clock high in standby mode.
EXTAL
XTAL
EXTAL
XTAL
External clock input
Open
External clock input
a. XTAL pin left open
b. Complementary clock input at XTAL pin
Figure 17.5 External Clock Input (Examples)
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 17.3 shows the clock timing, figure 17.6
shows the external clock input timing, and figure 17.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (tDEXT) has passed after the clock input. The system
must remain reset with the reset signal low during tDEXT, while the clock output is unstable.
433
Table 17.3 Clock Timing (Preliminary)
VCC = 3.0 V
to 5.5 V VCC = 5.0 V
± 10%
Item Symbol Min Max Min Max Unit Test Conditions
External clock input low
pulse width tEXL 30 — 15 — ns Figure 17.6
External clock input high
pulse width tEXH 30 — 15 — ns
External clock rise time tEXr —8 —5 ns
External clock fall time tEXf —8 —5 ns
Clock low pulse width tCL 0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHz Figure
80 — 80 — ns φ < 5 MHz 19.17
Clock high pulse width tCH 0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHz
80 — 80 — ns φ < 5 MHz
External clock output
settling delay time tDEXT* 500 — 500 — µs Figure 17.7
Note: * tDEXT includes a RES pulse width (tRESW). tRESW = 20 tcyc
EXTAL
tEXr tEXf
VCC × 0.7
0.3 V
tEXH tEXL
VCC × 0.5
Figure 17.6 External Clock Input Timing
434
VCC
STBY
EXTAL
φ (internal or
external)
RES
tDEXT
VIH
Figure 17.7 External Clock Output Settling Delay Timing
17.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
17.4 Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
17.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
435
17.5.1 Register Configuration
Table 17.4 summarizes the frequency division register.
Table 17.4 Frequency Division Register
Address* Name Abbreviation R/W Initial Value
H'EE01B Division control register DIVCR R/W H'FC
Note: * Lower 20 bits of the address in advanced mode.
17.5.2 Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
DIV0
0
R/W
2
—
1
—
1
DIV1
0
R/W
Reserved bits Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.
Bit 1
DIV1 Bit 0
DIV0 Frequency Division Ratio
0 0 1/1 (Initial value)
0 1 1/2
1 0 1/4
1 1 1/8
436
17.5.3 Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time tcyc in the AC electrical characteristics. Note that ømin = lower limit of the
operating frequency range. Ensure that ø is not below this lower limit.
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in the
division ratio. The waiting time for exit from software standby mode also changes when the
division ratio is changed. For details, see section 18.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
437
Section 18 Power-Down State
18.1 Overview
The H8/3008 has a power-down state that greatly reduces power consumption by halting the CPU,
and a module standby function that reduces power consumption by selectively halting on-chip
modules.
The power-down state includes the following three modes:
• Sleep mode
• Software standby mode
• Hardware standby mode
The module standby function can halt on-chip supporting modules independently of the power-
down state. The modules that can be halted are the 16-bit timer, 8-bit timer, SCI0, SCI1, and A/D
converter.
Table 18.1 indicates the methods of entering and exiting the power-down modes and module
standby mode, and gives the status of the CPU and on-chip supporting modules in each mode.
438
Table 18.1 Power-Down State and Module Standby Function
Notes: 1. State in which the corresponding MSTCR bit was set to 1. For details see section 18.2.2, Module Standby Control Register H (MSTCRH) and section
18.2.3, Module Standby Control Register L (MSTCRL).
2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
3. When P67 is used as the φ output pin.
4. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR
bit to 0, then set up the module registers again.
Legend
SYSCR: System control register
SSBY: Software standby bit
MSTCRH: Module standby control register H
MSTCRL: Module standby control register L
M
ode
S
leep
m
ode
S
oftware
s
tandby
m
ode
H
ardware
s
tandby
m
ode
M
odule
s
tandby
State
Entering
Conditions
SLEEP instruc-
tion executed
while SSBY = 0
in SYSCR
SLEEP instruc-
tion executed
while SSBY = 1
in SYSCR
Low input at
STBY pin
Corresponding
bit set to 1 in
MSTCRH and MSTCRL
Clock
Active
Halted
Halted
Active
CPU
Halted
Halted
Halted
Active
CPU
Registers
Held
Held
Undeter-
mined
—
16-Bit
Timer
Active
Halted
and
reset
Halted
and
reset
Halted*1
and
reset
8-Bit
Timer
Active
Halted
and
reset
Halted
and
reset
Halted*1
and
reset
SCI0
Active
Halted
and
reset
Halted
and
reset
Halted*1
and
reset
SCI1
Active
Halted
and
reset
Halted
and
reset
Halted*1
and
reset
A/D
Active
Halted
and
reset
Halted
and
reset
Halted*1
and
reset
Other
Modules
Active
Halted
and
reset
Halted
and
reset
Active
RAM
Held
Held
Held*2
—
φ clock
Output*3
φ output
High
output
High
impedance
High
impedance*1
I/O
Ports
Held
Held
High
impedance
—
Exiting
Conditions
• Interrupt
•RES
•STBY
• NMI
•IRQ0 to IRQ2
•RES
•STBY
•STBY
•RES
•STBY
•RES
• Clear MSTCR
bit to 0*4
439
18.2 Register Configuration
The H8/3008 has a system control register (SYSCR) that controls the power-down state, and
module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby
function. Table 18.2 summarizes these registers.
Table 18.2 Control Register
Address* Name Abbreviation R/W Initial Value
H'EE012 System control register SYSCR R/W H'09
H'EE01C Module standby control register H MSTCRH R/W H'78
H'EE01D Module standby control register L MSTCRL R/W H'00
Note: * Lower 20 bits of the address in advanced mode.
18.2.1 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
SSOE
0
R/W
Software standby
Enables transition to
software standby mode
RAM enable
Standby timer select 2 to 0
These bits select the
waiting time of the CPU
and peripheral functions
User bit enable
NMI edge select
Software standby
output port enable
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1
(SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3,
System Control Register (SYSCR).
440
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sleep mode (Initial value)
1 SLEEP instruction causes transition to software standby mode
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms. See table 18.3. If an external
clock is used, any setting can be selected.
Bit 6
STS2 Bit 5
STS1 Bit 4
STS0 Description
0 0 0 Waiting time = 8,192 states (Initial value)
1 Waiting time = 16,384 states
1 0 Waiting time = 32,768 states
1 Waiting time = 65,536 states
1 0 0 Waiting time = 131,072 states
1 0 1 Waiting time = 262,144 states
1 1 0 Waiting time = 1,024 states
1 1 1 Illegal setting
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS0 to CS7, AS, RD, HWR, and LWR) are kept as outputs or fixed high, or
placed in the high-impedance state in software standby mode.
Bit 1
SSOE Description
0 In software standby mode, the address bus and bus control signals
are all high-impedance (Initial value)
1 In software standby mode, the address bus retains its output state and
bus control signals are fixed high
441
18.2.2 Module Standby Control Register H (MSTCRH)
MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the SCI0, SCI1.
Bit
Initial value
Read/Write
7
PSTOP
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
MSTPH0
0
R/W
2
—
0
R/W
1
MSTPH1
0
R/W
φ clock stop
Enables or disables
output of the system clock
Module standby H1 to 0
These bits select modules
to be placed in standby
Reserved bits
MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 7
PSTOP Description
0 System clock output is enabled (Initial value)
1 System clock output is disabled
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Reserved: This bit can be written and read.
Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1
MSTPH1 Description
0 SCI1 operates normally (Initial value)
1 SCI1 is in standby state
442
Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby.
Bit 0
MSTPH0 Description
0 SCI0 operates normally (Initial value)
1 SCI0 is in standby state
18.2.3 Module Standby Control Register L (MSTCRL)
MSTCRL is an 8-bit readable/writable register that controls the module standby function, which
places individual on-chip supporting modules in the standby state. Module standby can be
designated for 16-bit timer, 8-bit timer, and A/D converter modules.
2
MSTPL2
0
R/W
1
—
0
R/W
0
MSTPL0
0
R/W
Reserved bits
Module standby L4 to L2, L0
These bits select modules to be
placed in standby
Bit
Initial value
Read/Write
7
—
0
R/W
6
—
0
R/W
5
—
0
R/W
4
MSTPL4
0
R/W
3
MSTPL3
0
R/W
MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5—Reserved: This bit can be written and read.
Bit 4—Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby.
Bit 4
MSTPL4 Description
0 16-bit timer operates normally (Initial value)
1 16-bit timer is in standby state
443
Bit 3—Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in
standby.
Bit 3
MSTPL3 Description
0 8-bit timer channels 0 and 1 operate normally (Initial value)
1 8-bit timer channels 0 and 1 are in standby state
Bit 2—Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in
standby.
Bit 2
MSTPL2 Description
0 8-bit timer channels 2 and 3 operate normally (Initial value)
1 8-bit timer channels 2 and 3 are in standby state
Bit 1—Reserved: This bit can be written and read.
Bit 0—Module Standby L0 (MSTPL0): Selects whether to place the A/D converter in standby.
Bit 0
MSTPL0 Description
0 A/D converter operates normally (Initial value)
1 A/D converter is in standby state
444
18.3 Sleep Mode
18.3.1 Transition to Sleep Mode
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a
transition from the program execution state to sleep mode. Immediately after executing the SLEEP
instruction the CPU halts, but the contents of its internal registers are retained. On-chip supporting
modules do not halt in sleep mode. Modules which have been placed in standby by the module
standby function, however, remain halted.
18.3.2 Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings
of the I and UI bits in CCR, IPR.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
18.4 Software Standby Mode
18.4.1 Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. On-chip supporting modules are reset and
halted. As long as the specified voltage is supplied, however, CPU register contents and on-chip
RAM data are retained. The settings of the I/O ports also held. When the WDT is used as a
watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before setting SSBY. Also, when
setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
445
18.4.2 Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or
IRQ2 pin, or by input at the RES or STBY pin.
Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the
CPU.
Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
18.4.3 Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 18.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies.
When Using an External Clock: Any setting is permitted.
446
Table 18.3 Clock Frequency and Waiting Time for Clock to Settle
DIV1 DIV0 STS2 STS1 STS0 Waiting Time 25 MHz 20 MHz 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1MHz
0
0 0 0 0 8192 states 0.3 0.4 0.46 0.51 0.65 0.8 1.0 1.3 2.0 4.1
0 0 1 16384 states 0.7 0.8 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2*
0 1 0 32768 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4
0 1 1 65536 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8
1 0 0 131072 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5
1 0 1 262144 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1
1 1 0 1024 states 0.04 0.05 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51
1 1 1 Illegal setting
0
1 0 0 0 8192 states 0.7 0.8 0.91 1.02 1.4 1.6 2.0 2.7 4.0 8.2*
0 0 1 16384 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4
0 1 0 32768 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8
0 1 1 65536 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5
1 0 0 131072 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1
1 0 1 262144 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1
1 1 0 1024 states 0.08 0.10 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0
1 1 1 Illegal setting
1
0 0 0 0 8192 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4*
0 0 1 16384 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8
0 1 0 32768 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5
0 1 1 65536 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1
1 0 0 131072 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1
1 0 1 262144 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3
1 1 0 1024 states 0.16 0.20 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0
1 1 1 Illegal setting
1
1 0 0 0 8192 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4* 32.8*
0 0 1 16384 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5
0 1 0 32768 states 10.5 13.1 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1
0 1 1 65536 states 21.0* 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1
1 0 0 131072 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3
1 0 1 262144 states 83.9 104.9 116.5 131.1 174.8 209.7 262.1 349.5 524.3 1048.6
1 1 0 1024 states 0.33 0.41 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1
1 1 1 Illegal setting
: Recommended setting
Unit
ms
ms
ms
ms
8.2*
16.4
32.8
65.5
131.1
262.1
1.0
16.4*
32.8
65.5
131.1
262.1
524.3
2.0
32.8*
65.5
131.1
262.1
524.3
1048.6
4.1
65.5
131.1
262.1
524.3
1048.6
2097.1
8.2*
447
18.4.4 Sample Application of Software Standby Mode
Figure 18.1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal.
φ
N
MI
N
MIEG
S
SBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby
mode (power-
down state)
Oscillator
settling time
(tosc2)
SLEEP
instruction
NMI exception
handling
C
lock
o
scillator
Figure 18.1 NMI Timing for Software Standby Mode (Example)
18.4.5 Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
448
18.5 Hardware Standby Mode
18.5.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin
goes low. Hardware standby mode reduces power consumption drastically by halting all functions
of the CPU, and on-chip supporting modules. All modules are reset except the on-chip RAM. As
long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are placed in the
high-impedance state.
Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data.
The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby
mode.
18.5.2 Exit from Hardware Standby Mode
Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when
STBY goes high, the clock oscillator starts running. RES should be held low long enough for the
clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a
transition to the program execution state.
18.5.3 Timing for Hardware Standby Mode
Figure 18.2 shows the timing relationships for hardware standby mode. To enter hardware standby
mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive
STBY high, wait for the clock to settle, then bring RES from low to high.
RES
STBY
Clock
oscillator
Oscillator
settling time
Reset
exception
handling
Figure 18.2 Hardware Standby Mode Timing
449
18.6 Module Standby Function
18.6.1 Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (SCI1, SCI0, 16-
bit timer, 8-bit timer, and A/D converter) independently in the power-down state. This standby
function is controlled by bits MSTPH2 to MSTPH0 in MSTCRH and bits MSTPL7 to MSTPL0 in
MSTCRL. When one of these bits is set to 1, the corresponding on-chip supporting module is
placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle.
18.6.2 Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
18.6.3 Usage Notes
When using the module standby function, note the following points.
On-chip Supporting Module Interrupts: Before setting a module standby bit, first disable
interrupts by that module. When an on-chip supporting module is placed in standby by the
module standby function, its registers are initialized, including registers with interrupt request
flags.
Pin States: Pins used by an on-chip supporting module lose their module functions when the
module is placed in module standby. What happens after that depends on the particular pin. For
details, see section 7, I/O Ports. Pins that change from the input to the output state require special
care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data
function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin,
and its output may collide with external SCI transmit data. Data collision should be prevented by
clearing the port DDR bit to 0 or taking other appropriate action.
Register Resetting: When an on-chip supporting module is halted by the module standby
function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0,
its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is
set to 1.
450
18.7 System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the
PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-
impedance state. Figure 18.3 shows the timing of the stopping and starting of system clock output.
When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 18.4 indicates
the state of the φ pin in various operating states.
T1 T2
(PSTOP = 1)
T3 T1 T2
(PSTOP = 0)
MSTCRH write cycle MSTCRH write cycle
High impedance
φ pin
T3
Figure 18.3 Starting and Stopping of System Clock Output
Table 18.4 φ Pin State in Various Operating States
Operating State PSTOP = 0 PSTOP = 1
Hardware standby High impedance High impedance
Software standby Always high High impedance
Sleep mode System clock output High impedance
Normal operation System clock output High impedance
451
Section 19 Electrical Characteristics
— Preliminary —
19.1 Absolute Maximum Ratings
Table 19.1 lists the absolute maximum ratings.
Table 19.1 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage VCC –0.3 to +7.0 V
Input voltage (except for port 7) Vin –0.3 to VCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Reference voltage VREF –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
452
19.2 DC Characteristics
Table 19.2 lists the DC characteristics. Table 19.3 lists the permissible output currents.
Table 19.2 DC Characteristics (1)
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC*1,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
Schmitt trigger
input voltages Port A,
P80 to P82
VT–
VT+
VT+ – VT–
1.0
—
0.4
—
—
—
—
VCC × 0.7
—
V
V
V
Input high
voltage RES, STBY,
NMI, MD2 to
MD0
VIH VCC – 0.7 — VCC + 0.3 V
EXTAL VCC × 0.7 — VCC + 0.3 V
Port 7 2.0 — AVCC + 0.3 V
Ports 4 to 6,
P83, P84, P90
to P95, port B
2.0 — VCC + 0.3 V
Input low
voltage RES, STBY,
MD2 to MD0
VIL –0.3 — 0.5 V
NMI, EXTAL,
ports 4 to 7,
P83, P84, P90
to P95, port B
–0.3 — 0.8 V
Output high
voltage All output pins
(except RESO)VOH VCC – 0.5
3.5 —
——
—V
VIOH = –200 µA
IOH = –1 mA
Output low
voltage All output pins
(except RESO)VOL — — 0.4 V IOL = 1.6 mA
A0 to A19 — — 1.0 V IOL = 10 mA
RESO — — 0.4 V IOL = 1.6 mA
Input leakage
current STBY, NMI,
RES,
MD2 to MD0
|Iin| — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
Port 7 — — 1.0 µA Vin = 0.5 V to
AVCC – 0.5 V
453
Item Symbol Min Typ Max Unit Test Conditions
Three-state
leakage
current
Ports 4 to 6,
A0 to A19,
Ports 8 to B
|ITSI| — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
RESO — — 10.0 µA Vin = 0 V
Input pull-up
MOS current Ports 4 and 5 –Ip50 — 300 µA Vin = 0 V
Input
capacitance NMI
All input pins
except NMI
Cin —
——
—50
15 pF
pF Vin = 0 V
f = fmin
Ta = 25°C
Current
dissipation*2Normal
operation ICC*3—49
(5.0 V) 100 mA f = 20 MHz
— — TBD mA f = 25 MHz
Sleep mode — 36
(5.0 V) 73 mA f = 20 MHz
— — TBD mA f = 25 MHz
Module
standby mode —19
(5.0 V) 51 mA f = 20 MHz
— — TBD mA f = 25 MHz
Standby mode — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
Analog power
supply current During A/D
conversion AICC — 0.6 1.5 mA
During A/D
and D/A
conversion
— 0.6 1.5 mA
Idle — 0.01 5.0 µA DASTE = 0
Reference
current During A/D
conversion AICC — 0.5 0.8 mA
During A/D
and D/A
conversion
— 2.0 3.0 mA
Idle — 0.01 5.0 µA DASTE = 0
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter
is not in use.
Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS,
respectively.
454
2. Given current consumption values are when all the output pins are made to unloaded
state and, furthermore, when the on-chip pull-up MOS is turned off under conditions
that VIH min = VCC – 0.5 V and VIL max = 0.5 V.
Also, the aforesaid current consumption values are when VIH min = VCC × 0.9 and VIL
max = 0.3 V under the condition of VRAM ≤ VCC < 4.5 V.
3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × VCC × f
ICC max. (when using the sleeve) = 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC × f
ICC max. (when the sleeve + module are standing by)
= 1.0 (mA) + 0.45 (mA/(MHz × V)) × VCC × f
Also, the typ. values for current dissipation are reference values.
455
Table 19.2 DC Characteristics (2)
Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 V to AVCC*1,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
Schmitt trigger
input voltages Port A,
P80 to P82
VT–
VT+
VT+ – VT–
VCC × 0.2
—
VCC × 0.07
—
—
—
—
VCC × 0.7
—
V
V
V
Input high
voltage RES, STBY,
NMI, MD2 to
MD0
VIH VCC × 0.9 — VCC + 0.3 V
EXTAL VCC × 0.7 — VCC + 0.3 V
Port 7 VCC × 0.7 — AVCC + 0.3 V
Ports 4 to 6
P83, P84, P90
to P95, port B
VCC × 0.7 — VCC + 0.3 V
Input low
voltage RES, STBY,
MD2 to MD0
VIL –0.3 — VCC × 0.1 V
NMI, EXTAL,
ports 4 to 7
P83, P84, P90 to
P95, port B
–0.3 — VCC × 0.2
0.8 V
VVCC < 4.0 V
VCC = 4.0 to
5.5 V
Output high
voltage All output pins
(except RESO)VOH VCC – 0.5 — — V IOH = –200 µA
VCC – 1.0 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)VOL — — 0.4 V IOL = 1.6 mA
A0 to A19 — — 1.0 V IOL = 5 mA
(VCC < 4.0 V)
IOL = 10 mA
(VCC = 4.0 to
5.5 V)
RESO — — 0.4 V IOL = 1.6 mA
Input leakage
current STBY, NMI,
RES,
MD2 to MD0
|Iin| — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
Port 7 — — 1.0 µA Vin = 0.5 V to
AVCC – 0.5 V
456
Item Symbol Min Typ Max Unit Test Conditions
Three-state
leakage
current
Ports 4 to 6,
A0 to A19,
Ports 8 to B
|ITSI| — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
RESO — — 10.0 µA Vin = 0 V
Input pull-up
MOS current Ports 4 and 5 –Ip10 — 300 µA Vin = 0 V
Input
capacitance NMI
All input pins
except NMI
Cin —
——
—50
15 pF
pF Vin = 0 V
f = fmin
Ta = 25°C
Current
dissipation*2Normal
operation ICC*3—14
(3.0 V) 51 mA f = 10 MHz
Sleep mode — 11
(3.0 V) 37 mA f = 10 MHz
Module
standby mode — 6.5
(3.0 V) 26 mA f = 10 MHz
Standby mode — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
Analog power
supply current During A/D
conversion AICC — 0.2 0.5 mA AVCC = 3.0 V
During A/D
and D/A
conversion
— 0.2 0.5 mA AVCC = 3.0 V
Idle — 0.01 5.0 µA DASTE = 0
Reference
current During A/D
conversion AICC — 0.3 0.5 mA VREF = 3.0 V
During A/D
and D/A
conversion
— 1.2 2.0 mA VREF = 3.0 V
Idle — 0.01 5.0 µA DASTE = 0
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter
is not in use.
Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS,
respectively.
2. Given current consumption values are when all the output pins are made to unloaded
state and, furthermore, when the on-chip pull-up MOS is turned off under conditions
that VIH min = VCC – 0.5 V and VIL max = 0.5 V.
Also, the aforesaid current consumption values are when VIH min = VCC × 0.9 and VIL
max = 0.3 V under the condition of VRAM ≤ VCC < 2.7 V.
457
3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × VCC × f
ICC max. (when using the sleeve) = 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC × f
ICC max. (when the sleeve + module are standing by)
= 1.0 (mA) + 0.45 (mA/(MHz × V)) × VCC × f
Also, the typ. values for current dissipation are reference values.
458
Table 19.2 DC Characteristics (3)
Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 V to AVCC*1,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
Schmitt trigger
input voltages Port A,
P80 to P82
VT–
VT+
VT+ – VT–
VCC × 0.2
—
VCC × 0.07
—
—
—
—
VCC × 0.7
—
V
V
V
Input high
voltage RES, STBY,
NMI, MD2 to
MD0
VIH VCC × 0.9 — VCC + 0.3 V
EXTAL VCC × 0.7 — VCC + 0.3 V
Port 7 VCC × 0.7 — AVCC + 0.3 V
Ports 4 to 6
P83, P84, P90
to P95, port B
VCC × 0.7 — VCC + 0.3 V
Input low
voltage RES, STBY,
MD2 to MD0
VIL –0.3 — VCC × 0.1 V
NMI, EXTAL,
ports 4 to 7
P83, P84, P90 to
P95, port B
–0.3 — VCC × 0.2
0.8 V
VVCC < 4.0 V
VCC = 4.0 to
5.5 V
Output high
voltage All output pins
(except RESO)VOH VCC – 0.5 — — V IOH = –200 µA
VCC – 1.0 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)VOL — — 0.4 V IOL = 1.6 mA
A0 to A19 — — 1.0 V IOL = 5 mA
(VCC < 4.0 V)
IOL = 10 mA
(VCC = 4.0 to
5.5 V)
RESO — — 0.4 V IOL = 1.6 mA
Input leakage
current STBY, RES,
NMI, MD2 to
MD0
|Iin| — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
Port 7 — — 1.0 µA Vin = 0.5 V to
AVCC – 0.5 V
459
Item Symbol Min Typ Max Unit Test Conditions
Three-state
leakage
current
Ports 4 to 6,
A0 to A19,
Ports 8 to B
|ITSI| — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
RESO — — 10.0 µA Vin = 0 V
Input pull-up
MOS current Ports 4 and 5 –Ip10 — 300 µA Vin = 0 V
Input
capacitance NMI
All input pins
except NMI
Cin —
——
—50
15 pF
pF Vin = 0 V
f = fmin
Ta = 25°C
Current
dissipation*2Normal
operation ICC*3—21
(3.5 V) 66 mA f = 13 MHz
Sleep mode — 16
(3.5 V) 48 mA f = 13 MHz
Module
standby mode —9
(3.5 V) 34 mA f = 13 MHz
Standby mode — 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
Analog power
supply current During A/D
conversion AICC — 0.2 0.5 mA AVCC = 3.0 V
During A/D
and D/A
conversion
— 0.2 0.5 mA AVCC = 3.0 V
Idle — 0.01 5.0 µA DASTE = 0
Reference
current During A/D
conversion AICC — 0.3 0.5 mA VREF = 3.0 V
During A/D
and D/A
conversion
— 1.2 2.0 mA VREF = 3.0 V
Idle — 0.01 5.0 µA DASTE = 0
RAM standby voltage VRAM 2.0 — — V
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter
is not in use.
Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS,
respectively.
2. Given current consumption values are when all the output pins are made to unloaded
state and, furthermore, when the on-chip pull-up MOS is turned off under conditions
that VIH min = VCC – 0.5 V and VIL max = 0.5 V.
Also, the aforesaid current consumption values are when VIH min = VCC × 0.9 and VIL
max = 0.3 V under the condition of VRAM ≤ VCC < 3.0 V.
460
3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × VCC × f
ICC max. (when using the sleeve) = 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC x f
ICC max. (when the sleeve + module are standing by)
= 1.0 (mA) + 0.45 (mA/(MHz × V)) × VCC × f
Also, the typ. values for current dissipation are reference values.
461
Table 19.3 Permissible Output Currents
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) A19 to A0
Other output pins IOL —
——
—10
2.0 mA
mA
Permissible output
low current (total) Total of 20 pins in
A19 to A0
ΣIOL ——80mA
Total of all output pins,
including the above — — 120 mA
Permissible output
high current (per pin) All output pins |–IOH| — — 2.0 mA
Permissible output
high current (total) Total of all output pins |–ΣIOH| ——40mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 19.3.
2. When directly driving a darlington pair or LED, always insert a current-limiting resistor in
the output line, as shown in figure 19.1.
H8/3008
Port 2 kΩ
Darlington pair
Figure 19.1 Darlington Pair Drive Circuit (Example)
462
19.3 AC Characteristics
Clock timing parameters are listed in table 19.4, control signal timing parameters in table 19.5,
and bus timing parameters in table 19.6. Timing parameters of the on-chip supporting modules are
listed in table 19.7.
Table 19.4 Clock Timing
Condition: Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V
Condition
ABC
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
Clock cycle time
Clock pulse low
width
tcyc
tCL
100
30 1000
—76.9
18 1000
—50
15 1000
—ns
ns Figure 19.3
to
figure 19.15
Clock pulse high
width tCH 30 —18 —15 —ns
Clock rise time tCr —20 —15 —10 ns
Clock fall time tCf —20 —15 —10 ns
Clock oscillator
settling time at
reset
tOSC1 20 —20 —20 —ms Figure 19.3
Clock oscillator
settling time in
software standby
tOSC2 7—7—7—ms Figure 18.1
463
Table 19.5 Control Signal Timing
Condition: Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V
Condition
ABCTest
Item Symbol Min Max Min Max Min Max Unit Conditions
RES setup time tRESS 200 —200 —150 —ns Figure 19.4
RES pulse width tRESW 10 —10 —10 —tcyc
Mode programming
setup time tMDS 200 —200 —200 —ns
RESO output delay
time tRESD —100 —100 —50 ns Figure 19.5
RESO output pulse
width tRESOW 132 —132 —132 —tcyc
NMI, IRQ setup time tNMIS 200 —200 —150 —ns Figure 19.6
NMI, IRQ hold time tNMIH 10 —10 —10 —ns
NMI, IRQ pulse width
(in recovery from
software standby
mode)
tNMIW 200 —200 —200 —ns
464
Table 19.6 Bus Timing
Condition: Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V
Condition
ABC
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
Address delay time
Address hold time
Read strobe delay
time
tAD
tAH
tRSD
—
0.5 tcyc
– 45
—
50
—
60
—
0.5 tcyc
– 35
—
40
—
50
—
0.5 tcyc
– 20
—
25
—
25
ns
ns
ns
Figure 19.7,
figure 19.8
Address strobe
delay time tASD —60 —50 —25 ns
Write strobe delay
time tWSD —60 —50 —25 ns
Strobe delay time tSD —60 —50 —25 ns
Write strobe pulse
width 1 tWSW1 1.0 tcyc
– 50 —1.0 tcyc
– 40 —1.0 tcyc
– 25 —ns
Write strobe pulse
width 2 tWSW2 1.5 tcyc
– 50 —1.5 tcyc
– 40 —1.5 tcyc
– 25 —ns
Address setup
time 1 tAS1 0.5 tcyc
– 45 —0.5 tcyc
– 29 —0.5 tcyc
– 20 —ns
Address setup
time 2 tAS2 1.0 tcyc
– 45 —1.0 tcyc
– 35 —1.0 tcyc
– 20 —ns
Read data setup
time tRDS 50 —40 —25 —ns
Read data hold
time tRDH 0—0—0—ns
465
Condition
ABC
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
Write data delay
time
Write data setup
time 1
Write data setup
time 2
tWDD
tWDS1
tWDS2
—
1.0 tcyc
– 50
2.0 tcyc
– 50
60
—
—
—
1.0 tcyc
– 40
2.0 tcyc
– 40
50
—
—
—
1.0 tcyc
– 30
2.0 tcyc
– 30
35
—
—
ns
ns
ns
Figure 19.9,
figure 19.10
Write data hold
time tWDH 0.5 tcyc
– 30 —0.5 tcyc
– 25 —0.5 tcyc
– 15 —ns
Read data access
time 1 tACC1 —2.0 tcyc
– 100 —2.0 tcyc
– 80 —2.0 tcyc
– 45 ns
Read data access
time 2 tACC2 —3.0 tcyc
– 100 —3.0 tcyc
– 80 —3.0 tcyc
– 45 ns
Read data access
time 3 tACC3 —1.5 tcyc
– 100 —1.5 tcyc
– 80 —1.5 tcyc
– 45 ns
Read data access
time 4 tACC4 —2.5 tcyc
– 100 —2.5 tcyc
– 80 —2.5 tcyc
– 45 ns
Precharge time 1 tPCH1 1.0 tcyc
– 40 —1.0 tcyc
– 30 —1.0 tcyc
– 20 —ns
Precharge time 2 tPCH2 0.5 tcyc
– 40 —0.5 tcyc
– 30 —0.5 tcyc
– 20 —ns
Wait setup time tWTS 40 —40 —25 —ns Figure 19.9
Wait hold time tWTH 5—5—5—ns
Bus request setup
time tBRQS 40 —40 —25 —ns Figure 19.10
Bus acknowledge
delay time 1 tBACD1 —60 —50 —30 ns
Bus acknowledge
delay time 2 tBACD2 —60 —50 —30 ns
Bus-floating time tBZD —60 —50 —30 ns
Note: In order to secure the address hold time relative to the rise of the RD strobe, address
update mode 2 should be used. For details see section 6.3.5, Address Output Method.
466
Table 19.7 Timing of On-Chip Supporting Modules
Condition: Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V
Condition
ABC Test
Module Item Symbol Min Max Min Max Min Max Unit Conditions
Ports
and
TPC
Output data
delay time
Input data setup
time
tPWD
tPRS
—
50
100
—
—
50
100
—
—
50
50
—
ns
ns
Figure 19.11
Input data hold
time tPRH 50 —50 —50 —ns
16-bit
timer Timer output
delay time tTOCD —100 —100 —50 ns Figure 19.12
Timer input
setup time tTICS 50 —50 —50 —ns
Timer clock
input setup time tTCKS 50 —50 —50 —ns Figure 19.13
Timer
clock
pulse
width
Single
edge
Both
edges
tTCKWH
tTCKWL
1.5
2.5
—
—
1.5
2.5
—
—
1.5
2.5
—
—
tcyc
tcyc
8-bit
timer Timer output
delay time tTOCD —100 —100 —50 ns Figure 19.12
Timer input
setup time tTICS 50 —50 —50 —ns
Timer clock
input setup time tTCKS 50 —50 —50 —ns Figure 19.13
Timer
clock
pulse
width
Single
edge
Both
edges
tTCKWH
tTCKWL
1.5
2.5
—
—
1.5
2.5
—
—
1.5
2.5
—
—
tcyc
tcyc
467
Condition
ABC Test
Module Item Symbol Min Max Min Max Min Max Unit Conditions
SCI Input
clock Asyn-
chronous tScyc 4—4—4—tcyc Figure 19.14
cycle Syn-
chronous 6—6—6—tcyc
Input clock rise
time tSCKr 1.5 —1.5 —1.5 —tcyc
Input clock fall
time tSCKf 1.5 —1.5 —1.5 —tcyc
Input clock
pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc
Transmit data
delay time tTXD —100 —100 —100 ns Figure 19.15
Receive data
setup time
(synchronous)
tRXS 100 —100 —100 —ns
Receive
data hold Clock
input tRXH 100 —100 —100 —ns
time (syn-
chronous) Clock
output 0—0—0—ns
CR
H
R
L
Chip output pin
C = 90 pF: ports 4, 6, 8, A
19
to A
0
, D
15
to D
8
C = 30 pF: ports 9, A, B, RESO
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
R = 2.4 k
R = 12 k
L
H
Ω
Ω
Figure 19.2 Output Load Circuit
468
19.4 A/D Conversion Characteristics
Table 19.8 lists the A/D conversion characteristics.
Table 19.8 A/D Conversion Characteristics
Condition: Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
fmax = 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
fmax = 13 MHz
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
fmax = 25 MHz
Condition
ABC
Item Min Typ Max Min Typ Max Min Typ Max Unit
Conver-
sion time:
134 states
Resolution
Conversion time (single
mode)
10
—10
—10
134 10
—10
—10
134 10
—10
—10
134 bits
tcyc
Analog input capacitance ——20 ——20 ——20 pF
Permissible
signal-source
impedance
φ ≤ 13 MHz
φ > 13 MHz
4.0 V ≤ AVCC
≤ 5.5 V
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
10
5
—
kΩ
kΩ
kΩ
2.7 V ≤ AVCC
< 4.0 V ——5——5——— kΩ
Nonlinearity error ——±7.5 ——±7.5 ——±3.5 LSB
Offset error ——±7.5 ——±7.5 ——±3.5 LSB
Full-scale error ——±7.5 ——±7.5 ——±3.5 LSB
Quantization error ——±0.5 ——±0.5 ——±0.5 LSB
Absolute accuracy ——±8.0 ——±8.0 ——±4.0 LSB
469
Condition
ABC
Item Min Typ Max Min Typ Max Min Typ Max Unit
Conver-
sion time:
70 states
Resolution
Conversion time (single
mode)
10
—10
—10
70 10
—10
—10
70 10
—10
—10
70 bits
tcyc
Analog input capacitance ——20 ——20 ——20 pF
Permissible
signal-source
impedance
φ ≤ 13 MHz
φ > 13 MHz
4.0 V ≤ AVCC
≤ 5.5 V
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
5
3
—
kΩ
kΩ
kΩ
2.7 V ≤ AVCC
< 4.0 V ——3——3——— kΩ
Nonlinearity error ——±15.5 ——±15.5 ——±7.5 LSB
Offset error ——±15.5 ——±15.5 ——±7.5 LSB
Full-scale error ——±15.5 ——±15.5 ——±7.5 LSB
Quantization error ——±0.5 ——±0.5 ——±0.5 LSB
Absolute accuracy ——±16 ——±16 ——±8.0 LSB
470
19.5 D/A Conversion Characteristics
Table 19.9 lists the D/A conversion characteristics.
Table 19.9 D/A Conversion Characteristics
Condition: Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
fmax = 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
fmax = 13 MHz
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
fmax = 25 MHz
Condition
ABC
Test
Item Min Typ Max Min Typ Max Min Typ Max Unit Conditions
Resolution 8 8 8 8 8 8 8 8 8 bits
Conversion time
(setting time) ——10 ——10 ——10 µs 20 pF
capacitive
load
Absolute accuracy —±2.0 ±3.0 —±2.0 ±3.0 —±1.5 ±2.0 LSB 2 MΩ
resistive load
——±2.0 ——±2.0 ——±1.5 LSB 4 MΩ
resistive load
471
19.6 Operational Timing
This section shows timing diagrams.
19.6.1 Clock Timing
Clock timing is shown as follows:
• Oscillator settling timing
Figure 19.3 shows the oscillator settling timing.
φ
VCC
STBY
RES
tOSC1 tOSC1
Figure 19.3 Oscillator Settling Timing
472
19.6.2 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 19.4 shows the reset input timing.
• Reset output timing
Figure 19.5 shows the reset output timing.
• Interrupt input timing
Figure 19.6 shows the interrupt input timing for NMI and IRQ5 to IRQ0.
φtRESS tRESS
tRESW
tMDS
RES
FWE
MD2 to MD0
Figure 19.4 Reset Input Timing
φ
RESO
tRESD
tRESOW
tRESD
Figure 19.5 Reset Output Timing
473
φ
N
MI
I
RQ
I
RQ
E
L
tNMIS tNMIH
tNMIS tNMIH
tNMIS
tNMIW
NMI
IRQj
IRQ : Edge-sensitive IRQ
: Level-sensitive IRQ (i = 0 to 5)
E
L
i
i
IRQ
(j = 0 to 5)
Figure 19.6 Interrupt Input Timing
474
19.6.3 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 19.7 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 19.8 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 19.9 shows the timing of the external three-state access cycle with one wait state
inserted.
• Bus-release mode timing
Figure 19.10 shows the bus-release mode timing.
475
T1T2
tCH
tAD
tCL
tCr
tCf
tASD tACC3
tAS1
tcyc
tcyc
tSD
tRDS
tAH
tPCH1
tPCH2
tRDH*
tPCH1
tSD tAH
tASD tACC3
tAS1
tACC1
tASD
tAS1
tWSW1
tWDS1 tWDH
tWDD
φ
A23 to A0,
CSn
AS
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
tRSD
Figure 19.7 Basic Bus Cycle: Two-State Access
476
T1T2T3
tACC4
tACC4
tAS2
tWDS2
tWSW2
tWSD
tWDD
tACC2 tRDS
φ
A23 to A0,
CSn
AS
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
Figure 19.8 Basic Bus Cycle: Three-State Access
477
T1T2TWT3
tWTS tWTS tWTH
φ
AS
RD (read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
WAIT
tWTH
A23 to A0,
CSn
Figure 19.9 Basic Bus Cycle: Three-State Access with One Wait State
BREQ
BACK
φ
A23 to A0,
AS, RD,
HWR, LWR
tBRQS tBRQS
tBACD1
tBZD
tBACD2
tBZD
Figure 19.10 Bus-Release Mode Timing
478
19.6.4 TPC and I/O Port Timing
Figure 19.11 shows the TPC and I/O port input/output timing.
T1T2T3
φ
Port 4 to
B (read)
Port 4, 6,
8 to B
(write)
tPRS tPRH
tPWD
Figure 19.11 TPC and I/O Port Input/Output Timing
19.6.5 Timer Input/Output Timing
16-bit timer and 8-bit timer timing is shown below.
• Timer input/output timing
Figure 19.12 shows the timer input/output timing.
• Timer external clock input timing
Figure 19.13 shows the timer external clock input timing.
φ
Output
compare*1
Input
capture*2
tTOCD
tTICS
Notes: 1. TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMO0, TMO2, TMIO1, TMIO3
2. TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMIO1, TMIO3
Figure 19.12 Timer Input/Output Timing
479
φtTCKS
tTCKS
tTCKWH
tTCKWL
TCLKA to
TCLKD
Figure 19.13 Timer External Clock Input Timing
19.6.6 SCI Input/Output Timing
SCI timing is shown as follows:
• SCI input clock timing
Figure 19.14 shows the SCI input clock timing.
• SCI input/output timing (synchronous mode)
Figure 19.15 shows the SCI input/output timing in synchronous mode.
SCK0, SCK1
tSCKW
tScyc
tSCKr tSCKf
Figure 19.14 SCI Input Clock Timing
tScyc
tTXD
tRXS tRXH
SCK0,
SCK1
TxD0, TxD1
(transmit
data)
RxD0, RxD1
(receive
data)
Figure 19.15 SCI Input/Output Timing in Synchronous Mode
480
481
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Symbol Description
Rd General destination register
Rs General source register
Rn General register
ERd General destination register (address register or 32-bit register)
ERs General source register (address register or 32-bit register)
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
PC Program counter
SP Stack pointer
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
disp Displacement
→Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+ Addition of the operands on both sides
– Subtraction of the operand on the right from the operand on the left
×Multiplication of the operands on both sides
÷ Division of the operand on the left by the operand on the right
∧Logical AND of the operands on both sides
∨Logical OR of the operands on both sides
⊕Exclusive logical OR of the operands on both sides
¬ NOT (logical complement)
( ), < > Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
482
Condition Code Notation
Symbol Description
Changed according to execution result
* Undetermined (no guaranteed value)
0 Cleared to 0
1 Set to 1
— Not affected by execution of the instruction
∆Varies depending on conditions, described in notes
483
Table A.1 Instruction Set
1. Data transfer instructions
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MO V.B @(d:16, ERs),
Rd
MO V.B @(d:24, ERs),
Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
MOV.B Rs, @(d:16,
ERd)
MOV.B Rs, @(d:24,
ERd)
MOV.B Rs, @–ERd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MO V.W @(d:16, ERs),
Rd
MO V.W @(d:24, ERs),
Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
W
W
2
2
2
4
8
2
2
4
6
2
4
8
2
2
4
6
4
2
2
4
8
2
4
#xx:8 → Rd8
Rs8 → Rd8
@ERs → Rd8
@(d:16, ERs) → Rd8
@(d:24, ERs) → Rd8
@ERs → Rd8
ERs32+1 → ERs32
@aa:8 → Rd8
@aa:16 → Rd8
@aa:24 → Rd8
Rs8 → @ERd
Rs8 → @(d:16, ERd)
Rs8 → @(d:24, ERd)
ERd32–1 → ERd32
Rs8 → @ERd
Rs8 → @aa:8
Rs8 → @aa:16
Rs8 → @aa:24
#xx:16 → Rd16
Rs16 → Rd16
@ERs → Rd16
@(d:16, ERs) → Rd16
@(d:24, ERs) → Rd16
@ERs → Rd16
ERs32+2 → @ERd32
@aa:16 → Rd16
2
2
4
6
10
6
4
6
8
4
6
10
6
4
6
8
4
2
4
6
10
6
6
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
484
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16,
ERd)
MOV.W Rs, @(d:24,
ERd)
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, Rd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MO V.L @(d:16, ERs),
ERd
MO V.L @(d:24, ERs),
ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
MOV.L ERs, @(d:16,
ERd)
MOV.L ERs, @(d:24,
ERd)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
POP.W Rn
POP.L ERn
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W
L
6
2
4
8
2
4
6
6
2
4
6
10
4
6
8
4
6
10
4
6
8
2
4
@aa:24 → Rd16
Rs16 → @ERd
Rs16 → @(d:16, ERd)
Rs16 → @(d:24, ERd)
ERd32–2 → ERd32
Rs16 → @ERd
Rs16 → @aa:16
Rs16 → @aa:24
#xx:32 → Rd32
ERs32 → ERd32
@ERs → ERd32
@(d:16, ERs) → ERd32
@(d:24, ERs) → ERd32
@ERs → ERd32
ERs32+4 → ERs32
@aa:16 → ERd32
@aa:24 → ERd32
ERs32 → @ERd
ERs32 → @(d:16, ERd)
ERs32 → @(d:24, ERd)
ERd32–4 → ERd32
ERs32 → @ERd
ERs32 → @aa:16
ERs32 → @aa:24
@SP → Rn16
SP+2 → SP
@SP → ERn32
SP+4 → SP
8
4
6
10
6
6
8
6
2
8
10
14
10
10
12
8
10
14
10
10
12
6
10
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
485
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
PUSH.W Rn
PUSH.L ERn
MOVFPE @aa:16,
Rd
MOVTPE Rs,
@aa:16
W
L
B
B
2
4
4
4
SP–2 → SP
Rn16 → @SP
SP–4 → SP
ERn32 → @SP
Cannot be used in the
H8/3008
Cannot be used in the
H8/3008
6
10
—— 0—
—— 0—
Cannot be used in the
H8/3008
Cannot be used in the
H8/3008
↔
↔
↔
↔
2. Arithmetic instructions
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS.L #1, ERd
ADDS.L #2, ERd
ADDS.L #4, ERd
INC.B Rd
INC.W #1, Rd
INC.W #2, Rd
B
B
W
W
L
L
B
B
L
L
L
B
W
W
2
2
4
2
6
2
2
2
2
2
2
2
2
2
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
Rd16+#xx:16 → Rd16
Rd16+Rs16 → Rd16
ERd32+#xx:32 →
ERd32
ERd32+ERs32 →
ERd32
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
ERd32+1 → ERd32
ERd32+2 → ERd32
ERd32+4 → ERd32
Rd8+1 → Rd8
Rd16+1 → Rd16
Rd16+2 → Rd16
2
2
4
2
6
2
2
2
2
2
2
2
2
2
—
—
—(1)
—(1)
—(2)
—(2)
—(3)
—(3)
——————
——————
——————
—— —
—— —
—— —
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
486
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
INC.L #1, ERd
INC.L #2, ERd
DAA Rd
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.L #1, ERd
SUBS.L #2, ERd
SUBS.L #4, ERd
DEC.B Rd
DEC.W #1, Rd
DEC.W #2, Rd
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
L
L
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
B
W
B
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
2
ERd32+1 → ERd32
ERd32+2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8–Rs8 → Rd8
Rd16–#xx:16 → Rd16
Rd16–Rs16 → Rd16
ERd32–#xx:32
→ ERd32
ERd32–ERs32
→ ERd32
Rd8–#xx:8–C → Rd8
Rd8–Rs8–C → Rd8
ERd32–1 → ERd32
ERd32–2 → ERd32
ERd32–4 → ERd32
Rd8–1 → Rd8
Rd16–1 → Rd16
Rd16–2 → Rd16
ERd32–1 → ERd32
ERd32–2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8 × Rs8 → Rd16
(unsigned multiplication)
Rd16 × Rs16 → ERd32
(unsigned multiplication)
Rd8 × Rs8 → Rd16
(signed multiplication)
Rd16 × Rs16 → ERd32
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder, RdL:
quotient)
(unsigned division)
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
14
22
16
24
14
—— —
—— —
—**—
—
—(1)
—(1)
—(2)
—(2)
—(3)
—(3)
——————
——————
——————
—— —
—— —
—— —
—— —
—— —
—**—
——————
— —————
—— ——
—— ——
——(6) (7) ——
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
487
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
W
B
W
B
B
W
W
L
L
B
W
L
W
L
W
L
2
4
4
2
2
4
2
6
2
2
2
2
2
2
2
2
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
Rd8–#xx:8
Rd8–Rs8
Rd16–#xx:16
Rd16–Rs16
ERd32–#xx:32
ERd32–ERs32
0–Rd8 → Rd8
0–Rd16 → Rd16
0–ERd32 → ERd32
0 → (<bits 15 to 8>
of Rd16)
0 → (<bits 31 to 16>
of ERd32)
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
22
16
24
2
2
4
2
6
2
2
2
2
2
2
2
2
——(6) (7) ——
——(8) (7) ——
——(8) (7) ——
—
—
—(1)
—(1)
—(2)
—(2)
—
—
—
—— 00—
—— 00—
—— 0—
—— 0—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
488
3. Logic instructions
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
NOT.B Rd
NOT.W Rd
NOT.L ERd
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
W
L
2
2
4
2
6
4
2
2
4
2
6
4
2
2
4
2
6
4
2
2
2
Rd8∧#xx:8 → Rd8
Rd8∧Rs8 → Rd8
Rd16∧#xx:16 → Rd16
Rd16∧Rs16 → Rd16
ERd32∧#xx:32 → ERd32
ERd32∧ERs32 → ERd32
Rd8∨#xx:8 → Rd8
Rd8∨Rs8 → Rd8
Rd16∨#xx:16 → Rd16
Rd16∨Rs16 → Rd16
ERd32∨#xx:32 → ERd32
ERd32∨ERs32 → ERd32
Rd8⊕#xx:8 → Rd8
Rd8⊕Rs8 → Rd8
Rd16⊕#xx:16 → Rd16
Rd16⊕Rs16 → Rd16
ERd32⊕#xx:32 → ERd32
ERd32⊕ERs32 → ERd32
¬Rd8 → Rd8
¬Rd16 → Rd16
¬Rd32 → Rd32
2
2
4
2
6
4
2
2
4
2
6
4
2
2
4
2
6
4
2
2
2
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
—— 0—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
489
4. Shift instructions
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
——
——
——
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
—— 0
C
MSB LSB
C
MSB LSB
C
MSB LSB
C
MSB LSB
MSB LSB
0C
MSB LSB
0C
C
MSB LSB
0C
MSB LSB
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
490
5. Bit manipulation instructions
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
BLD #xx:3, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
(#xx:3 of Rd8) ← 1
(#xx:3 of @ERd) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
(Rn8 of @ERd) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @ERd) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
(Rn8 of @ERd) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ←
¬(#xx:3 of Rd8)
(#xx:3 of @ERd) ←
¬(#xx:3 of @ERd)
(#xx:3 of @aa:8) ←
¬(#xx:3 of @aa:8)
(Rn8 of Rd8) ←
¬(Rn8 of Rd8)
(Rn8 of @ERd) ←
¬(Rn8 of @ERd)
(Rn8 of @aa:8) ←
¬(Rn8 of @aa:8)
¬(#xx:3 of Rd8) → Z
¬(#xx:3 of @ERd) → Z
¬(#xx:3 of @aa:8) → Z
¬(Rn8 of @Rd8) → Z
¬(Rn8 of @ERd) → Z
¬(Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
6
6
2
6
6
2
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——— ——
——— ——
——— ——
——— ——
——— ——
——— ——
—————
↔↔↔↔↔↔
↔
491
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
BIOR #xx:3, @ERd
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
(#xx:3 of @ERd) → C
(#xx:3 of @aa:8) → C
¬
(#xx:3 of Rd8) → C
¬
(#xx:3 of @ERd) → C
¬
(#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
C → (#xx:3 of @ERd24)
C → (#xx:3 of @aa:8)
¬
C → (#xx:3 of Rd8)
¬
C → (#xx:3 of @ERd24)
¬
C → (#xx:3 of @aa:8)
C∧(#xx:3 of Rd8) → C
C∧(#xx:3 of @ERd24) → C
C∧(#xx:3 of @aa:8) → C
C∧
¬
(#xx:3 of Rd8) → C
C∧
¬
(#xx:3 of @ERd24) → C
C∧
¬
(#xx:3 of @aa:8) → C
C∨(#xx:3 of Rd8) → C
C∨(#xx:3 of @ERd24) → C
C∨(#xx:3 of @aa:8) → C
C∨
¬
(#xx:3 of Rd8) → C
C∨
¬
(#xx:3 of @ERd24) → C
C∨
¬
(#xx:3 of @aa:8) → C
C⊕(#xx:3 of Rd8) → C
C⊕(#xx:3 of @ERd24) → C
C⊕(#xx:3 of @aa:8) → C
C⊕
¬
(#xx:3 of Rd8) → C
C⊕
¬
(#xx:3 of @ERd24) → C
C⊕
¬
(#xx:3 of @aa:8) → C
6
6
2
6
6
2
8
8
2
8
8
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
—————
—————
—————
—————
—————
——————
——————
——————
——————
——————
——————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
—————
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
492
6. Branching instructions
Mnemonic Operation Branch
Condition
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
If condition
is true then
PC ←
PC+d else
next;
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
Always
Never
C ∨ Z = 0
C ∨ Z = 1
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
N⊕V = 0
N⊕V = 1
Z ∨ (N⊕V)
= 0
493
Mnemonic OperationOperation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
BLE d:8
BLE d:16
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
—
—
—
—
—
—
—
—
—
—
—
2
4
2
4
2
2
4
2
4
2
2
PC ← ERn
PC ← aa:24
PC ← @aa:8
PC → @–SP
PC ← PC+d:8
PC → @–SP
PC ← PC+d:16
PC → @–SP
PC ← @ERn
PC → @–SP
PC ← @aa:24
PC → @–SP
PC ← @aa:8
PC ← @SP+
4
6
4
6
8
6
8
6
8
8
8
10
8
10
8
10
12
10
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
Branch
Condition
If condition
is true then
PC ← PC+d
else next;
Z ∨ (N⊕V) = 1
494
7. System control instructions
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
TRAPA #x:2
RTE
SLEEP
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs),
CCR
LDC @(d:24, ERs),
CCR
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16,
ERd)
STC CCR, @(d:24,
ERd)
STC CCR, @–ERd
STC CCR, @aa:16
STC CCR, @aa:24
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
—
—
—
B
B
W
W
W
W
W
W
B
W
W
W
W
W
W
B
B
B
—
2
2
2
4
6
10
4
6
8
2
4
6
10
4
6
8
2
2
2
2
PC → @–SP
CCR → @–SP
<vector> → PC
CCR ← @SP+
PC ← @SP+
Transition to powerdown
state
#xx:8 → CCR
Rs8 → CCR
@ERs → CCR
@(d:16, ERs) → CCR
@(d:24, ERs) → CCR
@ERs → CCR
ERs32+2 → ERs32
@aa:16 → CCR
@aa:24 → CCR
CCR → Rd8
CCR → @ERd
CCR → @(d:16, ERd)
CCR → @(d:24, ERd)
ERd32–2 → ERd32
CCR → @ERd
CCR → @aa:16
CCR → @aa:24
CCR∧#xx:8 → CCR
CCR∨#xx:8 → CCR
CCR⊕#xx:8 → CCR
PC ← PC+2
10
2
2
2
6
8
12
8
8
10
2
6
8
12
8
8
10
2
2
2
2
1—————
——————
——————
——————
——————
——————
——————
——————
——————
——————
14 16
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
495
8. Block transfer instructions
Mnemonic Operation
Condition Code
Operand Size
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
Addressing Mode and
Instruction Length (bytes)
Normal
Advanced
No. of
States*1
IHNZVC
EEPMOV. B
EEPMO V. W
—
—
4
4
if R4L ≠ 0
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until R4L=0
else next;
if R4 ≠ 0
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until R4L=0
else next;
——————
——————
8+4n*2
8+4n*2
Notes: 1. The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory. For other cases see section
A.3, Number of States Required for Execution.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous
value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
496
A.2 Operation Code Maps
Table A.2 Operation Code Map (1)
AH AL 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA
MULXU
BSET
BRN
DIVXU
BNOT
STC
BHI
MULXU
BCLR
LDC
BLS
DIVXU
BTST
ORC
OR.B
BCC
RTS
OR
XORC
XOR.B
BCS
BSR
XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND.B
BNE
RTE
AND
LDC
BNQ
TRAPA
BLD
BILD
BST
BIST
BVC
MOV
BPL
JMP
BMI
ADDX
SUBX
BGT
JSR
BLE
MOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
Instruction code:
Table A.2
(2) Table A.2
(2) Table A.2
(2) Table A.2
(2) Table A.2
(2)
BVS BLTBGE
BSR
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2) Table A.2
(2) Table A.2
(3)
1st byte 2nd byte
AH BHAL BL
ADD
SUB
MOV
CMP
MOV.B
EEPMOV
497
Table A.2 Operation Code Map (2)
AH ALBH 0123456789ABCDEF
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
79
7A
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
BHI
CMP
CMP
LDC/STC
BCC
OR
OR
BPL BGT
Instruction code:
BVS
SLEEP
BVC BGE
Table A.2
(3)
Table A.2
(3) Table A.2
(3)
BNE
AND
AND
INC
EXTU
DEC
BEQ
INC
EXTU
DEC
BCS
XOR
XOR
SHLL
SHLR
ROTXL
ROTXR
NOT
BLS
SUB
SUB
BRN
ADD
ADD
INC
EXTS
DEC
BLT
INC
EXTS
DEC
BLE
SHAL
SHAR
ROTL
ROTR
NEG
BMI
1st byte 2nd byte
AH BHAL BL
SUBS
ADDS
ADD
MOV
SUB
CMP
SHLL
SHLR
ROTXL
ROTXR
NOT
SHAL
SHAR
ROTL
ROTR
NEG
498
Table A.2 Operation Code Map (3)
AH
ALBH
BLCH
CL
0123456789ABCDEF
01406
01C05
01D05
01F06
7Cr06
7Cr07
7Dr06
7Dr07
7Eaa6
7Eaa7
7Faa6
7Faa7
MULXS
BSET
BSET
BSET
BSET
DIVIXS
BNOT
BNOT
BNOT
BNOT
MULXS
BCLR
BCLR
BCLR
BCLR
DIVXS
BTST
BTST
BTST
BTST
OR XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
AND
BLD
BILD
BST
BIST
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Instruction code:
*
*
*
*
*
*
*
*
1
1
1
1
2
2
2
2
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
Notes: 1.
2. r is the register designation field.
aa is the absolute address field.
1st byte 2nd byte
AH BHAL BL 3rd byte
CH DHCL DL
4th byte
LDCSTC LDC LDC LDC
STC STC STC
499
A.3 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × SI + J × SJ + K × SK + L × SL
+ M × SM + N × SN
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
From table A.4, I = L = 2 and J = K = M = N = 0
From table A.3, SI = 4 and SL = 3
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A.4, I = J = K = 2 and L = M = N = 0
From table A.3, SI = SJ = SK = 4
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
500
Table A.3 Number of States per Cycle
Access Conditions
On-Chip Sup- External Device
porting Module 8-Bit Bus 16-Bit Bus
Cycle On-Chip
Memory 8-Bit
Bus 16-Bit
Bus 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI26346 + 2m23 + m
Branch address read SJ
Stack operation SK
Byte data access SL3 2 3 + m
Word data access SM6 4 6 + 2m
Internal operation SN1
Legend
m: Number of wait states inserted into external device access
501
Table A.4 Number of Cycles per Instruction
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
1
1
2
1
3
1
ADDS ADDS #1/2/4, ERd 1
ADDX ADDX #xx:8, Rd
ADDX Rs, Rd 1
1
AND AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
1
1
2
1
3
2
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
1
2
21
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
502
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Bcc BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
BHI d:16
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BIAND BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
1
2
21
1
BILD BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
1
2
21
1
BIOR BIOR #xx:8, Rd
BIOR #xx:8, @ERd
BIOR #xx:8, @aa:8
1
2
21
1
BIST BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
1
2
22
2
BIXOR BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
1
2
21
1
BLD BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
1
2
21
1
503
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BNOT BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BOR BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
1
2
21
1
BSET BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BSR BSR d:8 Normal 2 1
Advanced 2 2
BSR d:16 Normal 2 1 2
Advanced 2 2 2
BST BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
1
2
22
2
BTST BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
1
2
21
1
CMP CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
1
1
2
1
3
1
DAA DAA Rd 1
DAS DAS Rd 1
504
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
DEC DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DIVXS DIVXS.B Rs, Rd
DIVXS.W Rs, ERd 2
212
20
DIVXU DIVXU.B Rs, Rd
DIVXU.W Rs, ERd 1
112
20
EEPMOV EEPMOV.B
EEPMOV.W 2
22n + 2*1
2n + 2*1
EXTS EXTS.W Rd
EXTS.L ERd 1
1
EXTU EXTU.W Rd
EXTU.L ERd 1
1
INC INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
1
JMP JMP @ERn 2
JMP @aa:24 2 2
JMP @@aa:8Normal 2 1 2
Advanced 2 2 2
JSR JSR @ERn Normal 2 1
Advanced 2 2
JSR @aa:24 Normal 2 1 2
Advanced 2 2 2
JSR @@aa:8 Normal 2 1 1
Advanced 2 2 2
LDC LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs), CCR
LDC @(d:24, ERs), CCR
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
1
1
2
3
5
2
3
4
1
1
1
1
1
1
2
505
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @–ERd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16, ERs), Rd
MOV.W @(d:24, ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16, ERd)
MOV.W Rs, @(d:24, ERd)
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
1
1
1
2
4
1
1
2
3
1
2
4
1
1
2
3
2
1
1
2
4
1
2
3
1
2
4
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
M OV.L @( d:16, ER s) , ER d
M OV.L @( d:24, ER s) , ER d
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
M OV.L ER s, @( d:16, ER d)
M OV.L ER s, @( d:24, ER d)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
3
1
2
3
5
2
3
4
2
3
5
2
3
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
506
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOVFPE MOVFPE @aa:16, Rd*221
MOVTPE MOVTPE Rs, @aa:16*221
MULXS MULXS.B Rs, Rd
MULXS.W Rs, ERd 2
212
20
MULXU MULXU.B Rs, Rd
MULXU.W Rs, ERd 1
112
20
NEG NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP NOP 1
NOT NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
1
1
2
1
3
2
ORC ORC #xx:8, CCR 1
POP POP.W Rn
POP.L ERn 1
21
22
2
PUSH PUSH.W Rn
PUSH.L ERn 1
21
22
2
ROTL ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
1
1
1
ROTR ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
1
1
1
ROTXL ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
1
1
1
ROTXR ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
1
1
1
RTE RTE 2 2 2
507
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
RTS RTS Normal 2 1 2
Advanced 2 2 2
SHAL SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
1
1
1
SHAR SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
1
1
1
SHLL SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
1
1
1
SHLR SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
1
1
1
SLEEP SLEEP 1
STC STC CCR, Rd
STC CCR, @ERd
ST C C CR , @( d:16, ER d)
ST C C CR , @( d:24, ER d)
STC CCR, @–ERd
STC CCR, @aa:16
STC CCR, @aa:24
1
2
3
5
2
3
4
1
1
1
1
1
1
2
SUB SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
1
2
1
3
1
SUBS SUBS #1/2/4, ERd 1
SUBX SUBX #xx:8, Rd
SUBX Rs, Rd 1
1
TRAPA TRAPA #x:2 Normal 2 1 2 4
Advanced 2 2 2 4
XOR XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
1
1
2
1
3
2
XORC XORC #xx:8, CCR 1
Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1
times each.
2. Not available in the H8/3008.
508
Appendix B Internal I/O Registers
B.1 Address List
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE000 — ————————
H'EE001 — ————————
H'EE002 — ————————
H'EE003 P4DDR 8 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4
H'EE004 — ————————
H'EE005 P6DDR 8 — P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6
H'EE006 — ————————
H'EE007 P8DDR 8 ———P8
4DDR P83DDR P82DDR P81DDR P80DDR Port 8
H'EE008 P9DDR 8 — — P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9
H'EE009 PADDR 8 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Port A
H'EE00A PBDDR 8 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B
H'EE00B — ————————
H'EE00C — ————————
H'EE00D — ————————
H'EE00E — ————————
H'EE00F — ————————
H'EE010 — ————————
H'EE011 MDCR 8 —————MDS2 MDS1 MDS0 System control
H'EE012 SYSCR 8 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME
H'EE013 BRCR 8 A23E A22E A21E A20E — — — BRLE Bus controller
H'EE014 ISCR 8 — — IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Interrupt
H'EE015 IER 8 — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E controller
H'EE016 ISR 8 — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
H'EE017 — ————————
H'EE018 IPRA 8 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
H'EE019 IPRB 8 IPRB7 IPRB6 — — IPRB3 IPRB2 — —
H'EE01A DASTCR 8 ———————DASTE D/A converter
H'EE01B DIVCR 8 ——————DIV1 DIV0 System control
H'EE01C MSTCRH 8 PSTOP —————MSTPH1 MSTPH0
H'EE01D MSTCRL 8 — — — MSTPL4 MSTPL3 MSTPL2 — MSTPL0
H'EE01E ADRCR 8 ———————ADRCTL Bus controller
H'EE01F CSCR 8 CS7E CS6E CS5E CS4E ————
509
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE020 ABWCR 8 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller
H'EE021 ASTCR 8 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
H'EE022 WCRH 8 W71 W70 W61 W60 W51 W50 W41 W40
H'EE023 WCRL 8 W31 W30 W21 W20 W11 W10 W01 W00
H'EE024 BCR 8 ICIS1 ICIS0 —*1—*1—*1—*1RDEA WAITE
H'EE025 — ————————
H'EE026 Reserved area (access prohibited)
H'EE027
H'EE028
H'EE029
H'EE02A
H'EE02B
H'EE02C
H'EE02D
H'EE02E
H'EE02F
H'EE030 Reserved area (access prohibited)
H'EE031
H'EE032
H'EE033
H'EE034
H'EE035
H'EE036
H'EE037
H'EE038
H'EE039
H'EE03A
H'EE03B
H'EE03C
H'EE03D
H'EE03E P4PCR 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Port 4
H'EE03F
510
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE040 Reserved area (access prohibited)
H'EE041
H'EE042
H'EE043
H'EE044
H'EE045
H'EE046
H'EE047
H'EE048
H'EE049
H'EE04A
H'EE04B
H'EE04C
H'EE04D
H'EE04E
H'EE04F
H'EE050 Reserved area (access prohibited)
H'EE051
H'EE052
H'EE053
H'EE054
H'EE055
H'EE056
H'EE057
H'EE058
H'EE059
H'EE05A
H'EE05B
H'EE05C
H'EE05D
H'EE05E
H'EE05F
511
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE060 Reserved area (access prohibited)
H'EE061
H'EE062
H'EE063
H'EE064
H'EE065
H'EE066
H'EE067
H'EE068
H'EE069
H'EE06A
H'EE06B
H'EE06C
H'EE06D
H'EE06E
H'EE06F
H'EE070 Reserved area (access prohibited)
H'EE071
H'EE072
H'EE073
H'EE074
H'EE075
H'EE076
H'EE077
H'EE078
H'EE079
H'EE07A
H'EE07B
H'EE07C
H'EE07D
H'EE07E
H'EE07F
512
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE080 Reserved area (access prohibited)
H'EE081
H'EE082
H'EE083
H'EE084
H'EE085
H'EE086
H'EE087
H'EE088
H'EE089
H'EE08A
H'EE08B
H'EE08C
H'EE08D
H'EE08E
H'EE08F
H'EE090 Reserved area (access prohibited)
H'EE091
H'EE092
H'EE093
H'EE094
H'EE095
H'EE096
H'EE097
H'EE098
H'EE099
H'EE09A
H'EE09B
H'EE09C
H'EE09D
H'EE09E
H'EE09F
513
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE0A0 Reserved area (access prohibited)
H'EE0A1
H'EE0A2
H'EE0A3
H'EE0A4
H'EE0A5
H'EE0A6
H'EE0A7
H'EE0A8
H'EE0A9
H'EE0AA
H'EE0AB
H'EE0AC
H'EE0AD
H'EE0AE
H'EE0AF
H'EE0B0 Reserved area (access prohibited)
H'EE0B1
H'EE0B2
H'EE0B3
H'EE0B4
H'EE0B5
H'EE0B6
H'EE0B7
H'EE0B8
H'EE0B9
H'EE0BA
H'EE0BB
H'EE0BC
H'EE0BD
H'EE0BE
H'EE0BF
514
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE0C0 Reserved area (access prohibited)
H'EE0C1
H'EE0C2
H'EE0C3
H'EE0C4
H'EE0C5
H'EE0C6
H'EE0C7
H'EE0C8
H'EE0C9
H'EE0CA
H'EE0CB
H'EE0CC
H'EE0CD
H'EE0CE
H'EE0CF
H'EE0D0 Reserved area (access prohibited)
H'EE0D1
H'EE0D2
H'EE0D3
H'EE0D4
H'EE0D5
H'EE0D6
H'EE0D7
H'EE0D8
H'EE0D9
H'EE0DA
H'EE0DB
H'EE0DC
H'EE0DD
H'EE0DE
H'EE0DF
515
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'EE0E0 Reserved area (access prohibited)
H'EE0E1
H'EE0E2
H'EE0E3
H'EE0E4
H'EE0E5
H'EE0E6
H'EE0E7
H'EE0E8
H'EE0E9
H'EE0EA
H'EE0EB
H'EE0EC
H'EE0ED
H'EE0EE
H'EE0EF
H'EE0F0 Reserved area (access prohibited)
H'EE0F1
H'EE0F2
H'EE0F3
H'EE0F4
H'EE0F5
H'EE0F6
H'EE0F7
H'EE0F8
H'EE0F9
H'EE0FA
H'EE0FB
H'EE0FC
H'EE0FD
H'EE0FE
H'EE0FF
516
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'FFF20 Reserved area (access prohibited)
H'FFF21
H'FFF22
H'FFF23
H'FFF24
H'FFF25
H'FFF26
H'FFF27
H'FFF28
H'FFF29
H'FFF2A
H'FFF2B
H'FFF2C
H'FFF2D
H'FFF2E
H'FFF2F
H'FFF30 Reserved area (access prohibited)
H'FFF31
H'FFF32
H'FFF33
H'FFF34
H'FFF35
H'FFF36
H'FFF37
H'FFF38
H'FFF39
H'FFF3A
H'FFF3B
H'FFF3C
H'FFF3D
H'FFF3E
H'FFF3F
517
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'FFF40 — ————————
H'FFF41 — ————————
H'FFF42 — ————————
H'FFF43 — ————————
H'FFF44 — ————————
H'FFF45 — ————————
H'FFF46 — ————————
H'FFF47 — ————————
H'FFF48 — ————————
H'FFF49 — ————————
H'FFF4A — ————————
H'FFF4B — ————————
H'FFF4C — ————————
H'FFF4D — ————————
H'FFF4E — ————————
H'FFF4F — ————————
H'FFF50 — ————————
H'FFF51 — ————————
H'FFF52 — ————————
H'FFF53 — ————————
H'FFF54 — ————————
H'FFF55 — ————————
H'FFF56 — ————————
H'FFF57 — ————————
H'FFF58 — ————————
H'FFF59 — ————————
H'FFF5A — ————————
H'FFF5B — ————————
H'FFF5C — ————————
H'FFF5D — ————————
H'FFF5E — ————————
H'FFF5F — ————————
518
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'FFF60 TSTR 8 —————STR2 STR1 STR0 16-bit timer,
H'FFF61 TSNC 8 —————SYNC2 SYNC1 SYNC0 (all channels)
H'FFF62 TMDR 8 — MDF FDIR — — PWM2 PWM1 PWM0
H'FFF63 TOLR 8 — — TOB2 TOA2 TOB1 TOA1 TOB0 TOA0
H'FFF64 TISRA 8 — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0
H'FFF65 TISRB 8 — IMIEB2 IMIEB1 IMIEB0 — IMFB2 IMFB1 IMFB0
H'FFF66 TISRC 8 — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0
H'FFF67 — ————————
H'FFF68 16TCR0 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16-bit timer
H'FFF69 TIOR0 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 channel 0
H'FFF6A 16TCNT0H 16
H'FFF6B 16TCNT0L
H'FFF6C GRA0H 16
H'FFF6D GRA0L
H'FFF6E GRB0H 16
H'FFF6F GRB0L
H'FFF70 16TCR1 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16-bit timer
H'FFF71 TIOR1 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 channel 1
H'FFF72 16TCNT1H 16
H'FFF73 16TCNT1L
H'FFF74 GRA1H 16
H'FFF75 GRA1L
H'FFF76 GRB1H 16
H'FFF77 GRB1L
H'FFF78 16TCR2 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16-bit timer
H'FFF79 TIOR2 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 channel 2
H'FFF7A 16TCNT2H 16
H'FFF7B 16TCNT2L
H'FFF7C GRA2H 16
H'FFF7D GRA2L
H'FFF7E GRB2H 16
H'FFF7F GRB2L
519
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'FFF80 8TCR0 16 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8-bit timer
H'FFF81 8TCR1 16 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 channels 0 and 1
H'FFF82 8TCSR0 16 CMFB CMFA OVF ADTE OIS3 OIS2 OS1 OS0
H'FFF83 8TCSR1 16 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0
H'FFF84 TCORA0 16
H'FFF85 TCORA1 16
H'FFF86 TCORB0 16
H'FFF87 TCORB1 16
H'FFF88 8TCNT0 16
H'FFF89 8TCNT1 16
H'FFF8A — ————————
H'FFF8B — ————————
H'FFF8C TCSR*28 OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT
H'FFF8D TCNT*28
H'FFF8E — ————————
H'FFF8F RSTCSR*28 WRST RSTOE ——————
H'FFF90 8TCR2 16 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8-bit timer
H'FFF91 8TCR3 16 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 channels 2 and 3
H'FFF92 8TCSR2 16 CMFB CMFA OVF — OIS3 OIS2 OS1 OS0
H'FFF93 8TCSR3 16 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0
H'FFF94 TCORA2 16
H'FFF95 TCORA3 16
H'FFF96 TCORB2 16
H'FFF97 TCORB3 16
H'FFF98 8TCNT2 16
H'FFF99 8TCNT3 16
H'FFF9A — ————————
H'FFF9B — ————————
H'FFF9C DADR0 8 D/A converter
H'FFF9D DADR1 8
H'FFF9E DACR 8 DAOE1 DAOE0 DAE —————
H'FFF9F — 8 ————————
520
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'FFFA0 TPMR 8 ————G3NOV G2NOV G1NOV G0NOV TPC
H'FFFA1 TPCR 8 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
H'FFFA2 NDERB 8 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
H'FFFA3 NDERA 8 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
H'FFFA4 NDRB*38 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8
NDR15 NDR14 NDR13 NDR12 ————
H'FFFA5 NDRA*38 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
NDR7 NDR6 NDR5 NDR4 ————
H'FFFA6 NDRB*38————————
————NDR11 NDR10 NDR9 NDR8
H'FFFA7 NDRA*38————————
————NDR3 NDR2 NDR1 NDR0
H'FFFA8 — ————————
H'FFFA9 — ————————
H'FFFAA — ————————
H'FFFAB — ————————
H'FFFAC — ————————
H'FFFAD — ————————
H'FFFAE — ————————
H'FFFAF — ————————
H'FFFB0 SMR 8 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI channel 0
H'FFFB1 BRR 8
H'FFFB2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'FFFB3 TDR 8
H'FFFB4 SSR 8 TDRE RDRF ORER FER/ERSPER TEND MPB MPBT
H'FFFB5 RDR 8
H'FFFB6 SCMR 8 ————SDIR SINV — SMIF
H'FFFB7 Reserved area (access prohibited)
H'FFFB8 SMR 8 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI channel 1
H'FFFB9 BRR 8
H'FFFBA SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'FFFBB TDR 8
H'FFFBC SSR 8 TDRE RDRF ORER FER/ERSPER TEND MPB MPBT
H'FFFBD RDR 8
H'FFFBE SCMR 8 ————SDIR SINV — SMIF
H'FFFBF Reserved area (access prohibited)
521
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'FFFC0 Reserved area (access prohibited)
H'FFFC1
H'FFFC2
H'FFFC3
H'FFFC4
H'FFFC5
H'FFFC6
H'FFFC7
H'FFFC8
H'FFFC9
H'FFFCA
H'FFFCB
H'FFFCC
H'FFFCD
H'FFFCE
H'FFFCF
H'FFFD0 — ————————
H'FFFD1 — ————————
H'FFFD2 — ————————
H'FFFD3 P4DR 8 P47P46P45P44P43P42P41P40Port 4
H'FFFD4 — ————————
H'FFFD5 P6DR 8 P67P66P65P64P63P62P61P60Port 6
H'FFFD6 P7DR 8 P77P76P75P74P73P72P71P70Port 7
H'FFFD7 P8DR 8 ———P8
4P83P82P81P80Port 8
H'FFFD8 P9DR 8 — — P95P94P93P92P91P90Port 9
H'FFFD9 PADR 8 PA7PA6PA5PA4PA3PA2PA1PA0Port A
H'FFFDA PBDR 8 PB7PB6PB5PB4PB3PB2PB1PB0Port B
H'FFFDB — ————————
H'FFFDC — ————————
H'FFFDD — ————————
H'FFFDE — ————————
H'FFFDF — ————————
522
Data Bit Names
Address
(Low) Register
Name Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'FFFE0 ADDRAH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D converter
H'FFFE1 ADDRAL 8 AD1 AD0 ——————
H'FFFE2 ADDRBH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFE3 ADDRBL 8 AD1 AD0 ——————
H'FFFE4 ADDRCH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFE5 ADDRCL 8 AD1 AD0 ——————
H'FFFE6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFE7 ADDRDL 8 AD1 AD0 ——————
H'FFFE8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0
H'FFFE9 ADCR 8 TRGE ———————
Notes: 1. Writing to bits 5 to 2 of BCR is prohibited.
2. For the procedure for writing to TCSR, TCNT, and RSTCSR, see section 11.2.4, Notes
on Register Rewriting.
3. The address depends on the output trigger setting.
Legend:
WDT: Watchdog timer
TPC: Programmable timing pattern controller
SCI: Serial communication interface
523
B.2 Functions
Bit
Initial value
R/W: 0
R/W
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
OCIDE
0
R/W
3
OCIAE
1
R/W
2
OCIBE
1
R/W
1
OVIE
1
0
Timer overflow interrupt enable
0
1
Interrupt requested by OVF flag is disabled
Interrupt requested by OVF flag is enabled
Output compare interrupt B enable
0
1
Interrupt requested by OCFB flag is disabled
Interrupt requested by OCFB flag is enabled
Output compare interrupt A enable
0
1
Interrupt requested by OCFA flag is disabled
Interrupt requested by OCFA flag is enabled
Input capture interrupt D enable
0
1
Interrupt requested by ICFD flag is disabled
Interrupt requested by ICFD flag is enabled
TIER—Timer Interrupt Enable Register H' 90 FRT
Register abbreviation
Register name Address to which register
is mapped Name of on-chip
supporting module
Names of the bits.
Dashes (—) indicate
reserved bits.
Full name of bit
Descriptions of
bit settings
Bit numbers
Initial bit values
Possible types of
access
R
W
R/W
Read only
Write only
Read and write
524
P4DDR—Port 4 Data Direction Register H'EE003 Port 4
Bit
Initial value
Read/Write 0
W
7
P47DDR
0
W
6
P46DDR
0
W
5
P45DDR
0
W
4
P44DDR
0
W
3
P43DDR
0
W
2
P42DDR
0
W
1
P41DDR
0
W
0
P40DDR
Port 4 input/output select
0
1
Generic input
Generic output
P6DDR—Port 6 Data Direction Register H'EE005 Port 6
Bit 76
P66DDR
5
P65DDR
4
P64DDR
3
P63DDR
2
P62DDR
1
P61DDR
0
P60DDR
Initial value
Read/Write 10
W0
W0
W0
W0
W0
W0
W
Port 6 input/output select
0
1
Generic input
Generic output
525
P8DDR—Port 8 Data Direction Register H'EE007 Port 8
Bit
Initial value
Read/Write
7654
P8
4
DDR
0
W
3
P8
3
DDR
0
W
2
P8
2
DDR
0
W
1
P8
1
DDR
0
W
0
P8
0
DDR
Port 8 input/output select
0
1
Generic input
Generic output
Initial value
Read/Write 111 0
W0
W0
W0
W
Modes 1 to 4
Modes 5 to 7 1110
W
1
W
P9DDR—Port 9 Data Direction Register H'EE008 Port 9
Bit
Initial value
Read/Write
7
1
6
0
W
5
P95DDR
0
W
4
P94DDR
0
W
3
P93DDR
0
W
2
P92DDR
0
W
1
P91DDR
0
W
0
P90DDR
Port 9 input/output select
0
1
Generic input
Generic output
1
526
PADDR—Port A Data Direction Register H'EE009 Port A
Bit
Initial value
Read/Write
7
PA7DDR
6
PA6DDR
5
PA5DDR
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
0
PA0DDR
Initial value
Read/Write 10
W0
W0
W0
W
Modes
3 and 4
Modes
1 and 2 0
W
0
W
Port A input/output select
0
1
Generic input
Generic output
0
W0
W
0
W0
W
0
W
PBDDR—Port B Data Direction Register H'EE00A Port B
Bit
Initial value
Read/Write
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
Port B input/output select
0
1
Generic input
Generic output
0
W
527
MDCR—Mode Control Register H'EE011 System control
Bit
Initial value
Read/Write 1
7
1
6
0
5
0
4
0
3
R
2
MDS2
R
1
MDS1
R
0
MDS0
Mode select 2 to 0
0
1
0
1
Operating Mode
***
Bit 2
MD2
Bit 1
MD1
Bit 0
MD0
0
1
0
1
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
0
1
0
1
0
1
Note: * Determined by the state of the mode pins (MD2 to MD0).
528
SYSCR—System Control Register H'EE012 System control
Bit
Initial value
Read/Write 0
R/W
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
1
R/W
3
UE
0
R/W
2
NMIEG
0
R/W
1
SSOE
1
R/W
0
RAME
NMI edge select
0
1An interrupt is requested at the falling edge of NMI
An interrupt is requested at the rising edge of NMI
RAM enable
0
1On-chip RAM is disabled
On-chip RAM is enabled
User bit enable
0
1CCR bit 6 (UI) is used as an interrupt mask bit
CCR bit 6 (UI) is used as a user bit
Standby timer select 2 to 0
Bit 6
STS2 Waiting Time = 8,192 states
Waiting Time = 16,384 states
Waiting Time = 32,768 states
Waiting Time = 65,536 states
Waiting Time = 131,072 states
Waiting Time = 26,2144 states
Waiting Time = 1,024 states
Illegal setting
Bit 5
STS1 Bit 4
STS0 Standby Timer
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Software standby
0
1SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
Software standby output port enable
0
1
In software standby mode,
all address bus and bus
control signals are high-
impedance
In software standby mode,
address bus retains output
state and bus control
signals are fixed high
529
BRCR—Bus Release Control Register H'EE013 Bus controller
Bit 7
A23E
6
A22E
5
A21E
4
A20E
3210
BRLE
Initial value
Read/Write 11111110
R/W
Modes
1 and 2
Address 23 to 20 enable
0
1
Address output
Other input/output
Bus release enable
0
1
The bus cannot be
released to an
external device
The bus can be
released to an
external device
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 01110
R/W
Modes
3 and 4
ISCR—IRQ Sense Control Register H'EE014 Interrupt Controller
Bit
Initial value
Read/Write 0
R/W
7
0
R/W
6
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
IRQ3SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
0
IRQ0SC
IRQ5 to IRQ0 sense control
0
1
Interrupts are requested when IRQ5 to IRQ0 are low
Interrupts are requested by falling-edge input at IRQ5 to IRQ0
530
IER—IRQ Enable Register H'EE015 Interrupt Controller
Bit
Initial value
Read/Write 0
R/W
7
0
R/W
6
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
IRQ5 to IRQ0 enable
0
1
IRQ5 to IRQ0 interrupts are disabled
IRQ5 to IRQ0 interrupts are enabled
ISR—IRQ Status Register H'EE016 Interrupt Controller
Bit
Initial value
Read/Write 0
7
0
6
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
IRQ5 to IRQ0 flags
0
Note: * Only 0 can be written to clear the flag.
Bits 5 to 0
IRQ5F to IRQ0F Setting and Clearing Conditions
1
(n = 5 to 0)
[Clearing conditions]
•Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
•IRQnSC = 0, IRQn input is high, and interrupt exception
handling is being carried out.
•IRQnSC = 1 and IRQn interrupt exception handling is being
carried out.
[Setting conditions]
•IRQnSC = 0 and IRQn input is low.
•IRQnSC = 1 and IRQn input changes from high to low.
531
IPRA—Interrupt Priority Register A H'EE018 Interrupt Controller
Bit
Initial value
Read/Write 0
R/W
7
IPRA7
0
R/W
6
IPRA6
0
R/W
5
IPRA5
0
R/W
4
IPRA4
0
R/W
3
IPRA3
0
R/W
2
IPRA2
0
R/W
1
IPRA1
0
R/W
0
IPRA0
Priority level A7 to A0
0
1
Priority level 0 (low priority)
Priority level 1 (high priority)
• Interrupt sources controlled by each bit
IPRA
Bit
Interrupt
source
Bit 7
IPRA7
IRQ
0
Bit 6
IPRA6
IRQ
1
Bit 5
IPRA5
IRQ
2
,
IRQ
3
Bit 4
IPRA4
IRQ
4
,
IRQ
5
Bit 3
IPRA3
Bit 2
IPRA2
Bit 1
IPRA1
Bit 0
IPRA0
WDT,
A/D con-
verter
16-bit
timer
channel 0
16-bit
timer
channel 1
16-bit
timer
channel 2
IPRB—Interrupt Priority Register B H'EE019 Interrupt Controller
Bit
Initial value
Read/Write 0
R/W
7
IPRB7
0
R/W
6
IPRB6
0
R/W
5
0
R/W
4
0
R/W
3
IPRB3
0
R/W
2
IPRB2
0
R/W
1
0
R/W
0
Priority level B7, B6, B3, and B2
0
1
Priority level 0 (low priority)
Priority level 1 (high priority)
Bit 7
IPRB7
Bit 6
IPRB6
Bit 5 Bit 4 Bit 3
IPRB3
Bit 2
IPRB2
Bit 1 Bit 0
8-bit timer
channels
0 and 1
8-bit timer
channels
2 and 3
SCI
channel 0
SCI
channel 1
• Interrupt sources controlled by each bit
IPRB
Bit
Interrupt
source
532
DASTCR—D/A Standby Control Register H'EE01A D/A
Bit
Initial value
Read/Write 1
7
1
6
1
5
1
4
1
3
1
2
1
1
0
R/W
0
DASTE
D/A standby enable
0
1
D/A output is disabled in software standby mode
D/A output is enabled in software standby mode
(Initial value)
533
DIVCR—Division Control Register H'EE01B System control
Bit
Initial value
Read/Write 1
7
1
6
1
5
1
4
1
3
1
2
0
R/W
1
DIV1
0
R/W
0
DIV0
Division ratio bits 1 and 0
Frequency Division Ratio
Bit 1
DIV1
Bit 0
DIV0 1/1
1/2
1/4
1/8
0
1
0
1
0
1
(Initial value)
534
MSTCRH—Module Standby Control Register H H'EE01C System control
76543210
PSTOP MSTPH1 MSTPH0
R/W R/W
R/W R/W
01111000
Module standby H1 to H0
Selection bits for placing modules
in standby state.
Bit
Initial value
Read/Write
Reserved bits
φ clock stop
Enables or disables ø clock output.
MSTCRL—Module Standby Control Register L H'EE01D System control
7654321 0
MSTPL2MSTPL3MSTPL4 MSTPL0
R/W R/W
R/WR/WR/WR/WR/W R/W
0000000 0
Module standby L4 to L2, L0
Selection bits for placing modules
in standby state.
Reserved bits
Bit
Initial value
Read/Write
535
ADRCR—Address Control Register H'EE01E Bus controller
7
—
1
—
Bit
Initial value
Read/Write
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
ADRCTL
1
R/W
2
—
1
—
1
—
1
—
Reserved bits Address control
Selects address update
mode 1 or address
update mode 2.
Description
ADRCTL
Address update mode 2 is selected
Address update mode 1 is selected (Initial value)
0
1
CSCR—Chip Select Control Register H'EE01F Bus controller
Bit
Initial value
Read/Write 0
R/W
7
CS7E
(n = 7 to 4)
0
R/W
6
CS6E
0
R/W
5
CS5E
0
R/W
4
CS4E
1
3
1
2
1
1
1
0
Chip select 7 to 4 enable
Description
Bit n
CSnE Output of chip select signal CSn is disabled (Initial value)
Output of chip select signal CSn is enabled
0
1
536
ABWCR—Bus Width Control Register H'EE020 Bus controller
Bit
Initial value
Initial value
Read/Write
1
0
R/W
7
ABW7
1
0
R/W
6
ABW6
1
0
R/W
5
ABW5
1
0
R/W
4
ABW4
1
0
R/W
3
ABW3
1
0
R/W
2
ABW2
1
0
R/W
1
ABW1
1
0
R/W
0
ABW0
Area 7 to 0 bus width control
Bus Width of Access Area
Bits 7 to 0
ABW7
to ABW0
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
0
1
Modes
1 and 3
Modes
2 and 4
ASTCR—Access State Control Register H'EE021 Bus controller
Bit
Initial value
Read/Write 1
R/W
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
Area 7 to 0 access state control
Number of States in Access Area
Bits 7 to 0
AST7
to AST0
Areas 7 to 0 are two-state access areas
Areas 7 to 0 are three-state access areas
0
1
537
WCRH—Wait Control Register H H'EE022 Bus controller
1
R/W
7
W71
1
R/W
6
W70
1
R/W
5
W61
1
R/W
4
W60
1
R/W
3
W51
1
R/W
2
W50
1
R/W
1
W41
1
R/W
0
W40
0
Area 4 wait control 1 and 0
0
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
0
Area 5 wait control 1 and 0
0
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
0
Area 6 wait control 1 and 0
0
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
0
Area 7 wait control 1 and 0
0
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
Bit
Initial value
Read/Write
538
WCRL—Wait Control Register L H'EE023 Bus controller
Bit
Initial value
Read/Write 1
R/W
7
W31
1
R/W
6
W30
1
R/W
5
W21
1
R/W
4
W20
1
R/W
3
W11
1
R/W
2
W10
1
R/W
1
W01
1
R/W
0
W00
Area 0 wait control 1 and 0
00
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
Area 1 wait control 1 and 0
00
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
Area 2 wait control 1 and 0
00
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
Area 3 wait control 1 and 0
00
1
0
1
No program wait is inserted
1 program wait state is inserted
2 program wait states are inserted
3 program wait states are inserted
1
539
BCR—Bus Control Register H'EE024 Bus controller
Bit
Initial value
Read/Write 1
R/W
7
ICIS1
1
R/W
6
ICIS0
0*1
—
5
—
0*1
—
4
—
0*1
—
3
—
1*2
—
2
—
1
R/W
1
RDEA
0
R/W
0
WAITE
0
1
WAIT pin wait input is disabled
WAIT pin wait input is enabled
Idle cycle insertion 0
0
1
No idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle insertion 1
Notes: 1. These bits can be read and written, but must not be set to 1. Normal operation cannot be
guaranteed if 1 is written in these bits.
2. 0 must not be written in bit 2.
0
1
No idle cycle is inserted in case of consecutive external read cycles for different areas
Idle cycle is inserted in case of consecutive external read cycles for different areas
Area division unit select
0
1
Area divisions are as follows:
Areas 0 to 7 are the same size
(2 Mbytes)
Wait pin enable
Area 0: 2 Mbytes Area 4: 1.93 Mbytes
Area 1: 2 Mbytes Area 5: 4 kbytes
Area 2: 8 Mbytes Area 6: 23.75 kbytes
Area 3: 2 Mbytes Area 7: 22 bytes
540
P4PCR—Port 4 Input Pull-Up Control Register H'EE03E Port 4
Bit
Initial value
Read/Write
0
R/W
7
P47PCR
0
R/W
6
P46PCR
0
R/W
5
P45PCR
0
R/W
4
P44PCR
0
R/W
3
P43PCR
0
R/W
2
P42PCR
0
R/W
1
P41PCR
0
R/W
0
P40PCR
Port 4 input pull-up control 7 to 0
0
1
Input pull-up transistor is off
Input pull-up transistor is on
Note: Valid when the corresponding P4DDR bit is cleared to 0
(designating generic input).
541
TSTR—Timer Start Register H'FFF60 16-bit timer (all channels)
7
—
1
—
Bit
Initial value
Read/Write
6
—
1
—
5
—
1
—
Reserved bits
4
—
1
—
3
—
1
—
2
STR2
0
R/W
1
STR1
0
R/W
0
STR0
0
R/W
0
1
16TCNT0 is halted (Initial value)
16TCNT0 is counting
Counter start 0
0
1
16TCNT1 is halted (Initial value)
16TCNT1 is counting
Counter start 1
0
1
16TCNT2 is halted (Initial value)
16TCNT2 is counting
Counter start 2
542
TSNC—Timer Synchro Register H'FFF61 16-bit timer (all channels)
7
—
1
—
Bit
Initial value
Read/Write
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
SYNC2
0
R/W
1
SYNC1
0
R/W
0
SYNC0
0
R/W
0
1
Channel 0 timer counter (16TCNT0) operates
independently (16TCNT0 presetting/clearing is
independent of other channels) (Initial value)
Channel 0 operates synchronously
Synchronous presetting/synchronous clearing
of 16TCNT0 is possible
Timer sync 0
0
1
Channel 1 timer counter (16TCNT1) operates
independently (16TCNT1 presetting/clearing is
independent of other channels) (Initial value)
Channel 1 operates synchronously
Synchronous presetting/synchronous clearing
of 16TCNT1 is possible
Timer sync 1
0
1
Channel 2 timer counter (16TCNT2) operates
independently (16TCNT2 presetting/clearing is
independent of other channels) (Initial value)
Channel 2 operates synchronously
Synchronous presetting/synchronous clearing
of 16TCNT2 is possible
Timer sync 2
Reserved bits
543
TMDR—Timer Mode Register H'FFF62 16-bit timer (all channels)
7
—
1
—
Bit
Initial value
Read/Write
6
MDF
0
R/W
5
FDIR
0
R/W
4
—
1
—
3
—
1
—
2
PWM2
0
R/W
1
PWM1
0
R/W
0
PWM0
0
R/W
0
1
Channel 0 operates normally (Initial value)
Channel 0 operates in PWM mode
PWM mode 0
0
1
Channel 1 operates normally (Initial value)
Channel 1 operates in PWM mode
PWM mode 1
0
1
Channel 2 operates normally (Initial value)
Channel 2 operates in PWM mode
PWM mode 2
0
1
OVF is set to 1 in TISRC when 16TCNT2
overflows or underflows (Initial value)
OVF is set to 1 in TISRC when 16TCNT2
overflows
Flag direction
0
1
Channel 2 operates normally (Initial value)
Channel 2 operates in phase counting mode
Phase counting mode
544
TOLR—Timer Output Level Setting Register H'FFF63 16-bit timer (all channels)
7
—
1
—
Bit
Initial value
Read/Write
6
—
1
—
5
TOB2
0
W
4
TOA2
0
W
3
TOB1
0
W
2
TOA1
0
W
1
TOB0
0
W
0
TOA0
0
W
0
1
TIOCA0 is 0
TIOCA0 is 1
Output level setting A0
0
1
TIOCB0 is 0
TIOCB0 is 1
Output level setting B0
0
1
TIOCA1 is 0
TIOCA1 is 1
Output level setting A1
0
1
TIOCB1 is 0
TIOCB1 is 1
Output level setting B1
0
1
TIOCA2 is 0
TIOCA2 is 1
Output level setting A2
0
1
TIOCB2 is 0
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
TIOCB2 is 1
Output level setting B2
545
TISRA—Timer Interrupt Status Register A H'FFF64 16-bit timer (all channels)
—
1
—
7
IMIEA2
0
R/W
6
IMIEA1
0
R/W
5
IMIEA0
0
R/W
4
—
1
—
3
IMFA2
0
R/(W)*
2
IMFA1
0
R/(W)*
1
IMFA0
0
R/(W)*
0
0
1
Input capture/compare match flag A0
[Clearing conditions]
Read IMFA0 when IMFA0=1, then write 0 in IMFA0
[Setting conditions]
•16TCNT0=GRA0 when GRA0 functions as an output compare register.
•16TCNT0 value is transferred to GRA0 by an input capture signal when
GRA0 functions as an input capture register.
0
1
Input capture/compare match flag A1
[Clearing conditions]
Read IMFA1 when IMFA1=1, then write 0 in IMFA1
[Setting conditions]
•16TCNT1=GRA1 when GRA1 functions as an output compare register.
•16TCNT1 value is transferred to GRA1 by an input capture signal when
GRA1 functions as an input capture register.
0
1
Input capture/compare match flag A2
[Clearing conditions]
Read IMFA2 when IMFA2=1, then write 0 in IMFA2
(Initial value)
(Initial value)
(Initial value)
[Setting conditions]
•16TCNT2=GRA2 when GRA2 functions as an output compare register.
•16TCNT2 value is transferred to GRA2 by an input capture signal when
GRA2 functions as an input capture register.
0
1IMIA0 interrupt requested by IMFA0 flag is disabled
IMIA0 interrupt requested by IMFA0 is enabled
Input capture/compare match interrupt enable A0
0
1IMIA1 interrupt requested by IMFA1 flag is disabled
IMIA1 interrupt requested by IMFA1 is enabled
Input capture/compare match interrupt enable A1
0
1IMIA2 interrupt requested by IMFA2 flag is disabled
(Initial value)
(Initial value)
(Initial value)
IMIA2 interrupt requested by IMFA2 is enabled
Input capture/compare match interrupt enable A2
Bit:
Initial value:
Read/Write:
Note: * Only 0 can be written to clear the flag.
546
TISRB—Timer Interrupt Status Register B H'FFF65 16-bit timer (all channels)
—
1
—
7
IMIEB2
0
R/W
6
IMIEB1
0
R/W
5
IMIEB0
0
R/W
4
—
1
—
3
IMFB2
0
R/(W)*
2
IMFB1
0
R/(W)*
1
IMFB0
0
R/(W)*
0
0
1
Input capture/compare match flag B0
[Clearing condition]
Read IMFB0 when IMFB0=1, then write 0 in IMFB0.
[Setting conditions]
16TCNT0=GRB0 when GRB0 functions as an output compare register.
16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0
functions as an input capture register.
0
1
Input capture/compare match flag B1
[Clearing condition]
Read IMFB1 when IMFB1=1, then write 0 in IMFB1.
[Setting conditions]
•16TCNT1=GRB1 when GRB1 functions as an output compare register.
•16TCNT1 value is transferred to GRB1 by an input capture signal when
GRB1 functions as an input capture register.
0
1
Input capture/compare match flag B2
[Clearing condition]
Read IMFB2 when IMFB2=1, then write 0 in IMFB2.
(Initial value)
(Initial value)
(Initial value)
[Setting conditions]
•16TCNT2=GRB2 when GRB2 functions as an output compare register.
•16TCNT2 value is transferred to GRB2 by an input capture signal when
GRB2 functions as an input capture register.
0
1
IMIB0 interrupt requested by IMFB0 flag is disabled
IMIB0 interrupt requested by IMFB0 is enabled
Input capture/compare match interrupt enable B0
0
1
IMIB1 interrupt requested by IMFB1 flag is disabled
IMIB1 interrupt requested by IMFB1 is enabled
Input capture/compare match interrupt enable B1
0
1
IMIB2 interrupt requested by IMFB2 flag is disabled
(Initial value)
(Initial value)
(Initial value)
IMIB2 interrupt requested by IMFB2 is enabled
Input capture/compare match interrupt enable B2
Note : * Only 0 can be written to clear the flag.
Bit:
Initial value:
Read/Write:
547
TISRC—Timer Interrupt Status Register C H'FFF66 16-bit timer (all channels)
—
1
—
7
OVIE2
0
R/W
6
OVIE1
0
R/W
5
OVIE0
0
R/W
4
—
1
—
3
OVF2
0
R/(W)*
2
OVF1
0
R/(W)*
1
OVF0
0
R/(W)*
0
0
1OVI0 interrupt requested by OVF0 flag is disabled
OVI0 interrupt requested by OVF0 flag is enabled
Overflow interrupt enable 0
0
1OVI1 interrupt requested by OVF1 flag is disabled
OVI1 interrupt requested by OVF1 flag is enabled
Overflow interrupt enable 1
0
1OVI2 interrupt requested by OVF2 flag is disabled
(Initial value)
(Initial value)
(Initial value)
OVI2 interrupt requested by OVF2 flag is enabled
Overflow interrupt enable 2
Bit:
Initial value:
Read/Write:
[Clearing condition]
Read OVF0 when OVF0 = 1, then write 0 in OVF0.
[Setting condition]
16TCNT0 overflowed from H'FFFF to H'0000.
Overflow flag 0
0
1
[Clearing condition]
Read OVF1 when OVF1 = 1, then write 0 in OVF1.
[Setting condition]
16TCNT1 overflowed from H'FFFF to H'0000.
Overflow flag 1
0
1
[Clearing condition]
Read OVF2 when OVF2 = 1, then write 0 in OVF2.
(Initial value)
(Initial value)
(Initial value)
[Setting condition]
16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000
to H'FFFF.
Overflow flag 2
0
1
Note : * Only 0 can be written to clear the flag.
548
16TCR0—Timer Control Register 0 H'FFF68 16-bit timer channel 0
Bit
Initial value
Read/Write 1
—
7
—
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
Timer prescaler 2 to 0
Description
Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Internal clock : ø
Internal clock : ø / 2
Internal clock : ø / 4
Internal clock : ø / 8
External clock A : TCLKA input
External clock B : TCLKB input
External clock C : TCLKC input
External clock D : TCLKD input
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock edge 1 and 0
Description
Bit 4
CKEG Bit 3
CKEG0 Rising edges counted
Falling edges counted
Both edges counted
0
1
—
0
0
1
Counter clear 1 and 0
Description
Bit 6
CCLR1 Bit 5
CCLR0 16TCNT is not cleared
16TCNT is cleared by GRA compare match or input capture
16TCNT is cleared by GRB compare match or input capture
Synchronous clear : 16TCNT is cleared in synchronization with
other synchronized timers
0
1
0
1
0
1
(Initial value)
(Initial value)
(Initial value)
549
TIOR0—Timer I/O Control Register 0 H'FFF69 16-bit timer channel 0
I / O control A2 to A0
Description
Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 No output at compare match (Initial value)
0 output at GRA compare match
1 output at GRA compare match
Output toggles at GRA compare match
(1 output on channel 2)
GRA captures rising edges of input
GRA captures falling edges of input
GRB captures both edges of input
GRA is an output
compare register
GRA is an input
capture register
I / O control B2 to B0
Description
Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 No output at compare match (Initial value)
0 output at GRB compare match
1 output at GRB compare match
Output toggles at GRB compare match
(1 output on channel 2)
GRB captures rising edges of input
GRB captures falling edges of input
GRB captures both edges of input
GRB is an output
compare register
GRB is an input
capture register
—
1
—
7
IOB2
0
R/W
6
IOB1
0
R/W
5
IOB0
0
R/W
4
—
1
—
3
IOA2
0
R/W
2
IOA1
0
R/W
1
IOA0
0
R/W
0
Bit:
Initial value:
Read/Write:
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
550
16TCNT0 H/L—Timer Counter 0 H/L H'FFF6A, H'FFF6B 16-bit timer channel 0
Bit
Initial value
Read/Write 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
Up-counter
GRA0 H/L—General Register A0 H/L H'FFF6C, H'FFF6D 16-bit timer channel 0
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
Output compare or input capture register
GRB0 H/L—General Register B0 H/L H'FFF6E, H'FFF6F 16-bit timer channel 0
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
Output compare or input capture register
551
16TCR1 Timer Control Register 1 H'FFF70 16-bit timer channel 1
7
—
1
—
Bit
Initial value
Read/Write
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
TIOR1—Timer I/O Control Register 1 H'FFF71 16-bit timer channel 1
7
—
1
—
Bit
Initial value
Read/Write
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
16TCNT1 H/L—Timer Counter 1 H/L H'FFF72, H'FFF73 16-bit timer channel 1
Bit
Initial value
Read/Write 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
552
GRA1 H/L—General Register A1 H/L H'FFF74, H'FFF75 16-bit timer channel 1
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
GRB1 H/L—General Register B1 H/L H'FFF76, H'FFF77 16-bit timer channel 1
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
16TCR2 Timer Control Register 2 H'FFF78 16-bit timer channel 2
7
—
1
—
Bit
Initial value
Read/Write
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Notes: 1. Bit functions are the same as for 16-bit timer channel 0.
2. When phase counting mode is selected in channel 2, the settings of bits
CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
553
TIOR2—Timer I/O Control Register 2 H'FFF79 16-bit timer channel 2
7
—
1
—
Bit
Initial value
Read/Write
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
16TCNT2 H/L—Timer Counter 2 H/L H'FFF7A, H'FFF7B 16-bit timer channel 2
Bit
Initial value
Read/Write 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
Phase counting mode :
Other mode : up/down-counter
up-counter
GRA2 H/L—General Register A2 H/L H'FFF7C, H'FFF7D 16-bit timer channel 2
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
554
GRB2 H/L—General Register B2 H/L H'FFF7E, H'FFF7F 16-bit timer channel 2
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
555
8TCR0—Timer Control Register 0
8TCR1—Timer Control Register 1 H'FFF80
H'FFF81 8-bit timer channel 0
8-bit timer channel 1
Bit
Initial value
Read/Write 0
R/W
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
Clock select 2 to 0
0
00
1
0
1
0
0
11
0
11
Clock input is disabled
Internal clock: counted on rising
edge of φ/8
Internal clock: counted on rising
edge of φ/64
Internal clock: counted on rising
edge of φ/8192
External clock
:
counted on falling edge
External clock
:
counted on rising edge
External clock: counted on both
rising and falling edges
Counter clear 1 and 0
00
1
0
1
Clearing is disabled
Cleared by compare match A
Cleared by compare match B/input capture B
Cleared by input capture B
1
Timer overflow interrupt enable
0
1
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0
1
CMIA interrupt requested by CMFA is disabled
CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B
0
1
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
1
Channel 0:
Count on 8TCNT1 overflow signal*
Channel 1:
Count on 8TCNT0 compare match
A*
Note: * If the clock input of channel 0 is the 8TCNT1
overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no
incrementing clock is generated. Do not use
this setting.
556
8TCSR0—Timer Control/Status Register 0 H'FFF82 8-bit timer channel 0
Output select A1 and A0
0
Description
Description
Description
Bit 1
OS1 Bit 0
OS0
ICE in
8TCSR1 Bit 3
OIS3
Bit 4
ADTE
TRGE*2
Bit 2
OIS2
1
0
1
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
Output/input capture edge select B3 and B2
0
0
1
0
1
0
1
0
1
0
1
0
1
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
1
A/D trigger enable
00
1
0
1
A/D converter start requests by compare match
A or an external trigger are disabled
A/D converter start requests by compare match
A or an external trigger are disabled
A/D converter start requests by an external trigger are enabled, and
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled, and
A/D converter start requests by an external trigger are disabled
Timer overflow flag
0[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
Bit
Initial value
Read/Write 0
R/(W)*1
7
CMFB
0
R/(W)*1
6
CMFA
0
R/(W)*1
5
OVF
0
R/W
4
ADTE
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
0
1
1[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match flag A
0[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
1[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
1[Setting conditions]
8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
• TCORB functions as an input capture register.
Notes: 1. Only 0 can be written to bits 7 to 5 to clear these flags.
2. TRGE is bit 7 of the A/D control register (ADCR).
Note: * TRGE is bit 7 of the A/D control register (ADCR).
1
557
8TCSR1—Timer Control/Status Register 1 H'FFF83 8-bit timer channel 1
Output select A1 and A0
0
Description
Description
Bit 1
OS1 Bit 0
OS0
ICE in
8TCSR1 Bit 3
OIS3 Bit 2
OIS2
1
0
1
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
Output/input capture edge select B3 and B2
0
0
1
0
1
0
1
0
1
0
1
0
1
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
1
Timer overflow flag
0[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
0
1
1[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match/input capture flag A
0[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
1[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0 [Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
1 [Setting conditions]
8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
• TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5 to clear these flags.
Bit
Initial value
Read/Write 0
R/(W)*
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/W
4
ICE
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
Input capture enable
0
1
TCORB is a compare match register
TCORB is an input capture register
558
TCORA0—Time Constant Register A0
TCORA1—Time Constant Register A1 H'FFF84
H'FFF85 8-bit timer channel 0
8-bit timer channel 1
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
TCORA0 TCORA1
TCORB0—Time Constant Register B0
TCORB1—Time Constant Register B1 H'FFF86
H'FFF87 8-bit timer channel 0
8-bit timer channel 1
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
TCORB0 TCORB1
8TCNT0—Timer Counter 0
8TCNT1—Timer Counter 1 H'FFF88
H'FFF89 8-bit timer channel 0
8-bit timer channel 1
Bit
Initial value
Read/Write 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
8TCNT0 8TCNT1
559
TCSR—Timer Control/Status Register H'FFF8C WDT
Bit
Initial value
Read/Write 0
R/(W)*
7
OVF
0
R/W
6
WT/IT
0
R/W
5
TME
4
11
3
0
R/W
2
CKS2
0
R/W
1
CKS1
Clock select 2 to 0
0
0φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
1
0
CKS0
0
R/W
0
1
0
1
0
1
0
1
1
0
1
Timer enable
0Timer disabled:
TCNT is initialized to H'00 and halted
1Timer enabled:
TCNT starts counting up
Timer mode select
0Interval timer:
requests interval timer interrupts
1Watchdog timer:
generates a reset signal
Overflow flag
0[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1[Setting condition]
TCNT changes from H'FF to H'00
Note: * Only 0 can be written to clear the flag.
CKS2 CKS1 CKS0 Description
560
TCNT—Timer Counter H'FFF8D (read), H'FFF8C (write) WDT
Bit
Initial value
Read/Write 0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
Count value
RSTCSR—Reset Control/Status Register H'FFF8F (read), H'FFF8E (write) WDT
Bit
Initial value
Read/Write 0
R/(W)*
7
WRST
0
R/W
6
RSTOE
1
5
1
4
1
3
1
2
1
1
1
0
Reset output enable
0External output of reset signal is disabled
External output of reset signal is enabled
1
Watchdog timer reset
0 [Clearing conditions]
• Reset signal at RES pin
• Read WRST when WRST = 1, then write 0 in WRST
1[Setting condition]
TCNT overflow generates a reset signal during watchdog timer
operation
Note: * Only 0 can be written in bit 7 to clear the flag.
561
8TCR2—Timer Control Register 2
8TCR3—Timer Control Register 3 H'FFF90
H'FFF91 8-bit timer channel 2
8-bit timer channel 3
Bit
Initial value
Read/Write 0
R/W
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
Clock select 2 to 0
0
00
1
0
1
0
0
11
0
11
Clock input is disabled
Internal clock: counted on rising edge
of φ/8
Internal clock: counted on rising edge
of φ/64
Internal clock: counted on rising edge
of φ/8192
External clock: counted on falling edge
External clock: counted on rising edge
External clock: counted on both
rising and falling edges
Counter clear 1 and 0
00
1
0
1
Clearing is disabled
Cleared by compare match A
Cleared by compare match B/input capture B
Cleared by input capture B
1
Timer overflow interrupt enable
0
1
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0
1
CMIA interrupt requested by CMFA is disabled
CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B
0
1
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
1
CSK2 CSK1 CSK0 Description
Channel 2:
Count on 8TCNT3 overflow signal*
Channel 3:
Count on 8TCNT2 compare match A*
Note: * If the clock input of channel 2 is the 8TCNT3 overflow
signal and that of channel 3 is the 8TCNT2 compare
match signal, no incrementing clock is generated. Do
not use this setting.
562
8TCSR2—Timer Control/Status Register 2
8TCSR3—Timer Control/Status Register 3 H'FFF92
H'FFF93 8-bit timer channel 2
8-bit timer channel 3
Bit
Initial value
Read/Write 0
R/(W)*
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/W
4
ICE
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
Timer overflow flag
0[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
Bit
Initial value
Read/Write 0
R/(W)*
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
1
—
4
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
8TCSR3
8TCSR2
1[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match/input capture flag A
0[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
1[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
1
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5 to clear these flags.
Output select A1 and A0
0
Description
Bit 1
OS1 Bit 0
OS0
1
0
1
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
0
1
Description
ICE in
8TCSR3 Bit 3
OIS3 Bit 3
OIS2
Output/input capture edge select B3 and B2
0
0
1
0
1
0
1
0
1
0
1
0
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
1
Input capture enable
0
1
TCORB is a compare match register
TCORB is an input capture register
563
TCORA2—Time Constant Register A2
TCORA3—Time Constant Register A3 H'FFF94
H'FFF95 8-bit timer channel 2
8-bit timer channel 3
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
TCORA2 TCORA3
TCORB2—Time Constant Register B2
TCORB3—Time Constant Register B3 H'FFF96
H'FFF97 8-bit timer channel 2
8-bit timer channel 3
Bit
Initial value
Read/Write 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W
1
R/W
TCORB2 TCORB3
8TCNT2—Timer Counter 2
8TCNT3—Timer Counter 3 H'FFF98
H'FFF99 8-bit timer channel 2
8-bit timer channel 3
Bit
Initial value
Read/Write 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
8TCNT2 8TCNT3
564
DADR0—D/A Data Register 0 H'FFF9C D/A
Bit
Initial value
Read/Write 0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
D/A conversion data
DADR1—D/A Data Register 1 H'FFF9D D/A
Bit
Initial value
Read/Write 0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
D/A conversion data
565
DACR—D/A Control Register H'FFF9E D/A
Bit
Initial value
Read/Write 0
R/W
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
1
4
1
3
1
2
1
1
1
0
D/A enable
Bit 7
DAOE1
D/A conversion is disabled
in channels 0 and 1
D/A conversion is enabled
in channel 0
D/A conversion is disabled
in channel 1
D/A conversion is disabled
in channel 0
D/A conversion is enabled
in channel 1
Description
D/A conversion is enabled
in channels 0 and 1
D/A conversion is enabled
in channels 0 and 1
D/A conversion is enabled
in channels 0 and 1
Bit 6 Bit 5
DAOE0 DAE
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
D/A output enable 0
0DA0 analog output is disabled
1Channel-0 D/A conversion and DA0
analog output are enabled
D/A output enable 1
0DA1 analog output is disabled
1Channel-1 D/A conversion and DA1
analog output are enabled
566
TPMR—TPC Output Mode Register H'FFFA0 TPC
Bit
Initial value
Read/Write 1
7
1
6
1
5
1
4
0
R/W
3
G3NOV
0
R/W
2
G2NOV
0
R/W
1
G1NOV
0
R/W
0
G0NOV
Group 0 non-overlap
0Normal TPC output in group 0. Output values
change at compare match A in the selected
16-bit timer channel
1Non-overlapping TPC output in group 0,
controlled by compare match A and B in the
selected 16-bit timer channel
Group 1 non-overlap
0Normal TPC output in group 1. Output values change
at compare match A in the selected 16-bit timer channel
1Non-overlapping TPC output in group 1, controlled by
compare match A and B in the selected 16-bit timer channel
Group 2 non-overlap
0Normal TPC output in group 2. Output values change at
compare match A in the selected 16-bit timer channel
1Non-overlapping TPC output in group 2, controlled by
compare match A and B in the selected 16-bit timer channel
Group 3 non-overlap
0Normal TPC output in group 3. Output values change at
compare match A in the selected 16-bit timer channel
1Non-overlapping TPC output in group 3, controlled by
compare match A and B in the selected 16-bit timer channel
567
TPCR—TPC Output Control Register H'FFFA1 TPC
Group 0 compare match select 1 and 0
Bit 1
G0CMS1 16-Bit Timer Channel Selected as Output Trigger
Bit 0
G0CMS0 TPC output group 0 (TP
3
to TP
0
) is triggered by
compare match in 16-bit timer channel 0
TPC output group 0 (TP
3
to TP
0
) is triggered by
compare match in 16-bit timer channel 1
TPC output group 0 (TP
3
to TP
0
) is triggered by
compare match in 16-bit timer channel 2
0
1
0
1
0
1
Group 1 compare match select 1 and 0
Bit 3
G1CMS1 16-Bit Timer Channel Selected as Output Trigger
Bit 2
G1CMS0 TPC output group 1 (TP
7
to TP
4
) is triggered by
compare match in 16-bit timer channel 0
TPC output group 1 (TP
7
to TP
4
) is triggered by
compare match in 16-bit timer channel 1
TPC output group 1 (TP
7
to TP
4
) is triggered by
compare match in 16-bit timer channel 2
0
1
0
1
0
1
Group 2 compare match select 1 and 0
Bit 5
G2CMS1 16-Bit Timer Channel Selected as Output Trigger
Bit 4
G2CMS0 TPC output group 2 (TP
11
to TP
8
) is triggered by compare match in 16-bit timer channel 0
TPC output group 2 (TP
11
to TP
8
) is triggered by compare match in 16-bit timer channel 1
TPC output group 2 (TP
11
to TP
8
) is triggered by compare match in 16-bit timer channel 2
0
1
0
1
0
1
Group 3 compare match select 1 and 0
Bit 7
G3CMS1 16-Bit Timer Channel Selected as Output Trigger
Bit 6
G3CMS0 TPC output group 3 (TP
15
to TP
12
) is triggered by compare match in 16-bit timer channel 0
TPC output group 3 (TP
15
to TP
12
) is triggered by compare match in 16-bit timer channel 1
TPC output group 3 (TP
15
to TP
12
) is triggered by compare match in 16-bit timer channel 2
0
1
0
1
0
1
Bit
Initial value
Read/Write
7
G3CMS1
6
G3CMS0
5
G2CMS1
4
G2CMS0
1
R/W
3
G1CMS1
1
R/W
2
G1CMS0
1
R/W
1
G0CMS1
1
R/W
0
G0CMS0
1
R/W
1
R/W
1
R/W
1
R/W
568
NDERB—Next Data Enable Register B H'FFFA2 TPC
Bit
Initial value
Read/Write 0
R/W
7
NDER15
0
R/W
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
2
NDER10
0
R/W
1
NDER9
0
R/W
0
NDER8
Next data enable 15 to 8
Bits 7 to 0
NDER15
to NDER8
Description
TPC outputs TP
15
to TP
8
are disabled
(NDR15 to NDR8 are not transferred to PB
7
to PB
0
)
TPC outputs TP
15
to TP
8
are enabled
(NDR15 to NDR8 are transferred to PB
7
to PB
0
)
0
1
NDERA—Next Data Enable Register A H'FFFA3 TPC
Bit
Initial value
Read/Write 0
R/W
7
NDER7
0
R/W
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
Next data enable 7 to 0
Bits 7 to 0
NDER7
to NDER0
Description
TPC outputs TP
7
to TP
0
are disabled
(NDR7 to NDR0 are not transferred to PA
7
to PA
0
)
TPC outputs TP
7
to TP
0
are enabled
(NDR7 to NDR0 are transferred to PA
7
to PA
0
)
0
1
569
NDRB—Next Data Register B H'FFFA4/H'FFFA6 TPC
• Same trigger for TPC output groups 2 and 3
Address H'FFFA4
Bit
Initial value
Read/Write 0
R/W
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
Store the next output data for TPC output group 3 Store the next output data for TPC output group 2
Address H'FFFA6
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Bit
Initial value
Read/Write
• Different triggers for TPC output groups 2 and 3
Address H'FFFA4
Bit
Initial value
Read/Write 0
R/W
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
1
3
1
2
1
1
1
0
Store the next output data for TPC output group 3
Address H'FFFA6
Bit
Initial value
Read/Write 0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
43
NDR11
2
NDR10
1
NDR9
1111
0
NDR8
Store the next output data for TPC output group 2
570
NDRA—Next Data Register A H'FFFA5/H'FFFA7 TPC
• Same trigger for TPC output groups 0 and 1
Address H'FFFA5
Bit
Initial value
Read/Write 0
R/W
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
Store the next output data for TPC output group 1 Store the next output data for TPC output group 0
Address H'FFFA7
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Bit
Initial value
Read/Write
• Different triggers for TPC output groups 0 and 1
Address H'FFFA5
Bit
Initial value
Read/Write 0
R/W
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
1
3
1
2
1
1
1
0
Store the next output data for TPC output group 1
Address H'FFFA7
Bit
Initial value
Read/Write 0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
43
NDR3
2
NDR2
1
NDR1
1111
0
NDR0
Store the next output data for TPC output group 0
571
SMR—Serial Mode Register H'FFFB0 SCI0
Bit
Initial value
Read/Write 0
R/W
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
4
O/E
0
R/W 0
R/W
3
STOP
0
R/W
2
MP
0
R/W
1
CKS1
Clock select 1 and 0
0
Bit 0
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
1
0
CKS0
0
R/W
Multiprocessor mode
0Multiprocessor function disabled
Multiprocessor format selected
1
Bit 1 Clock Source
CKS0CKS1
0
1
0
1
Stop bit length
0One stop bit
Two stop bits
1
Parity mode
0Even parity
Odd parity
1
Parity enable
0Parity bit is not added or checked
Parity bit is added and checked
1
GSM mode (for smart card interface)
0TEND flag is set 12.5 etu* after start bit
TEND flag is set 11.0 etu* after start bit
1
Character length
08-bit data
7-bit data
1
Communication mode (for serial communication interface)
0Asynchronous mode
Synchronous mode
1
Note: * etu: Elementary time unit (time required to transmit one bit)
572
BRR—Bit Rate Register H'FFFB1 SCI0
Bit
Initial value
Read/Write 1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
Serial communication bit rate setting
573
SCR—Serial Control Register H'FFFB2 SCI0
Bit
Initial value
Read/Write 0
R/W
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
Clock enable 1 and 0
(for serial communication interface)
Bit 1
CKE1 Bit 0
CKE0
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
0
1
0
1
0
1
Description
Transmit-end interrupt enable
0
1Transmit-end interrupt requests (TEI) are disabled
Transmit-end interrupt requests (TEI) are enabled
Receive interrupt enable
0
1Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Internal clock: SCK pin
available for generic I/O
Internal clock: SCK pin
used for serial clock output
Internal clock: SCK pin
used for clock output
Internal clock: SCK pin
used for serial clock output
External clock: SCK pin
used for clock input
External clock: SCK pin
used for serial clock input
External clock: SCK pin
used for clock input
External clock: SCK pin
used for serial clock input
Multiprocessor interrupt enable
0
1Multiprocessor interrupts are disabled (normal receive operation)
Multiprocessor interrupts are enabled
Receive enable
0
1
Receiving is
disabled
Receiving is
enabled
Transmit enable
0
1Transmitting is disabled
Transmitting is enabled
Transmit interrupt enable
0
1Transmit-data-empty interrupt request (TXI) is disabled
Transmit-data-empty interrupt request (TXI) is enabled
Clock enable 1 and 0 (for smart card interface)
SMR
GM Bit 1
CKE1 Bit 0
CKE0
0
0
1
0
1
0
1
0
1
0
1
Description
SCK pin available for generic I/O
SCK pin used for clock output
SCK pin output fixed low
SCK pin used for clock output
SCK pin output fixed high
SCK pin used for clock output
574
TDR—Transmit Data Register H'FFFB3 SCI0
Bit
Initial value
Read/Write 1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
Serial transmit data
575
SSR—Serial Status Register H'FFFB4 SCI0
Bit
Initial value
Read/Write 1
R/(W)*
7
TDRE 0
R/(W)*
6
RDRF 0
R/(W)*
5
ORER 0
R/(W)*
4
FER/ERS 0
R/(W)*
3
PER 1
R
2
TEND 0
R
1
MPB 0
R/W
0
MPBT
Transmit end (for serial communication interface)
0
Multiprocessor bit transfer
0
1Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
Multiprocessor bit
0
1Multiprocessor bit value in receive data is 0
Multiprocessor bit value in receive data is 1
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
[Setting conditions]
• Reset or transition to standby mode
• TE is cleared to 0 in SCR.
• TDRE is 1 when last bit of 1-byte serial character is
transmitted.
Parity error
0
1
[Clearing conditions] • Reset or transition to standby mode
• Read PER when PER = 1, then write 0 in PER.
[Setting condition] Parity error (parity of receive data does not match parity
setting of O/E bit in SMR)
Framing error (for serial communication interface)
0[Clearing conditions] • Reset or transition to standby mode
• Read FER when FER = 1, then write 0 in FER.
[Setting condition] Framing error (stop bit is 0)
Error signal status (for smart card interface)
0[Clearing conditions] • Reset or transition to standby mode
• Read ERS when ERS = 1, then write 0 in ERS.
[Setting condition] A low error signal is received.
1
1
Overrun error
0[Clearing conditions] • Reset or transition to standby mode
• Read ORER when ORER = 1, then write 0 in ORER.
[Setting condition] Overrun error (reception of the next serial data ends when RDRF = 1)
1
Receive data register full
0[Clearing conditions] • Reset or transition to standby mode
• Read RDRF when RDRF = 1, then write 0 in RDRF.
[Setting condition] Serial data is received normally and transferred from RSR to RDR.
1
Transmit data register empty
Note: * Only 0 can be written, to clear the flag.
0 [Clearing conditions] • Read TDRE when TDRE = 1, then write 0 in TDRE.
[Setting conditions] • Reset or transition to standby mode
• TE is 0 in SCR.
• Data is transferred from TDR to TSR, enabling new data to be written in TDR
1
1
Transmit end (for smart card interface)
0[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
[Setting conditions]
•Reset or transition to standby mode
•TE is cleared to 0 in SCR and FER/ERS is cleared to 0.
•TDRE is 1 and FER/ERS is 0 (normal transmission)
2.5 etu* (when GM = 0) or 1.0 etu (when GM = 1) after
1-byte serial character is transmitted.
1
Note: * etu: Elementary time unit (time required to transmit one bit)
576
RDR—Receive Data Register H'FFFB5 SCI0
Bit
Initial value
Read/Write 0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
Serial receive data
577
SCMR—Smart Card Mode Register H'FFFB6 SCI0
1
7
1
6
1
5
1
4
0
R/W
3
SDIR
0
R/W
2
SINV
1
1
0
R/W
0
SMIF
Smart card interface mode select
0
1
Smart card interface function is disabled
Smart card interface function is enabled
(Initial value)
Smart card data invert
0
1
Unmodified TDR contents are transmitted
Receive data is stored unmodified in RDR
(Initial value)
Inverted 1/0 logic levels of TDR contents are transmitted
1/0 logic levels of received data are inverted before storage in RDR
Smart card data transfer direction
0
1
TDR contents are transmitted LSB-first
Receive data is stored LSB-first in RDR
(Initial value)
TDR contents are transmitted MSB-first
Receive data is stored MSB-first in RDR
Bit
Initial value
Read/Write
578
SMR—Serial Mode Register H'FFFB8 SCI1
0
R/W
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
0
CKS0
Note: Bit functions are the same as for SCI0.
Bit
Initial value
Read/Write
BRR—Bit Rate Register H'FFFB9 SCI1
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
Note: Bit functions are the same as for SCI0.
Bit
Initial value
Read/Write
SCR—Serial Control Register H'FFFBA SCI1
0
R/W
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
Note: Bit functions are the same as for SCI0.
Bit
Initial value
Read/Write
579
TDR—Transmit Data Register H'FFFBB SCI1
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
SSR—Serial Status Register H'FFFBC SCI1
0
R/(W)*
7
TDRE
0
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER/ERS
0
R/(W)*
3
PER
1
R
2
TEND
0
R
1
MPB
0
R/W
0
MPBT
Bit
Initial value
Read/Write
Notes: Bit functions are the same as for SCI0.
* Only 0 can be written to clear the flag.
RDR—Receive Data Register H'FFFBD SCI1
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
580
SCMR—Smart Card Mode Register H'FFFBE SCI1
0
R/W
7
0
R/W
6
1
5
0
R/W
43
SDIR
2
SINV
1
1111
0
SMIF
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
581
P4DR—Port 4 Data Register H'FFFD3 Port 4
0
R/W
7
P4
7
0
R/W
6
P4
6
0
R/W
5
P4
5
0
R/W
4
P4
4
0
R/W
3
P4
3
0
R/W
2
P4
2
0
R/W
1
P4
1
0
R/W
0
P4
0
Data for port 4 pins
Bit
Initial value
Read/Write
P6DR—Port 6 Data Register H'FFFD5 Port 6
1
R
7
P6
7
0
R/W
6
P6
6
0
R/W
5
P6
5
0
R/W
4
P6
4
0
R/W
3
P6
3
0
R/W
2
P6
2
0
R/W
1
P6
1
0
R/W
0
P6
0
Data for port 6 pins
Bit
Initial value
Read/Write
582
P7DR—Port 7 Data Register H'FFFD6 Port 7
R
7
P7
7
R
6
P7
6
R
5
P7
5
R
4
P7
4
R
3
P7
3
R
2
P7
2
R
1
P7
1
R
0
P7
0
Data for port 7 pins
*
*******
Note: * Determined by pins P7
7
to P7
0
.
Bit
Initial value
Read/Write
P8DR—Port 8 Data Register H'FFFD7 Port 8
1
7
1
6
1
5
0
R/W
4
P8
4
0
R/W
3
P8
3
0
R/W
2
P8
2
0
R/W
1
P8
1
0
R/W
0
P8
0
Data for port 8 pins
Bit
Initial value
Read/Write
583
P9DR—Port 9 Data Register H'FFFD8 Port 9
1
7
1
6
0
R/W
5
P9
5
0
R/W
4
P9
4
0
R/W
3
P9
3
0
R/W
2
P9
2
0
R/W
1
P9
1
0
R/W
0
P9
0
Data for port 9 pins
Bit
Initial value
Read/Write
PADR—Port A Data Register H'FFFD9 Port A
0
R/W
7
PA
7
0
R/W
6
PA
6
0
R/W
5
PA
5
0
R/W
4
PA
4
0
R/W
3
PA
3
0
R/W
2
PA
2
0
R/W
1
PA
1
0
R/W
0
PA
0
Data for port A pins
Bit
Initial value
Read/Write
PBDR—Port B Data Register H'FFFDA Port B
0
R/W
7
PB
7
0
R/W
6
PB
6
0
R/W
5
PB
5
0
R/W
4
PB
4
0
R/W
3
PB
3
0
R/W
2
PB
2
0
R/W
1
PB
1
0
R/W
0
PB
0
Data for port B pins
Bit
Initial value
Read/Write
584
ADDRA H/L—A/D Data Register A H/L H'FFFE0, H'FFFE1 A/D
0
R
15
AD9
A/D conversion data
10-bit data giving an A/D conversion result
0
R
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
ADDRAH ADDRAL
Bit
Initial value
Read/Write
ADDRB H/L—A/D Data Register B H/L H'FFFE2, H'FFFE3 A/D
0
R
15
AD9
0
R
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
ADDRBH ADDRBL
A/D conversion data
10-bit data giving an A/D conversion result
Bit
Initial value
Read/Write
585
ADDRC H/L—A/D Data Register C H/L H'FFFE4, H'FFFE5 A/D
0
R
15
AD9
0
R
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
ADDRCH ADDRCL
A/D conversion data
10-bit data giving an A/D conversion result
Bit
Initial value
Read/Write
ADDRD H/L—A/D Data Register D H/L H'FFFE6, H'FFFE7 A/D
0
R
15
AD9
0
R
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
ADDRDH ADDRDL
A/D conversion data
10-bit data giving an A/D conversion result
Bit
Initial value
Read/Write
ADCR—A/D Control Register H'FFFE9 A/D
0
R/W
7
TRGE
1
6
1
5
1
4
1
3
1
2
1
1
0
R/W
0
Trigger Enable
0
1
A/D conversion start by external trigger or 8-bit timer
compare match is disabled
A/D conversion is started by falling edge of external
trigger signal (ADTRG) or 8-bit timer compare match
Bit
Initial value
Read/Write
586
ADCSR—A/D Control/Status Register H'FFFE8 A/D
0
R/(W)*
7
ADF
0
R/W
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
Channel select 2 to 0
Group Selection
0
1
0
1
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
0
CH2
1
0
1
0
1
0
1
0
1
Description
Single Mode Scan Mode
Clock select
0
1
Conversion time =
134 states (maximum)
Conversion time =
70 states (maximum)
Channel Selection
CH1 CH0 AN
0
AN
0,
AN
1
AN
0
to AN
2
AN
0
to AN
3
AN
4
AN
4,
AN
5
AN
4
to AN
6
AN
4
to AN
7
Scan mode
0
1Single mode
Scan mode
A/D start
0
1
A/D conversion is stopped
1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends
2. Scan mode: A/D conversion starts and continues, cycling among the selected channels ADST
is cleared to 0 by software, by a reset, or by a transition to standby mode
A/D interrupt enable
0
1A/D end interrupt request is disabled
A/D end interrupt request is enabled
A/D end flag
0 [Clearing condition]
Read ADF when ADF = 1, then write 0 in ADF
[Setting conditions]
• Single mode: A/D conversion ends
• Scan mode: A/D conversion ends in all selected channels
1
Note: * Only 0 can be written to clear the flag.
Bit
Initial value
Read/Write
587
Appendix C I/O Port Block Diagrams
C.1 Port 4 Block Diagram
P4n
RP4P
RP4
WP4
WP4D
WP4P
Reset
Reset
Reset
QD
R
C
P4 PCR
n
QD
R
C
P4 DDR
n
QD
R
C
P4 DR
n
WP4P:
RP4P:
WP4D:
WP4:
RP4:
n = 0 to 7
Write to P4PCR
Read P4PCR
Write to P4DDR
Write to port 4
Read port 4
Write to external address
Hardware
standby
External bus released
Read external
address
Internal data bus (upper)
Internal data bus (lower)
8-bit bus
mode 16-bit bus
mode
Figure C.1 Port 4 Block Diagram
588
C.2 Port 6 Block Diagrams
WP6D:
WP6:
RP6:
Write to P6DDR
Write to port 6
Read port 6
RP6
input
WP6D
Reset
QD
R
C
P6 DDR
0
WP6
Reset
QD
R
C
P6 DR
0
P60
Internal data bus
Bus controller
WAIT
input
enable
Bus controller
WAIT
Hardware Standby
Figure C.2 (a) Port 6 Block Diagram (Pin P60)
589
P61
WP6D:
WP6:
RP6:
Write to P6DDR
Write to port 6
Read port 6
WP6D
Reset
QD
R
C
P6 DDR
1
WP6
Reset
QD
R
C
P6 DR
1
RP6
Internal data bus
Bus
controller
Bus release
enable
BREQ input
Hardware Standby
Figure C.2 (b) Port 6 Block Diagram (Pin P61)
590
WP6D
Reset
Hardware standby
QD
R
C
P6 DDR
2
WP6
Reset
QD
R
C
P6 DR
2
RP6
P62
WP6D:
WP6:
RP6:
Write to P6DDR
Write to port 6
Read port 6
Internal data bus
Bus controller
Bus release
enable
BACK
output
Figure C.2 (c) Port 6 Block Diagram (Pin P62)
591
Read port 6RP6:
Hardware standby
RP6
P67φ output
φ output enable
Internal data bus
Figure C.2 (d) Port 6 Block Diagram (Pin P67)
592
C.3 Port 7 Block Diagrams
P7
n
RP7
RP7: Read port 7
n = 0 to 5
Internal data bus
A/D converter
Input enable
Channel select signal
Analog input
Figure C.3 (a) Port 7 Block Diagram (Pins P70 to P75)
P7
n
RP7
RP7: Read port 7
n = 6, 7
Internal data bus
D/A converter
Analog output
Output enable
A/D converter
Input enable
Channel select signal
Analog input
Figure C.3 (b) Port 7 Block Diagram (Pins P76 and P77)
593
C.4 Port 8 Block Diagrams
P80
RP8
WP8D
Reset
QD
R
C
P8 DDR
0
WP8
Reset
QD
R
C
P8 DR
0
WP8D:
WP8:
RP8:
Write to P8DDR
Write to port 8
Read port 8
Internal data bus
Interrupt
controller
input
IRQ
0
Figure C.4 (a) Port 8 Block Diagram (Pin P80)
594
P8
n
WP8D
Reset
QD
R
C
P8 DDR
n
WP8
Reset
QD
R
C
P8 DR
n
RP8
WP8D:
WP8:
RP8:
SSOE:
n = 1, 2
Write to P8DDR
Write to port 8
Read port 8
Software standby output port enable
Internal data bus
Bus controller
output
Interrupt
controller
IRQ
IRQ
CS
CS
2
3
1
2input
SSOE
Software standby
External bus released
Hardware standby
Figure C.4 (b) Port 8 Block Diagram (Pins P81 and P82)
595
A/D converter
WP8D
P83DR
C
QD
Write to P8DDR
Write to port 8
Read port 8
Software standby output port enable
WP8D:
WP8:
RP8:
SSOE:
WP8
R
Reset
Internal data bus
RP8
P83
Bus controller
CS1 output
Reset
Interrupt controller
IRQ3
input
ADTRG input
P83DDR
C
QD
R
SSOE
Software standby
External bus
released
Hardware standby
Figure C.4 (c) Port 8 Block Diagram (Pin P83)
596
P8
4
WP8D
QD
C
P8 DDR
4
WP8
Reset
QD
R
C
P8 DR
4
RP8
WP8D:
WP8:
RP8:
SSOE:
Write to P8DDR
Write to port 8
Read port 8
Software standby output port enable
Internal data bus
Bus controller
output
0
CS
SSOE
Software standby
External bus released
Hardware standby
Reset
R
Figure C.4 (d) Port 8 Block Diagram (Pin P84)
597
C.5 Port 9 Block Diagrams
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
P90
RP9
WP9D
Reset
Hardware
standby
QD
R
C
P9 DDR
0
WP9
Reset
QD
R
C
P9 DR
0
Internal data bus
SCI
Output
enable
Serial
transmit
data
Guard
time
Figure C.5 (a) Port 9 Block Diagram (Pin P90)
598
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
P91
RP9
WP9D
Reset
QD
R
C
P9 DDR
1
WP9
Reset
QD
R
C
P9 DR
1
Internal data bus
SCI
Output
enable
Serial
transmit
data
Guard time
Hardware
standby
Figure C.5 (b) Port 9 Block Diagram (Pin P91)
599
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
P9
2
WP9D
Reset
QD
R
C
P9 DDR
2
WP9
Reset
QD
R
C
P9 DR
2
RP9
Internal data bus
Input enable
Serial receive
data
SCI
Hardware standby
Figure C.5 (c) Port 9 Block Diagram (Pin P92)
600
P93DDR
C
QD
WP9D
RP9
P93DR
C
QD
P93
Serial receive data
Input enable
Write to P9DDR
Write to port 9
Read port 9
WP9D:
WP9:
RP9:
WP9
R
R
Reset
Internal data bus
Reset
SCI
Hardware standby
Figure C.5 (d) Port 9 Block Diagram (Pin P93)
601
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
WP9D
Hardware standby
Reset
QD
R
C
P9 DDR
4
WP9
Reset
QD
R
C
P9 DR
4
RP9
P9
4
Internal data bus
SCI
Clock input
enable
Clock output
enable
Clock output
Clock input
Interrupt
controller
inputIRQ
4
Figure C.5 (e) Port 9 Block Diagram (Pin P94)
602
R
P95DDR
C
QD
Reset
WP9D
WP9
RP9
R
P95DR
C
QD
Reset
P95
SCI
Clock input
enable
Clock output
enable
Clock output
Interrupt controller
IRQ5
input
Clock input
: Write to P9DDR
: Write to port 9
: Read port 9
WP9D
WP9
RP9
Internal data bus
Hardware standby
Figure C.5 (f) Port 9 Block Diagram (Pin P95)
603
C.6 Port A Block Diagrams
WPAD:
WPA:
RPA:
n = 0, 1
Write to PADDR
Write to port A
Read port A
PA
n
WPAD
Reset
Hardware standby QD
R
C
PA DDR
n
Reset
QD
R
C
PA DR
n
RPA
WPA
Internal data bus
TPC
output
enable
TPC
Next data
Output
trigger
Counter
clock input
16-bit timer
Counter
clock input
8-bit timer
Figure C.6 (a) Port A Block Diagram (Pins PA0 and PA1)
604
WPAD:
WPA:
RPA:
n = 2, 3
Write to PADDR
Write to port A
Read port A
PAn
RPA
WPA
WPAD
Reset
QD
R
C
PA DDR
n
Reset
QD
R
C
PA DR
n
Internal data bus
TPC
output
enable
TPC
Next
data
Output
trigger
Output
enable
Compare
match
output
Input
capture
Counter
clock
input
16-bit timer
Counter
clock input
8-bit timer
Hardware standby
Figure C.6 (b) Port A Block Diagram (Pins PA2 and PA3)
605
WPAD:
WPA:
RPA:
SSOE:
n = 4 to 7
Note: The PA7 address output enable setting is fixed at 1 in modes 3 and 4.
Write to PADDR
Write to port A
Read port A
Software standby output port enable
PAn
WPAD
Reset
RPA
WPA
QD
R
C
PAnDDR
Reset
QD
R
C
PAnDR
Internal address bus
Internal data bus
TPC
16-bit timer
TPC output
enable
Next data
Output trigger
Output enable
Compare match
output
Input capture
Software standby
SSOE
Bus released
Modes 3 and 4
Address output enable
Hardware
standby
Figure C.6 (c) Port A Block Diagram (Pins PA4 to PA7)
606
C.7 Port B Block Diagrams
PBn
WPBD:
WPB:
RPB:
SSOE:
n = 0 , 2
Write to PBDDR
Write to port B
Read port B
Software standby output port enable
Reset
QD
R
C
PB DDR
n
WPBD
Reset
QD
R
C
PB DR
n
WPB
RPB
Internal data bus
TPC output
enable
TPC
Next data
Output trigger
Output enable
Compare
match output
8-bit timer
Mode
1 to 5
Bus released
Bus controller
CS output enable
CS7
CS5 output
Software standby
Hardware
standby
SSOE
Figure C.7 (a) Port B Block Diagram (Pins PB0 and PB2)
607
R
PBnDDR
C
QD
Reset
Mode
1 to 5
WPBD
WPB
RPB
R
PBnDR
C
QD
Reset
PBnTPC
8-bit timer
TPC output enable
Bus controller
CS output enable
CS6
CS4 output
Next data
Output trigger
Output enable
Compare match output
TMO2
TMO3 input
Write to PBDDR
Write to port B
Read port B
Software standby output port enable
WPBD:
WPB:
RPB:
SSOE:
n = 1, 3
Bus released
Software standby
SSOE
Internal data bus
Hardware
standby
Figure C.7 (b) Port B Block Diagram (Pins PB1 and PB3)
608
PB4
WPBD:
WPB:
RPB:
Write to PBDDR
Write to port B
Read port B
WPB
RPB
Reset
QD
R
C
PB DDR
Hardware standby
4
WPBD
Reset
QD
R
C
PB DR
4
Internal data bus
TPC output
enable
Next data
Output trigger
TPC
Figure C.7 (c) Port B Block Diagram (Pin PB4)
609
R
PB5DDR
C
QD
Reset
WPBD
WPB
RPB
R
PB5DR
C
QD
Reset
PB5
TPC
TPC output enable
Next data
Output trigger
Write to PBDDR
Write to port B
Read port B
WPBD:
WPB:
RPB:
Internal data bus
Hardware standby
Figure C.7 (d) Port B Block Diagram (Pin PB5)
610
WPBD
Reset
Reset
QD
R
C
PB DDR
QD
R
C
PB DR
6
RPB
WPB
TPC
WPBD:
WPB:
RPB:
Write to PBDDR
Write to port B
Read port B
TPC
output
enable
Next data
Output
trigger
Internal data bus
6
PB6
Hardware standby
Figure C.7 (e) Port B Block Diagram (Pin PB6)
611
PB7
WPBD
Reset
Reset
QD
R
C
PB DDR
QD
R
C
PB DR
7
RPB
WPB
TPC
WPBD:
WPB:
RPB:
Write to PBDDR
Write to port B
Read port B
TPC
output
enable
Next data
Output
trigger
Internal data bus
7
Hardware standby
Figure C.7 (f) Port B Block Diagram (Pin PB7)
612
Appendix D Pin States
D.1 Port States in Each Mode
Table D.1 Port States
Pin
Name Mode Reset
Hardware
Standby
Mode Software
Standby Mode Bus-
Released Mode Program
Execution Mode
A7 to A0— L T (SSOE = 0)
T
(SSOE = 1)
Keep
TA
7 to A0
A15 to A8— L T (SSOE = 0)
T
(SSOE = 1)
Keep
TA
15 to A8
D15 to D8—TT T T D
15 to D8
P47 to P401, 3 T T Keep Keep I/O port
2, 4 T T T T D7 to D0
A19 to A16 —LT (SSOE = 0)
T
(SSOE = 1)
Keep
TA
19 to A16
P60— T T Keep Keep I/O port
WAIT
P61— T T (BRLE = 0)
Keep
(BRLE = 1)
T
T I/O port
BREQ
P62— T T (BRLE = 0)
Keep
(BRLE = 1)
H
L (BRLE = 0)
I/O port
(BRLE = 1)
BACK
AS, RD,
HWR, LWR — H T (SSOE = 0)
T
(SSOE = 1)
H
TAS, RD, HWR,
LWR
P67— Clock
output T (PSTOP = 0)
H
(PSTOP = 1)
Keep
(PSTOP = 0)
φ
(PSTOP = 1)
Keep
(PSTOP = 0)
φ
(PSTOP = 1)
Input port
613
Pin
Name Mode Reset
Hardware
Standby
Mode Software
Standby Mode Bus-
Released Mode Program
Execution Mode
P77 to P70— T T T T Input port
P80— T T Keep — I/O port
P81— T T (DDR=0)
T
(DDR=1, SSOE=0)
T
(DDR=1, SSOE=1)
H
(DDR=0)
Keep
(DDR=1)
T
(DDR=0)
Input port
(DDR=1)
CS3
P82— T T (DDR=0)
T
(DDR=1, SSOE=0)
T
(DDR=1, SSOE=1)
H
(DDR=0)
Keep
(DDR=1)
T
(DDR=0)
Input port
(DDR=1)
CS2
P83— T T (DDR=0)
T
(DDR=1, SSOE=0)
T
(DDR=1, SSOE=1)
H
(DDR=0)
Keep
(DDR=1)
T
(DDR=0)
Input port
(DDR=1)
CS1
P84— H T (DDR=0)
T
(DDR=1, SSOE=0)
T
(DDR=1, SSOE=1)
H
(DDR=0)
Keep
(DDR=1)
T
(DDR=0)
Input port
(DDR=1)
CS0
P95 to P90— T T Keep Keep I/O port
PA3 to PA0— T T Keep Keep I/O port
PA6 to PA41, 2 T T Keep Keep I/O port
3, 4 T T (Address output)*1
(SSOE = 0)
T
(SSOE = 1)
Keep
(Otherwise)*2
Keep
(Address output)*1
T
(Otherwise)*2
Keep
(Address output)*1
A23 to A21
(Otherwise)*2
I/O port
614
Pin
Name Mode Reset
Hardware
Standby
Mode Software
Standby Mode Bus-
Released Mode Program
Execution Mode
PA71, 2 T T Keep Keep I/O port
3, 4 L T (SSOE = 0)
T
(SSOE = 1)
Keep
TA
20
PB3 to PB0—TT (CS output)*3
(SSOE = 0)
T
(SSOE = 1)
H
(Otherwise)*4
Keep
(CS output)*3
T
(Otherwise)*4
Keep
(CS output)*3
CS7 to CS4
(Otherwise)*4
I/O port
PB7 to PB4— T T Keep Keep I/O port
Legend:
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1. When A23E, A22E, A21E = 0 in BRCR (bus release control register).
2. When A23E, A22E, A21E = 1 in BRCR (bus release control register).
3. When CS7E, CS6E, CS5E, CS4E = 1 in CSCR (chip select control register).
4. When CS7E, CS6E, CS5E, CS4E = 0 in CSCR (chip select control register).
615
D.2 Pin States at Reset
Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an
external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state.
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. Clock pin P67/φ goes to the output state at the next rise of φ after RES goes low.
AS, RD
(read)
D15 to D0
(write)
HWR, LWR
(write)
Internal reset
signal
RES
P67/φ
I/O port,
CS7 to CS1
CS0
A19 to A0
T1T2T3
Access to external
memory
H'00000
High impedance
High impedance
Figure D.1 Reset during Memory Access (Modes 1 and 2)
616
Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an
external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state.
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. However, when PA4 to PA6 are used as address bus pins, or when P83 to P81 and PB0
to PB3 are used as CS output pins, they go to the high-impedance state at the same time as RES
goes low. Clock pin P67/φ goes to the output state at the next rise of φ after RES goes low.
T1T2T3
Access to external
memory
H'00000
High impedance
High impedance
AS, RD
(read)
D15 to D0
(write)
HWR, LWR
(write)
Internal reset
signal
RES
P67/φ
I/O port,
PA4/A23 to PA6/A21,
CS7 to CS1
CS0
A20 to A0
Figure D.2 Reset during Memory Access (Modes 3 and 4)
617
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. RES must remain low
until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
t1≥ 10tcyc t2≥ 0 ns
STBY
RES
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, RES does not have to be
driven low as in (1).
Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
RES
t≥100 ns tOSC
618
Appendix F Product Code Lineup
Table F.1 H8/3008 Product Code Lineup
Product Type Product Code Mark Code Package
(Hitachi Package Code)
H8/3008 ROMless 5 V HD6413008F HD6413008F 100-pin QFP (FP-100B)
HD6413008TE HD6413008TE 100-pin TQFP (TFP-100B)
HD6413008FP HD6413008FP 100-pin QFP (FP-100A)
3 V HD6413008VF HD6413008VF 100-pin QFP (FP-100B)
HD6413008VTE HD6413008VTE 100-pin TQFP (TFP-100B)
HD6413008VFP HD6413008VFP 100-pin QFP (FP-100A)
619
Appendix G Package Dimensions
Figure G.1 shows the FP-100B package dimensions of the H8/3008. Figure G.2 shows the TFP-
100B package dimensions. Figure G.3 shows the FP-100A package dimensions.
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-100B
—
Conforms
1.2 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.10
16.0 ± 0.3
1.0
0.5 ± 0.2
16.0 ± 0.3
3.05 Max
75 51
50
26
125
76
100
14
0° – 8°
0.5
0.08 M
*0.22 ± 0.05
2.70
*0.17 ± 0.05
0.12
+0.13
–0.12
1.0
0.20 ± 0.04
0.15 ± 0.04
Figure G.1 Package Dimensions (FP-100B)
620
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
TFP-100B
—
Conforms
0.5 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
16.0 ± 0.2
14
0.08
0.10 0.5 ± 0.1
16.0 ± 0.2
0.5
0.10 ± 0.10
1.20 Max
*0.17 ± 0.05
0° – 8°
75 51
125
76
100 26
50
M
*0.22 ± 0.05
1.0
1.00
1.0
0.20 ± 0.04
0.15 ± 0.04
Figure G.2 Package Dimensions (TFP-100B)
621
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-100A
—
—
1.7 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.13 M
0° – 10°
*0.32 ± 0.08
*0.17 ± 0.05
3.10 Max
1.2 ± 0.2
24.8 ± 0.4
20
80 51
50
31
30
1
100
81
18.8 ± 0.4
14
0.15
0.65
2.70
2.4
0.20
+0.10
–0.20
0.58 0.83
0.30 ± 0.06
0.15 ± 0.04
Figure G.3 Package Dimensions (FP-100A)
622
Appendix H Comparison of H8/300H Series Product
Specifications
H.1 Differences between H8/3067 and H8/3062 Series, H8/3048 Series,
H8/3006 and H8/3007, and H8/3008
Item H8/3067, H8/3062
Series H8/3048
Series H8/3006, H8/3007 H8/3008
1 Operating
mode Mode 5 16 Mbyte ROM
enabled expanded
mode
1 Mbyte
ROM
enabled
expanded
mode
Mode 6 64 kbyte single-chip
mode 16 Mbyte
ROM
enabled
expanded
mode
2 Interrupt
controller Internal
interrupt
sources
36 (H8/3067)
27 (H8/3062 Series) 30 36 27
3 Bus
controller Burst ROM
interface Yes (H8/3067)
No (H8/3062 Series) No Yes No
Idle cycle
insertion
function
Yes No Yes Yes
Wait mode 2 modes 4 modes 2 modes 2 modes
Wait state
number
setting
Per area Common
to all
areas
Per area Per area
Address
output
method
Choice of address
update mode (fixed in
H8/3067F-ZTAT and
H8/3062F-ZTAT)
Fixed Fixed Choice of address
update mode
4 DRAM
interface Connectable
areas Area 2/3/4/5
(H8/3067 only) Area 3 Area 2/3/4/5 No
Precharge
cycle
insertion
function
Yes (H8/3067 only) No Yes No
Fast page
mode Yes (H8/3067 only) No Yes No
Address
shift amount 8 bit/9 bit/10 bit
(H8/3067 only) 8 bit/9 bit 8 bit/9 bit/10 bit No
623
Item H8/3067, H8/3062
Series H8/3048
Series H8/3006, H8/3007 H8/3008
5 Timer functions 16-bit
timers 8-bit
timers ITU 16-bit
timers 8-bit
timers 16-bit
timers 8-bit
timers
Number of
channels 16 bits × 3 8 bits × 4
(16 bits
× 2)
16 bits × 5 16 bits × 3 8 bits × 4
(16 bits
× 2)
16 bits × 3 8 bits × 4
(16 bits
× 2)
Pulse output 6 pins 4 pins
(2 pins) 12 pins 6 pins 4 pins
(2 pins) 6 pins 4 pins
(2 pins)
Input capture 6 2 10 6262
External
clock 4 systems
(selec-
table)
4 systems
(fixed) 4 systems
(selec-
table)
4 systems
(selec-
table)
4 systems
(fixed) 4 systems
(selec-
table)
4 systems
(fixed)
Internal clock φ, φ/2, φ/4,
φ/8 φ/8, φ/64,
φ/8192 φ, φ/2, φ/4,
φ/8 φ, φ/2, φ/4,
φ/8 φ/8, φ/64,
φ/8192 φ, φ/2, φ/4,
φ/8 φ/8, φ/64,
φ/8192
Comple-
mentary
PWM
function
No No Yes No No No No
Reset-
synchronous
PWM
function
No No Yes No No No No
Buffer
operation No No Yes No No No No
Output
initialization
function
Yes No No Yes No Yes No
PWM output 3 4 (2) 5 3 4 (2) 3 4 (2)
DMAC
activation 3 channels
(H8/3067
only)
No 4 channels 3 channels No No
A/D
conversion
activation
No Yes No No Yes Yes
Interrupt
sources 3 sources
× 3 8 sources 3 sources
× 5 3 sources
× 3 8 sources 8 sources
6 TPC Time base 3 kinds, 16-bit timer
base 4 kinds,
ITU base 3 kinds, 16-bit timer
base 3 kinds, 16-bit timer
base
7 WDT Reset
signal
external
output
function
Yes (except products
with on-chip flash
memory)
Yes Yes Yes
624
Item H8/3067, H8/3062
Series H8/3048
Series H8/3006, H8/3007 H8/3008
8 SCI Number of
channels 3 channels (H8/3067)
2 channels (H8/3062
Series)
2 channels 3 channels 2 channels
Smart card
interface Supported on all
channels Supported
on SCI0
only
Supported on all
channels Supported on all
channels
9 A/D
converter Conversion
start trigger
input
External trigger/8-bit
timer compare match External
trigger External trigger/8-bit
timer compare match External trigger/8-bit
timer compare match
Conversion
states 70/134 134/266 70/134 70/134
10 Pin
control φ pin φ/input port
multiplexing φ output
only φ/input port
multiplexing φ output/input port
A20 in 16 MB
ROM
enabled
expanded
mode
A20 / I/O port
multiplexing A20 output
Address bus,
AS, RD,
HWR, LWR,
CS7–CS0,
RFSH in
software
standby
state
High-level output/high-
impedance selectable
(RFSH: H8/3067 only)
High-level
output
(except
CS0)
Low-level
output
(CS0)
High-level output/high-
impedance selectable High-level output/high-
impedance selectable
CS7–CS0 in
bus-released
state
High-impedance High-level
output High-impedance High-impedance
11 Flash
memory
functions
Program/
erase
voltage
12 V application
unnecessary.
Single-power-supply
programming.
12 V
application
from off-
chip
Block
divisions 8 blocks (12 blocks in
H8/3064F-ZTAT) 16 blocks
625
H.2 Comparison of Pin Functions of 100-Pin Package Products
(FP-100B, TFP-100B)
Table H.1 Pin Arrangement of Each Product (FP-100B, TFP-100B)
On-chip-ROM Products ROMless Products
Pin
No. H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006,
H8/3007 H8/3008
1 VCC VCC/VCL*2VCC VCC VCC VCC/VCL*2
2 PB0/TP8/TMO0/
CS7
PB0/TP8/TMO0/
CS7
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/TMO0/
CS7
PB0/TP8/TMO0/
CS7
3 PB1/TP9/TMIO1/
DREQ0/CS6
PB1/TP9/TMIO1/
CS6
PB1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/TMIO1/
DREQ0/CS6
PB1/TP9/TMIO1/
CS6
4 PB2/TP10/TMO2/
CS5
PB2/TP10/TMO2/
CS5
PB2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/TMO2/
CS5
PB2/TP10/TMO2/
CS5
5 PB3/TP11/
TMIO3/DREQ1/
CS4
PB3/TP11/
TMIO3/CS4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
PB3/TP11/
TMIO3/DREQ1/
CS4
PB3/TP11/
TMIO3/CS4
6 PB4/TP12/
UCAS PB4/TP12 PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
UCAS PB4/TP12
7 PB5/TP13/
LCAS/SCK2
PB5/TP13 PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
LCAS/SCK2
PB5/TP13
8 PB6/TP14/TxD2PB6/TP14 PB6/TP14/
DREQ0/CS7
PB6/TP14/
DREQ0
PB6/TP14/TxD2PB6/TP14
9 PB7/TP15/RxD2PB7/TP15 PB7/TP15/
DREQ1/ADTRG PB7/TP15/
DREQ1/ADTRG PB7/TP15/RxD2PB7/TP15
10 RESO/FWE*1RESO/FWE*1RESO/VPP RESO RESO NC/RESO
11 Vss Vss Vss Vss Vss Vss
12 P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0
13 P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1
14 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0
15 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1
16 P94/SCK0/IRQ4P94/SCK0/IRQ4P94/SCK0/IRQ4P94/SCK0/IRQ4P94/SCK0/IRQ4P94/SCK0/IRQ4
17 P95/SCK1/IRQ5P95/SCK1/IRQ5P95/SCK1/IRQ5P95/SCK1/IRQ5P95/SCK1/IRQ5P95/SCK1/IRQ5
18 P40/D0P40/D0P40/D0P40/D0P40/D0P40/D0
19 P41/D1P41/D1P41/D1P41/D1P41/D1P41/D1
20 P42/D2P42/D2P42/D2P42/D2P42/D2P42/D2
21 P43/D3P43/D3P43/D3P43/D3P43/D3P43/D3
22 Vss Vss Vss Vss Vss Vss
23 P44/D4P44/D4P44/D4P44/D4P44/D4P44/D4
24 P45/D5P45/D5P45/D5P45/D5P45/D5P45/D5
626
On-chip-ROM Products ROMless Products
Pin
No. H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006,
H8/3007 H8/3008
25 P46/D6P46/D6P46/D6P46/D6P46/D6P46/D6
26 P47/D7P47/D7P47/D7P47/D7P47/D7P47/D7
27 P30/D8P30/D8P30/D8P30/D8D8D8
28 P31/D9P31/D9P31/D9P31/D9D9D9
29 P32/D10 P32/D10 P32/D10 P32/D10 D10 D10
30 P33/D11 P33/D11 P33/D11 P33/D11 D11 D11
31 P34/D12 P34/D12 P34/D12 P34/D12 D12 D12
32 P35/D13 P35/D13 P35/D13 P35/D13 D13 D13
33 P36/D14 P36/D14 P36/D14 P36/D14 D14 D14
34 P37/D15 P37/D15 P37/D15 P37/D15 D15 D15
35 Vcc Vcc Vcc Vcc Vcc Vcc
36 P10/A0P10/A0P10/A0P10/A0A0A0
37 P11/A1P11/A1P11/A1P11/A1A1A1
38 P12/A2P12/A2P12/A2P12/A2A2A2
39 P13/A3P13/A3P13/A3P13/A3A3A3
40 P14/A4P14/A4P14/A4P14/A4A4A4
41 P15/A5P15/A5P15/A5P15/A5A5A5
42 P16/A6P16/A6P16/A6P16/A6A6A6
43 P17/A7P17/A7P17/A7P17/A7A7A7
44 Vss Vss Vss Vss Vss Vss
45 P20/A8P20/A8P20/A8P20/A8A8A8
46 P21/A9P21/A9P21/A9P21/A9A9A9
47 P22/A10 P22/A10 P22/A10 P22/A10 A10 A10
48 P23/A11 P23/A11 P23/A11 P23/A11 A11 A11
49 P24/A12 P24/A12 P24/A12 P24/A12 A12 A12
50 P25/A13 P25/A13 P25/A13 P25/A13 A13 A13
51 P26/A14 P26/A14 P26/A14 P26/A14 A14 A14
52 P27/A15 P27/A15 P27/A15 P27/A15 A15 A15
53 P50/A16 P50/A16 P50/A16 P50/A16 A16 A16
54 P51/A17 P51/A17 P51/A17 P51/A17 A17 A17
55 P52/A18 P52/A18 P52/A18 P52/A18 A18 A18
56 P53/A19 P53/A19 P53/A19 P53/A19 A19 A19
57 Vss Vss Vss Vss Vss Vss
58 P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT
627
On-chip-ROM Products ROMless Products
Pin
No. H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006,
H8/3007 H8/3008
59 P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ
60 P62/BACK P62/BACK P62/BACK P62/BACK P62/BACK P62/BACK
61 P67/φP67/φ φ φ P67/φP67/φ
62 STBY STBY STBY STBY STBY STBY
63 RES RES RES RES RES RES
64 NMI NMI NMI NMI NMI NMI
65 Vss Vss Vss Vss Vss Vss
66 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL
67 XTAL XTAL XTAL XTAL XTAL XTAL
68 Vcc Vcc Vcc Vcc Vcc Vcc
69 P63/AS P63/AS P63/AS P63/AS AS AS
70 P64/RD P64/RD P64/RD P64/RD RD RD
71 P65/HWR P65/HWR P65/HWR P65/HWR HWR HWR
72 P66/LWR P66/LWR P66/LWR P66/LWR LWR LWR
73 MD0MD0MD0MD0MD0MD0
74 MD1MD1MD1MD1MD1MD1
75 MD2MD2MD2MD2MD2MD2
76 AVcc AVcc AVcc AVcc AVcc AVcc
77 VREF VREF VREF VREF VREF VREF
78 P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0
79 P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1
80 P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2
81 P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3
82 P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4
83 P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5
84 P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0
85 P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1
86 AVss AVss AVss AVss AVss AVss
87 P80/RFSH/IRQ0P80/IRQ0P80/RFSH/IRQ0P80/RFSH/IRQ0P80/RFSH/IRQ0P80/IRQ0
88 P81/CS3/IRQ1P81/CS3/IRQ1P81/CS3/IRQ1P81/CS3/IRQ1P81/CS3/IRQ1P81/CS3/IRQ1
89 P82/CS2/IRQ2P82/CS2/IRQ2P82/CS2/IRQ2P82/CS2/IRQ2P82/CS2/IRQ2P82/CS2/IRQ2
90 P83/CS1/IRQ3/
ADTRG P83/CS1/IRQ3/
ADTRG P83/CS1/IRQ3P83/CS1/IRQ3P83/CS1/IRQ3/
ADTRG P83/CS1/IRQ3/
ADTRG
91 P84/CS0P84/CS0P84/CS0P84/CS0P84/CS0P84/CS0
92 Vss Vss Vss Vss Vss Vss
628
On-chip-ROM Products ROMless Products
Pin
No. H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3006,
H8/3007 H8/3008
93 PA0/TP0/
TEND0/TCLKA PA0/TP0/TCLKA PA0/TP0/
TEND0/TCLKA PA0/TP0/
TEND0/TCLKA PA0/TP0/
TEND0/TCLKA PA0/TP0/
TCLKA
94 PA1/TP1/
TEND1/TCLKB PA1/TP1/TCLKB PA1/TP1/
TEND1/TCLKB PA1/TP1/
TEND1/TCLKB PA1/TP1/
TEND1/TCLKB PA1/TP1/
TCLKB
95 PA2/TP2/
TIOCA0/TCLKC PA2/TP2/
TIOCA0/TCLKC PA2/TP2/
TIOCA0/TCLKC PA2/TP2/
TIOCA0/TCLKC PA2/TP2/
TIOCA0/TCLKC PA2/TP2/
TIOCA0/TCLKC
96 PA3/TP3/
TIOCB0/TCLKD PA3/TP3/
TIOCB0/TCLKD PA3/TP3/
TIOCB0/TCLKD PA3/TP3/
TIOCB0/TCLKD PA3/TP3/
TIOCB0/TCLKD PA3/TP3/
TIOCB0/TCLKD
97 PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1/CS6/A23
PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1/A23
98 PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1/CS5/A22
PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1/A22
99 PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2/CS4/A21
PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2/A21
100 PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
Notes: 1. Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash
memory versions.
2. The 5 V operation models of the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask
version have a VCL pin, and require an external capacitor (0.1 µF).
H8/3008 Hardware Manual
Publication Date: 1st Edition, September 2000
Published by: Electronic Devices Sales & Marketing Group
Semiconductor & Integrated Circuits
Hitachi, Ltd.
Edited by: Technical Documentation Group
Hitachi Kodaira Semiconductor Co., Ltd.
Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
