ICS960002
0677A—07/03/02
Integrated
Circuit
Systems, Inc.
Block Diagram
Power PC Based LBP
Pentium is a trademark on Intel Corporation.
XTAL
OSC
PLL1
Spread
Spectrum
PLL2
Control Logic
Configuration
Resistor
USB
DIV 2
SSC [1:0]
USB_EN
CLK_SEL [1:0]
PCI_EN
ASIC2_EN
ASIC_SE
L
XIN
XOUT
CPU
ASIC1
ASIC2 (A, B)
PCI (1:0)
STOP
PCI
Divider
CPU
Divider
VDDCOR, DIG, USB=3.3V VDDCPU, ASIC1, ASIC2, PCI = 2.5V or3.3V
4
2
3
3
4
GNDCPU, ASIC1, ASIC2, PCI= 0VGNDCOR, DIG, USB=0V
2
Features
- CP U, AS IC, and PCI can run at 2.5V or 3.3V select abl e.
- Generat es t he fol l owing system cl oc ks:
1-CP U (2. 5V /3.3V) (66. 66MHz to 100.00M Hz)
2-P CI (2. 5V /3.3V) (33. 33M Hz )
2-A S IC (2. 5V /3.3V) (66. 66MHz to 100. 00M Hz )
1-A S IC (2. 5V /3.3V) (33. 33MHz to 100. 00M Hz )
1-US B (3 .3 V ) (4 8M Hz)
- S K EW Charac teristics:
CPU to ASIC < 250ps
- Ji tte r Characte ri stics
CPU/ASIC <150ps (cycle to cycle)
-S pread Spectrum features
Off
-0.5%, 1.0%, and 1. 25% Downspread
- P ower Managem ent
E nable/Dis able P CI , A S IC2, and/or US B i ndependant ly
- Uses ext ernal 14. 318M Hz crys tal or ref erenc e cl oc k
VDD GND
6, 7 1, 18 3. 3V Int er nal Logic and Cor e Power
8 11 PCI output s
14 12 USB out put s
19 21 ASI C1 output s
25 22 ASI C2 output s
26 28 CPU ouput s
Pin Number Description
Power Groups
GNDCOR 1 28 GND
SSC1/ASIC_3.3V_2.5# 2 27 CPUCLK0
SSC0/CPU_3.3V_2.5# 3 26 VDDCPU
X1 4 25 VDDASIC2
X2 5 24 ASIC2A/ASIC2A_EN*
VDDCOR 6 23 ASIC2B
VDDDIG 7 22 GND
VDDPCI 8 21 GND
PCICLK0/PCI_3.3V_2.5# 9 20 ASIC1
PCICLK1/PCI_EN* 10 19 VDDASIC1
GND 11 18 GND
GND 12 17 ASIC1_SEL*
USB0/USB_EN* 13 16 CLK_SEL1
VDDUSB 14 15 CLK_SEL0
ICS60002
Pin Configuration
Note: * 60Kohm to 120K ohm Internal Pullup Resistor
209Mil SSOP
2
ICS960002
0677A—07/03/02
Pin Descriptions
PIN # PIN NAME PIN TYPE DESCRIPTION
1 GNDCOR PWR Ground pin for the PLL core.
2 S SC1/ASIC _3.3V_2.5# IN S pread S pectrum amplitude c ontrol with ASIC 3.3V/2.5V# select.
3 S SC0/C PU_3.3V_2.5# IN S pread S pectrum amplitude c ontrol with CP U 3.3V/2.5V# selec t.
4 X1 IN Crystal input,nom inally 14.318M Hz.
5 X2 OUT Cr ys tal output, nominally 14 .318M Hz.
6 VDDCOR PWR 3.3V power for the PLL core.
7 VDDDIG PWR 3.3V internal digital pow er.
8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
9 PCICL K0/PCI_3.3 V_2 .5# I/O PCI clock o utp u t with CPU 3.3 V/2.5V# select.
10 PCICL K1 /PCI _ EN* I/O PCI clock o utp u t with latched PCI e n ab le function a t startu p .
11 GND P WR Ground pin for 3V outputs .
12 GND P WR Ground pin for 3V outputs.
13 USB 0/US B_E N* I/O US B cloc k output with latched U SB enable func tion at startup.
14 VDDUSB PWR Supply for USB clocks,3.3V nominal
15 CLK_S EL0 IN Function select pin. See table for details .
16 CLK_S EL1 IN Function select pin. See table for details .
17 AS IC1_S EL* IN Function select pin. S ee table for details.
18 GND P WR Ground pin for 3V outputs.
19 VDDASIC 1 P WR Supply for A SIC 1clocks,3.3V nominal
20 AS IC1 OUT ASIC1 clock output.
21 GND P WR Ground pin for 3V outputs.
22 GND P WR Ground pin for 3V outputs.
23 ASIC 2B O U T ASIC 2B clock output.
24 ASIC2A/ASIC2A_EN* I/O ASIC2A c lock output with latc hed P CI enable function at startup.
25 VDDASIC 2 P WR S upply for ASIC 2 cloc ks ,3.3V nominal
26 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
27 CPUCLK0 OUT CPU cloc k outputs.
28 GND P WR Ground pin for 3V outputs.
NOTE: Internal pull-up res itors on pin 10, 13, 17, and 24. No internal res is tor for pin 2, 3, 9, 15 or 16.
3
ICS960002
0677A—07/03/02
Frequency Tabl es
ASIC1_SEL=1 ASIC1_SEL=0
0 0 66.66 66.66 33.33 66.66
0 1 100.00 100.00 50.00 100.00
1 0 83.33 83.33 41.67 83.33
1 1 88.88 88.88 44.44 88.88
CLK_SEL1 CLK_SEL0 ASIC1 (MHz )
CPU (MHz ) ASIC2 [A, B]
(MHz)
Spread Spectr um Sel ect i on Tabl e
SSC1 SSC0
00
01
10
11
-0.50% Down Spread
-1.00% Down Spread
-1.25% Down Spread
Spr ead Spectrum Modulation [MHz]
OFF
Power M a nage m en t Ta ble
USB_EN PCI_EN ASIC2_EN USB PCICLK(1,0) ASIC2
0XX
Tri-state XX
1XX
48MHz XX
X0X XTri-state X
X1X X33.3MHz X
XX0 X X
Tri-state
XX1 X X
SELECTED
4
ICS960002
0677A—07/03/02
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses abov e those listed under
Absolute Maximum Ratings
ma y cause permanent damage to the de vice. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
f or e xtended periods may aff ect product reliability.
Elect r i cal Charact er i sti cs - AC Speci f i cat i on
TA = 0 - 70º C; V DD = 3. 3 V or 2. 5V +/-5% ; CL=20pF(unl es s ot herwise stat ed)
PARAMETERS SYMBO
LCONDITIONS MIN. TYP. MAX. UNITS
I nput F requenc y ZO14.31818 MHz
SST modulation sweep rate fmod 32.2 kHz
Out put Ri s e T i m e tr2B 0.8V to 2.0V with no load 0.5 1.5 ns
Output Fall Time tf2B 2.0V to 0.8V with no load 0.5 1.5 ns
Duty Cycl e dt2B At VDD/2 45 50 55 %
CPU and ASI C Skew tsk2B
Equal Power Supply for both
ASICandCPUatsame
Frequenc y; Cl = 20 pF 200 250 ps
Max. Absolute Period Jitter tjitabs2B CP U and ASIC onl y . -150 150 ps
Max. Jitter, cycle to cycle tjcyc-cyc2B CP U and A S I C onl y . 90 120 ps
5
ICS960002
0677A—07/03/02
Elect r i cal Charact er i stics - DC Speci f i cat i on
TA = 0 - 70º C; V DD = S ee tabl e below; CL = 20 pF (unless otherwise st ated)
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
VDDCOR
VDDDIG
VDDUSB
VDDPCI
VDDASIC1
VDDASIC2
VDDCPU
I nput High Vol t age V IH F or all normal i nput 2 V DD+0.3 V
I nput Low V ol t age V IL F or all normal i nput V SS-0.3 0.8 V
Output High Vol t age VOH IOH = -25mA 2.4 V
Output Low Voltage VOL I OL = 25mA 0. 4 V
Operat i ng S upply
Current IDD No Load 35 50 mA
3.63 V
V
V
2.75
3.63
Operat ing V ol t age
Nomi nal voltage i s
3.3V 2.97 3.3V
Nomi nal voltage i s
3. 3V or 2. 5V
2.25 2.5V
2.97 3.3V
6
ICS960002
0677A—07/03/02
Fig. 1
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K W
8.2K W
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of P ower-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register f or
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used both to
provide the solid CMOS programming voltage needed
during the power-up programming period and to provide
an insignificant load on the output clock during the
subsequent operating period.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. When no jumper
is installed the pin will be pulled high. With the jumper in
place the pin will be pulled low . If programmability is not
necessary , then only a single resistor is necessary . The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
7
ICS960002
0677A—07/03/02
Ordering Information
ICS960002
α
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
209 mil SSOP
MIN MAX MIN MAX
A--2.00--.079
A1 0.05 -- .002 --
A2 1.65 1.85 .065 .073
b 0.22 0.38 .009 .015
c 0.09 0.25 .0035 .010
D
E 7.40 8.20 .291 .323
E1 5.00 5.60 .197 .220
e
L 0.55 0.95 .022 .037
N
α0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
28 9.90 10.50 .390 .413
10-0033
Reference Doc.: JEDEC Publication 95,M O-150
SEE VARIATIONS SEE VARIATIONS
NDmm. D(inch)
SEE VARIATIONS SEE VARIATIONS
0.65 BASIC 0.0256 BASIC
209 mil SSOP
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Designation for tape and reel packaging
Packag e Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Example:
ICS XXXX y F - T
