"The new 0.8m Standard Cell family from AMI delivers superior performance and flexibility . . . one of the lowest cost and highest performance 0.8m standard cell ASIC products available today . . ." Designed for 3V, 5V, or 3V/5V mixed supplies 205 ps gate delays (fanout = 2) Double and Triple Metal Interconnect; up to 700,000 gate designs using megacells, ROM, RAM, and logic. Complete package lineup quad flatpack (QFP), LCC, DIP, grid array . . . Usable megacells Families of single and dual port RAMs, ROMs, microprocessors, controllers, datapath functions . . . "Made in America" engineering, manufacturing, and support No `overseas' delays to your important questions; we're right here, ready to help. Table of Contents Features....................................................................................... 1 AMI8Sx Standard Cell Family Overview .......................................... 1 Architectural Overview .................................................................. 2 Product Applications ..................................................................... 3 ASIC Design Tools and Methodology ............................................. 3 The Design Library ........................................................................ 5 DC Specifications ........................................................................ 6 Library Cell Selection Guide ................................................... 8 - 21 Delay Derating Information ............................................................ 22 Packaging .................................................................................... 23 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 AMI's "AMI8S" standard cell family continues the AMI leadership tradition of combining true compact building block standard cells and megacells with high speed memory and datapath functions. Using a 0.8 m high performance CMOS process, the AMI8S product can offer a lower cost alternative to gate array for high volume applications. * 1 to 8 mA drive per single I/O cell: Slew rate limiting available for 8mA drive. Custom configurations for I/O drive up to 96mA can be supported. * JTAG Boundary Scan macro support * Cost driven architecture: - Offers both 2 and 3 level metal interconnect to provide the lowest user cost for the number of gates and pads required. - Compiled memory blocks are compacted precisely to parameters. No leaf cell overhead. Features * 3V, 5V, and combined 3V/5V operation: Each individual pad cell can be driven independently by a 3V or 5V supply. 3V to 5V and 5V to 3V level shift is available in the I/O cells. The core can be either 3V for low power or 5V for high speed. * Extensive library for quick design: - 100% compatible with AMI's proven ASIC Standard Library. * Operating Temperature equals -55 to 125 oC: Few competing products allow this range. * Wide range of packaging: Full QFP and LCC line, DIPs and PGAs, individual die, (ball grid array package under study). Burn-in capability as needed. * Excellent performance: - 310 MHz maximum toggle rate on clocked flip-flops (TJ = 135 oC). - 205 ps delay (FO=2; l=2mm) for a 2-input NAND gate. * Automatic Test Program Generation: Includes scan macros (NETSCANTM) for high fault coverage. * Full operating voltage range from 2.7V to 5.5V * Clock tree generation: 400 ps clock skew (fan out = 3500 at 80 MHz). * ESD protection > 2kV; latchup > 100mA * Power is 3.1 W/MHz/gate (FO=2; VDD=5V) AMI8S Standard Cell Family Overview Feature Description Comment gates1 Up to 700,000 Up to 410,000 gates 50% memory, 50% megacell and user defined logic 100% user defined logic Up to 512 pins Up to 585 pins Test equipment limit; signal pins only Die size limit; includes power supply pins 169ps (Fanout=1, L=0mm) 205ps (Fanout=2, L=2mm) 2 input NAND gate, T=25oC, Vdd=5V 725ps (Fanout=2, L=2mm) CMOS Input buffer, T=25oC, Vdd=5V 1.17ns (CL=15pf) CMOS Output buffer,T=25oC, Vdd=5V MG29C01,MG29C10,MG65C02, MG80C85, MG82Cxx, MGMC51 Functionally compatible with popular standard designs; soft macrocells allow user modifications Datapath Synthesizers xx by yy multipliers, adders, subtracters, FIFOs, barrel shifters,... See page 5 for complete list and details Memory Compilers sync. single port RAM (over 4000 sizes) sync. dual port RAM (over 2000 sizes) sync ROM (over 8000 sizes) asynchronous single port RAM asynchronous dual port RAM Complexity I/O Count Internal Gate Delay Time Input Buffer Output Buffer Megacells Note 1: Compact memory arrays greatly increase gate count on an equivalent gate basis. 1 See page 5 for complete list and details Under development Under development 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 FIGURE 1: STANDARD CELL ARCHITECTURE Compiled memory blocks are individually compacted to minimize area [note 5] RAM BLOCK ROM BLOCK NA21 Vdd,Vss DF101 MG29C01 Soft Megacell Individually compacted cells [note 1] Fixed bus height, variable height and width design Power pad placement as required [note 3] Megacells and datapath functions are built from standard library cells [note 4] Routing channel width varies with local cell routing requirements [note 2] Architectural Overview Some important elements of the AMI8S standard cell family are: * Drawn gate length of 0.8 micron; 2 or 3 level metal interconnect selectable. unused channels are not lost as in gate array or embedded array products. For 3 level metal, this feature can combine with routing over cells to give a very area efficient design. * [Note 1] Each cell function is tightly compacted to a fixed bus height. Cells are then placed in rows allowing Vdd and Vss supplies to feed through the cells. Since some functions require more gates than others, their widths and heights may increase to allow for the added gates. Transistor sizes and routing are optimized for their function, giving a much tighter cell design than with gate arrays or fixed pad ring embedded array products. * [Note 3] Power pads are placed as required among I/O cells and can be placed in corners. Core power can be either 3V or 5V. Each individual I/O can be powered to 3V or 5V. Operating voltage range is 2.7V to 5.5V. * [Note 4] AMI's megacells and compiled datapath functions are soft cells. They are placed as if part of the customer defined logic. Full netlists are provided allowing modification by the customer for his design. * [Note 5] Compiled memory blocks are tightly compacted to the customers' defined parameters. * [Note 2] Rows of cells can be placed adjacently if little routing is required between them, or largely separated to allow a large data bus to route through. Tracks of 2 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 3 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 AMI Design Flow (cont) Working with an AMI design center, the customer is responsible for capturing and verifying the design using the AMI ASIC Standard Library. He is also responsible for creating the test vectors that will eventually serve as the logical part of the manufacturing test. Software aids such as logic synthesis, megacells, automatic test program generation, netlist rule checkers, etc. can greatly speed up this process. (A fault coverage check of the test vector set is optional and can be done as an additional service.) After layout has been completed the interconnect data is extracted from the physical layout to be fed back to the sign-off simulator for final circuit verification. This post layout interconnect data can be sent to the customer for final validation on his simulator. When the post-layout simulation has been completed and approved by the customer the design is then released for mask and wafer fabrication. The test program is developed in parallel using internal automatic test program generation software. Prototypes can then be tested before they are shipped. When the design is received by the factory, the "Design Start Package" is reviewed by AMI engineers. This start package, which is completed by the customer, contains the device specification, netlist, critical timing paths, and test vectors. The design is pre-screened on the Enhanced Design Utilities (EDU) and then resimulated on IKOS, AMI's sign-off simulator. The results are compared to the customer's simulation from the third-party CAE tool. Figure 3 outlines a typical software environment when using third party tools. AMI uses EDIF to speed ports between various software products. AMI's Enhanced Design Utilities Tools are intended to be used interactively at each stage of the design. EDU software is a set of design analysis tools that check both the design and test vectors for correctness and compatibility with in-house ASIC testers, and analyze the design for inefficiencies and possible flaws that could cause problems in manufacturing the device. Once the design has passed the initial screening it is then ready for placement and routing. The layout proceeds by first placing memory and megacells, assigning priority to critical paths, and designing the distribution and buffering of clocks. Next, the layout is completed with automatic place-and-route on the balance of the circuit. FIGURE 3: DESIGN ENVIRONMENT WITH THIRD PARTY SOFTWARE AMI Environment ** AMI ASIC Std. Library Logic Synthesis Memory Compiler HDL Optional Synthesis Tool ** AMI ASIC Stnd. Library Schematic Translation Physical Data Schematic Entry ** Design Database Netlist Translation Third Party Environment ** Enhanced Design Utilities supplied ** Elements in AMI Design Kit Vector Generation Estimated Delays ** Models & Symbols VHDL Timing Simulation Design Verification Place and Route Post Route Verification ATPG 4 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Memory Compiler Library Size Memory Compiler Increment Comments 2K x 32 16 words, 1 bit 1K x 32 16K x 32 2K x 32 1K x 32 16 words, 1 bit 64 words, 1 bit 16 words, 1 bit 16 words, 1 bit 7 ns typical access time on 1Kx16 11 ns typical cycle time on 1Kx16 8 ns typical access time on 1Kx16 4.5 ns typical access time on 256x16 Under development Under development min. max. SRAM (single-port, synchronous) 32 x 1 SRAM (dual-port, synchronous) ROM (synchronous) SRAM (single-port, asynchronous) SRAM (dual-port, asynchronous) 32 x 1 64 x 1 32 x 1 32 x 1 The Design Library Memory Compilers AMI provides a robust collection of building blocks for the AMI8S standard cell family. A broad range of primary cells is complemented with memory cell compilers and useful megafunctions. With such broad, US-based design talent, AMI can quickly design specific cells that customers need to add an edge in customization. The AMI8S family includes the line of memory compilers shown above. Each of the thousands of possible memory blocks is optimized precisely to the customers' parameters rather than built from a presized leaf cell that covers a range of sizes. This yields a better size and performance match for each application. Upon supplying the cell specification to AMI, the customer can receive an accurate simulation timing specification overnight by facsimile and a full simulation model for any AMI supported software environment within five working days. The AMI ASIC Standard Library The AMI ASIC Standard Library contains a rich set of core and pad cells which allow great flexibility in building competitive devices for customer applications. The library is portable across all AMI's gate array and standard cell families. The ASIC Standard Library is listed in detail on pages 9 to 21. Datapath Synthesizers AMI8S also supports the complex datapath functions listed here. These functions are synthesized from an input set of design parameters, and can be optimized for either minimum delay, minimum area or a compromise between the two. Contact AMI for the size range and parameter set for any desired functions. Soft Datapath Library (xx by yy) Name Function MGAxxyyDv Adder MGAxxyyEv Adder-subtracter MGBxxyyAv Arithmetic/barrel shifter MGBxxBv Barrel shifter MGBxxCv Arithmetic shifter MGCxxAv 2-function binary comparator MGCxxBv 6-function binary comparator MGDxxAv Decrementer MGFxxyyC1 Latch-based FIFO MGIxxAv Incrementer MGIxxBv Incrementer/decrementer MGMxxyyDv Signed/unsigned multiplier MGMxxyyEv Multiplier-accumulator MGSxxyyAv Signed/unsigned subtracter These logic synthesizers produce soft megacell schematics in the ASIC Standard Library, and a schematic symbol for incorporation and simulation with the design netlist. Megacells The AMI8S standard cell family supports soft megacell versions of many popular architectures. These products are listed on the following page. Soft megacells are functionally and logically compatible with the standard products of similar names, but are captured in the AMI ASIC Standard Library and are placed and routed with the user's defined logic. AMI supplies an actual gate level netlist and schematic of the soft megacell to the customer allowing him to make design changes or remove unneeded features as required. Test vectors are provided and can be used directly or incorporated into the overall design test. All soft megacells are static designs and use AMI's ASIC Standard Library to ensure portability. 5 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Soft Megacell Library Name Function Name Function MG1468C18 Real-time clock MG82C50A Asynchronous comm. element MG29C01 4-bit microprocessor slice MG82C54 Programmable interval timer MG29C10 Microprogram controller/sequencer MG82C55A Programmable peripheral interface MG65C02 8-bit microprocessor MG82C59A Programmable interrupt controller MG80C85 8-bit microprocessor MGMC51 8-bit microcontroller, 8051 compatible MG82C37A Programmable DMA controller MGMC51FB 8-bit microcontroller, 8051 compatible DC Specifications Operating Specifications Parameter VDD, Supply Voltage Ambient Temperature - Military - Commercial CMOS Input Specifications Minimum Maximum Units 2.7 5.5 Volts -55 125 C 0 70 C 0.3*VDD Volts (4.5V<VDD<5.5V; -55oC<T<125oC) Vil Low Level Input Voltage Vih High Level Input Voltage Iil Low Level Input Current -1.0 A Iih High Level Input Current 1.0 A Iil Input Pull-Up Current -30 -140 A Iih Input Pull-Down Current 30 185 A Vt- Schmitt Negative Threshold Vt+ Schmitt Positive Threshold Vh Schmitt Hysteresis TTL Input Specifications 0.7*VDD Volts 0.2*VDD Volts 0.8*VDD 1.0 Volts Volts (4.5V<VDD<5.5V; -55oC<T<125oC) Vil Low Level Input Voltage 0.8 Vih High Level Input Voltage Iil Low Level Input Current -1.0 A Iih High Level Input Current 1.0 A Iil Input Pull-Up Current -30 -140 A Iih Input Pull-Down Current 30 185 A Vt- Schmitt Negative Threshold 0.7 Vt+ Schmitt Positive Threshold Vh Schmitt Hysteresis 2.0 Volts Volts 2.1 0.4 6 Volts Volts Volts 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Output Operating Specifications (4.5V<VDD<5.5V;0C<T<70C) Parameter Minimum Maximum Units 0.4 Volts 1.0 mA Driver Vol Low Level Output Voltage Voh High Level Output Voltage Iol Low Level Output Current 1.0 mA Ioh High Level Output Current -1.0 mA 0.4 Volts 2.4 Volts 2.0 mA Driver Vol Low Level Output Voltage Voh High Level Output Voltage Iol Low Level Output Current 2.0 mA Ioh High Level Output Current -2.0 mA 0.4 Volts 2.4 Volts 4.0 mA Driver Vol Low Level Output Voltage Voh High Level Output Voltage Iol Low Level Output Current 4.0 mA Ioh High Level Output Current -4.0 mA 0.4 Volts 2.4 Volts 8.0 mA Driver Vol Low Level Output Voltage Voh High Level Output Voltage Iol Low Level Output Current 8.0 mA Ioh High Level Output Current -8.0 mA Maximum Units 2.4 Volts Absolute Maximum Ratings Parameter VDD, Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature - Plastic Packages - Ceramic Packages Minimum -0.3 -0.3 -10.0 -55 -65 Lead Temperature 7.0 VDD+0.3 10.0 125 150 300 Volts Volts mA C C C for 10 sec. Note that these specifications are to indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Further, operation at absolute maximum conditions for extended periods may adversely affect the long term reliability of the device. 7 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Library Cell Selection Guide This selection guide outlines the basic performance of each cell in the AMI ASIC Standard Library. Other custom cells can be created for specific needs. For detailed design analysis please contact an AMI ASIC Design Center for a software design kit and more detailed data sheets. An explanation of the information contained in the selection guide is listed below: Eq. Gates This column lists the equivalent gates of each core cell. It is a measure of the cell size normalized to the area of a 2-input NAND gate. A 2-input NAND gate (NA21) requires four transistors and is an industry standard for comparing gate array and standard cell products. I/O Cells This column lists the number of I/O sites (or pad sites) required to implement the listed I/O cell. Parameters The parameters column lists the mnemonics for the propagation delay or timing parameter whose values are given under "Propagation Delay": Input to output propagation delay for a rising edge on the output tPLH tPHL Input to output propagation delay for a falling edge on the output tZH High impedance to high level delay tZL High impedance to low level delay tsu Input setup time with respect to clock th Input hold time tPZ Valid to high impedance state on the output Propagation Delay This column shows the values of the delay parameter for three different loads. For output pad cells, 25pf, 50pf, and 75pf loads are used. For core cells and input pad cells, fanouts of two, four, and eight gates are used. A fanout consists of that number of NA21 input capacitive loads and an average interconnect capacitance based on past layout experience. Delays are in nanoseconds. Description This final column gives a short textual description of the cell. 8 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Simple Gates Name AA21 AA22 AA31 AA32 AA41 AA42 EN21 EO21 NA21 NA22 NA31 NA32 NA41 NA42 NA51 NA52 NA61 NA81 NO21 NO22 NO31 NO32 NO41 Eq Gates 1.3 1.7 1.7 2.3 2.0 2.3 2.1 2.1 1.0 1.7 1.4 2.2 1.7 3.0 2.0 3.7 3.8 4.7 1.0 1.7 1.4 2.2 1.8 Parameters Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 0.39 0.42 0.39 0.42 0.50 0.54 0.52 0.55 0.58 0.62 0.59 0.63 0.50 0.47 0.62 0.60 0.28 0.23 0.22 0.19 0.37 0.32 0.28 0.23 0.47 0.41 0.37 0.30 0.73 0.66 0.46 0.38 0.74 0.78 0.86 0.87 0.38 0.24 0.27 0.18 0.61 0.29 0.45 0.23 0.50 0.52 0.45 0.48 0.63 0.64 0.59 0.62 0.70 0.74 0.66 0.70 0.69 0.59 0.83 0.70 0.40 0.35 0.28 0.25 0.51 0.46 0.35 0.30 0.62 0.57 0.45 0.39 0.91 0.84 0.55 0.48 0.85 0.89 0.97 0.98 0.58 0.34 0.37 0.23 0.89 0.40 0.59 0.29 0.73 0.70 0.57 0.59 0.87 0.83 0.71 0.73 0.94 0.94 0.79 0.82 1.15 0.83 1.27 0.88 0.65 0.58 0.41 0.37 0.79 0.74 0.50 0.44 0.93 0.90 0.61 0.55 1.26 1.21 0.73 0.66 1.07 1.09 1.21 1.18 0.98 0.53 0.58 0.33 1.45 0.62 0.88 0.41 2-input AND gate tPLH tPHL 0.84 0.34 1.18 0.48 1.88 0.74 4-input NOR gate 9 2-input AND gate 3-input AND gate 3-input AND gate 4-input AND gate 4-input AND gate Exclusive NOR Exclusive OR 2-input NAND gate 2-input NAND gate 3-input NAND gate 3-input NAND gate 4-input NAND gate 4-input NAND gate 5-input NAND gate 5-input NAND gate 6-input NAND gate 8-input NAND gate 2-input NOR gate 2-input NOR gate 3-input NOR gate 3-input NOR gate 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Simple Gates (Continued) Name NO42 NO51 NO52 OR21 OR22 OR31 OR32 OR41 OR42 Eq Gates 2.5 2.1 3.7 1.7 1.8 1.8 2.0 2.2 2.5 Parameters Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 0.62 0.27 1.12 0.40 0.85 0.31 0.40 0.51 0.80 0.35 1.53 0.57 1.06 0.40 0.52 0.62 1.14 0.49 2.36 0.87 1.47 0.56 0.75 0.82 4-input NOR gate tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 0.39 0.55 0.47 0.71 0.47 0.80 0.53 0.94 0.54 1.03 0.46 0.62 0.58 0.83 0.54 0.88 0.65 1.07 0.61 1.12 0.57 0.74 0.80 1.05 0.66 1.02 0.88 1.31 0.73 1.27 2-input OR gate 5-input NOR gate 5-input NOR gate 2-input OR gate 3-input OR gate 3-input OR gate 4-input OR gate 4-input OR gate Complex Gates Name AN11 AN31 Eq Gates 1.7 1.8 6.0 Parameters tPLH tPHL tPLH tPHL A to S B to S AU11 CI to S ON11 ON31 1.8 1.7 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.57 0.46 0.69 0.48 1.39 1.33 1.49 1.31 1.27 1.29 0.55 0.48 0.50 0.45 0.78 0.61 0.95 0.65 1.51 1.46 1.62 1.44 1.39 1.42 0.76 0.63 0.72 0.61 1.19 0.91 1.48 1.08 1.74 1.70 1.86 1.67 1.63 1.65 1.16 0.94 1.19 0.94 10 Description Two 2-input ANDs into 2-input NOR 2-input AND into 3-input NOR One-bit full adder Two 2-input ORs into 2-input NAND 2-input OR into 3-input NAND 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Inverting Drivers Name INV1 INV2 INV3 INV4 INV5 INV6 Eq Gates 1.0 1.0 1.3 1.5 1.8 2.1 Parameters tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.22 0.19 0.16 0.14 0.13 0.11 0.12 0.11 0.11 0.09 0.10 0.09 0.33 0.29 0.21 0.19 0.17 0.15 0.15 0.14 0.13 0.12 0.12 0.11 0.56 0.47 0.33 0.29 0.24 0.22 0.21 0.19 0.18 0.16 0.17 0.15 Description Inverter Inverter Inverter Inverter Inverter Inverter Internal 3-State Drivers Name Eq Gates 2.0 ITA1 A to Q EN to Q 2.9 ITA2 A to Q EN to Q 1.4 ITB1 A to QN EN to QN 2.5 ITB2 A to QN EN to QN 1.4 ITD1 A to QN E to QN 2.5 ITD2 A to QN E to QN 1.3 ITE1 Parameters A to QN EN to QN E to QN tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.50 0.45 0.30 0.31 0.43 0.41 0.15 0.22 0.42 0.33 0.32 0.33 0.28 0.22 0.18 0.24 0.43 0.33 0.42 0.23 0.28 0.20 0.32 0.11 0.42 0.33 0.37 0.31 0.69 0.60 0.49 0.46 0.50 0.47 0.22 0.27 0.61 0.48 0.51 0.48 0.35 0.27 0.25 0.30 0.62 0.48 0.62 0.38 0.36 0.25 0.40 0.17 0.62 0.48 0.57 0.46 1.08 0.90 0.88 0.76 0.63 0.58 0.35 0.38 1.01 0.78 0.91 0.77 0.50 0.38 0.39 0.41 1.03 0.78 1.02 0.68 0.50 0.36 0.54 0.27 1.02 0.77 0.97 0.75 11 Description Internal non-inverting tri-state buffer Internal non-inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Clock Drivers Name IID2 IID4 IID6 Eq Gates 1.7 2.3 2.7 Parameters tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.26 0.27 0.28 0.31 0.33 0.36 0.31 0.32 0.32 0.34 0.35 0.39 0.43 0.42 0.38 0.40 0.40 0.43 Description Non-inverting clock driver Non-inverting clock driver Non-inverting clock driver Muxes and Decoders Name Eq Gates 6.3 DC24 Sx to QN EN to QN 15.2 DC38 Sx to QN EN to QN 2.5 MX21 Ix to Q S to Q 6.0 MX41 Ix to Q S to Q 13.9 MX81 Parameters Ix to Q S to Q tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.53 0.52 0.70 0.64 0.73 0.66 1.05 0.91 0.55 0.55 0.74 0.77 1.15 1.04 1.14 1.19 1.29 1.25 1.27 1.27 0.67 0.66 0.84 0.78 0.83 0.77 1.21 1.08 0.66 0.67 0.86 0.88 1.29 1.22 1.28 1.35 1.41 1.37 1.39 1.39 0.95 0.94 1.12 1.12 1.03 0.98 1.52 1.41 0.89 0.89 1.08 1.08 1.53 1.51 1.52 1.62 1.64 1.59 1.62 1.61 12 Description 2:4 line decoder 3:8 line decoder 2:1 digital multiplexer 4:1 digital multiplexer 8:1 digital multiplexer 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Sequential Logic Name Eq Gates Parameters 4.3 C to Q 4.9 D Setup D Hold C to Q DF081 DF091 D Setup D Hold 5.5 C to Q 6.5 D Setup D Hold C to Q 5.8 D Setup D Hold C to Q 6.9 D Setup D Hold C to Q 7.6 D Setup D Hold C to Q 2.2 D Setup D Hold D to Q DF0A1 DF0B1 DF101 DF111 DF121 GN to Q DL531 3.4 D Setup D Hold D to Q GN to Q DL541 D Setup D Hold 3.0 DL551 D to Q GN to Q D Setup D Hold Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tsu th tPLH tPHL tsu th 0.60 0.33 0.79 0.47 0.59 0.00 0.81 1.05 0.57 0.00 1.18 0.78 D-type F/F without set or reset 1.07 1.30 D-type F/F with active low set tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th 0.82 0.90 1.01 1.02 0.63 0.00 0.83 1.10 0.69 0.00 0.69 0.88 0.56 0.00 0.66 0.91 0.62 0.00 0.71 0.96 0.68 0.00 0.81 0.86 0.93 0.77 0.77 0.00 1.00 0.77 1.06 0.68 1.00 0.00 1.41 1.24 D-type F/F with active low reset 1.09 1.35 D-type F/F with active low set and reset 0.95 1.10 D-type buffered F/F with active low set 0.90 1.12 D-type buffered F/F with active low reset 0.95 1.18 D-type buffered F/F with active low set and reset 1.04 1.07 1.16 0.98 D-type latch without set or reset 1.40 0.98 1.46 0.88 D-type latch with active low reset tPLH tPHL tPLH tPHL tsu th 0.65 0.69 0.71 0.60 0.77 0.82 0.84 0.72 0.82 0.00 1.02 1.06 1.09 0.97 D-type latch with active low set 0.68 0.91 0.70 0.96 0.55 0.76 0.54 0.78 0.58 0.83 0.70 0.75 0.81 0.66 0.80 0.66 0.86 0.57 13 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Sequential Logic (Continued) Name Eq Gates 3.7 Parameters D to Q GN to Q DL561 4.6 D Setup D Hold D to Q GN to Q DL641 4.0 D Setup D Hold D to Q GN to Q DL651 4.7 D Setup D Hold D to Q GN to Q DL661 3.1 D Setup D Hold D to Q GN to Q DLZ01 4.3 D Setup D Hold D to Q GN to Q DLZ11 D Setup D Hold 6.9 JK091 C to Q J Setup J Hold K Setup K Hold Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th 0.80 0.78 0.84 0.66 0.94 0.91 0.97 0.79 0.93 0.00 1.22 1.08 1.28 1.00 0.71 0.00 1.10 1.14 1.17 1.05 0.63 0.00 1.20 1.24 1.24 1.11 0.73 0.00 0.89 1.00 1.01 0.90 0.90 0.00 1.21 1.06 1.28 0.97 1.11 0.00 1.20 1.16 1.24 1.04 D-type latch with active low set and reset 1.44 1.27 1.50 1.18 D-type buffered latch with active low reset 1.32 1.33 1.39 1.23 D-type buffered latch with active low set 1.42 1.43 1.47 1.30 D-type buffered latch with active low set and reset 1.12 1.22 1.23 1.13 D-type latch without set or reset and a dual-enable tri-state output 1.46 1.29 1.53 1.20 D-type latch with active low reset and a dual-enable tri-state output tPLH tPHL tsu th tsu th 0.87 1.14 1.01 1.29 1.03 0.00 0.85 0.00 1.28 1.57 JK-type F/F with active low set 1.11 0.99 1.17 0.90 0.99 1.04 1.05 0.95 1.09 1.15 1.13 1.01 0.78 0.87 0.89 0.78 1.07 0.93 1.15 0.84 14 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Sequential Logic (Continued) Name Eq Gates 7.3 C to Q 9.3 J Setup J Hold K Setup K Hold C to Q JK0A1 J Setup J Hold K Setup K Hold JK0B1 10.4 JKBB1 Parameters C to Q J Setup J Hold K Setup K Hold Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tsu th tsu th tPLH tPHL tsu th tsu th 1.01 1.10 1.21 1.24 1.08 0.00 0.95 0.00 1.03 1.31 1.10 0.00 0.96 0.00 1.61 1.48 JK-type F/F with active low reset 1.30 1.59 JK-type F/F with active low set and reset tPLH tPHL tsu th tsu th 0.75 1.05 0.89 1.19 1.18 0.00 0.96 0.00 1.14 1.43 JK-type buffered F/F with active low set and reset 0.89 1.16 15 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Special Cells Name BL02 QD01X1 QD03X1 QD11X1 TD08 PORA PORB Eq Gates 2.0 Parameters 2 I/O tPLH tPHL QO to QC 2 I/O QO to QC 2 I/O QO to QC 5.9 120.2 155.2 tPLH tPHL RST to POR RST to POR Propagation Delay (ns) 2 FO 4 FO 8 FO tPLH 0.33 0.42 0.69 0.65 0.82 0.85 2.17 1.61 8.18 8.34 4089.35 0.73 0.69 0.85 0.88 2.23 1.64 8.25 8.42 4089.38 0.80 0.76 0.91 0.95 2.33 1.74 8.37 8.56 4089.47 tPHL 11.13 11.17 11.28 tPLH 1142.64 1142.79 1143.10 tPHL 21.85 22.39 23.51 tPLH tPHL tPLH tPHL tPLH tPHL Description Tri-state bus latch 3.58MHz (1MHz - 10MHz) crystal oscillator 20MHz (10MHz - 32MHz) cyrstal oscillator 32KHz (1KHz - 1MHz) crystal oscillator with Schmitt Trigger Time delay cell, non-inverting Power-on-reset Power-on-reset for 3 volt operation Input Pad Cells Name IB01X1 IB03X1 IB05X1 IB07X1 IB09X1 IB0BX1 IB0DX1 IB30X1 Eq Gates 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O Parameters tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.62 0.84 0.61 0.83 0.61 0.83 0.69 1.01 0.69 1.01 0.69 1.01 2.24 1.77 1.23 2.52 0.66 0.88 0.65 0.88 0.65 0.87 0.73 1.06 0.73 1.06 0.73 1.06 2.29 1.82 1.28 2.60 0.73 0.95 0.73 0.95 0.73 0.95 0.80 1.15 0.80 1.15 0.80 1.15 2.39 1.91 1.36 2.72 16 Description CMOS input buffer CMOS input buffer with pull-up CMOS input buffer with pull-down TTL input buffer TTL input buffer with pull-up TTL input buffer with pull-down CMOS Schmitt trigger input buffer TTL Schmitt trigger input buffer 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Output Pad Cells Name OB01X1 OB01X2 OB01X3 OB01X5 OB03X1 OB03X2 OB03X3 OB03X5 OB06X1 OB06X2 OB06X3 OB07X1 OB07X2 OB07X3 Eq Gates 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O OB09X1 OB09X2 OB09X3 75pF tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 3.77 5.63 2.07 5.55 1.35 3.12 1.12 1.85 6.70 10.02 3.54 9.94 2.09 5.33 1.62 2.95 9.63 14.44 5.01 14.35 2.83 7.54 2.12 4.05 TTL output buffer, 1mA tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPZ tPLH tPZ tPLH tPZ tPZ tPHL tPZ tPHL tPZ tPHL A to Q 12.02 6.52 6.22 6.43 3.45 3.56 2.54 2.07 10.82 17.45 9.28 8.95 9.18 4.81 4.95 3.46 2.76 16.23 CMOS output buffer, 1mA 5.80 8.50 CMOS P-channel, open drain, inverting output buffer, 2mA 3.29 4.66 CMOS P-channel, open drain, inverting output buffer, 4mA 8.81 13.20 TTL N-channel, open drain output buffer, 1mA 8.70 13.11 TTL N-channel, open drain output buffer, 2mA tPLH tPHL tZH tZL 6.59 3.77 3.50 3.66 2.08 2.18 1.62 1.37 5.41 0.66 3.09 0.74 1.93 0.94 0.41 4.42 0.29 4.30 0.36 2.32 6.53 3.80 6.65 3.82 4.52 11.96 6.56 12.09 6.58 6.73 17.38 9.32 17.52 9.34 tPLH tPHL tZH tZL 3.71 3.81 3.84 3.81 6.43 6.58 6.57 6.58 9.16 9.34 9.30 9.34 CMOS tri-state output buffer, 2mA tPLH tPHL tZH tZL 2.18 2.23 2.38 2.22 3.56 3.62 3.75 3.61 4.92 5.00 5.12 4.99 CMOS tri-state output buffer, 4mA tPLH tPHL tZH tZL 3.70 5.68 3.83 5.69 6.63 10.05 6.76 10.07 9.56 14.47 9.69 14.48 TTL tri-state output buffer, 1mA A to Q A to Q EN to Q 1 I/O Description 50pF EN to Q 1 I/O Propagation Delay (ns) 25pF EN to Q 1 I/O OB15X1 Parameters A to Q EN to Q 17 TTL output buffer, 2mA TTL output buffer, 4mA TTL output buffer, 8mA CMOS output buffer, 2mA CMOS output buffer, 4mA CMOS output buffer, 8mA CMOS P-channel, open drain, inverting output buffer, 1mA TTL N-channel, open drain output buffer, 4mA CMOS tri-state output buffer, 1mA 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Output Pad Cells (Continued) Name Eq Gates 1 I/O OB15X2 OB15X3 OB83X5 1 I/O 1 I/O OB86X5 OB87X5 1 I/O 1 I/O OB89X5 75pF tPLH tPHL tZH tZL 2.26 5.68 2.40 5.68 3.74 10.07 3.87 10.07 5.21 14.47 5.34 14.47 TTL tri-state output buffer, 2mA tPLH tPHL tZH tZL 1.45 3.18 1.64 3.17 2.20 5.37 2.39 5.37 2.93 7.58 3.13 7.58 TTL tri-state output buffer, 4mA tPLH tPHL tPLH tPHL tPLH tPZ 1.37 3.12 2.10 2.21 2.38 1.10 2.11 5.21 3.47 3.59 3.75 2.85 7.26 4.83 4.97 5.11 TTL output buffer, 8mA, with controlled slew rate output tPZ tPHL A to Q tPLH tPHL tZH tZL 0.53 2.78 2.22 2.26 2.52 2.22 4.85 3.59 3.64 3.89 3.61 6.91 4.96 5.02 5.25 5.00 tPLH tPHL tZH tZL 1.48 3.19 1.77 3.16 2.23 5.33 2.52 5.31 2.96 7.43 3.26 7.41 A to Q A to Q EN to Q 1 I/O OB95X5 Description 50pF EN to Q 1 I/O Propagation Delay (ns) 25pF EN to Q 1 I/O OB81X5 Parameters A to Q EN to Q CMOS output buffer with controlled slew rate output, 8mA CMOS inverting open drain P-channel output buffer with controlled slew rate output, 8mA TTL open drain N-channel output buffer with controlled slew rate output, 8mA CMOS tri-state output buffer with controlled slew rate output, 8mA TTL tri-state output buffer with controlled slew rate output, 8mA Input/Output Pad Cells Name Eq Gates 1 I/O IO01X1 A to IO EN to IO 1 I/O IO01X2 A to IO EN to IO 1 I/O IO01X3 Parameters A to IO EN to IO Propagation Delay (nS) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 3.72 5.66 3.85 5.68 6.65 10.07 6.79 10.09 9.58 14.48 9.72 14.50 TTL I/O buffer, 1mA tPLH tPHL tZH tZL tPLH tPHL tZH tZL 2.27 5.68 2.40 5.68 1.45 3.18 1.65 3.17 3.74 10.10 3.88 10.10 2.20 5.38 2.40 5.38 5.22 14.50 5.35 14.51 2.94 7.59 3.14 7.59 TTL I/O buffer, 2mA 18 TTL I/O buffer, 4mA 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Input/Output Pad Cells (Continued) Name Eq Gates 1 I/O IO03X1 A to IO EN to IO 1 I/O IO03X2 A to IO EN to IO 1 I/O IO03X3 A to IO EN to IO 1 I/O IO3CX1 A to IO EN to IO 1 I/O IO3CX2 A to IO EN to IO 1 I/O IO3CX3 A to IO EN to IO 1 I/O IO3FX1 A to IO EN to IO 1 I/O IO3FX2 A to IO EN to IO 1 I/O IO3FX3 A to IO EN to IO 1 I/O IO41X1 A to IO EN to IO 1 I/O IO41X2 Parameters A to IO EN to IO Propagation Delay (nS) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 6.55 3.81 6.68 3.82 11.98 6.56 12.11 6.58 17.41 9.33 17.54 9.35 CMOS I/O buffer, 1mA tPLH tPHL tZH tZL 3.71 3.81 3.85 3.81 6.44 6.58 6.58 6.58 9.17 9.34 9.31 9.35 CMOS I/O buffer, 2mA tPLH tPHL tZH tZL 2.19 2.24 2.38 2.22 3.56 3.62 3.75 3.61 4.93 5.00 5.12 5.00 CMOS I/O buffer, 4mA tPLH tPHL tZH tZL 6.60 3.80 6.73 3.84 12.05 6.54 12.18 6.59 17.49 9.28 17.63 9.35 CMOS I/O buffer with pull-down, 1mA tPLH tPHL tZH tZL 3.73 3.81 3.88 3.82 6.47 6.55 6.61 6.56 9.20 9.30 9.34 9.32 CMOS I/O buffer with pull-down, 2mA tPLH tPHL tZH tZL 1.92 1.90 2.09 1.90 3.26 3.24 3.42 3.24 4.58 4.57 4.75 4.57 CMOS I/O buffer with pull-down, 4mA tPLH tPHL tZH tZL 3.74 5.67 3.87 5.71 6.68 10.05 6.81 10.10 9.61 14.43 9.74 14.50 TTL I/O buffer with pull-down, 1mA tPLH tPHL tZH tZL 2.27 5.67 2.41 5.67 3.75 10.06 3.89 10.07 5.23 14.44 5.36 14.46 TTL I/O buffer with pull-down, 2mA tPLH tPHL tZH tZL 1.46 3.19 1.65 3.18 2.21 5.39 2.40 5.39 2.94 7.59 3.14 7.59 TTL I/O buffer with pull-down, 4mA tPLH tPHL tZH tZL 3.69 5.68 3.83 5.70 6.59 10.11 6.75 10.13 9.49 14.53 9.66 14.55 TTL I/O buffer with pull-up, 1mA tPLH tPHL tZH tZL 2.26 5.71 2.41 5.70 3.73 10.13 3.88 10.13 5.19 14.55 5.35 14.55 TTL I/O buffer with pull-up, 2mA 19 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Input/Output Pad Cells (Continued) Name Eq Gates 1 I/O IO41X3 A to IO EN to IO 1 I/O IO42X1 A to IO EN to IO 1 I/O IO42X2 A to IO EN to IO 1 I/O IO42X3 A to IO EN to IO 1 I/O IO51X1 A to IO EN to IO 1 I/O IO51X2 A to IO EN to IO 1 I/O IO51X3 A to IO EN to IO 1 I/O IO81X5 A to IO EN to IO 1 I/O IO83X5 A to IO EN to IO 1 I/O IOBCX5 A to IO EN to IO 1 I/O IOBFX5 Parameters A to IO EN to IO Propagation Delay (nS) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 1.46 3.19 1.65 3.18 2.20 5.39 2.40 5.39 2.94 7.60 3.14 7.59 TTL I/O buffer with pull-up, 4mA tPLH tPHL tZH tZL 6.50 3.82 6.64 3.84 11.88 6.59 12.03 6.61 17.27 9.35 17.43 9.37 CMOS I/O buffer with pull-up, 1mA tPLH tPHL tZH tZL 3.70 3.84 3.84 3.84 6.41 6.60 6.56 6.60 9.13 9.37 9.28 9.37 CMOS I/O buffer with pull-up, 2mA tPLH tPHL tZH tZL 2.19 2.24 2.38 2.23 3.55 3.62 3.75 3.62 4.92 5.01 5.12 5.00 CMOS I/O buffer with pull-up, 4mA tPLH tPHL tZH tZL 6.54 3.81 6.67 3.82 11.97 6.57 12.10 6.59 17.40 9.33 17.53 9.35 CMOS I/O buffer with Schmitt trigger input, 1mA tPLH tPHL tZH tZL 3.71 3.83 3.85 3.83 6.44 6.59 6.58 6.59 9.17 9.36 9.31 9.36 CMOS I/O buffer with Schmitt trigger input, 2mA tPLH tPHL tZH tZL 1.92 1.91 2.08 1.90 3.25 3.24 3.41 3.24 4.58 4.58 4.74 4.58 CMOS I/O buffer with Schmitt trigger input, 4mA tPLH tPHL tZH tZL 1.48 3.20 1.78 3.17 2.23 5.35 2.53 5.32 2.97 7.45 3.27 7.43 TTL I/O tri-state buffer with controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.22 2.26 2.52 2.23 3.59 3.64 3.89 3.62 4.96 5.02 5.26 5.00 CMOS I/O tri-state buffer with controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.23 2.26 2.53 2.23 3.61 3.64 3.90 3.62 4.97 5.02 5.27 5.00 CMOS I/O tri-state buffer with pull-down and controlled slew rate output, 8mA tPLH tPHL tZH tZL 1.49 3.21 1.78 3.18 2.23 5.35 2.53 5.33 2.97 7.45 3.27 7.43 TTL I/O tri-state buffer with pull-down and controlled slew rate output, 8mA 20 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Input/Output Pad Cells (Continued) Name Eq Gates 1 I/O IOC1X5 Parameters A to IO EN to IO 1 I/O IOC2X5 A to IO EN to IO 1 I/O IOD1X5 A to IO EN to IO Propagation Delay (nS) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 1.48 3.21 1.78 3.18 2.23 5.36 2.52 5.34 2.96 7.46 3.26 7.44 TTL I/O tri-state buffer with pull-up and controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.22 2.27 2.52 2.24 3.60 3.65 3.90 3.63 4.96 5.04 5.26 5.01 CMOS I/O tri-state buffer with pull-up, and controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.22 2.26 2.52 2.23 3.60 3.65 3.89 3.62 4.96 5.03 5.26 5.00 CMOS I/O tri-state buffer with Schmitt trigger and controlled slew rate output, 8mA Power Cells Name Eq Gates Description CVDD 1.0 CVSS 1.0 PP01X 1 I/O Core cell input resistive tie-up to core Vdd bus Core cell input resistive tie-down to core Vss bus Vss power pad for core and pad cells PP02X 1 I/O Vdd power pad for core and pad cells PP04X 1 I/O PPC1X 1 I/O PPP1X 1 I/O Optional power pad pin for additional busess Vss power pad pin for input buffers and core cells only Vss power pad pin for output buffers only 21 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Delay Derating Information The propagation delays listed in the Selection Guide (pages 9 to 21) are for typical temperature, 25 oC, typical supply voltage, 5.0V., and typical processing conditions. To calculate the delay at other conditions (including Vdd equals 3.0V) the following equation can be used: Tpdx = Tpdx(typ)*KP*KV*KT where Tpdx(typ) is given in the Selection Guide. KP, the process derating coefficient, KT, the temperature derating coefficient, and KV, the supply voltage derating coefficient are described below. Delay Variations with Temperature (KT) Delay varies linearly with temperature. The following formulas and common operating points can be used. Temp KT -55 oC -25 oC 0 oC 25 oC 70 oC 100 oC 125 oC 0.79 0.87 0.94 1.00 1.11 1.19 1.26 Temp. Range KT Formula -55oC to 25oC KT=1.0-(25-TJoC )*2.58 x 10-3 25oC to 140oC KT=1.0+(TJoC-25)*2.58 x 10-3 Where TJ oC is the temperature at the silicon junction. Delay Variations with Process (KP) Delay variations with process are given as fixed constants determined at the limits of acceptable manufacturing of the process. These are described below. Derating Coefficient ( Kp ) Process Variation Point 1.40 Delay increase due to "Worst Case Speed" (WCS) fabrication 1.00 Typical delay; fabrication target 0.61 Delay reduction due to "Worst Case Power" (WCP) fabrication Delay Variations with Voltage (KV) VDD KV 2.7 V 3.0 V 3.3 V 4.5 V 4.75 V 5.0 V 5.25 V 5.5 V 1.74 1.54 1.39 1.07 1.03 1.00 0.97 0.94 Derating Coefficient,KV Delay varies nonlinearly with voltage. Some common operating points and a characteristic curve are shown. 1.8 1.5 1.2 0.9 2.5 22 3.0 3.5 4.0 4.5 Supply Voltage (volts) 5.0 5.5 0.8 micron CMOS Standard Cells Digital ASICs Products and Services August 1993 Packaging The AMI8S standard cell family can be packaged in a variety of popular packages. New packages are in development which will extend the package offering. Some special packages or packaging requirements can be supplied if requested. More details on special packages are available from an AMI sales representative. Available Packages ( ) = Lead Package Type time required Pin Count Plastic Quad Flatpack (PQFP) 44, 52, 64, 80, 100, 120, 128, 144, 160, 208, 2562 , 3041,2 Thin Quad Flatpack (TQFP) (48), 64, (80), 100, (128), (144), (176) Metal Quad Flatpack (MQUAD(R)) 128, 144 Ceramic Quad Flatpack (CQFP) 40, 44, 132, 144 Plastic Leaded Chip Carrier (PLCC) 20, 28, 44, 68, 84 Ceramic Leaded Chip Carrier (JLDCC) 28, 44, 68, 84 Ceramic Leadless Chip Carrier (CLCC) 20, 24, 28, 36, 40, 44, 48, 52, 68, 84 Plastic Dual In-line Package (PDIP) 8, 14, 16, 18, 20, 22, 24, 28, 40, 48 Plastic Pin Grid Array (PPGA) 69, 85, 101, 109, 121, 132, 145, 180 Ceramic Pin Grid Array (CPGA) (65), 68, 69, 84, 85, 101, 109, 121, 132, 145, 177, 181, 208, 476 Ball Grid Array (BGA) (169), (225), (313) Note 1: The 304 pin PowerQuad2 package has an added heat slug to improve power dissipation. Note 2: The 256 and 304 pin packages are supplied in a TapePak molded carrier ring. Copyright(R)1997, American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796 23