HARRIS SEMICOND SECTOR @] HARRIS CMOS Presettable Up/Down Counters (Dual Clock With Reset) High-Voltage Types (20-Volt Rating) CD40192 BCD Type CD40193 Binary Type @ CD40192B Presettable BCD Up/ Down Counter and the C0401938 Preset- table Binary Up:Down Counter each consist of 4 synchronously clocked, gated D type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RE- SET Four buffered O signal outputs as well as CARRY and BORROW outputs for mul- tiple-stage counting schemes are provided. The counter :s cleared so that all out- puts are in a fow state by a high on the RE- SET line. A RESET 15 accomplished asynchro- nously with the clock. Each output 1s individually programmable asynchronously with the clock to the level on the cor- responding jam input when the PRESET ENABLE control is ow. The counter counts up one count on the positive clock edge of the CLOCK UP sig- nal provided the CLOCK DOWN line :s high. The counter counts down one count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY and BORROW signals are high when the counter 1s counting up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW signal goes low one-half clock cycle after the counter reaches tts minimum count in the count-down made. Cascading of mulvple pack- ages 1s easity accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP respectively, of the pack age. The CD40192B and CD40193B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes}, 16- lead dual-in-line plastic packages (E suffix), and in chip form (H suffix). inputs, succeeding counter 4HE D EM 4302271 0037751 4 BAHAS T-45.23-09 CD40192B, CD40193B Types Features: & Individual clock fines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operationfq, = 8 MHz (typ.) @ 10 V CLOCK UP 4 CLOCK OOWN 4 a5-V, 10-V, and 15-V parametric ratings Standardized, symmetrical output RESET . characteristics Voo"'s @ 100% tested for quiescent current at 20 V = Maximum input current of 1 WA at 18 V 401928, D401938 over full package temperature range; 100 nA at 18 V and 25C = Noise margin over full package temperature FUNCTIONAL DIAGRAM 92C$-27561a1 range: WVatVpp FSV 2VatVpp=10V 2.5 V at Vpp = 18 V Meets all requirements of JEDEC Tentative te Yoo Standard No. 13B, Standard Specifications 2 at for Description of 'B' Series CMOS Devices" 3 RESEr 4 GoRROW 5 ERARY- 6 PRESET ENABLE Applications: 7 43 8 Up/down difference counting - EW = Multistage ripple counting Synchronous frequency dividers s2cs-27sean2 A/D and D/A conversion D401928, CD40193B Programmable binary or BCD counting TERMINAL ASSIGNMENT at $2 ater | o B (9) CONTROL LOGIC I @ SAME AS CONTROL LOGIC s2cm-2qeent Yoo tf ss # ALL INPUTS PROTECTED @Y COS/MOS PROTECTION NETWORK 9ete 26990. Fig. 7 CD401928 logic diagram (BCD).HARRIS SEMICOND SECTOR GUE D BM 4302271 0037752 & BS HAS CD40192B, CD40193B Types T4S-2 3-09 RESET _ RESET *o aa pccctcc-cne ra PE Pe I t #@ last ul { 1 J ! i $2 63 s4 a I rr? | Lae = Loss aa 3 *@ 1a Jay t | ove 3 J4 CLK LiL J * * * UP CONTROL LOGIC i a SAME AS CONTROL LoGiC | Un szcu-za9eea CARRY aoRRoWw t o r Q CcOUNTBh fF 8901 2 10987 aacs lem Fig. 2 ~ CD401928 timing diagram. 88 Yes =~ MALL -NPUTS PROTECTED ay 3 a 6O 7 oO 8 COS / MOS PROTECT:CN NETWORK a oz esas aac. -20382 RESET 4 a < =zF Fig. 2 C0401938 logic diagram {binary}. 2 3 u > 2G 8= cig Ue eux ON at = a4 x4 caRR SORROW cOUNT> Ow 450 2 Fon Is tes phe Fig. 5 CD401938 timing diagram. Fig. 4 internat togic of Flip-Hop. TRUTH TABLE CLOCK CLOCK PRESET uP DOWN ENABLE RESET ACTION <_ 1 1 0 COUNT UP NS 1 1 Qo NO COUNT 1 ~~ 1 0 COUNT DOWN 1 1 0 NO COUNT x x Q 0 PRESET x x 1 RESET GRAIN-TO-SOURCE VOLTAGE (Vogt=-V aC catwae Fig. 6 Typical output low {sink} 1 = HIGH LEVEL 0 = LOW LEVEL X = DONT CARE current characteristics. 3-433HARRIS SEMICOND SECTOR 44YE D GM 430ee27) 0037753 & BAHAS CD40192B, CD40193B Types T- 95-23-7079 MAXIMUM RATINGS, Absolute-Maximum Values: OC SUPPLY-VOLTAGE RANGE, (Vop) Voltages referenced to Vgg Terminal) ........ 00. cee cece cere cece neennnee INPUT VOLTAGE RANGE, ALLINPUTS .. DC INPUT CURRENT, ANY ONE INPUT 2.0.0... ccc cece cere ccna ner enttserescene POWER DISSIPATION PER PACKAGE (Pp): For Ta = 55C to $9009 occ eee c eee nee erate ee ee eee reeneeeneeins s0omwW For Ta = +100C to +1259C Derate Linearity at 12mW/C to 200mW DEVICE DISSIPATION PER OUTPUT TRANSISTOR FOR Ta = FULL PACKAGE-TEMPERATURE RANGE (All Package Types).......... 10OMW OPERATING-TEMPERATURE RANGE (Ta) ..... 0. cccsccerescveeeseens +. 7559C to +1250C STORAGE TEMPERATURE RANGE (Tgtg) cesses eee cece reeeee ene ne ee es ~65C to +150C ORAIN-TO- SOURCE VOLTAGE (VpglV 22es-241-a0, LEAD TEMPERATURE (DURING SOLDERING): Fig. 7 Mininuin output tow (sink) At distance 1/16 + 1/32 inch (1.59 + 0.79mm) from case for 10s max....... saeeee +265C current characteristics. ORAIN-TO-SOURCE VOLTAGE (ps]V RECOMMENDED OPERATING CONDITIONS at T, = 25C (unless otherwise specified) For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges. CHARACTERISTIC Voo L_LIMUS UNITS (v} Min. Max. Supply Voltage Range {For T, = Full Temp. Range} - 3 18 Vv Removal Time: io 40 ~ a _ - ns 5 RESET or PE 15 30 _ 3 Pulse Width: 5 480 ~ Fig. 8 Typical output high (source) RESET 10 300 7 ns current characteristics, 15 260 - _ 5 240 - ORAIM-T0-S0URCE VOLTAGE {o$IV PE 10 170 - ns 15 140 - 7 5 180 - 3 CLOCK 10 90 - ns : 15 60 - 5 5 2 Clock Input Frequency 10 oc 4 MHz 15 5.5 , 5 - 15 Clock Rise & Fall Time 10 - 15 US 15 - 5 eeeseaeszree Fig. 9 Minimum output high (source} current characteristics. e 4 z= 35 = rh OT Fs 5 t ctoen ANYON 1 i . RESET 3 PRESET ENAOLE 7 T = iF . ' bo- "rem 3 = * ESET OR PRESET EAGLE REMOVAL TIME s2cs-27se2a Q 40 60 . . . LOAD CAPACITANCE {CL )pF ACS + 24922. Fig. 10 Timing diagram defining lem . , uv , Fig. 11 Typical transition time asa function of load capacitance. 3-434HARRIS SEMICOND SECTOR 44E D im STATIC ELECTRICAL CHARACTERISTICS CD40192B, CD40193B Types CONDITIONS LIMITS AT INDICATED TEMPERATURES (C) CHARACTER- teen . TE UNITS Vo | Vin |Yoo (Vv) {v) | (vp 4} -55 | 40 +85 +125 | Min. | Typ. | Max. Quiescent Device - 0,5 5 5 5 150 150 - 0.04 5 Current, - _;9,10] 10 | 10 | 10 | 300 | 300 | | 004 1 10 '0D Max - _{91s[ 18 | 20 | 20 | 600 | 600 | | 004 | 20] - [0,20] 20 | 100 | 100 [3000 | 3000 | | 0.08 | 100 Output Low o4 [os] 5 | 064 |o61 | o42 | 0361051 1 (Sink) Current 05 [010{ 10] 16 {| 15 Ww 09 | 1.3 2.6 ~ fo. Min us fow[ {a2 [4 | 28 [241}a4) 68a | 2 Output High 46 | 05] 5 | -0.64]-0.61|-0.42 | -0.36]-0.51| 1 } mA {Source} 25 | 05] 5 | -2 [-18 [-13 |-1.15]-16] 23217 - Current. 95 [010] 10 [-16|-15 |-11 |-09]-13 | 2617 !OH Min 135 [015] 15 [-42 | -4 |-28 [-24 |-34 | -6a | Output Voltage - 0,5 5 0.05 - Oo 0,05 Low-Level. [0,10] 10 0.05 = 0 | 0.05 VoL Max ~ [0.15| 15 0.05 = a [eos] | Output Voltage = os 5 4.95 4.95 5 - High-Level, = 0.10] 10 9.95 995 | 10 = VOH Min. - 1015] 15 14.95 14.95 | 15 = input Low 05.4537 - 5 1.5 > _ 15 Voltage. 1.9 _ 10 3 _ _ 3 Miu Max. sigs] 2 1 a5 4 To 4 Input High 05,45) - | 5 3.5 35 | =| Voltage, 1,9 - 10 7 7 ~ = Vin Min, fr 513.5[ - | 15 W mf _ Pe Mee - oa} 18} sor] sor f sr | a1 | fero-8] aor! pa + 4-10 (0.102 -0.254) Ht=19 (2.819 - 3.022) 92CS-28930R1 Dimensions and pad layout for the CD40192BH (dimensions and pad layout for the CD40193BH are identical}. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as in- dicated. Grid graduations are in mils (10-3 inch). 3-435 4302271) 0037754 T mHAS T-4S:330F TEMPERATURE LOAD CAPACITANCE (.) oF acs 2ate6 Fig. 12 -- Typical propagation delay time as a function of load capacitance, 3, POWER OISSIPATION {Pp) aw 5 103, COMMERCIAL CMOS HIGH VOLTAGE ICs INPUT FREQUENCY (Fy) -KHE gees agsar Fig. 13 Dynamic power dissipation. = 88-96 (2.235 ~ 2.438)HARRIS SEMICOND SECTOR WUE D 4302271 0037755 1 BEHAS CD40192B, CD40193B Types T> YS-230 9 DYNAMIC ELECTRICAL CHARACTERISTICS at Tay = 25C Yoo Input ty, te = 20 ns, Cy = 50 pF, Ry = 200k BE CHARACTERISTIC VopL MTS lunits (V) ]Min.| Typ. | Max. cL | 25) Propagation Delay Time tpHL. tPLH: io _ 0 oa ns Sy #50 pF CLOCK UP or CLOCK DOWN to Q, RESET to Q 15 | - 80 | 180 9208-29988 7 5 | | 200 | 400 Fig. 14 Dynamic power dissipation test circuit: PE toQ 10 | [100 | 200] ns 15 f - 70 | 140 5 7 {160 | 320 CLOCK UP to CARRY, CLOCK DOWN to BORROW 104 - 80 ] 160} ns iS j - 60 | 120 _ 5 | ~ }300 7 600 RESET or PE to BORROW or CARRY 10 | [150 | 300 | as 15 | {110 | 220 5 | ~ [100 | 200 Transition Time, trHL. tTLH 10 | | 50} 100] ns Hh 40 } 80 92c3-27e0i81 a 40 80 Fig. 18 Quiescent-device-cutrent test circuit. Min. Removal Time, traq,* RESET or PE 10 | ~ 20 | 40 ns 15 f - 15 | 30 bo 5 | |240 | 480 b Min. Puise Width, ty RESET 10 | [150 | 300 | ns ners servers Vw ~- Lon 15 | {130 | 260 a r 8 _ 5 | |120 | 240 va ~ aa JT PE 10 | - | 85 [170] ns ~| i ~ NOTE: 1s | - 70 | 140 ss vest ANY COMBINATION st. 30 1180 OF INPUTS CLOCK io | as | 90 | ns e2es-2744iA1 6 |] - 30 60 Fig. 16 Input-voltage test circuit. 5 72 4 - Max. Clock Input Frequency, fo. 10 4 8 - MHz 15 {5.5 1 - y, bo $ ~ ~ 15 INPUTS t Clock Rise & Fall Time, t,, ty 10 | - - HS Yoo a nore. 15 | - ce G) ~_ MEASURE INPUTS SEQUENTIALLY, Input Capacitance, Cy: Vss ~ TO BOTH Yop ANO Vg _ CONNECT ALL UNUSED, RESET - f{- 10 15 pF INPUTS TO EXTRER Von OF Vs All Other Inputs = - 5 47.5 pF Vs * The ume required for RESET or PRESET ENABLE control to be removed before clocking {see timing . neeseartod diagram, Fig. 10, Fig. 17 {input current test circuit. vio 42 43 54 Hi J2 34 cLoce uP. coagrsz |cARAY CLOCK UP coanisz CARRY CLOCK GOWN cose93 BORROW CLOCK DOWN coforgs SORROW a @3 06 | 02 a3 L RESET PaESeT. ENABLE S2CS- 2ISGE3RT Fig. 18 Cascaded counter packages. 3-436