ANALOG DEVICES 12- and 14-Bit Hybrid Synchro/ Resolver-to-Digital Converters S$DC/RDC1740/1741/1742 FEATURES Internal lsolating Transformers Military Temperature Range Three Accuracy Options 14-Bit or 12-Bit Resolution High, Continuous Tracking Rate 32-Pin Welded Metal Package Hermetically Sealed Ratiometric Conversion Laser Trimmed - No External Adjustment Three-State Latched Outputs APPLICATIONS Flight Instrumentation Systems Military Servo Control Systems Artillery Fire Control Systems Aviontc Systems Antenna Monitoring Robotics Engine Controllers Coordinate Conversion Axis Transformation CNC Machine Tooling Process Control GENERAL DESCRIPTION The SDC/RDC1740/1741/1742 are hybrid 14- or 12-bit conti- nous tracking synchro or resolver to digital converters contained in 32-pin welded metal packages. In the core of this hybrid the conversion process is performed by a monolithic IC manufac- tured in Analog Devices proprietary BiMOS II process that combines the advantages of CMOS logic and bipolar high accu- racy linear circuits on the same chip. Internal isolating micro- transformers are used to provide truc isolation of the signal and reference inputs. The 14 or 12-bit digital word is in a threc- state digital form available in two bytes. Using separate EN- ABLE inputs for the most significant & bits and the least significant 6 or 4 bits not only simplifies multiplexing of more_ than one device onto a single data bus, but also enables the IN- FIBIT input to be used without interrupting the operation of the tracking loop. The converters are hermetically sealed in a 32-pin welded metal package. REV. A Information furnished by Ansiog Devices ic believed to be accurate and reliable. Howaver, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from ite use. No license granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM . SOC/ADC 17ADITIONLTTAR ue ner ie sn ve REF LO BCALING ane, | tig2, Ms & AND MATCH 8 we nesouven- |] SONPROL | aa) M5 FORMERS ad 0. s DENTAL u CONVERTER av owe ECOL nat + oe mee nae CONTROL | FABET soa wow eyts LOW.aYTE D-STATE SUPPER S-STATE BUFFER eusy 12746867 8 @ 10 3492 88 14 mee 34 OR 12-BNT DIGITAL OUTPUT WORD MODELS AVAILABLE The three synchro/resolver-to-digital converters described in this data sheet differ primarily in the areas of rcsolution, accuracy and dynamic performance as follows: Model SDCI740XYZ is a 14-bit converter with an overall accu- racy of +5,3 arc minutes and a resolution of 1.3 arc minutes. Model SDCI74EXYZ is a 12-bit converter with en overall accu- racy of + 15.3 arc minutes and a resolution of 5.3 arc minutes. Model SDC1742XYZ is 2 12-bit converter with an overall accu- racy of 28.5 arc minutes and a resolution of 5.3 arc minutes. Each model has two operating temperature range versions, those covering the industrial temperature range (0 to +70C) and the military temperature range ( 55C ta + 125C). The XYZ code defines the option as follows: (X) signifies the operating temper- ature range, (Y) signifies the reference frequency, (Z) signifies the signal and reference voltage whether it will accept synchro or resolver format. To ensure a high level of reliability each con- verter receives stringent precap visual inspection, environmental screening and final electrical test. Military temperature range devices and those processed to high reliability screening standards (suffix B) receive further levels of testing and screening to ensure high levels of reliability. More information about the option codes is given under the heading Ordering Information. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 West Coast Central Atlantic 714/641-9391 214/231-5096 215/643-7790SDC/RDC1 740/ 1 741 / 1 7142 SP ECIFICATIONS (typical at 25C unless otherwise specified) Parameter SDC/RDC1740 SDC/RDC1741 SDC/RDC1742 Units Comments Notes CONVERTER PERFORMANCE Accuracy 25.3 max +15.3 max 8.5 max are min 1,3 Tracking Rate 27 min 18 min rew/s 4 Resolution 14 2 aia Bits Output Coding Paralicl (LSB = 13 (1 ESB = 3.3 Natural Binary are min) arc min) Signal & Reference Frequency 400 . Hz Option X1Z. 2.6 * . kHz Option X4Z Repeatability of Position Output 1 . * LSB 4 Bandwidth 130 150 Hz 4 SIGNAL INPUT IMPEDANCE 9OV Signal 200 " * kQ Resistive Tolerance + 2% 4 26V Signal 57.7 * kQ 4 11.8V Signai 26 * * kn 4 REFERENCE INPUTS Reference Voltage 11.8, 26, 135 x * V mms See Ordering Reference Impedance Information 115V Ref 120 . ko Resistive Tolerance +5% 4 26V Ref 27 * * ko 4 11.8V Ref 12.3 . * kn 4 ACCELERATION CONSTANT 56000 80000 ial sec? Symbal K, 4 LARGE STEP RESPONSE BS typ 60 typ ibe ms 179 Step for Setting ta 1,3 100 max 75 max hel ms | LSB of Exror POWER LINES +V5a+15V 28 typ 35 max * * mA Quiescent Condition 1,3 -Vy=-15V 28 cyp 35 max * * mA Quiescent Condition 1,3 Vi=+5 35 typ 56 max * * mA Quiescent Condition 1,3 Power Dissipation 1.4 max _* * WV DIGITAL INPUTS (INTIIBIT, ENABLE L, ENABLE M) V (Input High) 2 min * * Vide V,=+5V 1,3 V (input Low) 0.7 max * . Vde Vi=t5V 1,3 I (Input High) 20 max * * BA Vint 2.4V 1,3 I (input Low} ~400 max * pA Vi =0.4V 1,3 ENABLE AND DISABLE TIME | 80 max . * ns 2,4 INHIBIT Sense Logic Low * a to INHIBIT . * Time to Dara Srable (after Negative-Going Edge of INHIBIT) 640 max . . ns 4 BUSY OUTPUT Sense Active Logic High when converier position ourput changing. Timing Positive going edge 50ns before change in position output. Width 400 typ * * ns 4 200 min * * ns 4 600 max * * ns 4 Load 2 min * . TTL 4 DIGITAL OUTPUTS Voltage Levels Logic High 2.4 min * * Vide Vue ty, 1,3 Tor= 7240p A Logic Low 0.4 max * * Vide Viar5v 1,3 lo. =9.6mA Load 6 max . . TTLSDC/RDC1740/1741/1742 Parameter SDC/RDC1740 SDC/ARDC1741 SDC/RDC1742_ | Units Comments Notes OPERATING TEMPERATURE RANGE Option SYZ Ow + 70 * * *c Option 4YZ ~$S to +125 * c DIMENSIONS 1.74x1.14x0.28 * * Inch See Package 4 (44.2% 28.9x7.)) . a mm Information WEIGHT 0.86 max . . oz 4 25 max . * grams NOTES Specified aver the sppropriate operating temperature range und for: (a) 10% signal and reference amplitude varistion; (b) + 10% signal and reference har- monic distortion; (c) +5% power supply variation; (d) + 10% variation in reference frequency. 7ENABLE M enables most significant 8 bits. ENABLE L enables least significant 4 bits (or 6 bits for SDC/RDC1740). 3100% tested at nominal values of power supplies, input signal voltages and operating frequency. Guaranteed by design. *Specifications same as SDC/RDC1740. **Specifications same as SDC/RDC1741. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS +Vgi tOGND. 0221 ccc eee +17.25Vde CasewGND .........0-. 0-2 eee +20V de ~V5toGND 20. ec cee eee 17.25V de Storage Temperature Range ......... 1. 65C to +150C tVE7O GND oo ccc cece cee e neces +7V de CAUTION: Reference Input HI to GND... .. 2.2262 eee +350V de Correct polarity voltages must be maintained on the +V, and -V; pins. The Reference Input LOtoGND ...........-.... +350V de + SV power supply must never go below GND potenual. Common Mode Range ... 0.6.6... 0. ee eee 175V rms NOTE $1, $2, $3, S4to GND 2.0... eee eSSOV de Absolute maximum ratings are those values beyond which damage to the de- Any Logical InputtoGND .............. -0.4V to +V, vice may occur. ORDERING INFORMATION For full definition, the converter part number should be suf- fixed by an option code. All the standard options and their option codes are shown below. For options not shown, please consult Analog Devices. SDC SDC=Synchro-to- Digital Converter RDC=Resolver-to-Digital Converter 1740 14-Bit Resolution, +5.3 are min Accuracy 1741 = 12-Bit Resolution, +15.3 arc min Accuracy 1742=12-Bit Resolution, +8.5 arc min Accuracy REV. A 174A X Y ZB TL High-Rel Processing Z=1 Signal 11.8V Reference 26V Synchro Z=2 Signal 90V Reference 115V Synchro Z=3 Signal 11.8V Reference 11.8V Resolver Z=4 Signal 26V Reference 26V_ Resolver Z=8 Signal 11.8V Reference 26V Resolver OOHz Reference Frequency .6kHz Reference Frequency X-4 -55C to +125C Operating Temperature Range X=5 O10 +70C Operating Temperature RangeSDC/RDC1740/1741/1742 PIN CONFIGURATION omsai ers |G) @ | orz | @) @ ]- ara] @) @ | even ora] |-. Ors ait oral @) @ for or! G) @ |maan 1 srenrpensivea jar wre! ) ginwtes) @& [nc mt 10 CASE aris! GD @ | we enya @ we svm{ @|* eT 14 & ve nerenance to} () @ | UP REFERENCE Wt G3) | ste nore: NOTE 1. FOR THE REGOLVER OPTION MIN 1716 4. COR THE SYNCHRG OPTION PIN 17 IS NOT CONNECTED. NOTE 3. FOR THE 1741 AND 1762 PINS 12 AND 14 ARE NOT CONNECTED. Bit Number Weight in Degrees 1 (MSB) 180.0000 2 90.0000 3 45,0000 4 22.$000 5 11.2500 6 5.6250 7 2.8125 8 1.4063 9 0.7031 10 0.3516 il 0.1758 12 (LSB for 1741/1742) 0.0879 13 0.0439 14 (LSB for 1740) 0.0220 Table |. Bit Weight Table PIN FUNCTION DESCRIPTION Pin Mnemonic Description 1-14 Bit 1-14 (1740) Parallel output data bits. 1-12 Bit 1-12 (1741/1742) 15 REF LO Input pins for the reference signal. 16 REF HI . 17 $4 OR NIC $4 signal input for Resolver option. N/C for Synchro option. 18 $3 19 = $2 Synchro/Resoiver input signals. 20 $1] 2 NIC No Connection. 22 N/C No Connection. 23 CASE Should be connected to OV GND. 24 NIC No Connection. 25 ENABLET ENABLE L enables the 6 or 4 least significant bits. 26 ENABLE M ENABLE M enables the most significant bits. Logic High sets the output data bits to a high impedance state; a Logic Low presents the data in the latches to the output pins. 27. s- BUSY Converter busy. A Logic High output indicates that the output latches are being updated and data should not be transferred. 28 INHIBIT Logic Low inhibits the data transfer from the counter co the output latches. 2900 +V5 Main positive power supply. 30 OVGND Power supply ground. 31 -Vs5 Main negative power supply. 32 +V, Logic power supply. -4- REV. ASDC/RDC1740/1741/1742 sOc/RDC 9740/3744/1742 UP REF HI owe UP REF LO SCAUNG AMP rm] ato +s RESISTORS SUPPLIES : MchO- CONTROL 8 TRANS. cos) SOLVER: ve 63 FORMERS DIGITAL 4 /. ov GND {RESOLVER OPTION) REF Vy at wet AEM CONTROL ERABTEL. toaie = HIGH-BYTE LOW.BYTE pusy 2-STATE GUPFER 2-STATE BUFFER 4123246678 9 1 41 12 13 14 | 44. OF 12-BIT DAGITAL OUTPUT WORD Figure 1. Functional Diagram of the SOC/RDC 1740/1 74171742 THEORY OF OPERATION In the synchro-to-digital converter configuration, the 3-wire syn- chro output should be connected to $1, 52 and $3 on the unit and the Scott T transformer pair will convert these signals into resolver format, i.e., V,=K Epo sin wt sin 0 (SIN) V,=K Eg sin wt cos 4 (COS) where 6 is the angle of the synchro shaft. In the resolver-to-digital converter configuration, the 4-wire resolver output should be connected to $1, 52, 83 and S4 on the unit and the transformers will act purely as isolators. To understand the conversion process, then assume that the cur- rent word state of the up-down counter is $. V, is multiplied by COS# and V. is multiplied by SIN@ to give: K Eg sin wt sin 6 cos } and K Ep sin wt cos @ sin >. These signals are subtracted by the error amplifier to give: K Ep sin wt (sin 6 cos ~cos 6 sin >) or K Ep sin wt sin (6-). A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null sin (6-6). The digital output (counter ), then represents the synchro/resolver shaft angle @ within the specified accuracy of the converter. INHIBIT INPUT The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. Releasing the INHIBIT automatically generates a busy pulse to refresh the output data. REV. A ENABLE INPUTS The ENABLE inputs determine the state of the output data. A Logic High maintains the output data pins in the high imped- ance condition, and application of a Logic Low presents the data in the latches to the output pins. ENABLE M enables the most significant 8 bits, while ENABLE L, enables the least sig- nificant 4 bits (6 bits in the SDC/RDC1740). The operation of the ENABLE inputs has no effect on the conversion process. DATA TRANSFER Data transfer can be accomplished using either the INHIBIT input or the trailing edge, positive to negative transition of the BUSY pulse output. The data will be valid 64Qns after the application of a Logic Lo to the INHIBIT input. This is regardless of the time when the INHIBIT is upplied and allows time for an active busy pulse to clear. By using the ENABLE M and ENABLE L inputs the two bytes of data can be transferred after which the INHIBIT should be returned to a Logic Hi state to enable the output latches to be updated. MAX DEPENDS ON 600ns MAX INPUT AATE 200ns MIN BUSY 200ns >| MAX Sons be MIN DATA VALID KX VALID Ke VALID Figure 2. Timing Diagram -5-SDC/RDC1740/1741/1742 BUSY OUTPUT The validicy of the output data is indicated by the state of the BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at TTL levels. A BUSY is initiated each time the input moves by an analog equivalent of an LSB and the internal counter is incremented or decremented or the INHIBIT input is released. Typically the width of the BUSY pulse is 400ns during the posi- tion data output updates. The trailing edge, positive to negative transition, of the BUSY pulse indicates that the position data output has been updated and is ready for transfer (data valid). The maximum toad on the BUSY output using the trailing edge of the BUSY pulse is 2 TTL loads. CONNECTING THE CONVERTER The power supply voltages connected to +V, and -Vs pins should be +15V and must not be reversed. The digital logic supply V, is connected to +5V. It is suggested that a parallel combination of a 0.1 ,F ceramic and a 6.8pF electrolytic capacitor is placed from each of the three supply pins to GND. . The pin marked CASE is connected electrically to the case and should be taken to a convenient zero volt potential in the system. The digital output is taken from Pin 1 through to Pin 12 for the SDC/RDC1741/1742 and Pin } through to Pin 14 for the SDC/RDC1740 where Pin | is the MSB. The reference connections are made to REF HI and REF LO. In the case of a synchro, the signals are connected to $1, 82 and $3 according to the following convention: Egy.s3"Eato-ani Sin wt sin 6 E3.s2=Egco-rin sit wt sin (8+ 120) Es2.5);=Exro-rni 210 wt sin (0+240) For a resolver, the signals are connected to $1, $2, $3 and $4 according to the following convention: Eg-s3* Earo-rent Sin mt sin @ Eg: se=Epntrvo sin wi cos 0 The BUSY, INHIBIT and ENABLE pins should be connected as deacribed under the heading Data Transfer. RESISTIVE SCALING OF INPUTS A feature of these converters is that the signal and reference inputs can be resistively scaled to accommodate any change of input signal and reference voltages. This means that a standard converter can be used with a person- ality card in systems where a wide range of input and reference voltages are encountered. , Note: The accuracy of the converter will be affected by the matching accuracies of resistors used for external scaling. To calculate the values of the external scaling resistors in the case of a synchro converter, add 1.11k2 per extra volt of signal in series with S1, $2 and $3 and Ikf per extra volt of reference in series with RHI. In the case of a resulver-to-digital converter, add 2.22k!2 in series with $1 and S2 per extra volt of signal and 1kQt per extra volt of reference in series with RHI. DYNAMIC PERFORMANCE The transfer function of the converter is given below. four Figure 3. Transfer Function of SDC/RDC1740/174 1/1742 Open loop gain: four _ Ky 1+8T; Gn 7 S$ TEST: Closed loop gain: Sour _ 1+ ST, tu 7 SST, 1+ STi + e+ RE Model SDC/RDC1740 Where K,=56,000 T1=0.01 T2=0.001525 The gain and phase diagrams are shown in Figures 4 and 5. Model SDC/RDC1741/1742 Where K,=80,000 T1=0.0087 T2=0.001569 The gain and phase diagrams arc shown in Figures 6 and 7. ACCELERATION ERROR A tracking converter employing a type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant K, of the converter. K= Input Acceleration Error in Output Angle The numerator and denominator have the same units. K, does nor define maximum acceleration, only the error due to accelera- tion, maximum acceleration is in the region of $ times the K, figure. The following is an example using the K, of the SDC1740. Acceleration of 50 revolutions sec? with K,=56000 Error in LSBs = re = 14.62LSBs REV. A~ SDC/ARDC1740/1741/1742 14.8 s 50 100 FREQUENCY - Ma Figure 4. SDC/RDC1740 Gain Plot 190 138 128 2 bo] 00 FREQUENCY - He Figure & SOC/RDC1740 Phase Plot 200 125 a 50 100 FREQUENCY - Hz Figure 6. SDC/RDC 1741/1742 Gain Plot 200 12.6 as 3 100 200 FREQUENCY - He Figure 7, SDC/ROC1741/1742 Phase Plot oN \ RELIABILITY The reliability of these products is very high duc to the exten- sive usc of custom chip circuits that decrease the active compo- nent count. Calculations of the MTBF figure under various s environmental conditions are available on request. As an example of the Mean Time Between Failures (MTBF) s2 , Pp calculated according to MIL-HDBK-217E, Figure 8 shows the MTBF in years versus case temperature in naval sheltered con- ditions for SDC/RDC1740/41/42. r @ 6 70 [ 100 TEMPERATURE ~ C Figure 8. SDC/ADC1740/41/42 MTBF Curve REV. A aSDC/RDC1740/1741/1742 OTHER PRODUCTS Many other hybrid products concerned with the conversion of synchro data are manufactured by Analog Devices, some of which are listed below. If you have any questions about our products or require advice about their use for a particular appli- cation, please contact our Applications Enginccring Depertment. The SDC/RDC1767 and SDC/RDC1768 are hybrid synchro- to-digital converters with isolating microtransformers similar -to the SDC/RDC1740/41/42 described on this data sheet with the additional features of analog velocity output and dc error output. The OSC1758 is a hybrid sine/cosine power oscillator which can provide a maximum power ourput of 1.5 watrs, over a frequency range of 0 to 10kHz. The DRCI745 and DRC1746 are 14- and 16-bit natural binary latched output hybrid digital-to-resolver converters. The accura- cies available ere +2 and +4 arc mins, and the outputs can sup- ply 2VA at 7V ems. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). bO)* PIN | BEAD COLOR .. SHCHHHSSEHOOHSS TOLERANCES: 0.008 (0.1271 UNLESS OTHESNEE STATED -8- REV. A