GA National Semiconductor F100328 Low Power Octal ECL/TTL General Description The F100328 is an octal latched bi-directional translator de- signed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is deter- mined by the DIR input. A LOW on the output enabie input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the F100328 transparent. August 1990 Bi-Directional Translator with Latch The F100328 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kf pull-down resistors. Features @ Identical performance to the F100128 at 50% of the supply current Connection Diagrams TL/F/10216-2 FAST and TRI-STATE are registered trademarks of National Semiconductor Corporation. @ Bi-directional translation The cut-off state is designed to be more negative than @ _w 2000V ESD protection normal ECL LOW level. This allows the output emitter-fol- m Latched outputs lowers to turn off, when the termination supply is 2.0V, m FAST TTL outputs presenting a high impedance to the data bus. This high im- pedance reduces termination power and prevents loss of @ TRI-STATE outputs low state noise margin when several loads share the bus. | Voltage compensated operating range = 4.2V to 5.7V Logic Symbol LIL ELELL Pin Names Description oN tas ta Ts Te 7 Eo-E7 ECL Data I/O er To-T7 TTL Data /O ee mR OE Output Enable Input Ey Ey Ep Ey Ey Es E7 LE Latch Enable Input ry ITT rid DIR Direction Controt Input TL/F/10219-1 Ail pins function at 100K ECL levels except for Tg-T7. 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak CT T Ty T3ers Ty Ts Tg Eg LE Yoo Ver Ym. To Bo 24b-r, i 6 2) (6) 7) Lirild tz asic, 0) 24 23 22 21 20 19 aE = Bo4 21F-Ey 27 '2 7 os 20HLe B53 srs Vor 6 19 Vor E14 srt Yoca 47 18-V,, E45 kts ome y- Ym ey 7 8 9 10 11 ao |" ys 16/-Tp 8 To) Tei0 IST, TORO Ey OF Yop Voc, DR Tp 1 EES Sa 55 BoM eT 3 TUF H0219-4 yo ish1, TL/F/10219-3 1990 National Semiconductor Corporation TL/F/10219 k RRD-820M80/Printed in U. S.A. YSIE] YUM 10} B/SUBAL [EUO!9941G-1g 111/194 12190 4aMOd MO] 8ZE0014Functional Diagram SEE DETAIL CF a | ECLO <_}> a-+t TILO ! i tH et a ECL 1 ~+ ~~ TTL 1 > 4 ECL2 - ~~ TTL2 > ECL3 ~ it TTL3 ECL4 ~< > + om TTL4 4 ECL5 ~ > a ~~ TTLS i a- ECL6 + at ee TIL G ECL? + - < TTL? (LE) LATCH ENABLE DIR) ECL/TTL (01A) DECODE |} (OE) OUTPUT ENABLE "> Note: LE, DIR, and OE use ECL logic levels TL/F/10219-5 Detail ECL-TTL TRANSLATOR ECL ECL OUTPUT BUFFER TTL D LATCH OUTPUT BUFFER Do E TTL E TTL ~ ECL TRANSLATOR LATCH ENABLE > > DIRECTION OUTPUT py > }_ ENABLE TL/F/10219-6 Truth Table ECL TTL OE DIR LE Port Port Notes LOW CT xX | LT euro Z L L H Input Zz 1,3 LOW L H H (Cut-Off) Input 2, H L L L L 1,4 H L L H H 1,4 H L H x Latched 1,3 H H L L L 2,4 H H L H H 2,4 H H H Latched x 2,3 HIGH Voltage Level LOW Voltage Level Don't Care High Impedance H L x Z Note 1; ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent.Absoiute Maximum Ratings (note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature (Tstg) 65C to + 150C Maximum Junction Temperature (Ty) Ceramic + 175C Plastic + 150C Vee Pin Potential to Ground Pin 7.0V to +0.5V Viti Pin Potential to Ground Pin +6.0V to 0.5V ECL Input Voltage (DC) Vee to +0.5V ECL Output Current {DC Output HIGH) 50 mA TTL Input Voltage (Note 4) 0.5V to +7.0V TTL Input Current (Note 4) 30 mA to + 5.0 mA Commercial Version Voltage Applied to Output in HIGH State TRI-STATE Output Current Applied to TTL Output in LOW State (Max) ESD (Note 2) 0.5V to + 5.5V Twice the Rated Io. (mA) 2 2000V Recommended Operating Conditions Case Temperature (Tc) Commercial Military ECL Supply Voltage (Ver) Commercial Military TTL Supply Voltage (Vt7_) Commercial Military TTL-to-ECL DC Electrical Characteristics Vee = 4.2V to 5.7V, Voc = Voca = GND, Tc = 0C to + 85C, VTL = +4.5V to +5.5V (Note 3) 0C to + 85C 56C to + 125C .7 to 4.2V .7V to 4.2V +4,5V to +5.5V +4.5V to +5.5V Symbol Parameter Min Max Units Conditions Vou Output HIGH Voltage 1025 955 ~ 870 mV Vin = Vieimax) Of ViL(Miny Vo. Output LOW Voltage ~1830 1705 1620 mv Loading with 502 to 2v Cutoff Voltage OE or DIR Low, ~ 2000 - 1950 mV Vin = Vin(Max) OF ViL(Min), Loading with 502 to 2V VoHc Output HIGH Voltage Vin = Vinumin) OF ViL(max) ane 1035 mv Corner Point High Loading with 509 to 2V VoLc Output LOW Voltage 1610 mv Corner Point Low Vie Input HIGH Voltage 2.0 5.0 Over Vit. Vee, Tc Range Vit Input LOW Voltage 0 0.8 Over VrtL, Vee, Tc Range ly Input HIGH Current 70 pA Vin = +2.7V Breakdown Test 1.0 mA Vin = +5.5V lie Input LOW Current 700 pA Vin = +0.5V Vecp Input Clamp 12 Vv lin = 18mA Diode Voltage , lee Vee Supply Current LE Low, OE and DIR High Inputs Open 159 75 mA Vee = 4.2V to 4.8V 169 75 Vee = 4.2V to 5.7V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful lite impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the worst case value for the parameter. Since these values normaily occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the aliowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. Note 4: Either voltage limit or current limit is sufficient to protect inputs.Commercial Version (Continued) ECL-to-TTL DC Electrical Characteristics Vee = 4.2V to 5.7V, Voc = Vera = GND, Tc = 0C to + 85C, CL = 50 pF, Vrr_ = +4.5V to +5.5 (Note 3) Symbol Parameter Min Typ Max Units Conditions VOH Output HIGH Voltage 2.7 3.1 Vv loH = 3MA, VrTL = 4.75V 24 29 Vv lon = 3MA, VT, = 4.50V VoL. Output LOW Voltage 0.3 0.5 Vv lot = 24 mA, Vrt_ = 4.50V Vin Input HIGH Voltage 1165 870 mv Guaranteed HIGH Signal for All Inputs Vic Input LOW Voltage 1830 1475 mv Guaranteed LOW Signal for All Inputs NW Input HIGH Current 350 pA Vin = Vin (Max) te Input LOW Current 0.50 pA Vin = Vic (Min) lozHT Oat High 70 A Vout = +2.7V lor | TRISTATECurent | 9p wa | Vour= +08v los SenPel Shor-Carcuit 150 60 mA | Vout = 0.0V, ViTL = +5.5V Ir Viti Supply Current 74 mA TTL Outputs LOW 49 mA TTL Outputs HIGH 67 mA TTL Outputs in TRI-STATE Ceramic Dual-in-Line Package TTL-to-ECL AC Electrical Characteristics Vee = 4.2V to -5.7V, VitL = +4.5V to +5.5V, Veo = Voca = GND T = = oO = o. Symbol Parameter c= oe Te = 25C To = 85C Units Conditions Min Max Min Max Min Max "LH Tn toEn 14 35 11 3.6 41 3.8 ns Figures 1 & 2 tPHL (Transparent) ns *PLH LEtoEn 1.7 3.6 1.7 3.7 1.9 3.9 ns Figures 1&2 fPHL ns tpzH OE to E, . +. 4. 1. 4.4 1. 4. (Cutoff to High) 3 2 5 7 8 ns Figures 1&2 tpHz OE to E, . (High to Cutotf) 1.5 4.5 1.6 4.5 1.6 4.6 ns Figures 1 & 2 tpHz DIR toE, . (High to Cutoff) 1.6 4.3 1.6 43 1.7 45 ns Figures 1& 2 {set Tyr to LE 1.4 1.4 14 ns Figures 1&2 thold Ty, tole 2.1 2.1 2.1 ns Figures 1&2 tow(H) Pulse Width LE 2.1 2.1 2.1 ns Figures 1&2 tTLH Transition Time . tre 20% 10 80%, 80% to 20% 0.6 1.6 0.6 1.6 0.6 1.6 ns Figures 1 & 2Commercial Version (continueg) Ceramic Dual-In-Line Package ECL-to-TTL AC Electrical Characteristics Vee = 4.2V to 5.7V, VTL = +4.5V to +5.5V, Voc = Voca = GND, CL = 50 pF Symbol Parameter Te = 0 Te = 25C Te = 85C Units Conditions Min Max Min Max Min Max 'PLH En to Tn 23 5.6 2.4 5.6 2.6 5.9 ns Figures 3 & 4 teHL (Transparent) 'PLH LE toTn 3.4 7.2 3.1 7.2 3.3 7.7 ns Figures 3& 4 tPHL tp2H OE to Tp 3.4 8.45 3.7 8.95 4.0 9.7 tezi (Enable Time) 3.8 9.2 4.0 9.2 43 9.95 ns Figures 3 & 5 tpyz OE to Tp 3.2 8.95 3.3 8.95 3.5 9.2 tpLz (Disable Time) 3.0 77 3.4 8.7 4d 9.95 ns Figures 3 & 5 tpHz DIR to T, 2.7 8.2 2.8 8.7 3.4 8.95 . tpiz (Disable Time) 2.8 7.45 3.4 7.95 4.0 9.2 ns Figures 3&6 tset E, to LE 1.1 1.1 V1 ns Figures 3 & 4 thoid E, to LE 2.1 2.1 2.6 ns Figures 3&4 tow(H) Pulse Width LE 41 41 41 ns Figures 3&4 PCC and Cerpak TTL-to-ECL AC Electrical Characteristics VEE = 4.2V to 5.7V, Vaz. = +4.5V to +5.5V Symbol Parameter Te = ore Te = 25C Te = 88C Units Conditions Min Max Min Max Min Max 'PLH Tn to En 14 3.3 14 3.4 14 3.6 ns Figures 1&2 tPHL (Transparent) ns 'PLH LEtoEn 1.7 3.4 1.7 3.5 1.9 3.7 ns Figures 1& 2 tPHL ns tpz7H OE to E, . a . 1. 2 1.7 . 7 (Cutoff to High) 1 4.0 5 4 4.6 ns Figures 1&2 tpHz OE to Ep, . 1. 43 1. ; 1. A Fi &2 (High to Cutott) 5 6 4.3 6 4 ns igures 7 tpuz DIR to E,, . 1. : . 4.4 . 4.3 (High to Cutoff) 6 4.1 1.6 1.7 ns Figures 1&2 tset Ty te LE 1.0 1.0 1.0 ns Figures 1 & 2 thoid Tp to LE 2.0 2.0 2.0 ns Figures 1&2 tpw(H) Pulse Width LE 2.0 2.0 2.0 ns Figures 1 & 2 tTLH Transition Time ; . 1. 0.6 : . 1. 7 tHe 20% to 80%, 80% to20% | 8 6 16 | 06 6 ns | Figures 182Commercial Version (continued) PCC and Cerpak ECL-to-TTL AC Electrical Characteristics Vee = 4.2V to 5.7V, Vigq_ = +4.5V to +5.5V, C, = 50 pF Symbol Parameter Te = oC Te = 25C To = 85C Units Conditions Min Max Min Max Min Max 'PLH En to Tn 23 5.4 2.4 5.4 2.6 5.7 ns Figures 3 & 4 teu. (Transparent) 'PLH LE toTh a4 7.0 34 7.0 3.3 75 ns Figures 3 & 4 tPHL tpZH OE to Th 3.4 B.25 3.7 8.75 4.0 9.5 tezi (Enable Time) 3.8 9.0 4.0 8.0 43 9.75 ns Figures 3.& tpHz OE to Tp, 3.2 8.75 3.3 8.75 3.5 9.0 Fi tpLz (Disable Time) 3.0 7.5 3.4 8.5 44 9.75 ns igures 3 & 5 tpHz DIR to Ty 2.7 8.0 2.8 8.5 3.1 8.75 ; teLz (Disable Time) 28 7.25 3.1 7.75 4.0 9.0 ns Figures 3 & 6 tset E, to LE 1.0 1.0 1.0 ns Figures 3 & 4 thold E, to LE 2.0 2.0 2.5 ns Figures 3 & 4 tow(H) Puise Width LE 4.0 4.0 4.0 ns Figures 3 & 4Military VersionPreliminary TTL-to-ECL DC Electrical Characteristics Vee = 4.2V to 5.7V, Vcc = Voca = GND, To = 55C to + 125C, VTL = +4.5V to +5.5V Symbol Parameter Min Max Units Tce Conditions Notes Vou Output HIGH Voltage | _ _ 0C to 1025 870 mV 4125C 1085 870 mv 55C Vin = Vin (Max) 0 or Vi. (Min) Vou Output LOW Voltage | _ ses | 4620 | mv . eo Loading with 5020 to 2.0V 1,2,3 1830 | 1555 mV 5C Cutoff Voltage Orc to 1950) WV |e 125 | OE or DIR Low 1850 mV 55C Vouc Output HIGH Voltage | _ OC to 1035 mV + 125C 1085 mV 55C Vin = Vin (Min) Loading with 123 Vote Output LOW Voltage mV orc to or Vi_ (Max) 5020 to 2.0v 1610 + 125C 1555 mV 5C Vin Input HIGH Voltage 20 Vv 55C to | Over VrtL, Veg, Tc Range 1,2,.3,4 + 125C VIL Input LOW Voltage 08 V ~5C to | Over Vitt, Vee, Tc Range 1,2.3,4 + 125C lin Input HIGH Current 70 pA pee Vin = +2.7V 1,2,3 Breakdown Test 55C to . = +6. 1.0 mA 4425C VIN .5V lit Input LOW Current _ 55C to | Vin = +0.5V 1.0 mA 4 125C 1,2,3 VFcp Input Clamp _ 56Cto | lin = 18MA Diode Voltage 12 V +125C 12,3 lee Vee Supply Current LE Low, OE and DIR High 55C to | Inputs Open 123 165 65 mA +125C | Vee = 4.2V to 4.8V _ -175 65 Vee = 4.2V to -5.7VMilitary VersionPreliminary (continue) ECL-to-TTL DC Electrical Characteristics Vee = 4.2V to 5.7V, Voc = Voca = GND, Tc = 55C to + 125C, CL = 50 pF, Vrq, = +4.5V to + 5.5V Symbol Parameter Min Max Units Te Conditions Notes Vou Output HIGH Voltage 2.5 mV Orc to +125C | loy = 1MA, VTL = 4.50V 2.4 55C lon = 3 MA, VTTL = 4.50V 123 VoL Output LOW Voltage 65C _ _ - 0.5 mV 4425C lo = 24mA, Vrt_ = 4.50V Vin Input HIGH Voltage 1165 _870 mV 55C Guaranteed HIGH Signal 1.2.3.4 +125C for All Inputs ViL Input LOW Voltage _ _ 55C to Guaranteed LOW Signal 1830 | 1475 | mV +125C for All Inputs 1,2,3,4 lH Input HIGH Current 350 A 0C to Vee = 5.7V 123 500 Me +125C Vin = Vin (Max} a Ne Input LOW Current 55C to Vee = 4.2V 0.50 pA +125C Vin = Vit (Min) 1.2.3 lozHT TRI-STATE Current 55C to 7 = +27 1, 2, Output High 0 pA +125C Vout = + 2.7V 2,3 loz_t TRI-STATE Current 55C to 1. A Vv, = +0.5V 1,2 Output Low m + 125C OUT 0 2,3 los Output Short-Circuit 55C to - - = 0. = +5, CURRENT 150 60 mA +1425C Vout = 0.0V, Vit 5.5V 1,2,3 IL Viti Supply Current 75 mA 55C to TTL Outputs Low 50 mA 4425C TTL Output High 1,2,3 70 mA TTL Output in TRISTATE Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking {to guarantee junction temperature equals 55C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at 55C, + 25C, and + 125C, Subgroups, 1, 2 3, 7, and 8. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at -55C, + 25C, and + 125C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing Vou/ VoL. Ceramic Dual-In-Line Package TTL-to-ECL AC Electrical Characteristics Vee = 4.2V to 5.7V, VITL = +4.5V to +5.5V, Voc = Voca = GND = - = o = 4+ C) Symbol Parameter Te 55C Te = 25C Tec 126C Units | Conditions | Notes Min Max Min Max Min Max 'PLH Tuto En 1.0 3.9 11 3.6 1 4.0 "S| Figures 1&2 TPHL (Transparent) ns 1.23 'eLH LE to En 1.2 3.8 1.4 3.7 1606 42-| OS | Figures 1 &2 TPHL ns 1PZH OE to E, . (Cutoff to HIGH) 1.0 4.3 1.5 4.4 1.7 5.2 ns Figures 1 & 2 tpHz OE to Ep, . 1.5 5.1 1.6 4.5 1.6 5.1 Fi 7&2 (HIGH to Cutoff) ns Cures tpHz DIR to Ep, . 1. 4.7 1.6 43 1.7 4.9 Fi 7&2) 1,2,3 (HIGH to Cutoff) 6 ms | Sgeres es tset Tp to LE 2.5 2.0 2.5 ns Figures 1&2 4 thold Tn to LE 2.5 2.0 2.5 ns Figures 1 & 2 tow(H) Pulse Width LE 2.6 2.0 2.5 ns Figures 1 & 2 4 tTLH Transition Time . 0.4 2.3 0.5 2.1 0.4 2.4 Fi 1&2 4 trHe 20% to 80%, 80% to 20% mS | SiguresMilitary VersionPreliminary (continued) Ceramic Dual-in-Line Package ECL-to-TTL AC Electrical Characteristics Vee = ~4.2V to 5.7V, ViTL = +4.5V to +5.5V, Voc = Voca = GND, CL = 50 pF = "O = o, = + Or Symbol Parameter Te 55C To = 26C Te 125C Units Conditions Notes Min Max Min Max Min Max 'PLH En to Tn 23 6.4 2.4 5.6 2.6 6.3 ns | Figures3& 4 {PHL (Transparent) 123 'PLH LE toTn 3.1 8.0 34 73 3.3 8.0 ns | Figures3&4 TPH tpzH OE toTh 3.2 8.9 3.7 9.0 4.0 10.2 tezi (Enable Time) 3.6 9.4 4.0 9.3 43 10.4 ns | Figures 3&5 tpyz OE toT, 3.2 9.9 3.3 9.0 3.5 9.4 . teLz (Disable Time) | 3.0 97 3.4 8.8 4t 10.6 ns | Figures3&5 | 1,23 tpHz DIR to Th 2.6 9.4 2.8 8.8 2.9 9.1 Fi teLz (Disable Time) | 2.7 8.5 34 8.0 4.0 9.7 ns gures 3 & 6 tset E, to LE 2.5 2.0 2.5 ns Figures 3 & 4 4 thoid E, to LE 3.0 2.5 3.0 ns Figures 3&4 tow(H) Pulse Width LE 25 2.0 5.0 ns Figures 3 & 4 4 Cerpak TTL-to-ECL AC Electrical Characteristics Vee = 4.2V to 5.7V, ViTL = +4.5V to +5.5V = 5 = 25 = +125 Symbol Parameter Te ss Tc = 25C Te 125C | units | Conditions | Notes Min Max Min Max Min Max 'PLH Tn to En 1.0 3.9 1.1 3.6 14 4.0 MS | Figures 1&2 tpHL (Transparent) ns 12.3 tPLH LE to En 1.2 3.8 1.4 3.7 16 42 "S| Figures 1&2 tPHL ns tpzH OE toE, . . . ; 4.4 . ; 7 (Cutoff to HIGH) 1.0 43 1.5 1.7 5.2 ns Figures 1&2 tpHz OE toE, . 1. . . . 1.6 5.1 (HIGH to Cutoth 5 5.1 1.6 4.5 ns Figures 1&2 tpHz DIR to E, . 1. 7 6 . 1.7 . 12, (HIGH to Cutoff) 6 4 1 4.3 4.9 ns Figures 1&2 | 1,2,3 tset Tr to LE 2.5 2.0 2.5 ns Figures 1&2 4 thold T, to LE 2.5 2.0 2.6 ns Figures 7 & 2 tow(H) Pulse Width LE 2.5 2.0 2.5 ns Figures 1&2 4 tTLH Transition Time . 0.4 . 5 . ; 2.4 fi trHe 20% to 80%, B0% to 20% 23 24 0.4 ns | Figurest&2) 4Military VersionPreliminary (Continued) Cerpak ECL-to-TTL AC Electrical Characteristics Ver = 4.2V to 5.7V, VrTL = +4.5V to +5.5V, CL = 50 pF Tre = 55 = = + 0 Symbol Parameter c 5S Te = 26C Te 125C Units Conditions Notes Min Max Min Max Min Max "LH En to Tn 23 6.4 2.4 5.6 2.6 6.3 ns | Figures3&4 {PHL (Transparent) 1.2.3 'PLH LE toTn 3.1 8.0 34 7.3 3.3 8.0 ns | Figures3&4 tPHL tezH OE to Th 3.2 8.9 3.7 9.0 4.0 10.2 Fi tpzi (Enable Time) 3.6 9.4 4.0 9.3 43 10.4 ns igures 3 & 5 tpuz OE to Tp 3.2 9.9 3.3 9.0 3.5 9.4 Figures 3 & 5 teLz (Disable Time) | 3.0 9.7 3.4 8.8 44 10.6 ns igures3&S | 1,2,3 tpyz DIR to Tp 2.6 9.4 2.8 8.8 2.9 9.4 teiz (Digable Time) | 2.7 8.5 3.1 8.0 4.0 97 ns | Figures 3 & 6 tset En to LE 2.5 2.0 2.5 ns Figures 3 & 4 4 thoid E, tole 3.0 2.5 3.0 ns | Figures3&4 tpwiH) Pulse Width LE 2.5 2.0 5.0 ns Figures 3 & 4 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immediately after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Nate 2: Screen tested 100% on each device at + 25C, temperature only, Subgroup AQ. Note 3: Sample tested (Method 5005, Table 1) on each mfg. lot at + 25C, Subgroup AQ, and at + 125C and 55C temperatures, Subgroups A10 and A11. Note 4: Not tested at + 25C, + 125C and 55C temperature (design characterization data). 10Test Circuitry Vo = 5 Ver = -4,5V peewee eee ene, ' 3 ' S/H ' ' ov _! TTL t ' T ER \ i ' S/H OUT 1 t ' ECL I 500 =10 LE DIR off TERMINATOR 4 ATTENUATOR ' -4V NET ' wae w awe = = & ww @ @ J - eeene ; fren 4 kRewwad emnans ECL Fic, 6 tTERMINATOR beeen d NET roves (SEE CIRCUIT SHOWN Fe BELOW) Frp_7 TTL FORCING FUNCTION F eq, ECL FORCING FUNCTION TL/E/10219-7 peseee ee eee ee ey | -0.95 ' ' ' 1 F d 4 i ECL 1.71 500 ' 1 S/H 4 500, ' ' Y ay = ECL ' TERMINATOR ? bCeeeewewwreweeeae ea @ aw & NET TL/F/10219-8 FIGURE 1, TTL to ECL AC Test Circuit Switching Waveforms TIL DATA xX x i}, YS To het tpy 4 ( l | ! | T t | | | LATCH ENABLE I T I I | OUTPUT ENABLE \ 1 ' 1 ' \ I T ' T DIRECTION CONTROL | I I qT I I I 1 t | | I { 1 ' ( | qT qT l ' I | | t T F l | t t 1 I | l 80% ECL OUTPUT 20% ' t ' i | 1 I reef lee! Le tpp ts ty tpp tpyz toyz tezu FL/F/10219-9 FIGURE 2. TTL to ECL TransitionPropagation Delay and Transition Times 1Test Circuitry (Continued) Vo = 5Y Yoo = OV Vee = ~45V | pee cece eeeenneuee - | ' 95 OUT S/H T a S/H ' 50a ' 500 LE OR OEf ft gy = ec TERMINATOR poonns NET t HF t bewaaed groans ECL tFra 4 TERMINATOR beaannd NET peeeny (USE CIRCUIT SHOWN ABOVE) Frnt F eq, ECL FORCING FUNCTION C_ = 50 pF including stray and jig capacitance. Note: 502 to ground termination must be included on ECL I/O pins not monitored by a 50 scope to prevent oscillatory feedback. FIGURE 3. ECL-to-TTL AC Test Circuit Switching Waveforms (continued) ECL DATA B 4 4 | | | | sro LATCH ENABLE ' t ' | | ] TTL OUTPUT TL/F/10219-11 Note: DIR is LOW, and OE is HIGH FIGURE 4. ECL-to-TTL TransitionPropagation Delay and Transition Times a a TL/F/10219-10 12Switching Waveforms (continued) OUTPUT ENABLE TTL OUTPUT TTL OUTPUT 0.3V 7 } Yo. (TTL) Note: DIR is LOW, LE is HIGH TLAF/10219-14 FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times DIRECTION CONTROL tpHz = N\ 0.3 You (TL) ov trrz be 3.5V TTL OUTPUT 7 0.3 | Voy (TTL) Note: OE is HIGH, LE is HIGH TL/F/10219-15 FIGURE 6. ECL-to-TTL Transition, DiR to TTL Output, Disable Time 13Applications F100360 yl parity F100328 | paprry GEN. WRITE DATA PY ECL => LATCH 3 L jor Tm & a H 1 OE 2 RULE = WRITE DATA x 2 Fo >] ECL WRITE DATA z L DR LATCH PARITY Ove > TTL OUTPUT DATA = Hor mM Ve y dir LATCH 9 _ z IG PICE ECL & d adic a & F100328 CACHE 2 3 512 KBYTE F100328 z = ADDRESSES. MEMORY ARRAY & = > ECL ADDRESS [ 8 5 L4 pr LATCH TH fe 5 H+0E om by ADRS r pir e 6 _ PARITY F100360 z > PYLE cs pata of? 71 PARITY POE ECL FH = 3 aw PARITY | CHECKER a WE te .- F100328 DATA > 2 F100328 St fe 2 5 > TT a 3 ECL wo 2 ~ g z F100370 E > t 1 OR a Z DECODER CONTROL > H] OF LATCH fi Le READ/ | WRITE CONTROL F100328 INPUT DATA STROBE ENABLE OUTPUT DATA MEMORY READ DATA LATCH STROBE TL/F/10219-12 FIGURE 7. Applications DiagramMOS/TTL SRAM Interface Using F100328 ECL-TTL Latched Translator Ordering Information The device number is used to form part of a simplified purchasing code where A package type and temperature range are defined as follows: 100328 D CG QR Device Type (Basic) = Special Variations QR = Commercial grade device with Package Code burn-in D = Ceramic DIP QB = Military grade device with F = Quad Cerpak environmental and burn-in Q = Plastic Leaded Chip Carrier (PCC) processing Temperature Range CG = Commercial (0C to + 85C) M = Military ( 55C to + 125C) 14Physical Dimensions inches (milimeters) m 1.215 | ~ (30.86) 0.025 MAX 0.030 0.055 (0.635) (0.762 1.397) RAD fg RAD TYP 0.390 t iaa06) 0.370 MAX (9.398) GLASS y UG) Lz} Wy Lea ts) Ley 2) Led Let bol ot Lug 0.037 + 0.005 . 0.940 +0.127) 0.005 + GLASS 0.055 + 0.005 ( 0.400 -0.430 0.180 (0.127) SEALANT (397 t 0127) | 0.020 0.070 (10.16 10.92) (4.572) MIN (0.508 1.778) t MAX A | 4 A 4 (5.795) th + ; MAX v A 86 94 | A t o4 ko Y 95 +5 |. sm-on2 TYP TYP in 203 0.305) 0.125 TYP 0.055 0.100 0.010 0.018 + 0.003 (3.175) 0.485 + 0.050 (1397) (2.540 + 0.254) (0.457 +0.076) MIN ~~ 2.a741270) MAX TYP TYP BOTH ENDS J24E (REY G} 24-Lead Ceramic Dual-In-Line Package (0.400 Wide) (D) NS Package Number J24E G SPACES AT 0.326, {8.280) NOM SQUARE 0.045 (1.143) x a5" 0.410 ~ 0.430 (10.44 10.92} SQUARE (CONTACT DIMENSION) 0.920 a 0.0130.018 8.032 ~ 0.040 (0.508) (0.390-0.457) _0.165-0.180 (0.81311 i iT re {4.191 4.572) =F pnt ae wer=nam Pin NO. if I. at [q-0.026 = 0.032, ows oe 0.118 WENT (0.660 a) (2.642 2.997) Lg 0450. T as ass 6.495 (12.32 12.57) SQUARE W288 (REV G) Note: Pedestal as shown on base is not available for F100K ECL products. 28-Lead Plastic Chip Carrier (V) NS Package Number V28Ational Translator with Latch irec F100328 Low Power Octal ECL/TTL Bi- Physical Dimensions inches (millimeters) (Continued) Lit. # 103904 - a 0,370 _ _ _ 0.004 0.006_ 0250-0360 | (9-398) |g 250--0.360 (0.102 0.152) (6.350 9.144) MIN SQUARE (6.350 9.144) TYP TP PIN'NO. 1 \ 24 23 22 21 20 19 ; 18 0 JI 1e__ a 5 1. a c 8B_== oO 789101112 0.075 (1.905) S PLCS 0.0150.018 | MAX x 0.035 0.050 (0.406. oasT 0.058 9.005 (0.889 1.270) (1.270 0.127) 0.085 0.400 > (2.159) (10.16) MAX SQUARE MAX GLASS W24B (REV C) 24-Lead Quad Cerpak (F) NS Package Number W24B LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b} support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the fife support device or system, or to affect its safety or effectiveness. be reasonably expected to result in a significant injury -- f to the user. Sf Corporation GmbH dapan Ltd. Kong Ltd. Do Bras Ltda. {Austrata) PTY, Ltd. 2900 Semiconductor Drive industriestrasse 10: Sanseido Bidg. 5F Suite 513, 5th Floor Av. Bog. Faria Lima, 1383 1st Floor, 441 St. Kilda Ad. P.O. Box 58090 D-8080 Furstenteldbruck 4-15 Nishi Shinjuku Chinachem Golden Plaza, 6.0 Andor-Conj. 62 Melbourne, 3004 Santa Clara, CA 95052-8090 West Germany Tek (408) 721-5000 Tet: (0-81-44) 1 103-0 TWX: (910) 339-9240 Telex; 527-649 Fax: (08141) 103554 Shinjuku-Ku, Tokyo 160, Japan Tat: 3-299-7001 FAX: 3-299-7000 77 Mody Road, Tsimshatsui East, 01451 Sao Paulo, SP, Brasil Kowloon, Hong Kong Tal: 3-7231200 Jalex: 52996 NSSEA HX Fax: 3-3112536 Victory, Australia Tak (03) 267-5000 Fax: 61-3-2677458 Tal: (55/11) 212.5066 Fax (65/11) 211-1181 NSBR BA National does not assume any responsibility for use of any circuitry described, ne circuit patent licenses are implied and National reserves the right al any ime ithout notice to change said circuitry and specifications. 16