September 2006
A
Copyright © Alliance Memory. All rights reserved.
AS7C1026C
5 V 64K X 16 CMOS SRAM
12/5/06, v 1.0 Alliance Memory P. 1 of 9
®
Features
• Industrial (-40o to 85oC) temperature
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 15 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• Easy memory expansion with CE,OE inputs
• TTL-compatible, three-state I/O
• Upper and Lower byte pin
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection >
_ 2000 volts
Logic block diagram
65,536 x 16
Array
OE
CE
WE Address decoder
redoced sserddA
A0
A1
A2
A3
A4
A5
A7
VCC
GND
8A
9A
01A
11A
21A
31A
41A
51A
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
A6
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
C6201C7SA
AS7C1026C
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®
Functional description
The AS7C1026C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 15 ns with output enable access times (tOE) of 6 ns are ideal for high-
performance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1026C is packaged in
common industry standard packages.
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Key: H = high, L = low, X = don’t care.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +7.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
Power dissipation PD– 1.25 W
Storage temperature (plastic) Tstg –55 +125 °C
Ambient temperature with VCC applied Tbias –55 +125 °C
DC current into outputs (low) IOUT – 50 mA
Truth table
CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode
H X X X X High Z High Z Standby (ISB), ISBI)
L H L L H DOUT High Z Read I/O0–I/O7 (ICC)
L H L H L High Z DOUT Read I/O8–I/O15 (ICC)
L H L L L DOUT DOUT Read I/O0–I/O15 (ICC)
L L X L L DIN DIN Write I/O0–I/O15 (ICC)
L L X L H DIN High Z Write I/O0–I/O7 (ICC)
L L X H L High Z DIN Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
HHigh Z High Z Output disable (ICC)
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®
Recommended operating conditions
Notes:
VIL min = -1.5V for pulse width less than 5ns, once per cycle.
VIH max = VCC+2.0V for pulse width less than 5ns, once per cycle.
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
Input voltage VIH 2.2 – VCC + 0.5 V
VIL –0.5 – 0.8 V
Ambient operating temperature (Industrial) TA–40 – 85 o C
DC operating characteristics (over the operating range)1
Parameter Sym Test conditions
AS7C1026C-15
UnitMin Max
Input leakage current | ILI | VCC = Max,
VIN = GND to VCC
– 5 µA
Output leakage current | ILO | VCC = Max, CE = VIH,
VOUT = GND to VCC
– 5 µA
Operating power supply current ICC
VCC = Max,
CE ? VIL, IOUT = 0mA,
f = fMax
– 210 mA
Standby power supply current
ISB
VCC = Max,
CE ? VIH , f = fMax
– 60 mA
ISB1
VCC = Max, CE ? VCC–0.2 V,
VIN ? 0.2 V or
VIN ? VCC–0.2 V, f = 0
– 10 mA
Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 – V
Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0 V 6 pF
I/O capacitance CI/O I/O VOUT = 0 V 7 pF
Note:
This parameter is guaranteed by device characterization, but is not production tested.
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Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
Read cycle (over the operating range)3,9
Parameter Symbol
AS7C1026C-15
Unit NotesMin Max
Read cycle time tRC 15 – ns
Address access time tAA – 15 ns 3
Chip enable (CE) access time tACE – 15 ns 3
Output enable (OE) access time tOE – 7 ns
Output hold from address change tOH 4 – ns 5
CE low to output in low Z tCLZ 4 – ns 4, 5
CE high to output in high Z tCHZ – 6 ns 4, 5
OE low to output in low Z tOLZ 0 – ns 4, 5
Byte select access time tBA – 7 ns
Byte select Low to low Z tBLZ 0 – ns 4, 5
Byte select High to high Z tBHZ – 6 ns 4, 5
OE high to output in high Z tOHZ – 6 ns 4, 5
Power up time tPU 0 – ns 4, 5
Power down time tPD – 12 ns 4, 5
Undefined output/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data validPrevious data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
AS7C1026C
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Write waveform 1 (WE controlled)11
Write cycle (over the operating range) 11
Parameter Symbol
AS7C1026C-15
Unit NotesMin Max
Write cycle time tWC 15 – ns
Chip enable (CE) to write end tCW 9 – ns
Address setup to write end tAW 9 – ns
Address setup time tAS 0 – ns
Write pulse width tWP 9 – ns
Write recovery time tWR 0 – ns
Address hold from end of write tAH 0 – ns
Data valid to write end tDW 7 – ns
Data hold time tDH 0 – ns 5
Write enable to output in high Z tWZ – 6 ns 4, 5
Output active from write end tOW 1 – ns 4, 5
Byte select low to end of write tBW 9 – ns
Address
CE
LB, UB
WE
Data
IN
Data
OUT
t
WC
t
CW
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data undefined high Z
Data valid
t
AH
AS7C1026C
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Write waveform 2 (CE controlled)11
AC test conditions
Notes:
1 During VCC power-up, a pul l - u p r esistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% te sted.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltag e.
5 This parameter is guarante ed, but not tested.
6WE
is high for read cycl e.
7CE
and OE are low for read cy cle.
8 Address is valid prior to or coincident with CE transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning addre ss.
10 N/A.
11 All write cycle timings are referenc ed from the last valid addre ss to the first transitioning address.
12 Not applicable.
13 C = 30 pF, ex cept all high Z and low Z parameters where C = 5 pF.
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data
OUT
Data undefined
high Z high Z
t
AS
t
AW
Data valid
t
CLZ
t
AH
168
Ω
Thevenin Equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
3 ns
D
OUT
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A .
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5
AS7C1026C
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®
Package dimensions
44-pin TSOP 2
Min
(mm) Max
(mm)
A1.2
A1 0.05 0.15
A2 0.95 1.05
b0.30 0.45
c0.120 0.21
D18.31 18.52
E10.06 10.26
He 11.68 11.94
e0.80 (typical)
l0.40 0.60
D
He
1234567891011121314
4443 424140 39383736 35 3433 32 31
1516
3029
1718 1920
2827 2625
c
l
A1
A2
e
44-pin TSOP 2
0–5
°
21
24
22
23
E
A
b
Seating
plane
44-pin SOJ
44-pin SOJ
400 mil
Min (in) Max (in)
A0.128 0.148
A10.025 –
A20.105 0.115
B0.026 0.032
b0.015 0.020
c0.007 0.013
D1.120 1.130
E0.370 NOM
E10.395 0.405
E20.435 0.445
e0.050 NOM
e
Pin 1
A1
b
B
AA2
E2
E1
D
c
E
AS7C1026C
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®
Ordering codes
Package Volt/Temp 15 ns
Plastic SOJ, 400 mil 5V Industrial AS7C1026C-15JIN
TSOP 2, 10.2 x 18.4 mm 5V Industrial AS7C1026C-15TIN
Part numbering system
AS7C 1026C –XX X X X
SRAM prefix Device number Access time
Package:
J = SOJ 400 mil
T = TSOP 2, 10.2 x
18.4 mm
Temperature range:
I = industrial: -40° C
to 85° C
N = LEAD FREE
PART
Alliance Memory, Inc.
1116 South Amphlett
San Mateo, CA 94402
Tel: 650-525-3737
Fax: 650-525-0449
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C1026C
Document Version: v 1.0
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance.
All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents
Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended
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or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any
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Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may
reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
AS7C1026C
®
®
