Semiconductor Components Industries, LLC, 2005
May, 2005 − Rev. 5 1Publication Order Number:
MC74LCX125/D
MC74LCX125
Low−Voltage CMOS
Quad Buffer
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX125 is a high performance, non−inverting quad
buffer operating from a 2.3 to 3.6 V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A V I specification of 5.5 V allows MC74LCX125 inputs
to be safely driven from 5.0 V devices. The MC74LCX125 is suitable
for memory address driving and all TTL level bus oriented transceiver
applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OEn) inputs, when HIGH, disable the outputs by placing them in a
HIGH Z condition.
Features
Designed for 2.3 to 3.6 V VCC Operation
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in all Three Logic States (10 A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance: Human Body Model >2000 V
Machine Model >200 V
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
14
1
SOIC−14
D SUFFIX
CASE 751A
14
1
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
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A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
= Pb−Free Package
(Note: Microdot may be in either location)
LCX125G
AWLYWW
1
14
LCX
125
ALYW
1
14
MC74LCX125
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2
Figure 1. Pinout: 14−Lead (Top View)
1314 12 11 10 9 8
21 34567
VCC OE3D3 O3OE2D2 O2
OE0D0 O0OE1 D1 O1 GND
PIN NAMES
Function
Output Enable Inputs
Data Inputs
3−State Outputs
Pins
OEn
Dn
On
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High o r Low Voltage Level and Transitions Are
Acceptable; for ICC reasons, DO NOT FLOAT Inputs
OEn Dn On
L
L
H
L
H
X
L
H
Z
INPUTS OUTPUTS
TRUTH TABLE
D0 2O0
3
OE
0
1
D1 5O1
6
OE
1
4
D2 9O2
8
OE
2
10
D3 12 O3
11
OE
3
13
Figure 2. Logic Diagram
MAXIMUM RATINGS
Symbol Parameter Value Condition Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIDC Input Voltage −0.5 VI +7.0 V
VODC Output Voltage −0.5 VO +7.0 Output in 3−State V
−0.5 VO VCC + 0.5 Output in HIGH or LOW State. (Note 1) V
IIK DC Input Diode Current −50 VI < GND mA
IOK DC Output Diode Current −50 VO < GND mA
+50 VO > VCC mA
IODC Output Source/Sink Current ±50 mA
ICC DC Supply Current Per Supply Pin ±100 mA
IGND DC Ground Current Per Ground Pin ±100 mA
TSTG Storage Temperature Range −65 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
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RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage Operating
Data Retention Only 2.0
1.5 2.5, 3.3
2.5, 3.3 3.6
3.6 V
VIInput Voltage 0 5.5 V
VOOutput Voltage (HIGH or LOW State)
(3−State) 0
0VCC
5.5 V
IOH HIGH Level Output Current VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
− 24
− 12
− 8
mA
IOL LOW Level Output Current VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
+ 24
+ 12
+ 8
mA
TAOperating Free−Air Temperature −40 +85 °C
t/VInput Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V,
VCC = 3.0 V 0 10 ns/V
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol Characteristic Condition Min Max Unit
VIH HIGH Level Input Voltage (Note 2) 2.3 V VCC 2.7 V 1.7 V
IH
g( )
2.7 V VCC 3.6 V 2.0
VIL LOW Level Input Voltage (Note 2) 2.3 V VCC 2.7 V 0.7 V
IL
g( )
2.7 V VCC 3.6 V 0.8
VOH HIGH Level Output Voltage 2.3 V VCC 3.6 V; IOL = 100 A VCC 0.2 V
OH
g
VCC = 2.3 V; IOH = −8 mA 1.8
VCC = 2.7 V; IOH = −12 mA 2.2
VCC = 3.0 V; IOH = −18 mA 2.4
VCC = 3.0 V; IOH = −24 mA 2.2
VOL LOW Level Output Voltage 2.3 V VCC 3.6 V; IOL = 100 A 0.2 V
OL
g
VCC = 2.3 V; IOL= 8 mA 0.6
VCC = 2.7 V; IOL= 12 mA 0.4
VCC = 3.0 V; IOL = 16 mA 0.4
VCC = 3.0 V; IOL = 24 mA 0.55
IIInput Leakage Current 2.3 V VCC 3.6 V; 0 V VI 5.5 V ±5A
ICC Quiescent Supply Current 2.3 VCC 3.6 V ; VI = GND or VCC 10 A
CC
y
2.3 VCC 3.6 V; 3.6 VI or VO 5.5 V ±10
ICC Increase in ICC per Input 2.3 VCC 3.6 V; VIH = VCC − 0.6 V 500 A
2. These values of VI are used to test DC electrical characteristics only.
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AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500
Limits
TA = −40°C to +85°C
VCC = 3.3 V ± 0.3 V VCC = 2.7 V VCC = 2.5 V ± 0.2 V
CL = 50 pF CL = 50 pF CL = 30 pF
Symbol Parameter Waveform Min Max Min Max Min Max Unit
tPLH
tPHL Propagation Delay Time
Input to Output 1 1.5
1.5 6.0
6.0 1.5
1.5 6.5
6.5 1.5
1.5 7.2
7.2 ns
tPZH
tPZL Output Enable Time to
High and Low Level 2 1.5
1.5 7.0
7.0 1.5
1.5 8.0
8.0 1.5
1.5 9.1
9.1 ns
tPHZ
tPLZ Output Disable Time From
High and Low Level 2 1.5
1.5 6.0
6.0 1.5
1.5 7.0
7.0 1.5
1.5 7.2
7.2 ns
tOSHL
tOSLH Output−to−Output Skew
(Note 3) 1.0
1.0 ns
3. Skew is defined as the absolute value of the dif ference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol Characteristic Condition Min Typ Max Unit
VOLP Dynamic LOW Peak Voltage
(Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V 0.8
0.6 V
V
VOLV Dynamic LOW Valley Voltage
(Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V −0.8
−0.6 V
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF
COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF
CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF
ORDERING INFORMATION
Device Package Shipping
MC74LCX125D SOIC−14 55 Units / Rail
MC74LCX125DG SOIC−14
(Pb−Free) 55 Units / Rail
MC74LCX125DR2 SOIC−14 2500 Tape & Reel
MC74LCX125DR2G SOIC−14
(Pb−Free) 2500 Tape & Reel
MC74LCX125DT TSSOP−14* 96 Units / Rail
MC74LCX125DTG TSSOP−14* 96 Units / Rail
MC74LCX125DTR2 TSSOP−14* 2500 Tape & Reel
MC74LCX125DTR2G TSSOP−14* 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74LCX125
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5
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
0 V
VOH
VOL
Dn
On
tPHL
tPLH
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
0 V
0 V
OEn
On
tPZH
3.0 V
tPHZ
tPZL tPLZ
On
VmiVmi
Vmo Vmo
Figure 3. AC Waveforms
VCC
VOH − 0.3 V
VOL + 0.3 V
GND
Symbol
VCC
3.3 V ± 0.3 V 2.7 V 2.5 V ± 0.2 V
Vmi 1.5 V 1.5 V VCC/2
Vmo 1.5 V 1.5 V VCC/2
VmiVmi
Vmo
Vmo
PULSE
GENERATOR
RT
DUT
VCC
RL
CL
CL= 50 pF at VCC = 3.3 0.3 V or equivalent (includes jig and probe capacitance)
CL= 30 pF at VCC = 2.5 0.2 V or equivalent (includes jig and probe capacitance)
RL= R1 = 500 or equivalent
RT= ZOUT of pulse generator (typically 50 )
Figure 4. Test Circuit
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PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
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PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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Phone: 81−3−5773−3850
MC74LCX125/D
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