1
Data sheet acquired from Harris Semiconductor
SCHS147D
Features
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at VCC = 5V,
CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high
speed silicon gate CMOS decoders well suited to memory
address decoding or data routing applications. Both circuits
feature low power consumption usually associated with
CMOS circuitry, yet have speeds comparable to low power
Schottky TTL logic. Both circuits have three binary select
inputs (A0, A1 and A2). If the device is enabled, these inputs
determine which one of the eight normally high outputs of
the HC/HCT138 series will go low or which of the normally
low outputs of the HC/HCT238 series will go high.
Two active low and one active high enables (E1, E2, and E3)
are provided to ease the cascading of decoders. The
decoder’s 8 outputs can drive 10 low power Schottky TTL
equivalent loads.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC138F -55 to 125 16 Ld CERDIP
CD54HC138F3A -55 to 125 16 Ld CERDIP
CD74HC138E -55 to 125 16 Ld PDIP
CD74HC138M -55 to 125 16 Ld SOIC
CD54HCT138F -55 to 125 16 Ld CERDIP
CD54HCT138F3A -55 to 125 16 Ld CERDIP
CD74HCT138E -55 to 125 16 Ld PDIP
CD74HCT138M -55 to 125 16 Ld SOIC
CD54HC238F3A -55 to 125 16 Ld CERDIP
CD74HC238E -55 to 125 16 Ld PDIP
CD74HC238M -55 to 125 16 Ld SOIC
CD74HC238NSR -55 to 125 16 Ld SOP
CD54HCT238F3A -55 to 125 16 Ld CERDIP
CD74HCT238E -55 to 125 16 Ld PDIP
CD74HCT238M -55 to 125 16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
October 1997 - Revised April 2002
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2002, Texas Instruments Incorporated
CD54/74HC138, CD54/74HCT138,
CD54/74HC238, CD54/74HCT238
High Speed CMOS Logic 3-to-8 Line Decoder/
Demultiplexer Inverting and Non-Inverting
[ /Title
(CD74
HC138
,
CD74
HCT13
8,
CD74
HC238
,
CD74
HCT23
8)
/Sub-
ject
(High
Speed
2
Pinout CD54HC138, CD54HCT138, CD54HC238, CD54HCT238
(CERDIP)
CD74HC138, CD74HCT138, CD74HCT238
(PDIP, SOIC)
CD74HC238
(PDIP, SOIC, SOP)
TOP VIEW
Signal names in parentheses are for ’HC138 and ’HCT138.
Functional Diagram
TRUTH TABLE ’HC138, ’HCT138
INPUTS
OUTPUTSENABLE ADDRESS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
XHXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HLLHHHHHHHHHHL
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
E1
E2
E3
GND
(Y7) Y7
VCC
Y1 (Y1)
Y2 (Y2)
Y3 (Y3)
Y4 (Y4)
Y5 (Y5)
Y6 (Y6)
Y0 (Y0)
15
14
13
12
10
7
9
11
1
2
3
5
6
4
E3
E2
E1
A2
A1
A0 Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
HC/HCT
238 HC/HCT
138
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
3
TRUTH TABLE ’HC238, ’HCT238
INPUTS
OUTPUTSENABLE ADDRESS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXHXXXLLLLLLLL
LXXXXXLLLLLLLL
XHXXXXLLLLLLLL
HLLLLLHLLLLLLL
HLLLLHLHLLLLLL
HLLLHLLLHLLLLL
HLLLHHLLLHLLLL
HLLHLLLLLLHLLL
HLLHLHLLLLLHLL
HLLHHLLLLLLLHL
HLLHHHLLLLLLLH
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 3):
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
5
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
A0-A2 1.5
E1, E2 1.25
E3 1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC -55oC T O 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH, tPHL CL= 50pF 2 - - 150 - 190 - 225 ns
Address to Output 4.5 - - 30 - 38 - 45 ns
CL= 15pF 5 - 13 - - - - - ns
CL= 50pF 6 - - 26 - 33 - 38 ns
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
6
Enable to Output
HC/HCT138 tPLH, tPHL CL= 50pF 2 - - 150 - 190 - 265 ns
4.5 - - 30 - 38 - 53 ns
6 - - 26 - 33 - 45 ns
Output Transition Time
(Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Power Dissipation
Capacitance, (Notes 5, 6) CPD CL= 15pF 5 - 67 - - - - - pF
Input Capacitance CIN - - - - 10 - 10 - 10 pF
HCT TYPES
Propagation Delay
Address to Output tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - - - - - ns
Enable to Output
HC/HCT138 tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns
Enable to Output
HC/HCT238 tPLH, tPHL CL= 15pF 4.5 - - 40 - 50 - 60 ns
Output Transition Time
(Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Power Dissipation
Capacitance, (Notes 5, 6) CPD CL= 15pF 5 - 67 - - - - - pF
Input Capacitance CIN - - - - 10 - 10 - 10 pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = VCC2 fi(CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC -55oC T O 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
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