SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Reads and Writes Can Be Asynchronous
or Coincident
D
Organization:
– SN74ACT7200L – 256 ×9
– SN74ACT7201LA – 512 ×9
– SN74ACT7202LA – 1024 ×9
D
Fast Data Access Times of 15 ns
D
Read and Write Frequencies up to 40 MHz
D
Bit-Width and Word-Depth Expansion
D
Fully Compatible With the
IDT7200/7201/7202
D
Retransmit Capability
D
Empty, Full, and Half-Full Flags
D
TTL-Compatible Inputs
D
Available in 28-Pin Plastic DIP (NP),
Small-Outline (DV), and 32-Pin Plastic
J-Leaded Chip-Carrier (RJ) Packages
description
The SN74ACT7200L, SN74ACT7201LA, and
SN74ACT7202LA are constructed with dual-port
SRAM and have internal write and read address
counters to provide data throughput on a first-in,
first-out (FIFO) basis. Write and read operations
are independent and can be asynchronous or
coincident. Empty and full status flags prevent
underflow and overflow of memory, and
depth-expansion logic allows combining the
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible.
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
15 ns.
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-
acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0°C
to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
DV OR NP PACKAGE
(TOP VIEW)
3213231
14
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
D6
D7
NC
FL/RT
RS
EF
XO/HF
Q7
Q6
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
430
15 16 17 18 19
Q3
Q8
NC
Q4
D3
D8
W
NC
V
D4
D5
RJ PACKAGE
(TOP VIEW)
20
Q5
CC
GND
R
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN74ACT7200L logic symbol
5
D1 Q1
10
4
D2 Q2
11
3
D3 Q3
12
27
D4 Q4
16
26
D5 Q5
17
25
D6 Q6
18
24
D7 Q7
19
2
D8 Q8
13
1D
6
D0 Q0
9
2,4 CT = 0 (RST)
22
FIFO 256 × 9
Φ
SN74ACT7200L
3
1
G2
(EXPAND)
7
(1ST LOAD)
23
2,4 (REXMIT)
15
G4
(CT = WR PNTR – RD PNTR)
6 (WR PNTR)
6 C1
5 (RD PNTR)
5EN3
(CT = 256) G6
8
21
(CT = 0) G5
20
(EXPAND)
CT > 128
2(CT = 255) G6
4(CT = 255) G6
RS
W
XI
FL/RT
R
FF
EF
XO/HF
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN74ACT7201LA logic symbol
Q1
10
4
D2 Q2
11
3
D3 Q3
12
27
D4 Q4
16
26
D5 Q5
17
25
D6 Q6
18
24
D7 Q7
19
2
D8 Q8
13
1D
6
D0 Q0
9
2,4 CT = 0 (RST)
22
FIFO 512 × 9
Φ
SN74ACT7201LA
5
D1
3
1
G2
(EXPAND)
7
(1ST LOAD)
23
2,4 (REXMIT)
15
G4
(CT = WR PNTR – RD PNTR)
6 (WR PNTR)
6 C1
5 (RD PNTR)
5EN3
(CT = 512) G6
8
21
(CT = 0) G5
20
(EXPAND)
CT > 256
2(CT = 511) G6
4(CT = 511) G6
RS
W
XI
FL/RT
R
FF
EF
XO/HF
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN74ACT7202LA logic symbol
Q1
10
5
D1 4
D2 3
D3 27
D4 26
D5 25
D6 24
D7 2
D8
Q2
11
Q3
12
Q4
16
Q5
17
Q6
18
Q7
19
Q8
13
1D
6
D0 Q0
9
2,4 CT = 0 (RST)
22
FIFO 1024 × 9
Φ
SN74ACT7202LA
3
1
G2
(EXPAND)
7
(1ST LOAD)
23
2,4 (REXMIT)
15
G4
(CT = WR PNTR – RD PNTR)
6 (WR PNTR)
6 C1
5 (RD PNTR)
5EN3
(CT = 1024) G6
8
21
(CT = 0) G5
20
(EXPAND)
CT > 512
2(CT = 1023) G6
4(CT = 1023) G6
RS
W
XI
FL/RT
R
FF
EF
XO/HF
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
Read
Pointer
Location 1
Location 2
256 × 9 or
512 × 9 or
1024 × 9
RAM
Write
Pointer
Write
Control
Reset
Logic
Read
Control
Status-
Flag
Logic
Expansion
Logic
RS
W
XI
FL/RT
R
D0D8
Q0Q8
FF
EF
XO/HF
9
9
256 ×9 for SN74ACT7200L; 512 ×9 for SN74ACT7201LA; 1024 ×9 for SN74ACT7202LA
RESET AND RETRANSMIT FUNCTION TABLE
(single-device depth; single-or multiple-device width)
INPUTS INTERNAL TO DEVICE OUTPUTS
FUNCTION
RS FL/RT XI READ POINTER WRITE POINTER EF FF XO/HF
FUNCTION
L X L Location zero Location zero L H H Reset device
HL L Location zero Unchanged X X X Retransmit
H H L Increment if EF high Increment if FF high X X X Read/write
RESET AND FIRST-LOAD FUNCTION TABLE
(multiple-device depth; single-or multiple-device width)
INPUTS INTERNAL TO DEVICE OUTPUTS
FUNCTION
RS FL/RT XI READ POINTER WRITE POINTER EF FF
FUNCTION
L L Location zero Location zero L H Reset first device
L H Location zero Location zero L H Reset all other devices
H X X X X X Read/write
XI is connected to XO/HF of the previous device in the daisy chain (see Figure 15).
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME I/O DESCRIPTION
D0D8 I Data inputs
EF OEmpty-flag output. EF is low when the read pointer is equal to the write pointer, inhibiting any operation initiated by a read
cycle. When the FIFO is empty , a data word can be read automatically at Q0Q8 by holding R low when loading the data
word with a low-level pulse on W.
FF O
Full-flag output. FF is low when the write pointer is one location less than the read pointer, indicating that the device is
full and inhibiting any operation initiated by a write cycle. FF goes low when the number of writes after reset exceeds the
number of reads by 256 for the SN74ACT7200L, 512 for the SN74ACT7201LA, and 1024 for the SN74ACT7202LA.
When the FIFO is full, a data word can be written automatically into memory by holding W low while reading out another
data word with a low-level pulse on R.
FL/RT I
First-load/retransmit input. FL/RT performs two separate functions. When cascading two or more devices for word-depth
expansion, FL/RT is tied to ground on the first device in the daisy chain to indicate that it is the first device loaded and
unloaded; it is tied high on all other devices in the depth-expansion chain.
A device is not used in depth expansion when its expansion (XI) input is tied to ground. In that case, FL/RT acts as a
retransmit enable. A retransmit operation is initiated when FL/RT is pulsed low . This sets the internal read pointer to the
first location and does not affect the write pointer. R and W must be at a high logic level during the low-level FL/RT
retransmit pulse. Retransmit should be used only when less than 256/512/1024 writes are performed between resets;
otherwise, an attempt to retransmit can cause the loss of unread data. The retransmit function can affect XO/HF
depending on the relative locations of the read and write pointers.
GND Ground
Q0Q8 O Data outputs. Q0Q8 are in the high-impedance state when R is high or the FIFO is empty.
RI
Read-enable input. A read cycle begins on the falling edge of R if EF is high. This activates Q0Q8 and shifts the next
data value to this bus. The data outputs return to the high-impedance state as R goes high. As the last stored word is
read by the falling edge of R, EF transitions low but Q0Q8 remain active until R returns high. When the FIFO is empty ,
the internal read pointer is unchanged by a pulse on R.
RS IReset input. A reset is performed by taking RS low . This initializes the internal read and write pointers to the first location
and sets EF low , FF high, and HF high. Both R and W must be held high for a reset during the window shown in Figure 7.
A reset is required after power up before a write operation can take place.
VCC Supply voltage
WIWrite-enable input. A write cycle begins on the falling edge of W if FF is high. The value on D0D8 is stored in memory
as W returns high. When the FIFO is full, FF is low, inhibiting W from performing any operation on the device.
XI IExpansion-in input. XI performs two functions. XI is tied to ground to indicate that the device is not used in depth
expansion. When the device is used in depth expansion, XI is connected to the expansion-out (XO) output of the previous
device in the depth-expansion chain.
XO/HF O
Expansion-out/half-full-flag output. XO/HF performs two functions. When the device is not used in depth expansion (i.e.,
when XI is tied to ground), XO/HF indicates when half the memory locations are filled. After half of the memory is filled,
the falling edge on W for the next write operation drives XO/HF low . XO/HF remains low until a rising edge of R reduces
the number of words stored to exactly half of the total memory.
When the device is used in depth expansion, XO/HF is connected to XI of the next device in the daisy chain. XO/HF drives
the daisy chain by sending a pulse to the next device when the previous device reaches the last memory location.
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (any input), VI 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH
High level in
p
ut voltage
XI 2.6
V
V
IH
High
-
le
v
el
inp
u
t
v
oltage
Other inputs 2
V
VIL Low-level input voltage 0.8 V
IOH High-level output current –2 mA
IOL Low-level output current 8 mA
TAOperating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range, VCC = 5.5 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH VCC = 4.5 V, IOH = – 2 mA 2.4 V
VOL VCC = 4.5 V, IOL = 8 mA 0.4 V
IOZH VO = VCC, R VIH ±10 µA
IOZL VO = 0.4 V, R VIH ±10 µA
IIVI = 0 to 5.5 V –1 1 µA
I
ta = 15 and 25 ns 125
mA
I
CC1
ta = 35 and 50 ns 50 80
mA
I
ta = 15 and 25 ns
R W RS and FL/RT at V
15
mA
I
CC2
ta = 35 and 50 ns
R
,
W
,
RS
, an
d
FL/RT
a
t
V
IH 5 8
mA
ICC3
ta = 15 and 25 ns
VI=V
CC 02V
0.5
mA
I
CC3
ta = 35 and 50 ns
V
I =
V
CC
0
.
2
V
0.5
mA
Ci§VI = 0, TA = 25°C, f = 1 MHz 8 pF
Co§VO = 0, TA = 25°C, f = 1 MHz 8 pF
ICC1 = supply current; ICC2 = standby current; ICC3 = power-down current. ICC measurements are made with outputs open (only capacitive
loading).
§This parameter is sampled and not 100% tested.
Tested at fclock = 20 MHz
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FIGURE
ACT7200L-15
ACT7201LA-15
ACT7202LA-15
ACT7200L-25
ACT7201LA-25
ACT7202LA-25
ACT7201LA-35
ACT7202LA-35
ACT7200L-50
ACT7201LA-50
ACT7202LA-50 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency, R or W 40 28.5 22.2 15 MHz
tc(R) Cycle time, read 1(a) 25 35 45 65 ns
tc(W) Cycle time, write 1(b) 25 35 45 65 ns
tc(RS) Cycle time, reset 7 25 35 45 65 ns
tc(RT) Cycle time, retransmit 4 25 35 45 65 ns
tw(RL) Pulse duration, R low 1(a) 15 25 35 50 ns
tw(WL) Pulse duration, W low 1(b) 15 25 35 50 ns
tw(RH) Pulse duration, R high 1(a) 10 10 10 15 ns
tw(WH) Pulse duration, W high 1(b) 10 10 10 15 ns
tw(RT) Pulse duration, FL/R T low 4 15 25 35 50 ns
tw(RS) Pulse duration, RS low 7 15 25 35 50 ns
tw(XIL) Pulse duration, XI low 10 15 25 35 50 ns
tw(XIH) Pulse duration, XI high 10 10 10 10 10 ns
tsu(D) Setup time, data before W1(b), 6 11 15 18 30 ns
tsu(RT) Setup time, R and W high
before FL/RT4 15 25 35 50 ns
tsu(RS) Setup time, R and W high
before RS7 15 25 35 50 ns
tsu(XI-R) Setup time, XI low
before R10 10 10 10 15 ns
tsu(XI-W) Setup time, XI low
before W10 10 10 10 15 ns
th(D) Hold time, data after W1(b), 6 0 0 0 5 ns
th(E-R) Hold time, R low after EF5, 11 15 25 35 50 ns
th(F-W) Hold time, W low after FF6, 12 15 25 35 50 ns
th(RT) Hold time, R and W high
after FL/RT4 10 10 10 15 ns
th(RS) Hold time, R and W high
after RS7 10 10 10 15 ns
Released in RJ package only
These values are characterized but not currently tested.
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 13)
PARAMETER FIGURE
ACT7200L-15
ACT7201LA-15
ACT7202LA-15
ACT7200L-25
ACT7201LA-25
ACT7202LA-25
ACT7201LA-35
ACT7202LA-35ACT7200L-50
ACT7201LA-50
ACT7202LA-50 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
taAccess time, R or EF to
data out valid 1(a), 3,
515 25 35 50 ns
tv(RH) Valid time, data out valid
after R1(a) 5 5 5 5 ns
ten(R-QX) Enable time, R to Q
outputs at low impedance1(a) 5 5 10 10 ns
ten(W-QX) Enable time, W to Q
outputs at low
impedanceठ5 5 5 5 15 ns
tdis(R) Disable time, R to Q
outputs at high
impedance1(a) 15 18 20 30 ns
tw(FH) Pulse duration, FF high in
automatic write mode 6 15 25 30 45 ns
tw(EH) Pulse duration, EF high in
automatic read mode 5 15 25 30 45 ns
tpd(W-F) Propagation delay time,
W to FF low 2 15 25 30 45 ns
tpd(R-F) Propagation delay time,
R to FF high 2, 6, 12 15 25 30 45 ns
tpd(RS-F) Propagation delay time,
RS to FF high 7 25 35 45 65 ns
tpd(RS-HF) Propagation delay time,
RS to XO/HF high 7 25 35 45 65 ns
tpd(W-E) Propagation delay time,
W to EF high 3, 5, 11 15 25 30 45 ns
tpd(R-E) Propagation delay time,
R to EF low 3 15 25 30 45 ns
tpd(RS-E) Propagation delay time,
RS to EF low 7 25 35 45 65 ns
tpd(W-HF) Propagation delay time,
W to XO/HF low 8 25 35 45 65 ns
tpd(R-HF) Propagation delay time,
R to XO/HF high 8 25 35 45 65 ns
tpd(R-XOL) Propagation delay time,
R to XO/HF low 9 15 25 35 50 ns
tpd(W-XOL) Propagation delay time,
W to XO/HF low 9 15 25 35 50 ns
tpd(R-XOH) Propagation delay time,
R to XO/HF high 9 15 25 35 50 ns
tpd(W-XOH) Propagation delay time,
W to XO/HF high 9 15 25 35 50 ns
tpd(RT-FL) Propagation delay time,
FL/RT to HF, EF, FF valid 4 25 35 45 65 ns
Released in RJ package only
These values are characterized but not currently tested.
§Only applies when data is automatically read (see Figure 5)
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ta
tc(R)
tw(RH)
tw(RL)
ta
tv(RH) tdis(R)
ten(R-QX)
Valid Valid
R
Q0 –Q8
(a) READ
(b) WRITE
Valid
D0 –D8 Valid
W
tw(WH)
tc(W)
tw(WL)
tsu(D) th(D)
Figure 1. Asynchronous Waveforms
W
FF
R
tpd(W-F) tpd(R-F)
Last Write Ignored
Write First Read Additional Reads
Figure 2. Full-Flag Waveforms
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ÎÎ
ÎÎ
ÎÎ
R
EF
W
tpd(R-E) tpd(W-E)
Last Read Ignored
Read First Write Additional Writes
Valid
D0 –D8
ÎÎ
ÎÎ
ÎÎ
ta
Figure 3. Empty-Flag Waveforms
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
FL/RT
tc(RT)
tw(RT)
tsu(RT) th(RT)
W, R
tpd(RT-FL)
XO/HF, EF, FF Valid Flag
NOTE A: The EF, FF, and XO/HF status flags are valid after completion of the retransmit cycle.
Figure 4. Retransmit Waveforms
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
W
R
th(E-R)
tw(EH)
Valid
Q0 –Q8
EF
tpd(W-E) ta
ten(W-QX)
Figure 5. Automatic-Read Waveforms
R
W
th(F-W)
tw(FH)
Valid
D0 –D8
FF
tpd(R-F)
th(D)
tsu(D)
Figure 6. Automatic-Write Waveforms
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
RS
tc(RS)
tw(RS)
W
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
R
tsu(RS) th(RS)
XO/HF, FF
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
EF
tpd(RS-E)
tpd(RS-HF)
tpd(RS-F)
Figure 7. Master-Reset Waveforms
W
R
XO/HF
Half Full or Less More Than Half Full Half Full or Less
tpd(W-HF)
tpd(R-HF)
Figure 8. Half-Full Flag Waveforms
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
W
R
XO/HF
tpd(W-XOL)
tpd(W-XOH)
Write to Last
Physical Location
Read From Last
Physical Location
tpd(R-XOL) tpd(R-XOH)
Figure 9. Expansion-Out Waveforms
W
R
XI
Write to First
Physical Location
Read From First
Physical Location
tw(XIL) tw(XIH)
tsu(XI-W)
tsu(XI-R)
Figure 10. Expansion-In Waveforms
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
W
EF
tpd(W-E)
R
th(E-R)
Figure 11. Minimum Timing for an Empty-Flag Coincident-Read Pulse
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
R
FF
W
th(F-W)
tpd(R-F)
Figure 12. Minimum Timing for a Full-Flag Coincident-Write Pulse
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
1.5 V1.5 V
3 V
3 V
GND
GND
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data,
Enable
Input
1.5 V 1.5 V 3 V
3 V
GND
GND
High-Level
Input
Low-Level
Input
tw
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
tpd tpd
Input 1.5 V 1.5 V
1.5 V1.5 V
3 V
GND
VOH
VOL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
From Output
Under Test
30 pF
(see Note A)
680
1100
5 V
LOAD CIRCUIT
VOL
VOH
tPLZ 3 V
tPHZ
1.5 V 1.5 V 3 V
GND
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tPZL
1.5 V
0 V
1.5 V
tPZH
Output
Enable
Low-Level
Output
High-Level
Output
NOTE A: Includes probe and jig capacitance
Figure 13. Load Circuit and Voltage Waveforms
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Combining two or more devices to create one FIFO with a greater number of memory bits is accomplished in two
different ways. Width expansion increases the number of bits in each word by connecting FIFOs with the same depth
in parallel. Depth expansion uses the built-in expansion logic to daisy-chain two or more devices for applications
requiring more than 256, 512, or 1024 words of storage. Width expansion and depth expansion can be used together.
width expansion
Word-width expansion is achieved by connecting the corresponding input control to multiple devices with the
same depth. Status flags (EF, FF, and HF) can be monitored from any one device. Figure 14 shows two FIFOs
in a width-expansion configuration. Both devices have their expansion-in (XI) inputs tied to ground. This
disables the depth-expansion function of the device, allowing the first-load/retransmit (FL/RT) input to function
as a retransmit (RT) input and the expansion-out/half-full (XO/HF) output to function as a half-full (HF) flag.
depth expansion
The SN74ACT7200L/7201LA/7202LA is easily expanded in depth. Figure 15 shows the connections used to
depth expand three SN74ACT7200L/7201LA/7202LA devices. Any depth can be attained by adding additional
devices to the chain. The SN74ACT7200L/7201LA/7202LA operates in depth expansion under the following
conditions:
D
The first device in the chain is designated by tying FL to ground.
D
All other devices must have their FL inputs at a high logic level.
D
XO of each device must be tied to XI of the next device.
D
External logic is needed to generate a composite FF and EF. All FF outputs must be ORed together and
all EF outputs must be ORed together.
D
RT and HF functions are not available in the depth-expanded configuration.
combined depth and width expansion
Both expansion techniques can be used together to increase depth and width. This is done by first creating
depth-expanded units and then connecting them in a width-expanded configuration (see Figure 16).
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
D0D8
D0D8
W
R
FL/RT
RS
XI
W
R
FL/RT
RS
XI
D0D18
W
R
RT
RS
18 D0 – D8
D9 – D18
Q0 – Q8
Q9 – Q18
18
9
99
9
Q0Q8
Q0Q8
EF
FF
XO/HF
EF
FF
XO/HF
Q0Q18
EF
FF
HF
EF
FF
HF
SN74ACT7200L/7201LA/7202LA
SN74ACT7200L/7201LA/7202LA
Figure 14. Word-Width Expansion: 256/512/1024 Words × 18 Bits
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
XO/HF
FF
XO/HF
D0D8
D0D8
W
R
FL/RT
RS
XI
W
R
FL/RT
RS
XI
D0D8
W
R
VCC
RS
9 9
99
Q0Q8
Q0Q8
EF
EF
FF
Q0Q8
EF
FF
XO/HF
D0D8
W
R
FL/RT
RS
XI
99
Q0Q8
EF
FF
SN74ACT7200L/7201LA/7202LA
SN74ACT7200L/7201LA/7202LA
SN74ACT7200L/7201LA/7202LA
9 9
Figure 15. Word-Depth Expansion: 768/1536/3072 Words × 9 Bits
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
20 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Q0Q17 Q0Q26
D0D26 D9D26
W, R, RS
Q0Q8 Q9Q17 Q18Q26
D0D8 D9D17 D18D26
ACT7200L,
ACT7201LA, or
ACT7202LA
Depth-
Expansion
Block
ACT7200L,
ACT7201LA, or
ACT7202LA
Depth-
Expansion
Block
ACT7200L,
ACT7201LA, or
ACT7202LA
Depth-
Expansion
Block
18 27
99 9
9 9 9
1827
Figure 16. Word-Depth Plus Word-Width Expansion