Package LW 16-pin SOICW
▪ Multiplexed LED displays
▪ Incandescent lamps
Package A 16-pin DIP
Description
A merged combination of bipolar and MOS technology
gives these devices an interface flexibility beyond the reach
of standard logic buffers and power driver arrays. Typical
applications include driving multiplexed LED displays or
incandescent lamps.
The A6821 has an eight-bit CMOS shift register and CMOS
control circuitry, eight CMOS data latches, and eight bipolar
current-sinking Darlington output drivers.
The CMOS inputs are compatible with standard CMOS logic
levels. TTL circuits may require the use of appropriate pull-up
resistors. By using the serial data output, the drivers can be
cascaded for interface applications requiring additional drive
lines.
The A6821SA is furnished in a standard 16-pin plastic DIP.
The A6821EA is a 16-pin plastic DIP, capable of operation
from -40°C to 85°C. The A6821SLW is a 16-lead wide-body
SOIC, for surface-mount applications. These devices are lead
(Pb) free, with 100% matte tin plated leadframes.
26185.112E
Features and Benefits
▪ 3.3 to 5 V logic supply range
▪ Power on reset (POR)
▪ To 10 MHz data input rate
▪ CMOS, TTL compatible
▪ –40°C operation available
▪ Schmitt trigger inputs for improved noise immunity
▪ Low-power CMOS logic and latches
▪ High-voltage current-sink outputs
▪ Internal pull-up/pull down resistors
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Packages:
Applications:
Functional Block Diagram
A6821
MOS
BIPOLAR
OUT 1OUT 2
LOGIC
GROUND STROBE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
OUT 3
CLOCK
SERIAL
DATA IN
S ER IAL-PAR ALLE L S HIFT R EGIS TE R
LATCHES
VDD
LOGIC
SUPPLY
OUT 6OUT 7OUT 8
OUT 4OUT 5
POWER
GROUND
SUB
Not to scale
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6821
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Logic Supply Voltage VDD 7V
Input Voltage Range VIN
Caution: CMOS devices have input-static
protection, but are susceptible to damage when
exposed to extremely high static-electrical
charges.
–0.3 to VDD + 0.3 V
Output Voltage VOUT 50 V
Continuous Output Current IOUT 500 mA
Power Dissipation PD
A package 2.1 W
LW package 1.5 W
Operating Ambient Temperature TA
Range E –40 to 85 ºC
Range S –20 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Selection Guide
Part Number Package Ambient (ºC) Packing
A6821SA-T 16-pin DIP –20 to 85 25 pieces per tube
A6821EA-T* 16-pin DIP –40 to 85 25 pieces per tube
A6821SLWTR-T 16-pin wide body SOIC –20 to 85 1000 pieces per reel
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is
obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant
should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer
available. Status date change November 2, 2009. Deadline for receipt of LAST TIME BUY orders is April 30, 2010.
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6821
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V
Characteristic Symbol Test Conditions
Vdd = 3.3 V Vdd = 5 V
Units
Min. Typ. Max. Min. Typ. Max.
Output Leakage Current ICEX VOUT = 50 V – – 10 – – 10 A
Collector–Emitter Saturation
Voltage VCE(SAT)
IOUT = 100 mA – – 1.1 – – 1.1 V
IOUT = 200 mA – – 1.3 – – 1.3 V
IOUT = 350 mA – – 1.6 – – 1.6 V
Input Voltage VIN(1) 2.2 – – 3.3 – – V
VIN(0) – – 1.1 – – 1.7 V
Input Resistance RIN 50 – – 50 – – k
Serial Data Output Voltage VOUT(1) IOUT = –200 A 2.8 3.05 – 4.5 4.75 – V
VOUT(0) IOUT = 200 A – 0.15 0.3 – 0.15 0.3 V
Maximum Clock Frequency2fc10 – – 10 – – MHz
Logic Supply Current
IDD(1) One output on, OE = L, ST = H – – 2.0 – – 2.0 mA
IDD(0)
All outputs off, OE = H, ST = H,
P1 through P8 = L – – 100 – – 100 A
Output Enable-to-Output Delay tdis(BQ) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
ten(BQ) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Strobe-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
tp(STH-QH) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Output Fall Time tfVCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Output Rise Time trVCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Clock-to-Serial Data Out Delay tp(CH-SQX) IOUT = ±200 A – 50 – – 50 – ns
1Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin.
2Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed.
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
OE = Output Enable
ST = Strobe
Serial Shift Register Contents Serial Latch Contents Output Output Contents
Data Clock Data Strobe Enable
Input Input I1I2I3... I8Output Input I1I2I3... I8Input I1I2I3... I8
R7
R7
R
1R2R3... R8
R8
X X X ... X X
X
L
R1R2... R7
L
L
R1R2R3... R8
P1P2P3... P8P8P1P2P3... P81
P2P3... P8
XXX...X
LP
HH
HH
H
R1R2... R7
H
H
H...
Truth Table
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6821
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Timing Requirements and Specifi cations
(Logic Levels are VDD and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT ENABLE
OUT
N
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A B
D E
LOW = ALL OUTP UTS E NABLE D
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
OUTPUT ENABLE
OUT
N
DATA
10%
50%
dis(BQ)
t
en(BQ)
t
HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be
attainable; operation at high temperatures will reduce the specifi ed maxi-
mum clock frequency.
Powering-on with the inputs in the low state ensures that the registers and
latches power-on in the low state (POR).
Serial Data present at the input is transferred to the shift register on the logical
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK
pulses, the registers shift data information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the input prior to the rising edge of the
CLOCK input waveform.
Information present at any register is transferred to the respective latch
when the STROBE is high (serial-to-parallel conversion). The latches will
continue to accept new data as long as the STROBE is held high. Applica-
tions where the latches are bypassed (STROBE tied high) will require that
the OUTPUT ENABLE input be high during serial data entry.
When the OUTPUT ENABLE input is high, all of the output buffers are
disabled (OFF). The information stored in the latches or shift register is not
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE
input low, the outputs are controlled by the state of their respective latches.
Key Description Symbol Time (ns)
A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25
B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25
C Clock Pulse Width tw(CH) 50
D Time Between Clock Activation and Strobe tsu(C) 100
E Strobe Pulse Width tw(STH) 50
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6821
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8 67% 59% 54% 49% 43%
7 77% 68% 62% 56% 49%
6 90% 79% 72% 65% 57%
5 100% 95% 86% 78% 68%
4 100% 100% 100% 98% 86%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%
A6821SLW
A6821SA/A6821EA
Number of
Outputs ON
Ambient Temperature
25°C40°C50°C60°C70°C
8 90% 79% 72% 65% 57%
7 100% 90% 82% 74% 65%
6 100% 100% 96% 86% 76%
5 100% 100% 100% 100% 91%
4 100% 100% 100% 100% 100%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%
Terminal List Table
Name Description Pin
CLK Clock 1
Serial Data In 2
Logic Ground* 3
VDD Logic Supply 4
Serial Data Out 5
ST Strobe 6
OE Output Enable (active low) 7
SUB Power Ground* 8
OUT8Serial Data Output 9
OUT7Serial Data Output 10
OUT6Serial Data Output 11
OUT5Serial Data Output 12
OUT4Serial Data Output 13
OUT3Serial Data Output 14
OUT2Serial Data Output 15
OUT1Serial Data Output 16
* There is an indeterminate resistance between logic ground and power ground.
For proper operation, these terminals must be externally connected together.
Maximum Allowable Duty Cycle, IOUT = 200 mA, VDD = 5 V
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6821
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LW
16-pin Wide Body SOIC
2
3
4
5
6
7
8
SERIAL
DATA OUT
SERIAL
DATA IN
OUTPUT
ENABLE
LOGIC
SUPPLY
STROBE
LOGIC
GROUND
CLOCK CLK
V
ST
OE
DD
1
SUB
POWER
GROUND
SHIFT REGISTER
LATCHES
9
10
11
12
13
14
15
16 OUT
1
OUT
2
OUT
3
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
Package A
16-pin DIP
2
3
4
5
6
7
8
SERIAL
DATA OUT
SERIAL
DATA IN
OUTPUT
ENABLE
LOGIC
SUPPLY
STROBE
LOGIC
GROUND
CLOCK CLK
V
ST
OE
DD
1
SUB
POWER
GROUND
SHIFT REGISTER
LATCHES
9
10
11
12
13
14
15
16 OUT
1
OUT
2
OUT
3
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
Typical Input Circuits Typical Output Driver
CLOCK
SERIAL
DATA IN
VDD
STROBE
OUTPUT
ENABLE
VDD
OUT
7.2 k 3 k
SUB
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6821
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package A
16-pin DIP
Package LW
16-pin Wide Body SOIC
2
19.05±0.25
5.33 MAX
0.46 ±0.12
1.27 MIN
1
16
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
0.25 +0.10
–0.05
7.62
2.54
For Reference Only
(reference JEDEC MS-001 BB)
Dimensions in inches, metric dimensions (mm) in brackets, for reference only
9.50
0.65
2.25
1.27
C
SEATING
PLANE
1.27
0.25
0.20 ±0.10
0.41 ±0.10 2.65 MAX
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
10.30±0.20
C0.10
16X
21
16
GAUGE PLANE
SEATING PLANE
For Reference Only
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
A
BReference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
BPCB Layout Reference View
21
16
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6821
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2004-2009, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
