IS61C256AH _ IS61M256 a ISST 32K x 8 HIGH-SPEED CMOS STATIC RAM AUGUST 1995 FEATURES DESCRIPTION * High-speed access time: 10, 12, 15, 20, 25 ns The ISS/1S61C256AH and IS61M256 are very high-speed, low power, 32,768 word by 8-bit static RAMs. They are * Low active power: 400 mW (typical) fabricated using /SS/'s high-performance CMOS technology. * Low standby power This highly reliable process coupled with innovative circuit 250 pW (typical) CMOS standby design techniques, yields access times as fast as 10 ns 55 mW (typical) TTL standby mas Fully static operation: no clock or refresh When CEis HIGH (deselected), the device assumes a standby required mode at which the power dissipation can be reduced down to * TTL compatible inputs and outputs 250 uW (typical) with CMOS input levels. * Single 5V power supply Easy memory expansion is provided by using an active LOW * Mix-mode outputs on IS61M256 Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C256AH and IS61M256 are pin compatible with other 32K x 8 SRAMs and are available in 28-pin PDIP, SOJ, and TSOP packages. FUNCTIONAL BLOCK DIAGRAM 256 X 1024 MEMORY ARRAY AQ-A14 DECODER vcc > GND > vO DATA CIRCUIT 00-07 COLUMN 1/0 oO m CONTROL CIRCUIT | Al = mi (SSI reserves Ihe right to make changes to its products al any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1995, Integrated Silicon Solution, Inc. integrated Silicon Solution, Inc. 2-9 SR 995AH2551S61C256AH 1S61M256 PIN CONFIGURATION a [SSI PIN CONFIGURATION 28-Pin DIP and SOJ 28-Pin TSOP WJ ; A1a (1 2e[] vec o C22 aif] ato AN 23 207) CE At2 [l2 271) WE Ag C24 19] v07 a7 []3 26(] A13 AB 25 18 5 vO6 A13 [7] 26 179) vos Ae [4 251] a8 WE (27 16] vO4 as []5 24[] ag voc [] 28 18] 03 aia 147] GND AA is 6 2at] att A12 2 13[-} voe A3 []7 221] OE a7 43 12 vot AG 4 1 (00 a2 []8 aif] ato aot "et ve Ai [9 20[] CE a4 Ch6 of] at Ao [] 10 191] 07 a3 C7 sP) Ae voo [14 181] O06 A3 [47 al A2 vor [] 12 171] vos ae oF at vo2 [] 13 16[] 04 as C15 B AO GN 14 15[] 03 as (4 117] vOo of Hv A7 (3 12 vo1 Ai2 [Je 13[-] oe Ata C1 147] GND vec C128 * 15 03 we ([] 27 16f[_] oa A13 (26 1777 vos As C] 25 t8{_] 1/06 Ag ([] 24 ee vo7 Atty C23 20{7] CE OE [J 22 Reverse Pinout 211) Ato PIN DESCRIPTIONS AO0-A14 Address Inputs TRUTH TABLE CE Chip Enable Input WE GE GE OE Output Enable Input Mode WE E E WOOperation Vcc Current WE : Not Selected X H X High-Z Ise1, IsB2 WE Write Enable Input (Power-down) VO0-VO7 _ Bidirectional Ports Output DisabledH LH High-Z Icct, loc2 Vec Power Read H L L Dout Icc1, loca GND Ground Write L L x Din lect, Icc2 ABSOLUTE MAXIMUM RATINGS") Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND 0.5 to +7.0 Vv TBIAS Temperature Under Bias 55 to +125 C TstG Storage Temperature 65 to +150 C Pr Power Dissipation 1.5 Ww lout DC Output Current (LOW) 20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2-10 Integrated Silicon Solution, ine. Rev. F 0995 SR81995AH2561S61C256AH IS61M256 [SST OPERATING RANGE Range Ambient Temperature Vee" Commercial 0C to +70C 5V + 10% Industrial -40C to +85C 5V + 10% Notes: 1. Vcc = 5V + 5% for 10 ns only. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit Vou Output HIGH Voltage Vcc = Min., lon = -4.0 mA 2.4 _ Vv VoL Output LOW Voltage Vcc = Min., lo. = 8.0 mA _ 0.4 Vv VIH Input HIGH Voltage 2.2 Veco + 0.5 Vv Viv input LOW Voltage) -0.5 0.8 Vv lu Input Leakage GND < Vin < Vcc Com. -5 5 pA Ind. ~10 +10 ILo Output Leakage GND < Vout < Vcc, Com. -5 5 HA Outputs Disabled Ind. -10 +10 Notes: 1. Vit = -3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS (Over Operating Range) 10 ns -12 ns -15 ns -20 ns -25 ns Symbol Parameter Test Conditions Min. Max. Min, Max. Min. Max. Min. Max. Min, Max. Unit lec Vee Dynamic Operating Vcc = Max., CE = Vin Com. 180 160 150 140 130 mA Supply Current lout = 0 mA, f = fmax Ind. - 170 160 150 140 Isp TTL Standby Current = Vcc = Max., Com. - 2 -- 2 2 2 2 mA (TTL Inputs) Vin = Vin or Vie Ind. - - = 0 - 30 ~ 80 39 CE > Vin, f= 0 Isp2 CMOS Standby Vcc = Max., Com. - 5 2 = 2 2 2 mA Current (CMOS Inputs) CE>Vcc-0.2V, ind. - -- 10 0 10 10 Vin 2 Vec - 0.2V, or Vin <0.2V, f=0 Notes: 1. Atf = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE") Symbol Parameter Conditions Max. Unit Cin input Capacitance Vin = OV 8 pF Cout Output Capacitance Vout = OV 10 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vcc = 5.0V. integrated Silicon Solution, Inc. 2-11 SRI 995AH2861S61C256AH IS61M256 ISS READ CYCLE SWITCHING CHARACTERISTICS" (Over Operating Range) 10 ns 12 ns -15 ns -20 ns -25 ns Symbol Parameter Min. Max Min. = Max. Min. Max. Min. Max. Min. Max. Unit tre Read Cycle Time 10 12 _ 15 ao 35 ns taa Address Access Time _ 10 _ 12 15 2 _ 25 ns toHaA = Output Hold Time 2 2 _ 2 _ 2 - 2 ns tace CE Access Time - 10 _ 12 _ 15 - 2 - 2 ns tooe OE Access Time - 5 6 _ 7 8 ~ 9 ns tizoe OE to Low-Z Output 0 0 0 ~ oO 0 ns tHzoE OE to High-Z Output - 6 7 9g 10 ns tice CE to Low-Z Qutput 2 = 3 _ 3 3 = 3 - ns tuzce CE to High-Z Output - - 7 - 8 - 9 10 ns teu CE to Power-Up oO 0 0 oO 0 _ ns tro CE to Power-Down - 10 12 15 1 2 ns Notes: t. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured +500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level OV to 3.0V Input Rise and Fall Times 3ns Input and Output Timing 1.5V and Reference Levels Output Load See Figures 1a and 1b AC TEST LOADS 5V OUTPUT 480 (2 30 pF Including jig and scope = = Figure 1a. 255 Q 480 Q 5V OUTPUT 5 pF 255 Including jig and scope = Figure 1b. 2-12 integrated Silicon Solution, Inc. Rev. F 0995 SR81995AH256IS61C256AH 1S61M256 [SSI AC WAVEFORMS READ CYCLE NO. 1") ADDRESS = . E -1OHA ae toHA DOUT DATA VALID READ CYCLE NO. 2") tRC .--.--_-| tRC y ADDRESS tAA _ <# {OHA OE \ NX 7 -<i-- {DOE Le tHZOE | CE \ pt tLZ08 7 <t- tACE 4 at tLZCE m |< tHZCE - DOUT HIGH 2 < xX DATA VALID - hat {PU a PD ____| icc SUPPLY 50% 50% CURRENT (SB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vie. 3. Address is valid prior to or coincident with CE LOW transitions. integrated Silicon Solution, Inc. 2-13 Rev. F 0995 SAB199SAH2561S61C256AH IS61M256 a [SSI WRITE CYCLE SWITCHING CHARACTERISTICS" (Over Operating Range) -10 ns -12 ns -15 ns -20 ns -25 ns Symbol Parameter Min. Max Min. = Max. Min. = Max. Min. Max. Min. Max. Unit twe Write Cycle Time 10 - 12 - 15 20 _ 25 ns tsce. CE to Write End 9 = 10 _ 12 - 13.0- 1 ns taw Address Setup Time 9 10 12 _ 15 20 _ ns to Write End tHa Address Hold 0 _ 0 _ 0 _ 0 _ 0 _ ns from Write End tsa Address Setup Time 0 0 _ 0 _ 0 _ 0 _ ns tewe"' WE Pulse Width 8 8 - 10 _ 100 15 ns tso Data Setup to Write End 8 _ 8 _ 9 _ Ww 12 _ ns tHo Data Hold from Write End 0 - 0 _ 0 _ 0 - 0 _ ns tuzwe WE LOW to High-Z Output 6 - 6 7 - 8 10 ns tiawe WEHIGH to Low-Z Output 0 0 - 0 _ 0 0 _ ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure ta. 2. Tested with the load in Figure 1b. Transition is measured +500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)? two ADDRESS /+___ tsce. __ tHA CE \ 7 - WE <0-tSA x }- tLZ2wWe -> DOUT DATA UNDEFINED > an re * |ae t0 ole tHD DIN DATA-IN VALID 2-14 Integrated Silicon Solution, Ine. Rev. F 0995. SRB 1995AH2561S61C256AH 1S61M256 WRITE CYCLE NO. 2 (CE Controlled)" [SST ADDRESS CE WE DOUT DIN j<%$ AA tw, ____________ x jt-tSA ~~ SN tSCE iN tat THA jh ZL tPWE UN |} THZWE >| DATA UNDEFINED |< tAW_- __________ | KY fo tL2WE > HIGH-Z / tSD -< tHD DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. /O will assume the High-Z state if OF > Vin. Integrated Silicon Solution, inc. Rev. F 0995 SRB1995AH256 2-15IS61C256AH 1S61M256 [SSI ORDERING INFORMATION: IS61C256AH Commercial Range: 0C to +70C ORDERING INFORMATION: 1S61C256AH Industrial Range: 40C to +85C Speed (ns) Order Part Number Package Speed (ns) Order Part Number Package 10 IS61C256AH-10N 300-mil Plastic DIP 12 IS61C256AH-12NI 300-mil Plastic DIP 10 IS61C256AH-10J 300-mil Plastic SOJ 12 IS61C256AH-12JI 300-mil Plastic SOJ 12 1S61C256AH-12N 300-mil Plastic DIP 15 1S61C256AH-15NI 300-mil Plastic DIP 12 1S61C256AH-12J 300-mil Plastic SOJ 15 1S61C256AH-15uJl 300-mil Plastic SOJ 15 IS61C256AH-15N 300-mil Plastic DIP 20 IS61C256AH-20NI 300-mil Plastic DIP 15 IS61C256AH-15J 300-mil Plastic SOJ 20 IS61C256AH-20JI 300-mil Plastic SOJ 15 1S61C256AH-15T 450-MIL TSOP : . 25 IS61C256AH-25NI 300-mil Plastic DIP 15 IS61C256AH-15TR TSOP Reverse Pinout 25 IS61C256AH-25ul 300-mit Plastic SOJ 20 1S61C256AH-20N 300-mil Plastic DIP 20 1S61C256AH-20J 300-mil Plastic SOJ 20 1S61C256AH-20T 450-MIL TSOP 20 IS61C256AH-20TR TSOP Reverse Pinout 25 1IS61C256AH-25N 300-mil Plastic DIP 25 IS61C256AH-25J 300-mil Plastic SOJ ORDERING INFORMATION: IS61M256 Commercial Range: 0C to +70C Speed (ns) Order Part Number Package 10 IS61M256-10N 300-mil Plastic DIP 10 IS61M256-10J 300-mil Plastic SOJ 12 IS61M256-12N 300-mil Plastic DIP 12 IS61M256-12J 300-mil Plastic SOJ 15 IS61M256-15N 300-mil Plastic DIP 15 IS61M256-15J 300-mil Piastic SOU 20 IS61M256-20N 300-mi! Plastic DIP 20 1S61M256-20J 300-mil Plastic SOJ 25 IS61M256-25N 300-mil Plastic DIP 25 1S61M256-25J 300-mil Plastic SOJ 2-16 Integrated Silicon Solution, inc. Rev. F 0995 SR81995AH256