SN54ABT573, SN74ABT573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190F − JANUARY 1991 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DTypical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C
DHigh-Drive Outputs (−32-mA IOH, 64-mA IOL)
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54ABT573 ...J OR W PACKAGE
SN74ABT573A . . . DB, DW, N, NS,
OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
SN54ABT573...FK PACKAGE
(TOP VIEW)
2D
1D
OE
8Q
7Q 1Q
8D
GND
LE
VCC
SN74ABT573A . . . RGY PACKAGE
(TOP VIEW)
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
LE V
GND
CC
OE
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube SN74ABT573AN SN74ABT573AN
QFN − RGY Tape and reel SN74ABT573ARGYR AB573A
SOIC DW
Tube SN74ABT573ADW
ABT573A
SOIC − DW Tape and reel SN74ABT573ADWR ABT573A
40°Cto85°C
SOP − NS Tape and reel SN74ABT573ANSR ABT573A
−40°C to 85°CSSOP − DB Tape and reel SN74ABT573ADBR AB573A
TSSOP PW
Tube SN74ABT573APW
AB573A
TSSOP − PW Tape and reel SN74ABT573APWR AB573A
VFBGA − GQN
Tape and reel
SN74ABT573AGQNR
AB573A
VFBGA − ZQN (Pb-free) Tape and reel SN74ABT573AZQNR AB573A
CDIP − J Tube SNJ54ABT573J SNJ54ABT573J
−55°C to 125°CCFP − W Tube SNJ54ABT573W SNJ54ABT573W
55 C
to
125 C
LCCC − FK Tube SNJ54ABT573FK SNJ54ABT573FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT573, SN74ABT573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190F − JANUARY 1991 − REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
terminal assignments
1234
A1D OE VCC 1Q
B3D 3Q 2D 2Q
C5D 4D 5Q 4Q
D7D 7Q 6D 6Q
EGND 8D LE 8Q
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
OE LE D
OUTPUT
Q
L H H H
LHL L
LLX Q
0
H X X Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
2
19
LE
1D
C1
1D 1Q
Pin numbers shown are for the DB, DW, FK, J, N, NS, PW, RGY, and W packages.
SN74ABT573A . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1234
A
B
C
D
E
SN54ABT573, SN74ABT573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190F − JANUARY 1991 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO −0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT573 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT573A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): GQN/ZQN package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 37°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54ABT573 SN74ABT573A
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current −24 −32 mA
IOL Low-level output current 48 64 mA
Δt/ΔvInput transition rise or fall rate Outputs enabled 5 5 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54ABT573, SN74ABT573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190F − JANUARY 1991 − REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT573 SN74ABT573A
UNIT
PARAMETER TEST CONDITIONS MIN TYP†MAX MIN MAX MIN MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 −1.2 V
VCC = 4.5 V, IOH = −3 mA 2.5 2.5 2.5
V
VCC = 5 V, IOH = −3 mA 3 3 3
V
VOH
V45V
IOH = −24 mA 2 2 V
VCC = 4.5 V IOH = −32 mA 2* 2
V
V45V
IOL = 48 mA 0.55 0.55
V
VOL VCC = 4.5 V IOL = 64 mA 0.55* 0.55 V
Vhys 100 mV
IIVCC = 5.5 V, VI = VCC or GND ±1±1±1μA
IOZH VCC = 5.5 V, VO = 2.7 V 10‡10‡10‡μA
IOZL VCC = 5.5 V, VO = 0.5 V −10‡−10‡−10‡μA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 μA
ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 μA
IO§VCC = 5.5 V, VO = 2.5 V −50 −100 −180 −50 −180 −50 −180 mA
V55V I 0
Outputs high 1 250 250 250 μA
ICC
VCC = 5.5 V, IO = 0,
VI=V
CC or GND
Outputs low 24 30 30 30 mA
ICC
V
I =
V
CC or
GND
Outputs disabled 0.5 250 250 250 μA
ΔICC¶VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1.5 1.5 1.5 mA
CiVI = 2.5 V or 0.5 V 3.5 pF
CoVO = 2.5 V or 0.5 V 6.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†All typical values are at VCC = 5 V.
‡This data sheet limit may vary among suppliers.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT573
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
MIN
MAX
twPulse duration, LE high 3.3 3.3 ns
t
Setup time data before LE↓
High 1.9 2.5
ns
tsu Setup time, data before LE
↓
Low 1.5 2.5 ns
thHold time, data after LE↓1 2.5 ns
SN54ABT573, SN74ABT573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190F − JANUARY 1991 − REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT573A
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
MIN
MAX
twPulse duration, LE high 3.3 3.3 ns
t
Setup time data before LE↓
High 1.9 1.9
ns
tsu Setup time, data before LE↓Low 1.5 1.5 ns
thHold time, data after LE↓1.8†1.8†ns
†This data-sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT573
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CMIN MAX UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX
MIN
MAX
tPLH
D
Q
1.9 3.2 5.4 1.4 6.4
ns
tPHL
D Q 2.2 4.2 5.7 1.6 6.7 ns
tPLH
LE
Q
2.2 4 6.1 2 7.1
ns
tPHL
LE Q3.2 5.2 6.7 2.8 7.5 ns
tPZH
OE
Q
1.2 3.2 4.7 0.8 6.2
ns
tPZL
OE Q2.7 4.7 6.2 2 7.2 ns
tPHZ
OE
Q
2.5 4.9 6.4 2.2 7.7
ns
tPLZ
OE Q2 4.2 6 1.4 7 ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT573A
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CMIN MAX UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX
MIN
MAX
tPLH
D
Q
1.9 3.2 5.4 1.9 5.9
ns
tPHL
D Q 2.2 4.2 5.7 2.2 6.2 ns
tPLH
LE
Q
2.2 4 6.1 2.2 6.6
ns
tPHL
LE Q3.2 5.2 6.7 3.2 7.2 ns
tPZH
OE
Q
1.2 3.2 4.7 1.2 5.2
ns
tPZL
OE Q2.5†4.7 6.2 2.5†6.7 ns
tPHZ
OE
Q
2.5 4.9 6.4 2.5 7.1†
ns
tPLZ
OE Q2 4.2 6 2 6.5 ns
†This data-sheet limit may vary among suppliers.
SN54ABT573, SN74ABT573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190F − JANUARY 1991 − REVISED SEPTEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
Output
Control
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9321901Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9321901Q2A
SNJ54ABT
573FK
5962-9321901QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9321901QR
A
SNJ54ABT573J
5962-9321901QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9321901QS
A
SNJ54ABT573W
SN74ABT573ADBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI -40 to 85
SN74ABT573ADBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573ADW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573ADWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573AN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT573AN
SN74ABT573ANE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT573AN
SN74ABT573ANSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74ABT573ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT573A
SN74ABT573APW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573APWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85
SN74ABT573APWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB573A
SN74ABT573ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AB573A
SN74ABT573ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AB573A
SNJ54ABT573FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9321901Q2A
SNJ54ABT
573FK
SNJ54ABT573J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9321901QR
A
SNJ54ABT573J
SNJ54ABT573W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9321901QS
A
SNJ54ABT573W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT573 :
•Catalog: SN74ABT573
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ABT573ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ABT573ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74ABT573ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74ABT573APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74ABT573ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ABT573ADBR SSOP DB 20 2000 367.0 367.0 38.0
SN74ABT573ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74ABT573ANSR SO NS 20 2000 367.0 367.0 45.0
SN74ABT573APWR TSSOP PW 20 2000 367.0 367.0 38.0
SN74ABT573ARGYR VQFN RGY 20 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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