© Semiconductor Components Industries, LLC, 2009
September, 2019 − Rev. 4 1Publication Order Number:
FQD3P50/D
MOSFET – P-Channel,
QFET)
FQD3P50
-500 V, 4.9 W, -2.1 A
Description
This P−Channel enhancement mode power MOSFET is produced
using ON Semiconductor’s proprietary planar stripe and DMOS
technology. This advanced MOSFET technology has been especially
tailored to reduce on−state resistance, and to provide superior
switching performance and high avalanche energy strength. These
devices are suitable for switched mode power supplies, active power
factor correction (PFC), and electronic lamp ballasts.
Features
•−2.1 A, −500 V, RDS(on) = 4.9 W (Max.) @ VGS = −10 V,
ID = −1.05 A
•Low Gate Charge (Typ. 18 nC)
•Low Crss (Typ. 9.5 pF)
•100% Avalanche Tested
•These Devices are Pb−Free and are RoHS Compliant
ABSOLUTE MAXIMUM RATINGS (T
C
= 20
°
C unless otherwise noted)
Symbol
Parameter
Value
Unit
V
DSS
Drain−Source Voltage
−500
V
IDDrain Current
− Continuous (TC = 25°C)
− Continuous (TC = 100°C) −2.1
−1.33
A
I
DM
Drain Current − Pulsed (Note 1)
−8.4
A
V
GSS
Gate−Source Voltage
±
30
V
E
AS
Single Pulsed Avalanche Energy (Note 2)
250
mJ
I
AR
Avalanche Current (Note 1)
−2.1
A
E
AR
Repetitive Avalanche Energy (Note 1)
5.0
mJ
dv/dt
Peak Diode Recovery dv/dt (Note 3)
−4.5
V/ns
PD
Power Dissipation (T
A
= 25
°
C) (Note 4)
2.5 W
Power Dissipation (TC = 25°C)
− Derate above 25°C50
0.4 W
W/°C
T
J
, T
STG
Operating and Storage Temperature
Range
−55 to +150
°
C
T
L
Maximum lead temperature for soldering
purposes, 1/8″ from case for 5 seconds
300
°
C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be af fected.
1. Repetitive Rating: Pulse width limited by maximum junction temperature.
2. L = 102 mH, IAS = −2.1 A, VDD = −50 V, RG = 25 W, Starting TJ = 25°C.
3. ISD ≤ −2.7 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, Starting TJ = 25°C.
4. When mounted on the minimum pad size recommended (PCB Mount).
Device Package Shipping†
ORDERING INFORMATION
DPAK3
CASE 369AS
MARKING DIAGRAM
$Y = ON Semiconductor Logo
&Z = Assembly Code
&3 = Date Code (Year and Week)
&K = Lot Code
FQD3P50 = Specific Device Code
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†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
FQD3P50 DPAK3
(Pb−Free) 2,500 /
Tape & Reel
G
S
D
G
S
D
$Y&Z&3&K
FQD
3P50
FQD3P50
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2
THERMAL CHARACTERISTICS
Symbol Parameter
FQD3P50
Unit
R
θJC Thermal Resistance, Junction−to−Case, Max. 2.5 °C/W
R
θJA Thermal Resistance, Junction−to−Ambient, Max. (Note 5) 50 °C/W
R
θJA Thermal Resistance, Junction−to−Ambient, Max. 110 °C/W
5. When mounted on the minimum pad size recommended (PCB Mount).
ELECTRICAL CHARACTERISTICS (T
C
= 25
°
C unless otherwise noted)
Symbol
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
DSS Drain−Source Breakdown Voltage
V
GS
= 0 V, I
D
= −250 mA
−500 − − V
D
BV
DSS
/
D
T
J
ficient
I
D
= −250 mA, Referenced to 25
°
C
−
0.42
−
V/
°
C
IDSS Zero Gate Voltage Drain Current
V
DS
= −500 V, V
GS
= 0 V
−
−
−1
m
A
V
DS
= −400 V, T
C
= 125
°
C
− − −10 m
A
I
GSSF Gate−Body Leakage Current, Forward
V
GS
= −30 V, V
DS
= 0 V
− − −100 nA
I
GSSR Gate−Body Leakage Current, Reverse
V
GS
= 30 V, V
DS
= 0 V
− − 100 nA
ON CHARACTERISTICS
V
GS(th)
V
DS
= V
GS
, I
D
= −250 mA
−3.0
−
−5.0
V
R
DS(on)
V
GS
= −10 V, I
D
= −1.05 A
−
3.9
4.9
W
g
FS
V
DS
= −50 V, I
D
= −1.05 A
−
2.1
−
S
DYNAMIC CHARACTERISTICS
C
iss
VDS = −25 V, VGS = 0 V,
f = 1.0 MHz
−
510
660
pF
C
oss Output Capacitance − 70 90 pF
C
rss Reverse Transfer Capacitance − 9.5 12 pF
SWITCHING CHARACTERISTICS
t
d(on)
VDD = −250 V, ID = −2.7 A,
RG = 25 W
(Note 6)
−
12
35
ns
t
r
−
56
120
ns
t
d(off)
−
35
80
ns
t
f
−
45
100
ns
Q
gTotal Gate Charge VDS = −400 V, ID = −2.7 A,
VGS = −10 V
(Note 6)
− 18 23 nC
Q
gs Gate−Source Charge − 3.6 − nC
Q
gd Gate−Drain Charge − 9.2 − nC
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
SMaximum Continuous Drain−Source Diode Forward Current − − −2.1 A
I
SM Maximum Pulsed Drain−Source Diode Forward Current − − −8.4 A
V
SD Drain−Source Diode Forward Voltage
V
GS
= 0 V, I
S
= −2.1 A
− − −5.0 V
t
rr Reverse Recovery Time VGS = 0 V, IS = −2.7 A,
dIF / dt = 100 A/ms − 270 − ns
Q
rr
−
1.5
−
m
C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Essentially independent of operating temperature.
FQD3P50
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3
TYPICAL PERFORMANCE CUR VES
Crss
Coss
Ciss
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
Figure 3. On−Resistance Variation vs.
Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variant vs.
Source Current and Temperature
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
−VDS, DRAIN−SOURCE VOLTAGE (V)
0.1
0.01
−ID, DRAIN CURRENT (A)
110
0.1
1
VGS
Top: −15.0 V
−10.0 V
−8.0 V
−7.0 V
−6.5 V
−6.0 V
Bottom: −5.5 V
Notes:
1. 250 ms Pulse Test
2. TC = 25°C
−VGS, GATE−SOURCE VOLTAGE (V)
2
0.1
−ID, DRAIN CURRENT (A)
Notes:
1. VDS = 50 V
2. 250 ms Pulse Test
−55°C
25°C
150°C
1
46810
−ID, DRAIN CURRENT (A)
0
2
RDS(on), DRAIN SOURCE
ON−RESISTANCE (W)
Note:
1. TJ = 25°C
2468
3
4
5
6
7
8
VGS = −10 V
VGS = −20 V
−VSD, SOURCE−DRAIN VOLTAGE (V)
0.0
0.1
−IDR, REVERSE DRAIN CURRENT (A)
150°C
1
0.5 1.0 1.5 2.0 2.5 3.0
Notes:
1. VGS = 0 v
2. 250 ms Pulse Test
25°C
−VDS, DRAIN−SOURCE VOLTAGE (V)
0.1
0
CAPACITANCE (pF)
Notes:
1. VGS = 0 V
2. f = 1 MHz
110
200
400
600
800
1000
1200 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
QG, TOTAL GATE CHARGE (nC)
0
0
−VGS, GATE−SOURCE VOLTAGE (V)
Note: ID = −2.7 A
2
4
6
8
10
12
2 4 6 8 10 12 14 201816
VDS = −100 V
VDS = −250 V
VDS = −400 V
FQD3P50
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4
TYPICAL PERFORMANCE CUR VES (CONTINUED)
DC
10 ms
1 ms
100 μs
Figure 7. Breakdown Voltage Variation vs.
Temperature Figure 8. On−Resistance Variation vs.
Temperature
Figure 9. Maximum Safe Operation Area Figure 10. Maximum Drain Current vs.
Case Temperature
Figure 11. Transient Thermal Response Curve
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
t1
PDM
t2
TJ, JUNCTION TEMPERATURE (°C)
−100
0.8
−BVDSS, (NORMALIZED)
DRAIN−SOURCE BREAKDWON VOLTAGE
Notes:
1. VGS = 0 V
2. ID = −250 mA
0.9
1.0
1.1
1.2
−50 0 50 100 150 200
TJ, JUNCTION TEMPERATURE (°C)
−100
0.0
RDS(on), (NORMALIZED)
DRAIN−SOURCE ON−RESISTANCE
Notes:
1. VGS = −10 V
2. ID = −1.35 A
−50 0 50 100 150 200
0.5
1.0
1.5
2.0
2.5
TC, CASE TEMPERATURE (°C)
25
0.0
−ID, DRAIN CURRENT (A)
50 75 100 125 150
0.0
0.5
1.0
1.5
2.0
2.5
TJ, JUNCTION TEMPERATURE (°C)
1
0.01
−ID, DRAIN CURRENT (A)
Notes:
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
0.1
1
10
10 100 1000
Operation in This Area
is Limited by RDS(on)
t1, SQUARE WAVE PULSE DURATION (s)
0.00001
0.01
ZqJC, THERMAL RESPONSE
Notes:
1. ZqJC(t) = 2.5°C/W Max.
2. Duty Factor, D = t1/t2
3. TJM − TC = PDM × ZqJC(t)
0.1
1
0.0001 0.001 0.01 0.1 1 10
FQD3P50
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5
Figure 12. Gate Charge Test Circuit & Waveform
Figure 13. Resistive Switching Test Circuit & Waveforms
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
RL
VDS
VGS
−10 V
RG
DUT
VDD
VDS
VGS 10%
90%
10%
90% 90%
ton toff
trtf
td(on) td(off)
Qg
Qgd
Qgs
VGS
Charge
VDS
VGS
DUT
−3 mA
VDD
VDS
RG
DUT
−10 V
L
ID
tp
VDD
tpTime
IAS
BVDSS
ID(t)
VDS(t)
EAS +1
2@LIAS2@
BVDSS
BVDSS *VDD
−10 V
300 nF
200 nF
50 kW
Same Type
as DUT
FQD3P50
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6
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
L
VDD
RG
ISD
VDS
+
−
VGS
Same Type
as DUT
− dv/dt controlled by RG
− ISD controlled by pulse period
Driver
VGS
(Driver)
ISD
(DUT)
VDS
(DUT)
VSD
IRM
10 V
di/dt
VDD
IFM, Body Diode Forward Current
Body Diode Reverse Current
Body Diode Recovery dv/dt
Body Diode
Forward Voltage Drop
D+Gate Pulse Width
Gate Pulse Period
QFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
DPAK3 (TO−252 3 LD)
CASE 369AS
ISSUE O
DATE 30 SEP 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DPAK3 (TO−252 3 LD)
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