WJCE6353 - INTEL - Datasheet.Live

Intel Corporation

Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

Features

• Compliant with ETSI 300 744 DVB-T, Nordig-Unified

1.0.2 and DTG performance specifications.

• High performance with fast fully blind acquisition and

tracking capability.

• Low power consumption: less than 0.32 W, and

eco-friendly standby and sleep modes.

• Digital filtering of adjacent channels.

• Single 8 MHz SAW filter for 6, 7 & 8 MHz OFDM.

• Superior single frequency network performance.

• Fast AGC to track out signal fades.

• Good Doppler tracking capability.

• Enhanced frequency capture range to include triple

offsets.

• External 4 MHz clock or single low-cost 20.48 MHz

crystal, tolerance up to +/-200 ppm.

• Automatic mode (2 K/8 K), guard and spectral inversion

detection.

• Very low driver software overhead due to on-chip

state-machine control.

• Novel RF level detect facility via a separate ADC.

• Pre and post Viterbi-decoder bit error rates, and

uncorrectable block count.

Applications

• Digital terrestrial set-top boxes

• Integrated digital televisions

• Personal video recorders

•PC-TV receivers

• Portable applications

Description

The CE6353 is a superior fourth generation fully compliant

ETSI ETS300 744 COFDM demodulator that exceeds, with

margin, the performance requirements of all known DVB-T

digital terrestrial television standards, including Unified

Nordig and DTG.

A high performance 10 bit on-chip ADC is used to sample the

44 or 36 MHz IF analog signal. Advanced digital filtering of

the upper and lower channel enables a single 8 MHz channel

SAW filter to be used for 6, 7 and 8 MHz OFDM signal

reception. All sampling and other internal clocks are derived

from a single 20.48 MHz crystal or a 4 MHz clock input, the

tolerance of which may be relaxed as much as 200 ppm.

The CE6353 has a wide frequency capture range able to

automatically compensate for the combined offset intro-

duced by the tuner xtal and broadcaster triple frequency

offsets.

An on-chip state machine controls all acquisition and tracking

operations of the CE6353 as well as controlling the tuner via

a 2-wire bus. Any frequency range can be automatically

scanned for digital TV channels. This mechanism ensures

minimal interaction, maximum flexibility and fast acquisition

- very low software overhead.

Also included in the design is a 7-bit ADC to detect the RF

signal strength and thereby efficiently control the tuner RF

AGC.

Users have access to all the relevant signal quality infor-

mation, including input signal power level, signal-to-noise

ratio, pre-Viterbi BER, post-Viterbi BER, and the uncor-

rectable block counts. The error rate monitoring periods are

programmable over a wide range.

The device is packaged in a 10 x 10 mm 64-pin LQFP and is

very low power.

Document no. D55752-002 November 2006

Ordering Information

WJCE6353 882206 64 Pin LQFP* Trays

WJCE6353 S L9G5 882170 64 Pin LQFP* Tape and Reel

* Pb Free Matte Tin (RoHS compliant)

Working temperature range: -10°C to +80°C

CE6353

Nordig Unified DVB-T COFDM Terrestrial

Demodulator for

PC-TV and hand-held Digital TV (DTV)

Data Sheet

Figure 1 - Block Diagram

Data Sheet CE6353

Intel Corporation

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MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG

enabled platforms may require licenses from various entities, including Intel Corporation.

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TECHNICAL DOCUMENTATION - NOT FOR RESALE

Change History

Issue Date Description

D55752-002 November

2006

Added package drawing, minor corrections to pin outline drawing, removal of

non-lead-free part numbers and improvements in the descriptions in electrical

characteristics. Corrections to the current capability of the MPEG and STATUS

outputs in the “Pin Description Table” on page 9 and the MOCLK output current in

“DC Electrical Characteristics” on page 22*.

*. Note that these are only corrections to bring the documentation in line with actual device performance, and do not imply any change to the CE6353

or to any applications.

D55752-001 April 2006 Converted to Intel format

1.00 February 2005 First issue of document

CE6353 Data Sheet

Table of Contents

Intel Corporation

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1 Pin & Package Details.......................................................................................................................................................................7

1.1 Package dimensions........................................................................................................................................................... 7

1.2 Pin Outline............................................................................................................................................................................... 7

1.3 Pin Allocation ......................................................................................................................................................................... 8

1.4 Pin Description...................................................................................................................................................................... 9

2 Functional Description..................................................................................................................................................................11

2.1 Analogue-to-Digital Converter..................................................................................................................................12

2.2 Automatic Gain Control................................................................................................................................................. 12

2.3 IF to Baseband Conversion .........................................................................................................................................12

2.4 Adjacent Channel Filtering ..........................................................................................................................................13

2.5 Interpolation and Clock Synchronisation............................................................................................................. 13

2.6 Carrier Frequency Synchronisation........................................................................................................................13

2.7 Symbol Timing Synchronisation............................................................................................................................... 13

2.8 Fast Fourier Transform.................................................................................................................................................13

2.9 Common Phase Error Correction .............................................................................................................................13

2.10 Channel Equalisation ................................................................................................................................................... 13

2.11 Impulse Filtering.............................................................................................................................................................13

2.12 Transmission Parameter Signalling (TPS)........................................................................................................ 13

2.13 De-Mapper.........................................................................................................................................................................14

2.14 Symbol and Bit De-Interleaving.............................................................................................................................14

2.15 Viterbi Decoder...............................................................................................................................................................14

2.16 MPEG Frame Aligner....................................................................................................................................................14

2.17 De-interleaver.................................................................................................................................................................14

2.18 Reed-Solomon Decoder .............................................................................................................................................14

2.19 De-scrambler....................................................................................................................................................................14

2.20 MPEG Transport Interface........................................................................................................................................ 14

3 Interfaces.............................................................................................................................................................................................15

3.1 2-Wire Bus............................................................................................................................................................................15

3.1.1 Host............................................................................................................................................................................................................................15

3.1.2 Tuner.........................................................................................................................................................................................................................15

3.1.3 Examples of 2-wire bus messages:..........................................................................................................................................................16

3.1.4 Primary 2-wire bus timing.............................................................................................................................................................................16

3.2 MPEG........................................................................................................................................................................................17

3.2.1 Data Output Header Format........................................................................................................................................................................17

3.2.2 MPEG Data Output Signals............................................................................................................................................................................18

3.2.3 MPEG Output Timing ........................................................................................................................................................................................18

3.2.4 MOCLKINV = 1......................................................................................................................................................................................................18

3.2.5 MOCLKINV = 0......................................................................................................................................................................................................19

4 Electrical Characteristics .............................................................................................................................................................21

4.1 Operating Conditions......................................................................................................................................................21

4.2 Absolute Maximum Ratings........................................................................................................................................ 21

4.3 DC Electrical Characteristics.......................................................................................................................................22

4.4 AC Electrical Characteristics.......................................................................................................................................22

4.5 Crystal Specification and External Clocking ......................................................................................................23

4.5.1 Selection of External Components...........................................................................................................................................................24

4.5.1.1 Loop Gain Equation..............................................................................................................................................................................24

Data Sheet CE6353

Table of Contents

Intel Corporation

4.5.1.2 List of Equation Parameters ..........................................................................................................................................................24

4.5.1.3 Calculating Crystal Power Dissipation ......................................................................................................................................25

4.5.1.4 Capacitor Values ...................................................................................................................................................................................25

4.5.1.5 Oscillator/Clock Application Notes..............................................................................................................................................25

5 Application Circuit........................................................................................................................................................................... 27

CE6353 Data Sheet

List of Figures

Intel Corporation

Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2 - Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3 - Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 4 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7 - DVB Transport Packet Header Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8 - MPEG Output Data Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11 - VIN & VIN equivalent circuit for inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12 - VIN & VIN input impedance (approximate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13 - RFLEV equivalent circuit for input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14 - Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15 - External Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 16 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Data Sheet

List of Tables

Intel Corporation

Table 1 - Pin Names - numeric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2 - Pin Names - alphabetical order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3 - 2-wire bus address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 4 - Timing of 2-Wire Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

CE6353 Data Sheet

Intel Corporation

1 Pin & Package Details

1.1 Package dimensions

Figure 2 - Package dimensions

1.2 Pin Outline

Figure 3 - Pin Outline

Data Sheet CE6353

Intel Corporation

1.3 Pin Allocation

Table 1 - Pin Names - numeric

Pin Function Pin Function Pin Function Pin Function

1Vss 17 SADD1 33 Vdd 49 MDO0

2Vdd 18 SADD0 34 RFLEV 50 MDO1

3Vss 19 CVdd 35 CLK2/GPP0 51 MDO2

4CLK1 20 Vss 36 DATA2/GPP1 52 MDO3

5DATA1 21 PLLVdd 37 CVdd 53 MDO4

6IRQ 22 PLLGND 38 Vss 54 Vdd

7CVdd 23 XTI 39 CVdd 55 Vss

8Vss 24 XTO 40 Vss 56 MDO5

9RESET 25 Vss 41 AGC2/GPP2 57 MDO6

10 SLEEP 26 PLLTEST 42 AGC1 58 MDO7

11 STATUS 27 OSCMODE 43 GPP3 59 CVdd

12 SADD4 28 AVdd 44 SMTEST 60 Vss

13 Vdd 29 AGnd 45 Vdd 61 MOCLK

14 Vss 30 VIN 46 Vss 62 BKERR

15 SADD3 31 VIN 47 MOSTRT 63 MICLK

16 SADD2 32 AGnd 48 MOVAL 64 CVdd

Table 2 - Pin Names - alphabetical order

Function Pin Function Pin Function Pin Function Pin

AGC1 42 GPP3 43 PLLTEST 26 Vdd 54

AGC2/GPP2 41 IRQ 6PLLVdd 21 VIN 30

AGnd 29 MDO0 49 RESET 9VIN 31

AGnd 32 MDO1 50 RFLEV 34 Vss 1

AVdd 28 MDO2 51 SADD0 18 Vss 3

BKERR 62 MDO3 52 SADD1 17 Vss 8

CLK1 4MDO4 53 SADD2 16 Vss 14

CLK2/GPP0 35 MDO5 56 SADD3 15 Vss 20

CVdd 7MDO6 57 SADD4 12 Vss 25

CVdd 19 MDO7 58 SLEEP 10 Vss 38

CVdd 37 MICLK 63 SMTEST 44 Vss 40

CVdd 39 MOCLK 61 STATUS 11 Vss 46

CVdd 59 MOSTRT 47 Vdd 2Vss 55

CVdd 64 MOVAL 48 Vdd 13 Vss 60

DATA1 5OSCMODE 27 Vdd 33 XTI 23

DATA2/GPP1 36 PLLGND 22 Vdd 45 XTO 24

CE6353 Data Sheet

Intel Corporation

1.4 Pin Description

Pin Description Table

Pin No Name Pin Description I/O Type V mA

MPEG pins

47 MOSTRT MPEG packet start O

CMOS Tristate

3.3

248 MOVAL MPEG data valid O 3.3

49-53, 56-58 MDO(0:4)/MDO(5:7) MPEG data bus O 3.3

61 MOCLK MPEG clock out O 3.3 12

62 BKERR Block error O 3.3 2

63 MICLK MPEG clock in I

CMOS 3.3

11 STATUS Status output O 3.3 2

6IRQ Interrupt output O Open drain 56

Control pins

4CLK1 Serial clock I CMOS 5

5DATA1 Serial data I/O Open drain 56

23 XTI Low phase noise oscillator I

CMOS

24 XTO O

10 SLEEP Device power down I 3.3

12, 15-18 SADD(4:0) Serial address set I 3.3

44 SMTEST Production test (only set low) I 3.3

35 CLK2/GPP0 Serial clock tuner I/O

Open drain

36 DATA2/GPP1 Serial data tuner I/O 56

42 AGC1 Primary AGC O 56

41 AGC2/GPP2 Secondary AGC I/O 56

43 GPP(3) General purpose I/O I/O 56

9RESET Device reset I CMOS 5

27 OSCMODE Crystal oscillator mode I CMOS 3.3

26 PLLTEST PLL analog test O (tristated)

Analog inputs

30 VIN positive input I

31 VIN negative input I

34 RFLEV RF level I

Supply pins

21 PLLVdd PLL supply S 1.8

22 PLLGnd S 0

7, 19, 37, 39, 59, 64 CVdd Core logic power S 1.8

2, 13, 45, 54, Vdd I/O ring power S 3.3

Data Sheet CE6353

Intel Corporation

1, 3, 8, 14, 20, 25,

38, 40, 46, 55, 60 Vss Core and I/O ground S 0

28 AVdd ADC analog supply S 1.8

29, 32 AGnd S 0

33 Vdd 2nd ADC supply S 3.3

Pin Description Table (continued)

Pin No Name Pin Description I/O Type V mA

CE6353 Data Sheet

Intel Corporation

2 Functional Description

A functional block diagram of the CE6353 OFDM demodulator is shown in Figure 4. This accepts an IF analogue signal and

delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and frequency synchroni-

zation operations are all digital and there are no analogue control loops except the AGC. The frequency capture range is

large enough for all practical applications. This demodulator has novel algorithms to combat impulse noise as well as

co-channel and adjacent channel interference. If the modulation is hierarchical, the OFDM outputs both high and low

priority data streams. Only one of these streams is FEC-decoded, but the FEC can be switched from one stream to another

with minimal interruption to the transport stream.

Figure 4 - OFDM Demodulator Diagram

The FEC module shown in Figure 5 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder

separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to provide the

best performance over a wide range of channel conditions. The trace-back depth of 128 ensures minimum loss of perfor-

mance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi and Reed-Solomon decoders

are equipped with bit-error monitors. The former provides the bit error rate (BER) at the OFDM output. The latter is the

more useful measure as it gives the Viterbi output BER. The error collecting intervals of these are programmable over a

very wide range.

Data Sheet CE6353

Intel Corporation

Figure 5 - FEC Block Diagram

The FSM controller shown in Figure 4 controls both the demodulator and the FEC. It also drives the 2-wire bus to the

tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the received

signal. It can also be used to scan any defined frequency range searching for OFDM channels. This mechanism provides

the fast channel scan and acquisition performance, whilst requiring minimal software overhead in the host driver.

The algorithms and architectures used in the CE6353 have been optimized to minimize power consumption.

2.1 Analogue-to-Digital Converter

The CE6353 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz

bandwidth OFDM signal, with its spectrum centred at:

• 36.17 MHz IF

• 43.75 MHz IF

•5-10MHz near-zero IF

An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL is highly program-

mable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.

2.2 Automatic Gain Control

An AGC module compares the absolute value of the digitized signal with a programmable reference. The error signal is

filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which has to be RC

low-pass filtered to obtain the voltage to control the amplifier.

The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC clipping and

a small value results in excessive quantization noise. Hence the optimum value has been determined assuming the input

signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit theorem in statistics to the

OFDM signal, which consists of a large number of randomly modulated carriers. This reference or target value may have to

be lowered slightly for some applications. Slope control bits have been provided for the AGCs and these have to be set

correctly depending on the gain-versus-voltage slope of the gain control amplifiers.

The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking. The AGC

is free running during OFDM channel changes and locks to the new channel while the tuner lock is being established. This

is one of the features of CE6353 used to minimize acquisition time. A robust AGC lock mechanism is provided and the

other parts of the CE6353 begin to acquire only after the AGC has locked.

2.3 IF to Baseband Conversion

Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred at approximately 8.9 MHz.

The first step of the demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in

baseband. A correction for spectral inversion is implemented during this conversion process. Note also that the CE6353

has control mechanisms to search automatically for an unknown spectral inversion status.

CE6353 Data Sheet

Intel Corporation

2.4 Adjacent Channel Filtering

Adjacent channels, in particular the Nicam digital sound signal associated with analogue channels, are filtered prior to the

FFT.

2.5 Interpolation and Clock Synchronisation

CE6353 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the signal at a

fixed rate, for example, 45.056 MHz. Conversion of the 45.056 MHz signal to the OFDM sample rate is achieved using the

time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled by factors 6/8 and 7/8 for 6

and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is programmed in a CE6353 register

(defaults are for 45 MHz sampling and 8 MHz OFDM). The clock recovery phase locked loop in the CE6353 compensates

for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock.

2.6 Carrier Frequency Synchronisation

There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to

broadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz in 2 K and 8 K modes, without

the need for an analogue frequency control (AFC) loop.

The default frequency capture range has been set to ±286 kHz in the 2 K and 8 K mode. However, these values can be

increased, if necessary, by programming an on-chip register (see details in the design manual). It is recommended that a

larger capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to

adjust the tuner. After the OFDM module has locked (the AFC will have been previously disabled), the frequency offset

can be read from an on-chip register.

2.7 Symbol Timing Synchronisation

This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter-symbol

interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated to dynami-

cally adapt to time-variations in the transmission channel.

2.8 Fast Fourier Transform

The FFT module uses the trigger information from the timing synchronization module to set the start point for an FFT. It

then uses either a 2 K or 8 K FFT to transform the data from the time domain to the frequency domain. An extremely

hardware-efficient and highly accurate algorithm has been used for this purpose.

2.9 Common Phase Error Correction

This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of the

tuner phase noise on system performance.

2.10 Channel Equalisation

This consists of two parts. The first part involves estimating the channel frequency response from pilot information.

Efficient algorithms have been used to track time-varying channels with a minimum of hardware.

The second part involves applying a correction to the data carriers based on the estimated frequency response of the

channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.

2.11 Impulse Filtering

CE6353 contains several mechanisms to reduce the impact of impulse noise on system performance.

2.12 Transmission Parameter Signalling (TPS)

An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS carriers in

every symbol and all these carry one bit of TPS. These bits, when combined, include information about the transmission

mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition, the first eight bits of the

cell identifier are contained in even frames and the second eight bits of the cell identifier are in odd frames. The TPS

module extracts all the TPS data, and presents these to the host processor in a structured manner.

Data Sheet CE6353

Intel Corporation

2.13 De-Mapper

This module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature compo-

nents of the data carriers as well as per-carrier channel state information (CSI). The de-mapping algorithm depends on the

constellation (QPSK, 16 QAM or 64 QAM) and the hierarchy (α= 0, 1, 2 or 4). Soft decisions for both low- and high-priority

data streams are generated.

2.14 Symbol and Bit De-Interleaving

The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de-interleaver

modules consist largely of memory to invert these interleaving functions and present the soft decisions to the FEC in the

original order.

2.15 Viterbi Decoder

The Viterbi decoder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit-stream. The

decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the branch metrics

and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivor memory.

The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A trace-back depth of 128 is

used to minimize any loss in performance, especially at high code rates.

The decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors at its

input, on the assumption that the Viterbi output BER is significantly lower than its input BER.

2.16 MPEG Frame Aligner

The Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used to ensure

correct lock and to prevent loss of lock due to noise impulses.

2.17 De-interleaver

Errors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a number

of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The de-interleaver is a

memory unit which implements the inverse of the convolutional interleaving function introduced by the transmitter.

2.18 Reed-Solomon Decoder

Every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a

systematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable of correcting

up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors.

In addition to efficiently performing this decoding function, the Reed-Solomon decoder in CE6353 keeps a count of the

number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This information can

be used to compute the post-Viterbi BER.

2.19 De-scrambler

The de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with a

pseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transport packets. The TEI bit of the packet header

may be set if required to indicate uncorrectable packets.

2.20 MPEG Transport Interface

MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present the

MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio,

constellation, hierarchy and code rate. There is also an option for the data to be extracted from the with a clock provided

by the user.

CE6353 Data Sheet

Intel Corporation

3Interfaces

3.1 2-Wire Bus

3.1.1 Host

The primary 2-wire bus serial interface uses pins:

• DATA1 (pin5) serial data, the most significant bit is sent first.

• CLK1 (pin 4) serial clock.

The 2-wire bus address is determined by a combination of internal settings and applying Vdd or Gnd to the SADD[4:0]

pins:

When the CE6353 is powered up, the RESET pin 9 should be held low for at least 50 ms after Vdd has reached normal

operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address. ADDR[0]

is the R/W bit.

The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive mode,

the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD register takes

an 8-bit value that determines which of 256 possible register addresses is written to by the following byte. Not all

addresses are valid and many are reserved registers that must not be changed from their default values. Multiple byte

reads or writes will auto-increment the value in RADD, but care should be taken not to access the reserved registers

accidentally.

Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address is not

recognized, the CE6353 will ignore all activity until a valid chip address is received. The 2-wire bus START command does

NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a particular read register with

a write command, followed immediately with a read data command. If required, this could next be followed with a write

command to continue from the latest address. RADD would not be sent in this case. Finally, a STOP command should be

sent to free the bus.

When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out is the

contents of register 00.

3.1.2 Tuner

The CE6353 has a General Purpose Port that can be configured to provide a secondary 2-wire bus.

Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.

The allocation of the pins is: GPP0 pin 35 = CLK2*, GPP1 pin 36 = DATA2.

Table 3 - 2-wire bus address

Address bits ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1]

Internal/external settings Gnd Gnd SADD[4] SADD[3] SADD[2] SADD[1] SADD[0]

Normal TNIM settings Gnd Gnd Gnd Vdd Vdd Vdd Vdd

*. Please note that in this configuration, this pin is an output only and therefore does not allow a clock-hold function in the slave device.

Data Sheet CE6353

Intel Corporation

3.1.3 Examples of 2-wire bus messages:

KEY: S Start condition W Write (= 0)

P Stop condition R Read (= 1)

A Acknowledge NA NOT Acknowledge

Italics CE6353 output RADD Register Address

Write operation - as a slave receiver:

Read operation - CE6353 as a slave transmitter:

Write/read operation with repeated start - CE6353 as a slave transmitter:

3.1.4 Primary 2-wire bus timing

Figure 6 - Primary 2-Wire Bus Timing

Where: S = Start

Sr = Restart, i.e., start without stopping first.

P=Stop.

SDEVICEWARADD ADATA ADATA AP

ADDRESS (n) (reg n) (reg n+1)

SDEVICERADATAADATA ADATA NA P

ADDRESS (reg 0) (reg 1) (reg 2)

SDEVICE WARADD ASDEVICE RADATA ADATA NA P

ADDRESS (n) ADDRESS (reg n) (reg n+1)

Sr P

LOW

ttR

tHD;STA HD;DAT

HIGH

ttSU;DAT SU;STA

DATA1

CLK1

tBUFF

tSU;STO

CE6353 Data Sheet

Intel Corporation

3.2 MPEG

3.2.1 Data Output Header Format

Figure 7 - DVB Transport Packet Header Byte

After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.

Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any uncorrectable

packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but note that if this bit is already

1, for example, due to a channel error which has not been corrected, it will remain high at output).

Table 4 - Timing of 2-Wire Bus

Parameter Symbol

Values with 4MHz clock Values with 20.48 MHz

clock*

*. Or 27.00 MHz clock

Unit

Min. Max. Min. Max.

CLK clock frequency (Primary) fCLK 0100 0 400kHz

Bus free time between a STOP and START

condition. tBUFF 4.7 1.3 µs

Hold time (repeated) START condition. tHD;STA 4.0 0.6 µs

LOW period of CLK clock. tLOW 4.7 1.3 µs

HIGH period of CLK clock. tHIGH 4.0 0.6 µs

Set-up time for a repeated START condition. tSU;STA 4.7 0.6 µs

Data hold time (when input). tHD;DAT 03.450 0.9µs

Data set-up time tSU;DAT 250 100 ns

Rise time of both CLK and DATA signals. tR1000 20 + 0.1Cb†

†. Cb = the total capacitance on either clock or data line in pF to maximum of 400pF.

300 ns

Fall time of both CLK and DATA signals, (100pF to

ground). tF300 20 + 0.1Cb†300 ns

Set-up time for a STOP condition. tSU;STO 4.0 0.6 µs

TEI

010001111st byte

2nd byte

Transport

Packet

Header

4 bytes

184 Transport packet bytes

188 byte packet output

MDO[7] MDO[0]

Data Sheet CE6353

Intel Corporation

3.2.2 MPEG Data Output Signals

The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in the packet

synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running clock once symbol

lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 8 with MOCLKINV = ‘1’, the default

state, see register 0x50.

All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK (MOCLKINV = 1)

to present stable data and signals on the positive edge of the clock.

A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during the

inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of a packet

and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet where uncor-

rectable bytes are detected and will remain low until the last byte has been clocked out.

Figure 8 - MPEG Output Data Waveforms

3.2.3 MPEG Output Timing

Maximum delay conditions: Vdd = 3.0V, CVdd = 1.62V, Tamb = 80oC, Output load = 10pF.

Minimum delay conditions: Vdd = 3.6V, CVdd = 1.98V, Tamb = -10oC, Output load = 10pF.

MOCLK frequency = 45.06 MHz.

3.2.4 MOCLKINV =1

Parameter

Delay conditions

Units

Maximum Minimum

Data output delay tD3.0 1.0

nsSetup Time tSU 7.0 10.0

Hold Time tH7.0 10.0

MDO7:0

MOCLKINV=1

MOCLK

MOSTRT

MOVAL

BKERR

Tp Ti

1st byte packet n 188 byte packet n 1st byte packet n+1

CE6353 Data Sheet

Intel Corporation

Figure 9 - MPEG Timing - MOCLKINV =1

3.2.5 MOCLKINV =0

MDOSWAP = 0

The hold time is better when MOCLKINV = 1, therefore this should be used if possible.

Figure 10 - MPEG Timing - MOCLKINV =0

Parameter

Delay Conditions

Units

Maximum Minimum

Data output delay tD3.0 1.0

nsSetup Time tSU 18.0 20.0

Hold Time tH1.0 0.2

tSU

MOCLK

MDO

MOSTRT

MOVAL

BKERRB }

BKERR

tSU

MOCLK

MDO

MOSTRT

MOVAL

BKERRB }

BKERR

Data Sheet CE6353

Intel Corporation

CE6353 Data Sheet

Intel Corporation

4 Electrical Characteristics

4.1 Operating Conditions

4.2 Absolute Maximum Ratings

Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for

extended periods may reduce reliability. Functionality at or above these conditions is not implied.

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Units

Power supply voltage: periphery Vdd 3.0 3.3 3.6 V

core CVdd 1.62 1.8 1.98 V

Power supply current: periphery *

*. Current from the 3.3 V supply will be mainly dependent on the external loads.

IddP1mA

core IddC170 mA †

†. Current given is for optimum performance, lower current is possible with reduced performance.

Input clock frequency ‡

‡. The min/max frequencies given are those supported by the oscillator cell. Required system frequencies are as defined in the design manual. Frequen-

cies outside these limits are acceptable with an external clock signal.

XTI 16.00 20.48 25.00 MHz

CLK1 primary serial clock frequency **

**. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.

fCLK 400 kHz

Ambient operating temperature -10 80 °C

Maximum Operating Conditions

Parameter Symbol Min. Max. Unit Conditions

Power supply

Vdd

-0.3

+3.6 V

CVdd +2.0 V

Voltage on input pins (5 V rated)

5.5 V

Voltage on input pins (3.3 V rated)

Vdd + 0.3

Voltage on analog input pins (VIN & VIN) V Pin 33 = Vdd

Voltage on analog input pins (VIN & VIN) CVdd + 0.3 Pin 33 = CVdd*

*. this condition will only occur if CE6353 is being used in a board originally designed for the MT352. All other applications should have Vdd

(3V3) on this pin.

Voltage on output pins (5 V rated)

5.5 V

Voltage on output pins (3.3V rated) Vdd + 0.3 V

ESD ratings (all pins):

HBM

CDM

±2000

±800

Storage temperature TSTG -55 150 °C

Operating ambient temperature TOP -10 80 °C

Junction temperature TJ 125 °C

Data Sheet CE6353

Intel Corporation

4.3 DC Electrical Characteristics

4.4 AC Electrical Characteristics

DC Electrical Characteristics

Parameter Conditions Pins Symbol Min. Typ. Max. Unit

Operating

voltage

periphery Vdd 3.0 3.3 3.6 V

core CVdd 1.62 1.8 1.98 V

Supply current *

*. Current given is for optimum performance, lower current is possible with reduced performance.

1.62>CVdd>1.98 IddC170 mA

Supply current sleep mode 300 µA

Outputs

Output levels

IOH 2mA

3.0>Vdd>3.6 MDO(7:0), MOVAL, MOSTRT,

STATUS, BKERR

VOH 2.4 V

IOL 2mA

3.0>Vdd>3.6

VOL 0.4 V

IOH 12mA

3.0>Vdd>3.6 MOCLK

VOH 2.4 V

IOL 12mA

3.0>Vdd>3.6

VOL 0.4 V

IOL 6mA

3.0>Vdd>3.6

GPP(3:0), DATA1, AGC1,

AGC2, IRQ

VOL 0.4 V

Output capacitance Not including track

MDO(7:0), MOVAL, MOSTRT,

MOCLK, STATUS, BKERR 3.0 pF

GPP(3:0), DATA1, AGC1,

AGC2,IRQ 3.6 pF

Output leakage (tri-state) 1µA

Inputs

Input levels 3.0>Vdd>3.6

-0.5 ≥ Vin ≥

Vdd+0.5V

MICLK, SADD(4:0)SLEEP,

OSCMODE

VIH 2.0

Input levels 3.0>Vdd>3.6

-0.5 ≥ Vin ≥ +5.5V

GPP(3:0), CLK1, DATA1,

RESET

VIH 2.0 V

Input levels 3.0>Vdd>3.6

Capacitances do not

include track

All inputs VIL 0.8 V

Input leakage Current SLEEP, SMTEST, MICLK, CLK1,

OSCMODE

±1 µA

Input capacitance 1.8 pF

Input capacitance SADD(4:0), DATA1, GPP(3:0) 3.6 pF

AC Electrical Characteristics

Parameter Conditions Pins Min. Typ. Max. Unit Notes

Analogue Inputs

Input levels

3.0>Vdd>3.6

-0.5 ≥ Vin ≥ Vdd+0.5V VIN and VIN 0.8*

*. capacitively coupled signal.

Vp-p

Nominal conditions for all 1’s on the

ADC outputs.† See Figure 11 for

more detail.

†. for normal use, the AGC must control the level on the VIN/VIN pins.

3.0>Vdd>3.6

-0.5 ≥ Vin ≥ +5.5V RFLEV 0.0 Vdd V See Figure 13 for more detail.

Input impedance 3.0>Vdd>3.6 VIN, VIN See Figure 12 for more detail.

RFLEV 25k Ω D.C. signal

CE6353 Data Sheet

Intel Corporation

Figure 11 - VIN & VIN equivalent circuit for inputs

Figure 12 - VIN & VIN input impedance (approximate)

Figure 13 - RFLEV equivalent circuit for input

4.5 Crystal Specification and External Clocking

Parallel resonant fundamental frequency (preferred) 20.4800 MHz

Tolerance over operating temperature range ± 150 ppm

Tolerance overall ± 200 ppm

Data Sheet CE6353

Intel Corporation

Typical load capacitance 20 pF

Drive level 0.4 mW max

Equivalent series resistance <40 Ω

Figure 14 - Crystal Oscillator Circuit

4.5.1 Selection of External Components

The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is greater

than unity. Correct selection of the two capacitors is very important and the following method is recommended to obtain

values for C1 and C2. Alternatively there is a calculator available (ZLAN-125) that will calculate the external component

values for you.

4.5.1.1 Loop Gain Equation

Although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to ensure

that oscillations will occur across all variations in temperature, process and supply voltage, and that the circuit will exhibit

good start-up characteristics.

Equation 1 -

Equation 2 -

4.5.1.2 List of Equation Parameters

A total loop gain (between 5 and 25)

Cin C1 + Cpar

Cout C2 + Cpar

Cpar parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track capacitances,

package capacitance and cell input capacitance. Normally Cpar ≈ 4pF.

Zo 9.143kΩ - output impedance of amplifier at 1.8V operation - typical

gm 8.736mA/V - transconductance of amplifier at 1.8V operation -typical

Rf 2.3MΩ - internal feedback resistor

ESR maximum equivalent series resistance of crystal - given by crystal manufacturer (Ω)

f fundamental frequency of crystal (Hz)

XTI XT0

XTI

OSCMODE

A = Cout.gm

Cin

Cout + Cin

Rf.Cin

Zin

-11

Zin = 1

(2.π.f.Cout)2.ESR

CE6353 Data Sheet

Intel Corporation

4.5.1.3 Calculating Crystal Power Dissipation

To calculate the power dissipated in a crystal the following equation can be used.

Equation 3 -

Pc = power dissipated in crystal at resonant frequency (W)

Vpp = maximum peak to peak output swing of amplifier is 1.8V for all CVdd

Zin = crystal network impedance (see Equation 2)

4.5.1.4 Capacitor Values

Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with Equation 4

below.

Equation 4 -

Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.

Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the resulting

crystal load capacitance CL (see Equation 5) is close to the crystal manufacturers recommended CL (standard values for CL

are 15pF, 20pF and 30pF). The crystal will then operate very near its specified frequency.

Equation 5 -

Cpar12 =parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin capacitance

(including any socket used) and the printed circuit board’s track-to-track capacitance.

Cpar12 ≈2pF.

If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s recom-

mended CL may be acceptable. Larger values of CL tend to reduce the influence of circuit variations and tolerances on

frequency stability. Smaller values of CL tend to reduce startup time and crystal power dissipation. Care must however be

taken that CL does not fall outside the crystal pulling range or the circuit may fail to start up altogether. It is also possible

to quote CL to the crystal manufacturer who can then cut a crystal to order which will resonate, under the specified load

conditions, at the desired frequency.

Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is not

feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain condition is still

satisfied. This must be done using Equation 1.

4.5.1.5 Oscillator/Clock Application Notes

• On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other

signal tracks must not be allowed to cross through this area. The component tracks should preferably be ringed by

a ground track connected to the chip ground (0V) on adjacent pins either side of the crystal pins. It is also

advisable to provide a ground plane for the circuit to reduce noise.

• External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVdd) and

current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell’s amplitude

clamping circuit.

• An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To limit the

current taken from the signal source a resistor should be placed between the clock source and XTI. The

recommended value for this series resistor is 470 Ω for a clock signal switching between 0V and CVdd. The

current the clock source needs to source/sink is then ≤1.9 mA. The XTO pin must be left unconnected in this

configuration. See Figure 15.

• AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty cycle of the

Pc = 8.Zin

Vpp2

Cin = Cout = gm

(2.π.f)2.ESR when: C1 = C2 = Cout - Cpar

-- .

CL = Cout . Cin

Cout + Cin

+Cpar12

Note: 2 >

>0.5

Data Sheet CE6353

Intel Corporation

OSCOUT signal cannot be guaranteed in such a configuration.

• AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that the

circuit shown in Figure 15 be used to correctly bias the oscillator inputs: The common-mode voltage VCM for XTI

and XTO, (set by the 36 kΩ and 22 kΩ resistors) must be in the range 800 mV to CVdd and the amplitude Vpp of

the clock signal must be >100 mV. See Figure 15.

Figure 15 - External Clocking

• External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode voltage VCM

for the differential clock signals must be in the range 800 mV to CVdd, and the peak-to-peak signal amplitude Vpp

must be >100 mV. It is recommended that differential clock signals have VCM =1.0V. For Vpp>400mV a resistor

of ≥390 Ω in series with XTI or XTO may be required to limit the current taken from or supplied to the clock

sources.

CE6353 Data Sheet

Intel Corporation

5 Application Circuit

Figure 16 - Typical Application Circuit

Data Sheet CE6353

Intel Corporation