ADS5424-SP
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SLWS194D –MAY 2008–REVISED SEPTEMBER 2013
CLASS V, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS5424-SP
1FEATURES
• 14-Bit Resolution • Military Temperature Range
( –55°C to 125°C Tcase)
• 105-MSPS Maximum Sample Rate • QML-V Qualified, SMD 5962-07206
• SNR = 70 dBc at 105 MSPS and 50 MHz IF • Engineering Evaluation (/EM) Samples are
• SFDR = 78 dBc at 105 MSPS and 50 MHz IF Available (1)
• 2.2-VPP Differential Input Range
• 5-V Supply Operation APPLICATIONS
• 3.3-V CMOS Compatible Outputs • Single and Multichannel Digital Receivers
• 2.3-W Total Power Dissipation • Base Station Infrastructure
• 2s Complement Output Format • Instrumentation
• On-Chip Input Analog Buffer, Track and Hold, • Video and Imaging
and Reference Circuit
• 52-Pin Ceramic Nonconductive Tie-Bar RELATED DEVICES
Package (HFG) • Clocking: CDC7005
• Amplifiers: OPA695, THS4509
(1) These units are intended for engineering evaluation only.
They are processed to a non-compliant flow (e.g. No Burn-In,
etc.) and are tested to a temperature rating of 25°C only.
These units are not suitable for qualification, production,
radiation testing or flight use. Parts are not warranted for
performance over the full MIL specified temperature range of
- 55°C to 125°C or operating life.
DESCRIPTION/ORDERING INFORMATION
The ADS5424 is a 14-bit, 105-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, while
providing 3.3-V CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the
on-chip track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided
to further simplify the system design. The ADS5424 has outstanding low noise and linearity, over input
frequency. With only a 2.2-VPP input range, ADS5424 simplifies the design of multicarrier applications, where the
carriers are selected on the digital domain.
The ADS5424 is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The ADS5424 is built on
state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full military
temperature range (–55°C to 125°C Tcase)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Reference
Timing
CLK+
OVR D[13:0]
CLK−
6
DMID DRY
VREF
AIN
AIN TH1
5 5
Σ
DAC2ADC2
ADC3
Σ
DAC1ADC1
A3
A1 TH2 TH3
C1
C2
AVDD DRVDD
GND
Digital Error Correction
A2
+
−
+
−
ADS5424-SP
SLWS194D –MAY 2008–REVISED SEPTEMBER 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted)(1)
ADS5424 UNIT
AVDD to GND 6
Supply voltage V
DRVDD to GND 5
Analog input to GND –0.3 V to AVDD + 0.3 V
Clock input to GND –0.3 V to AVDD + 0.3 V
CLK to CLK ±2.5 V
Digital data output to GND –0.3 V to DRVDD + 0.3 V
TCCharacterized case operating temperature range –55°C to 125 °C
TJMaximum junction temperature 150 °C
Tstg Storage temperature range –65°C to 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
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RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage 4.75 5 5.25 V
DRVDD Output driver supply voltage 3 3.3 3.6 V
ANALOG INPUT
Differential input range 2.2 VPP
VCM Input common mode voltage 2.4 V
DIGITAL OUTPUT
Maximum output load 10 pF
CLOCK INPUT
ADCLK input sample rate (sine wave) 30 105 MSPS
Clock amplitude, differential sine wave 3 VPP
Clock duty cycle 50%
TCOpen case temperature range –55 125 °C
ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad)
Typical values at TC= 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bits
ANALOG INPUTS
Differential input range 2.2 Vpp
Differential input resistance See Figure 11 1 kΩ
Differential input capacitance See Figure 11 1.5 pF
Analog input bandwidth 570 MHz
INTERNAL REFERENCE VOLTAGES
VREF Reference voltage 2.38 2.4 2.41 V
DYNAMIC ACCURACY
No missing codes Tested
DNL Differential linearity error fIN = 10 MHz –0.98 ±0.5 1.5 LSB
TC= 25°C and
fIN = 10 MHz –5.0 ±3.0 +5.0 LSB
TC,MAX
INL Integral linearity error fIN = 10 MHz TC= TC,MIN –-6.9 +6.9 LSB
Offset error –1.5 0 1.5 %FS
Offset temperature coefficient 0.0007 %FS/°C
Gain error –5 0.9 5 %FS
Gain temperature coefficient 0.006 %FS/°C
POWER SUPPLY
VIN = full scale, fIN = 70
IAVDD Analog supply current FS= 105 MSPS 355 410 mA
MHz
VIN = full scale, fIN = 70
IDRVDD Output buffer supply current FS= 105 MSPS 47 55 mA
MHz
Total power with 10-pF
Power dissipation load on each digital output FS= 105 MSPS 1.9 2.3 W
to ground, fIN = 70 MHz
Power-up time FS= 105 MSPS 20 ms
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ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)
Typical values at TC= 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC AC CHARACTERISTICS
TC= 25°C 70.5 72.4
fIN = 10 MHz TC= TC,MAX 71.0
TC= TC,MIN 70.5
fIN = 30 MHz Full Temp Range 70.0 71.5
fIN = 50 MHz 70.9
SNR Signal-to-noise ratio TC= 25°C 68.2 70.1 dBc
fIN = 70 MHz TC= TC,MAX 67.0
TC= TC,MIN 68.0
fIN = 100 MHz 68.9
fIN = 170 MHz 66.3
fIN = 230 MHz 64.0
TC= 25°C 72.0 81.6
fIN = 10 MHz Full Temp Range 71.0
TC= 25°C 77.0 80.6
fIN = 30 MHz TC= TC,MAX 69.0
TC= TC,MIN 75.0
fIN = 50 MHz 78.1
SFDR Spurious free dynamic range dBc
TC= 25°C 68.0 82.6
fIN = 70 MHz TC= TC,MAX 69.0
TC= TC,MIN 67.0
fIN = 100 MHz 82.5
fIN = 170 MHz 68.0
fIN = 230 MHz 65.4
TC= 25°C 68.6 71.3
fIN = 10 MHz TC= TC,MAX 68.3
TC= TC,MIN 68.2
TC= 25°C 69.4 70.2
fIN = 30 MHz TC= TC,MAX 67.0
TC= TC,MIN 69.4
SINAD Signal-to-noise + distortion fIN = 50 MHz 69.9 dBc
TC= 25°C 65.8 69.7
fIN = 70 MHz TC= TC,MAX 64.6
TC= TC,MIN 65.0
fIN = 100 MHz 68.6
fIN = 170 MHz 64.0
fIN = 230 MHz 61.1
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ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)
Typical values at TC= 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TC= 25°C 72.0 81.8
fIN = 10 MHz Full Temp Range 71.0
TC= 25°C 77.0 80.6
fIN = 30 MHz TC= TC,MAX 69.0
TC= TC,MIN 75.0
fIN = 50 MHz 86.5
HD2 Second harmonic dBc
TC= 25°C 68.0 85.0
fIN = 70 MHz TC= TC,MAX 69.0
TC= TC,MIN 67.0
fIN = 100 MHz 86.1
fIN = 170 MHz 93.0
fIN = 230 MHz 71.0
TC= 25°C 72.0 81.6
fIN = 10 MHz Full Temp Range 71.0
TC= 25°C 77.0 81.3
fIN = 30 MHz TC= TC,MAX 69.0
TC= TC,MIN 75.0
fIN = 50 MHz 78.1
HD3 Third harmonic dBc
TC= 25°C 68.0 82.6
fIN = 70 MHz TC= TC,MAX 69.0
TC= TC,MIN 67.0
fIN = 100 MHz 83.3
fIN = 170 MHz 68.0
fIN = 230 MHz 65.4
fIN = 10 MHz Full Temp Range 75.0 85.5
TC= 25°C 80.0 83.8
fIN = 30 MHz TC= TC,MAX 74.0
TC= TC,MIN 80.0
fIN = 50 MHz 87.0
Worst other harmonic/spur (other than TC= 25°C 74.0 83.0 dBc
HD2 and HD3) fIN = 70 MHz TC= TC,MAX 72.0
TC= TC,MIN 74.0
fIN = 100 MHz 82.5
fIN = 170 MHz 79.8
fIN = 230 MHz 78.0
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ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)
Typical values at TC= 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TC= 25°C 71.0 77.8
fIN = 10 MHz Full Temp Range 70.0
TC= 25°C 75.0 77.4
fIN = 30 MHz TC= TC,MAX 68.0
TC= TC,MIN 73.8
fIN = 50 MHz 76.7
THD Total harmonic distortion dBC
TC= 25°C 67.4 79.6
fIN = 70 MHz TC= TC,MAX 67.2
TC= TC,MIN 66.4
fIN = 100 MHz 79.9
fIN = 170 MHz 67.6
fIN = 230 MHz 64.1
TC= 25°C 11.1 11.7
fIN = 10 MHz TC= TC,MAX 11.0
TC= TC,MIN 11.0
TC= 25°C 11.2 11.5
ENOB Effective number of bits fIN = 30 MHz TC= TC,MAX 10.8 Bits
TC= TC,MIN 11.2
TC= 25°C 10.6 11.4
fIN = 70 MHz TC= TC,MAX 10.4
TC= TC,MIN 10.5
RMS idle channel noise Input pins tied together 0.9 LSB
DIGITAL CHARACTERISTICS (Unchanged after 100 kRad)
Typical values at TC= 25 °C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, AVDD = 5 V, DRVDD = 3.3 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital Outputs
Low-level output voltage CLOAD = 10 pF(1) 0.1 0.6 V
High-level output voltage CLOAD = 10 pF(1) 2.6 3.2 V
Output capacitance 3 pF
DMID 1.65 1.8 V
(1) Equivalent capacitance to ground of (load + parasitics of transmission lines)
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TIMING CHARACTERISTICS(1)(Unchanged after 100 kRad)
Typical values at TC= 25°C, Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS
PARAMETER MI TYP MAX UNIT
N
Aperture Time
tAAperture delay 500 ps
tJClock slope independent aperture uncertainty (jitter) 150 fs
kJClock slope dependent jitter factor 50 μV
Clock Input
tCLK Clock period 9.5 ns
tCLKH Clock pulse width high 4.75 ns
tCLKL Clock pulse width low 4.75 ns
Clock to DataReady (DRY)
tDR Clock rising 50% to DRY falling 50% 2.2 3.0 4.7 ns
tDR +
tC_DR Clock rising 50% to DRY rising 50% ns
tCLKH
tC_DR_50% Clock rising 50% to DRY rising 50% with 50% duty cycle 7.0 7.8 9.5 ns
clock
Clock to DATA, OVR(2)
trData VOL to data VOH (rise time) 0.6 ns
tfData VOH to data VOL (fall time) 0.6 ns
Cycl
L Latency 3 es
Valid DATA(3) to clock 50% with 50% duty cycle clock
tsu_c 1.8 3.6 ns
(setup time)
th_c Clock 50% to invalid DATA(3) (hold time) 2.6 4.1 ns
DataReady (DRY)/DATA, OVR(2)
Valid DATA(3) to DRY 50% with 50% duty cycle clock
tsu(DR)_50% 0.9 1.40 ns
(setup time)
DRY 50% to invalid DATA(3) with 50% duty cycle clock
th(DR)_50% 3.9 6.3 ns
(hold time)
(1) All values obtained from design and characterization.
(2) Data is updated with clock rising edge or DRY falling edge.
(3) See VOH and VOL levels.
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N
N+1
N+2
N+3
N+4
NN−1N−2N−3
tA
tsu(C) th(C)
th(DR)
N + 1
NN + 2 N + 3 N + 4
tC_DR
tr
tCLK tCLKL
CLK, CLK
D[13:0], OVR
DRY
AIN
tCLKH
tDR
tsu(DR)
tf
ADS5424-SP
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Figure 1. Timing Diagram
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15 16
D3
D2
D1
D0(LSB)
DMID
GND
DRVDD
OVR
DNC
AVDD
GND
AVDD
GND
39
38
37
36
35
34
33
32
31
30
29
28
27
17
1
2
3
4
5
6
7
8
9
10
11
12
13
DRVDD
GND
VREF
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
18 19 20 21
HFGPACKAGE
(TOP VIEW)
51 50 49 48 47
52 46 44 43 42
45
22 23 24 25 26
41 40
14
DRY
D13(MSB)
D12
D11
D10
D9
D8
D7
D6
DRVDD
GND
D5
D4
AVDD
GND
AVDD
GND
AVDD
GND
C1
GND
AVDD
GND
C2
GND
AVDD
ADS5424-SP
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SLWS194D –MAY 2008–REVISED SEPTEMBER 2013
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL DESCRIPTION
NAME NO.
DRVDD 1, 33, 43 3.3 V power supply, digital output stage only
2, 4, 7, 10, 13, 15, 17,
GND 19, 21, 23, 25, 27, 29, Ground
34, 42
VREF 3 2.4 V reference. Bypass to ground with a 0.1 μF microwave chip capacitor.
CLK 5 Clock input. Conversion initiated on rising edge
CLK 6 Complement of CLK, differential input
8, 9, 14, 16, 18, 22, 26,
AVDD 5 V analog power supply
28, 30
AIN 11 Analog input
AIN 12 Complement of AIN, differential analog input
C1 20 Internal voltage reference. Bypass to ground with a 0.1 μF chip capacitor.
C2 24 Internal voltage reference. Bypass to ground with a 0.1 μF chip capacitor.
DNC 31 Do not connect
OVR 32 Overrange bit. A logic level high indicates the analog input exceeds full scale.
DMID 35 Output data voltage midpoint. Approximately equal to (DVCC)/2
D0 (LSB) 36 Digital output bit (least significant bit); two's complement
D1–D5, D6–D12 37–41, 44–50 Digital output bits in two's complement
D13 (MSB) 51 Digital output bit (most significant bit); two's complement
DRY 52 Data ready output
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1.00
10.00
100.00
1000.00
80 90 100 110 120 130 140 150 160 170 180
Continuous Tj (°C)
Years estimated life
Electromigration Fail Mode
ADS5424-SP
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THERMAL CHARACTERISTICS
PARAMETER TEST CONDITIONS TYP UNIT
RθJA Junction-to-free-air thermal resistance Board Mounted, Per JESD 51-5 methodology 21.81 °C/W
RθJC Junction-to-case thermal resistance MIL-STD-883 Test Method 1012 0.849 °C/W
THERMAL NOTES
This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the
bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is
required on the surface of the PCB directly underneath the body of the package. During normal surface mount
flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an
efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a
thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat
removal. TI typically recommends a 16-mm2board-mount thermal pad. This allows maximum area for thermal
dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of
thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad
must be electrically at ground potential.
Figure 2. ADS5424 Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
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THD +10Log10 PS
PD
SINAD +10Log10 PS
PN)PD
SNR +10Log10 PS
PN
ADS5424-SP
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DEFINITION OF SPECIFICATIONS
Temperature Drift
Analog Bandwidth The temperature drift coefficient (with respect to gain
The analog input frequency at which the power of the error and offset error) specifies the change per
fundamental is reduced by 3 dB with respect to the degree celsius of the parameter from TMIN or TMAX. It
low-frequency value is computed as the maximum variation of that
parameter over the whole temperature range divided
Aperture Delay by TMAX – TMIN.
The delay in time between the rising edge of the input
sampling clock and the actual time at which the Signal-to-Noise Ratio (SNR)
sampling occurs SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
Aperture Uncertainty (Jitter) dc and in the first five harmonics.
The sample-to-sample variation in aperture delay
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse SNR is given either in units of dBc (dB to carrier)
width) to the period of the clock signal. Duty cycle is when the absolute power of the fundamental is used
typically expressed as a percentage. A perfect as the reference, or dBFS (dB to full scale) when the
differential sine wave clock results in a 50% duty power of the fundamental is extrapolated to the
cycle. converter’s full-scale range.
Maximum Conversion Rate Signal-to-Noise and Distortion (SINAD)
The maximum sampling rate at which certified SINAD is the ratio of the power of the fundamental
operation is given. All parametric testing is performed (PS) to the power of all the other spectral components
at this sampling rate unless otherwise noted. including noise (PN) and distortion (PD), but excluding
dc.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions
Differential Nonlinearity (DNL) SINAD is given either in units of dBc (dB to carrier)
An ideal ADC exhibits code transitions at analog input when the absolute power of the fundamental is used
values spaced exactly 1 LSB apart. DNL is the as the reference, or dBFS (dB to Full Scale) when the
deviation of any single step from this ideal value, power of the fundamental is extrapolated to the
measured in units of LSB. converter’s full-scale range.
Integral Nonlinearity (INL) Total Harmonic Distortion (THD)
INL is the deviation of the ADC transfer function from THD is the ratio of the power of the fundamental (PS)
a best-fit line determined by a least-squares curve fit to the power of the first five harmonics (PD).
of that transfer function, measured in units of LSB.
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value. Gain error is THD is typically given in units of dBc (dB to carrier).
given as a percentage of the ideal input full-scale Spurious-Free Dynamic Range (SFDR)
range. The ratio of the power of the fundamental to the
Offset Error highest other spectral component (either spur or
The offset error is the difference, given in number of harmonic). SFDR is typically given in units of dBc (dB
LSBs, between the ADC's actual value average idle to carrier).
channel output code and the ideal average idle Two-Tone Intermodulation Distortion
channel output code. This quantity is often mapped IMD3 is the ratio of the power of the fundamental (at
into mV. frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1– f2or 2f2– f1).
IMD3 is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when it is
referred to the full-scale range
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AIN-Input Amplitude-dB
AC Performance -dB
f =92.16MSPS
f =170MHz
S
IN
AIN-Input Amplitude-dB
AC Performance -dB
f =92.16MSPS
f =70MHz
S
IN
ADS5424-SP
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TYPICAL CHARACTERISTICS
Typical values are at TA= 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted)
AC PERFORMANCE AC PERFORMANCE
vs vs
INPUT AMPLITUDE (70 MHz) INPUT AMPLITUDE (170 MHz)
Figure 3. Figure 4.
AC PERFORMANCE AC PERFORMANCE
vs vs
CLOCK LEVEL (70 MHz) CLOCK LEVEL (170 MHz)
Figure 5. Figure 6.
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DRV -SupplyVoltage-V
DD
SNR-Signal-to-Noise-dBc
DRV -SupplyVoltage-V
DD
SFDR-Sprious-FreeDynamicRange-dBc
ADS5424-SP
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA= 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted)
SPURIOUS-FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIO
vs vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
Figure 7. Figure 8.
SNR SFDR
vs vs
INPUT FREQUENCY and SAMPLING FREQUENCY INPUT FREQUENCY and SAMPLING FREQUENCY
Figure 9. Figure 10.
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CLK
1 kΩ
1 kΩ
AVDD
AVDD
CLK
Bandgap
Clock Buffer
AVDD
Bandgap VREF
25 Ω
−
+
1.2 kΩ
1.2 kΩ
AIN BUF T/H
500 Ω
BUF
500 Ω
VREF
AVDD
BUF T/H
AVDD
AIN
DRVDD
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EQUIVALENT CIRCUITS
Figure 11. Analog Input Figure 12. Digital Output
Figure 13. Clock Input Figure 14. Reference
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10 kΩ
DRVDD
10 kΩ
DMID
AVDD
Bandgap +
−DAC IOUTP
IOUTM
C1, C2
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EQUIVALENT CIRCUITS (continued)
Figure 15. Decoupling Pin Figure 16. DMID Generation
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RT
100 Ω
+
−
OPA695
5 V
R1
400 Ω
ADS5424M
CIN
RIN
0.1 µF1:1
−5 V
R2
57.5 Ω
VIN
AV = 8V/V
(18 dB)
RS
100 Ω
1000 µF
RIN AIN
AIN
R0
50W
Z0
50W
1:1
ADT1−1WT
R
50W
AC Signal
Source ADS5424M
AIN
AIN
ADS5424-SP
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5424 is a 14-bit, 105-MSPS, monolithic pipeline analog to digital converter. Its bipolar analog core
operates from a 5-V supply, while the output uses 3.3-V supply for compatibility with the CMOS family. The
conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series of
small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process
results in a data latency of three clock cycles, after which the output data is available as a 14 bit parallel word,
coded in binary 2's complement format.
INPUT CONFIGURATION
The analog input for the ADS5424 (see Figure 11) consists of an analog differential buffer followed by a bipolar
track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.
The input common mode is set internally through a 500-Ωresistor connected from 2.4 V to each of the inputs.
This results in a differential input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings
symmetrically between 2.4 ±0.55 V and 2.4 –0.55 V. This means that each input is driven with a signal of up to
2.4 ±0.55 V, so that each input has a maximum signal swing of 1.1 VPP for a total differential input signal swing of
2.2 VPP. The maximum swing is determined by the internal reference voltage generator eliminating any external
circuitry for this purpose.
The ADS5424 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 17 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. If voltage gain is required, a step-up transformer can be used. For higher gains
that would require impractical higher turn ratios on the transformer, a single-ended amplifier driving the
transformer can be used (see Figure 18). Another circuit optimized for performance would be the one on
Figure 19, using the THS4304 or the OPA695. Texas Instruments has shown excellent performance on this
configuration up to 10-dB gain with the THS4304 and at 14-dB gain with the OPA695. For the best performance,
they need to be configured differentially after the transformer (as shown) or in inverting mode for the OPA695
(see SBAA113); otherwise, HD2 from the op amps limits the useful frequency.
Figure 17. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
Figure 18. Using the OPA695 With the ADS5424
16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADS5424-SP
2.7 pF
14-Bit
105 MSPS
AIN
AIN VREF
ADS5424M
+5V
THS4509
CM
348 Ω
348 Ω
100 Ω
100 Ω
69.8 Ω
VIN
From
50 Ω
Source
225 Ω
225 Ω
69.8 Ω49.9 Ω
49.9 Ω
0.22 µF 0.22 µF0.1 µF 0.1 µF
0.22 µF
49.9 Ω
−
+
THS4304
ADS5424M
1:1
5 V
CM RF
CM
VIN
From
50 Ω
Source
RG
CM
+
−
THS4304
5 V
CM RF
RG
VREF
AIN
AIN
ADS5424-SP
www.ti.com
SLWS194D –MAY 2008–REVISED SEPTEMBER 2013
Figure 19. Using the THS4304 With the ADS5424
Texas Instruments offers a wide selection of single-ended operational amplifiers (including the THS3201,
THS3202 and OPA847) that can be selected depending on the application. An RF gain block amplifier, such as
Texas Instrument's THS9001, also can be used with an RF transformer for high input frequency applications. For
applications requiring dc-coupling with the signal source, instead of using a topology with three single-ended
amplifiers, a differential input/differential output amplifier like the THS4509 (see Figure 20) can be used, which
minimizes board space and reduces the number of components.
Figure 20. Using the THS4509 With the ADS5424
On this configuration, the THS4509 amplifier circuit provides 10-dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5424.
The 225-Ωresistors and 2.7-pF capacitor between the THS4509 outputs and ADS5424 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz (–3 dB).
For this test, an Agilent signal generator is used for the signal source. The generator is an ac-coupled 50-Ω
source. A bandpass filter is inserted in series with the input to reduce harmonics and noise from the signal
source.
Input termination is accomplished via the 69.8-Ωresistor and 0.22-μF capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ωresistor is inserted to ground across the
69.8-Ωresistor and 0.22-μF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348-Ωfeedback resistor. See the THS4509 data
sheet for further component values to set proper 50-Ωtermination for other common gains.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADS5424-SP
CLK
ADS5424
M
CLK
0.1 µF1:4
Clock
Source
MA3X71600LCT−ND
CLK
ADS5424M
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
ADS5424-SP
SLWS194D –MAY 2008–REVISED SEPTEMBER 2013
www.ti.com
Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a
single power supply input with VS+ =5VandVS– = 0 V (ground). This maintains maximum headroom on the
internal transistors of the THS4509.
CLOCK INPUTS
The ADS5424 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input-frequency applications, where
jitter may not be a big concern, the use of single-ended clock (see Figure 21) could save cost and board space
without any trade-off in performance. When driven on this configuration, it is best to connect CLKM (pin 11) to
ground with a 0.01-μF capacitor, while CLKP is ac-coupled with a 0.01-μF capacitor to the clock source, as
shown in Figure 22.
Figure 21. Single-Ended Clock
Figure 22. Differential Clock
For jitter sensitive applications, the use of a differential clock has advantages (as with any other ADCs) at the
system level. The first advantage is that it allows for common-mode noise rejection at the PCB level. A further
analysis (see Clocking High Speed Data Converters, SLYT075) reveals one more advantage. The following
formula describes the different contributions to clock jitter:
(Jittertotal)2= (EXT_jitter)2+ (ADC_jitter)2= (EXT_jitter)2+ (ADC_int)2+ (K/clock_slope)2
The first term represents the external jitter, coming from the clock source, plus noise added by the system on the
clock distribution, up to the ADC. The second term is the ADC contribution, which can be divided in two portions.
The first does not depend directly on any external factor. The second contribution is a term inversely proportional
to the clock slope. The faster the slope, the smaller this term will be. As an example, the ADC jitter contribution
could be computed from a sinusoidal input clock of 3-Vpp amplitude and Fs = 80 MSPS:
ADC_jitter = sqrt ((150 fs)2+ (5 × 10–5/(1.5 × 2 × PI × 80 × 106))2) = 164 fs
The use of differential clock allows for the use of bigger clock amplitudes without exceeding the absolute
maximum ratings. This, on the case of sinusoidal clock, results on higher slew rates, which minimize the impact
of the jitter factor inversely proportional to the clock slope.
Figure 23 shows this approach. The back-to-back Schottky can be added to limit the clock amplitude in cases
where this would exceed the absolute maximum ratings, even when using a differential clock.
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Product Folder Links: ADS5424-SP
CLK
ADS5424M
CLK
D
VBB
MC100EP16DT
50 Ω
100 nF
100 nF
50 Ω
113 Ω
Q
Q
D
100 nF
100 nF
100 nF
499 W499 W
ADS5424-SP
www.ti.com
SLWS194D –MAY 2008–REVISED SEPTEMBER 2013
Figure 23. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, as PECL. In this case, the slew rate of the edges will most
likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope dependent ADC jitter. Nevertheless, observe that for the
ADS5424, this term is small and has been optimized. Using logic gates to square a sinusoidal clock may not
produce the best results as logic gates, which may not have been optimized to act as comparators, adding too
much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩresistors. It is
recommended to use an ac coupling, but if for any reason, this scheme is not possible, due to, for instance,
asynchronous clocking, the ADS5424 presents a good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that,
ideally, a 50% duty cycle should be provided.
DIGITAL OUTPUTS
The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal
(DRY, pin 52), and an out-of-range indicator (OVR, pin 32) that equals 1 when the output reaches the full-scale
limits.
The output format is two's complement. When the input voltage is at negative full scale (around –1.1-V
differential), the output will be, from MSB to LSB, 10 0000 0000 0000. Then, as the input voltage is increased,
the output switches to 10 0000 0000 0001, 10 0000 0000 0010 and so on until 11 1111 1111 1111 right before
mid-scale (when both inputs are tight together if we neglect offset errors). Further increases on input voltage,
outputs the word 00 0000 0000 0000, to be followed by 00 0000 0000 0001, 00 0000 0000 0010 and so on until
reaching 01 1111 1111 1111 at full-scale input (1.1-V differential).
Although the output circuitry of the ADS5424 has been designed to minimize the noise produced by the
transients of the data switching, care must be taken when designing the circuitry reading the ADS5424 outputs.
Output load capacitance should be minimized by minimizing the load on the output traces, reducing their length
and the number of gates connected to them, and by the use of a series resistor with each pin. Typical numbers
on the data sheet tables and graphs are obtained with 100-Ωseries resistor on each digital output pin, followed
by a 74AVC16244 digital buffer as the one used in the evaluation board.
POWER SUPPLIES
The use of low noise power supplies with adequate decoupling is recommended, being the linear supplies the
first choice versus switched ones, which tend to generate more noise components that can be coupled to the
ADS5424.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: ADS5424-SP
ADS5424-SP
SLWS194D –MAY 2008–REVISED SEPTEMBER 2013
www.ti.com
The ADS5424 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for the
digital outputs supply (DRVDD), we recommend the use of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied together inside the package. Customers willing to experiment
with different grounding schemes should know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and
29, while DRGND pins are 2, 34, and 42. We recommend that both grounds are tied together externally, using a
common ground plane. That is the case on the production test boards and modules provided to customer for
evaluation. To obtain the best performance, user should lay out the board to assure that the digital return
currents do not flow under the analog portion of the board. This can be achieved without splitting the board and
with careful component placement and increasing the number of vias and ground planes.
Finally, notice that the metallic heat sink under the package is also connected to analog ground.
LAYOUT INFORMATION
The evaluation board represents a good guideline of how to lay out the board to obtain the maximum
performance out of the ADS5424. General design rules for use of multilayer boards, single ground plane for both,
analog and digital ADC ground connections, and local decoupling ceramic chip capacitors should be applied. The
input traces should be isolated from any external source of interference or noise, including the digital outputs as
well as the clock traces. Clock also should be isolated from other signals, especially on applications where low
jitter is required, as high IF sampling.
Besides performance oriented rules, special care has to be taken when considering the heat dissipation out of
the device. The thermal package information describes the TJA values obtained on the different configurations.
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Product Folder Links: ADS5424-SP
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-0720601VXC ACTIVE CFP HFG 52 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-
0720601VXC
ADS5424MHFG-V
ADS5424HFG/EM PREVIEW CFP HFG 52 TBD Call TI N / A for Pkg Type 25 Only ADS5424HFG/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5424-SP :
•Catalog: ADS5424
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
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