a e re 8 AdLib systems OCR Evaluation Operational Description July 2002 TFEC041OG 2 .5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 1 Document Organization This document is primarily intended for designers who require design implementation information and block interface specifications . This is a companion document to the TFEC0410G document group, which consists of the following documents : . TFEC0410G Product Description . TFEC041OG Operational Description . TFEC041OG Hardware Register Memory Map . TFEC041OG Hardware Design Guide . TFEC041OG System Design Guide This document contains the following information divided into the following sections: . Block Diagrams (Section 3 on page 23) . Device Overview (Section 2 on page 6) . Top-Level Overview (Section 4 on page 29) . DW and FEC (Section 5 on page 37-Section 18 on page 112) . SONET FEC (BCH Weak/in Band) Supermacro (Section 19 on page 113) . BCH Macro (Section 20 on page 118) . BCH Overhead Processing (Section 21 on page 128-Section 37 on page 166) . Microprocessor Interface (Section 38 on page 167) . TFEC Primary Clock Inputs (Section 39 on page 179) . TFEC Clock Multiplexers (Section 40 on page 180) . TFEC Data Multiplexers (Section 41 on page 182) . TFEC Phase Detectors (Section 42 on page 183) . TFEC Loopbacks (Section 43 on page 185) . TFEC Valid Modes (Section 44 on page 186) . Outline Diagram (Section 45 on page 187) . List of Acronyms (Section 46 on page 188) . Ordering Information (Section 47 on page 203) AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 Table of Contents Contents Page 1 Document Organization . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... 1 2 Device Overview .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . . .. . . ... . . ... . .... . ... . . .. . . ... . . .. 6 2.1 Device Modes Overview ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . .... . ... . ... . . ... . . .. . . .. . . . ... . .... . ... . .... . ... 8 2.2 System Interface Overview ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . ... . .... . ... . .... . ... 9 2.3 Section/Line Overhead Insert/Drop Overview (Figure 3) .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .... . ... 9 2.4 TOAC Insert/Drop Channel Overview . . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 10 2.4.1 Mode 1-Full TOAC Drop/Insert Mode .. .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .. 10 2.4.2 Mode 2-Partial Insert/Drop Mode . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 12 2.5 In-Band (Weak) FEC Overview (Bose-Chaudhuri-Hocquenghem (BCH-3)) ... . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . .... . . 13 2.6 Strong FEC (G.975) and Digital Wrapper (OTN) Processing Overview . ... . ... . . ... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . .. 14 2.6.1 Elastic Stores (ES) .. . .... ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 14 2.6.2 RS Encoder/Decoder and Digital Wrapper Basis Frame Format ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 15 2.6.3 FEC Overhead and Digital Wrapper Overhead Definition .. .... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .. 17 2.6.4 FEC/DW-DWAC (Digital Wrapper Access Channel) Drop/Insert Block . . . .. . . ... . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .. 18 2.6.5 Receive/Transmit FEC/DW Framer .. . . ... . ... . . ... . .... .... . ... . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 19 2.7 Line Interface-MUX/DeMUX Overview . . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 19 2.8 Alarm Status Output Signals Overview ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .. 20 2.9 Microprocessor Interface Overview . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 20 2.9.1 Transfer Error Acknowledge (TEA N) (with MPC860 and MC68360 Only) . . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 20 2.9.2 Interrupt Structure .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .... . . 20 2.10 Clocking Overview . . .. . . ... . . .. . . . .. . . ... . .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . .. 21 3 Block Diagrams. . .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 23 4 Top-Level Overview .. . ... . . .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 29 4.1 Top-Level Functionality . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 29 4.2 Top-Level Clocking . . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 29 4.3 Top-Level Loss-of-Clock Detectors . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 31 4.4 Top-Level Reset Architecture (Hardware/Software) . . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 32 4.5 Top-Level Loopback Control Signals .. . . .. . . . .. . . .. . . . .. . . ... . .... . .. . . ... . .... . ... . .... . ... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 33 4.6 Top-Level Powerup Control Registers . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 33 4.7 Top-Level Phase Detectors ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . .. 34 4.7.1 PD Engine . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . .. 34 4.8 Top-Level Line Timing Signal Reference . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . .. 35 4.9 Top-Level Alarm Status Output Signals (Through GPIO) .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . .. 36 5 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro .. . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 37 5.1 Strong FEC Introduction ... . . .. . . . .. . . ... . ... . . ... . .... .... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . .. 37 5.2 Functional Description of Strong FEC . . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 38 5.2.1 Strong FEC Mode Description ... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 39 5.2.2 Strong FEC Overhead and Digital Wrapper Overhead Definition ... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .. 41 5.3 Strong FEC Supermacro Clocking Domain Specification .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .. 44 5.4 Alarm Definition Table .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . .. 44 5.5 OTUk Overhead Generation . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 45 5.6 Strong FEC Alarm Actions . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 51 5.7 Overview, General Functional Description, and Block Diagram of Strong FEC Supermacro Submacros .. . . 52 5.7.1 Elastic Store (ES) Macro . . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 52 5.7.2 DW Macro. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . .. 52 5.7.3 Reed-Solomon (RS) Macro . . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 52 5.7.4 Scram bler/Descrambier Macro . . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 52 5.7.5 Error Insert Macro .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . .... . . 53 5.7.6 Framer Macro . ... . . .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . .... . . 53 5.7.7 Interleaver/Deinterleaver Macro ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .. 53 6 Strong FEC Supermacro Elastic Store (Transmit Direction) . . ... . .... .... . ... . . ... . . .. . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .. 54 2 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 with Strong/Weak FEC and Digital Wrapper Table of Contents (continued) Contents Page 6.1 Elastic Store (Tx) Functional Description . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 54 7 Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF) . . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . . ... . . .. . . . .. . . ... . 55 7.1 Functional Description of FEC/DW Framer .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... . . 55 7.1 .1 Loss-of-Signal (LOS) Detector .. .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 55 7.1 .2 Framer (A1 and A2) . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . . 56 7.1 .3 Loss-of-Frame (LOF) Detector .. .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 60 7.1 .4 Provisioning and Alarm Operation in 10 Gbits/s Mode.. . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . . 60 8 Digital Wrapper Insert . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . .... . ... . .... . . 61 8.1 Functional Description of Digital Wrapper Insert . ... . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... . . 61 8.1 .1 Framing Bytes Insert .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... . . 62 8.1 .2 Internal FEC Overhead Byte Insert (OHO to OH3) .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 63 8.1 .3 BIP-8 Calculation . . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... . ... . . .. . .... . . 65 8.1 .4 General Definition of BEI, BDI, and IAE Insert and Monitor ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... . . 66 8.1 .5 OTU Section Monitoring (SM) ... . ... . . .. . . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 68 8.1 .6 Path Monitoring Insert (PM).. . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . . 72 8.1 .7 PM Statistics ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 74 8.1 .8 Tandem Connection Insert (TCMi) . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... . . 74 8.1 .9 TCM Statistics . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 76 8.1 .10 Alarm Indication Signal (AIS), Open Connection Indication (OCI), Locked (LCK), and Fixed Pattern Insert . . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... . . 76 8.1 .11 DWAC Insert. . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .... . . .. . . ... . . 79 8.1 .12 PRBS Insert and Monitor . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 80 8.1 .13 Digital Wrapper Check Byte Insert . .. . . ... . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 82 9 Strong FEC Supermacro Reed-Solomon (RS) Encoder .. . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 82 9.1 Functional Description of RS Encoder . . . .. . . ... . .... . ... . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . . 82 10 Strong FEC Supermacro Scrambler ... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 83 10.1 Functional Description of Strong FEC Supermacro Scrambler.. . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . .... . ... . .... . . 83 11 Strong FEC Supermacro Error Insert . .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 84 11 .1 Functional Description of Error Insert. ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 84 12 Interleaver .. . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 86 12.1 Functional Description of Interleaver. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . ... . . .. . . ... . . 86 13 Deinterleaver . . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . .... . ... . .... . . 86 13.1 Functional Description of Deinterleaver . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .... . ... . .... . . 86 14 Framer Receive Direction Requirements . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 86 15 Strong FEC Supermacro Descrambler ... . ... . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... . . 88 15.1 Functional Description of Descrambler . . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . .... .... . ... . .... . . 88 16 Reed-Solomon (RS) Decoder ... . . ... . .... .... . ... . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . . 89 16.1 Functional Description of RS Decoder .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... . . 89 16.1 .1 Error Detect and Correct . .. . . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . . 89 16.1 .2 BER Monitor . . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . . .. . . ... . . 89 16.1 .3 Error Count.. . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .... . ... . .... . . 90 17 Digital Wrapper Drop ... . . ... . .... ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . ... . ... . . ... . ... . .... . ... . .... . . 94 17.1 Functional Description of Digital Wrapper Drop .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . .... . ... . .... . . 94 17.1 .1 Internal FEC Overhead Bytes Monitor (OHO to OH3) . . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... . . .. . . . .. . . ... . 94 17.1 .2 BIP-8 Monitor (See Figure 32 on Page 65) . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . .... . . 96 17.1 .3 BII Monitor-BDI Detect and BEI Monitor .. . ... . .... .... . ... . . ... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . . .. . .... . . 97 17.1 .4 OTU Section Monitoring (SM) . . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... . . 97 17.1 .5 ODU Path Monitoring (PM). . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... . . 99 17.1 .6 ODUk Tandem Connection Monitoring (TCM) ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... 104 17.1 .7 DWAC Drop. . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 106 17.1 .8 Insertion of AIS, OCI, and Other Fixed Patterns . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . .... 107 Agere Systems Inc. 3 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 Table of Contents (continued) Contents Page 17.1 .9 PRBS Monitor .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . 17.1 .10 PRBS Insert ... . . .. . . ... . . .. . . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . 17.1 .11 No Fix Stuff Mode . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . 18 Elastic Store (Receive Direction) ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 18.1 Functional Description of Elastic Store Receive Direction . ... . .... . ... . .... . ... . ... . . ... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . ... . 19 SONET FEC (BCH Weak/in Band) Supermacro . . . .. . . . .. . . .. . . . .. . . ... . .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . .... 19.1 SONFEC (BCH Weak/in Band) Introduction .. . ... . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . 19.2 Functional Description of SONET FEC (BCH Weak/in Band) Supermacro . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . 19.3 SONFEC AIS/RDI Generation . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . ... . ... . . ... . ... . 19.3 .1 SONFEC (BCH Weak/in Band) Overview . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 19.3 .2 Transmit AIS . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . .... 19.3 .3 Receive AIS . . . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .... . ... . ... . 19.3 .4 Transmit RDI Generation . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 19.4 SONFEC Interrupt Structure . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . 20 BCH Macro .... . ... . .... . ... . . .. . . . .. . . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . ... . . .. . . . ... . ... . .... . ... . .... 20.1 Functional Description of BCH Macro ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . 20.1 .1 BCH Encoder . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . 20.1 .2 BCH Decoder .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . 20.1 .3 BCH Statistics (BCH-Stat) .. . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . 21 SONFEC Input MUX and Output MUX ... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . 21 .1 Functional Description of SONEC Input MUX and Output MUX . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . 22 Loss-of-Signal (LOS) Detector and Framer . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . 22.1 Functional Description of LOS Detector and Framer .... . ... . .... .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . 22.1 .1 Loss-of-Signal (LOS) Detector .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . 22.1 .2 Framer (A1 and A2).. . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . 23 Transmit Alignment FIFO. . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . ... . .. . . . .. . . ... . . ... . ... . 23.1 Functional Description of Transmit Alignment FIFO . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . 24 B1 Monitoring . . . .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 24.1 Functional Description of B1 Monitoring . . ... . .. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . .... .... . ... . .... 25 Descrambler .. . . .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 25.1 Functional Description of the Descrambler . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . 26 Transpose Demultiplexer . . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . 26.1 Functional Description of the Transpose Demultiplexer (TDMX) ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . 27 RDI/AIS Detection ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . 27.1 Functional Description of RDI/AIS Detection . . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . ... . .... 28 B2 Monitoring . . . .. . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 28.1 Functional Description of B2 Monitoring . . ... . .. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . .... .... . ... . .... 29 BER-SD/SF Detection . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . .... 29.1 Functional Description of BER-SD/SF Detection .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . 30 Receive Transport Overhead Processing ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 30.1 Functional Description of the Receive Transport Overhead Processing. . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . 30.1 .1 Global Overhead Byte Processing .. . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . 31 Transmit Transport Overhead (TOH) Processor . . ... . . ... . ... . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 31 .1 Functional Description of TOH Processor .. . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . 31 .1 .1 Global Overhead Byte Insertion .. . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . 32 Receive TOAC Drop/Transmit TOAC Insert . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . ... . . ... . ... . .... . ... . .... . ... . ... . .... 32.1 Receive TOAC Drop . . . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . 32.2 Transmit TOAC Insert . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . 32.3 TOAC Modes . ... . . .. . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . 32.3 .1 Full TOAC Insert/Drop Mode .. . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . ... . ... . . ... . ... . 32.3 .2 Partial TOAC Insert/Drop Mode.. . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . 4 110 111 111 112 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AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 with Strong/Weak FEC and Digital Wrapper Table of Contents (continued) Contents Page 33 Receive/Transmit Payload Processing ... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 33.1 Receive Payload Processing ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... 33.2 Transmit Payload Processing .. . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 34 B2 Computing . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . .... . ... . .... 34.1 Functional Description of B2 Computing . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... 35 Transpose Multiplexer (TMX) ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 35.1 Functional Description of the TMX . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... 36 Scrambler .. . . .. . . . .. . . ... . ... . . ... . .... ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . . ... . .. . . ... . . ... . ... . .... . ... . .... 36.1 Functional Description of the Scrambler in the Transpose Multiplexer . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . ... . .... 37 B1 Computing . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . .... . ... . .... 37.1 Functional Description of B1 Computing . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... 38 Microprocessor Interface . . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 38.1 Microprocessor Interface Overview... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 38.2 Subblock Address Space Assignment . .. . . ... . .... . ... . .... .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . . ... . ... . .... 38.3 Microprocessor Interface Modes... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 38.4 Microprocessor Interface Pinout Descriptions. . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . . ... . ... . .... 38.5 Reset Behavior ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .... . ... . .... 38.6 Microprocessor Data Bus Width . . .. . . .. . . . .. . . ... . .... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . .... . ... . . .. . . ... 38.7 Transfer Error Acknowledge (Mode 1 and Mode 2 Only).. . .... . ... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 38.8 Interrupt Structure . . . . .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . ... . ... . . ... . ... . .... . ... . .... 38.9 Interrupt Alarm and Interrupt Persistency Registers . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . ... . . ... . ... . .... . ... . .... . ... . ... . .... 38.10 Performance Monitor (PM) Clock . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... .... . ... . .... 38.11 General Purpose Input/Output (GPIO) . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 39 TFEC Primary Clock Inputs ... ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .... . ... . ... . .... . ... . .... 40 TFEC Clock Multiplexers .. . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... 40.1 Clock Multiplexers and Register Bits Selection . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . ... . .... 40.2 Clock Selection .. . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . ... . ... . . ... . ... . .... . ... . .... 41 TFEC Data Multiplexers . ... . .... .... . ... . . ... . ... . . .. . . . .. . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 41 .1 Data Multiplexers and Register Bits Selection . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . . ... . ... . . ... . ... . .... 42 TFEC Phase Detectors . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . .... 42.1 Clock Division Select .. . . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . ... . . ... . ... . .... . ... . .... 42.2 Clock Selection .. . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 43 TFEC Loopbacks . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . .. . . ... . . ... . ... . .... . ... . .... 44 TFEC Valid Modes ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 44.1 General Conditions on Primary Clock Inputs ... . ... . .... .... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... . ... . . .. . . ... . ... . . .. . . ... 45 Outline Diagram .. . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 45.1 792-Pin PBGAM1TH ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . ... . .... . ... . .... 46 List of Acronyms . . . ... . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . ... . ... . . ... . . .. . . .. . . . .. . . ... . . ... . ... . .... . ... . .... 47 Ordering Information . ... . . ... . .... .... . ... . . ... . ... . . .. . . . .. . . .. . . . .. . . ... . .... . ... . .... . ... . ... . . ... . . .. . ... . . ... . . .. . . .. . . . ... . ... . . ... . ... . .... . ... . .... Agere Systems Inc. 162 162 163 164 164 165 165 165 165 166 166 167 167 167 168 168 170 171 171 172 172 173 174 179 180 180 180 182 182 183 183 183 185 186 186 187 187 188 203 5 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 Operational Description July 2002 Device Overview The following diagrams show simplified pictures of the major blocks and I/O information of the TFEC0410G device . The device has a flexible setup to allow for operation in terminal and regenerator applications . Figure 1 shows the device in 2.5 Gbits/s mode, and Figure 2 on page 7 shows the device in 10 Gbits/s mode. For convenience, two symbol sets are provided for the transmit and receive line and system interface pins, based on the mode of the device . I 9~ T _ 80 LINE SIDE U) U) Z ~_I y 20 5 W .I ~I UI OI~~ O O O O O O <1 o w > _ o ~I U 0 I~ Y U 1 . 1 aI 1I O O H I . TCLKL0-[1-4] TDLO 4[3 :0] TDLO 313 :0] RCLKLI-[1-4] RDLI 4_[3 :0] Il SYSTEM SIDE H H . 1 :15 PHASE DIET TDSI 413:0] TDSI 313:0] TDSI 213:0] TDSI 1[3:0] TCLKSI-[1-4] SECTION/LINE OVERHEAD STS-48 MONITORIINSERT BCH-3 ENCODE AND DIGITAL WRAPPER WITH OPTICAL CHANNEL OVERHEAD PROCESSING RDLI 3_[3 :0] RDLI 2_[3 :0] Il SONFEC STRONG FEC (REED-SOLOMON) OUT-OF-BAND TERFACE LINE STS-48 WI X4 DWFEC TDLO 1_[3 :0] O O a O O WI 8 + JTAGINTERFACE TDLO 2[3 :0] ~I UI U U T Y SYSTEM STS-48 RCLKS0-[1-4] RDLI 1[3 :0] RDSO 4[3 :0] RDSO 313 :0] RDSO 2[3 :0] RXREF0-[1-4] IDDQ N RDSO 1[3 :0] RST N I MICROPROCESSOR INTERFACE I X4 DIET . MPMODE AS, MPTYPE IM, MPDB 8 -16 : MPPAREN J ZI I = Z a ZI ZI ~ Q H ZI ZI ZI ZI , O O O Q O U I a Y I I U UI } a Q U O I WI cn I =I W Figure 1 . TFEC I/O Block Diagram-2 .5 Gbits/s Mode 6 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) T 0 LU01 1 0 0 LINE SIDE -1 t,-, z Y z ~c C, 0 0 Tr, z>_ 2 U)i 01-, OC 0 W' W'U 0n_ U SYSTEM SIDE 4SE DET . ~ 79 JTAG INT E RFACE TCLKLO_[1 ] -a- - DWFEC TDLO_[1 5 :0] :6 RCLKI J1] STRONG FEC (REED-SOLOMON) OUT-OF-BAND INTERFACE LINE STS-192 TCLKSI_[1] SECTION/LINE OVERHEAD STS-192 MONITORIINSERT BCH-3 ENCODE AND DIGITAL WRAPPER WITH OPTICAL CHANNEL OVERHEAD PROCESSING RDLI_[15 :0] TDSI_[15 :0] SONFEC INTERFACE SYSTEM STS-192 RCLKS011] RDS0_[15 :0] RXREF0_[1] IDDQ N RST N ---------MICROPROCESSOR INTERFA - MPMODE-AS, MPTYPE IM, MPD13 8 16, M PPAR MN Z Z Z Z Z Z OF U)i . . . . . . Z 6 < F 6 ~c EL F3 TT 0 AASE DIET I UQ 0< EL of 1 =I W of Figure 2. TFEC I/O Block Diagram-10 Gbits/s Mode Agere Systems Inc. 7 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 2.1 Device Overview (continued) Device Modes Overview The TFEC0410G has several functional modes to allow for operation in terminal and regenerator applications . Table 1, TFEC041OG Operating Modes, on page 8 outlines the system and line interface rate requirements in different applications . Other combinations which may be acceptable operating modes of the device can be programmed, but are not guaranteed to function error-free . Table 1 . TFEC041OG Operating Modes Mode Strong FEC/Digital Wrapper-Terminal Strong FEC/Digital Wrapper-Regenerator Strong FEC or Digital Wrapper with Strong FEC-Bidirectional Mode Weak FEC-Terminal Receive Interface Rx-Line (Gbits/s) 10.7 (10 .66) 2 .66 11 .05 10.7 (10 .66) 2 .66 11 .05 10.7 (10 .66) 2 .66 Rx-System (Gbits/s) 9.953 2.488 Internal Internal 9.953 2 .488 Internal Internal 9.953 2 .488 2 .488 2 .5G H 2 .5G 9.953 2 .488 9.953 2 .488 10.7 (10 .66) 2 .66 10.7 (10 .66) 2 .66 10.7 (10 .66) 2 .66 10.7 (10.66)/9 .953 2 .66/2 .488 2 .66/2 .488 2 .66/2 .488 9.953 2 .488 9.953 2 .488 10.7 (10 .66) 2 .66 10.7 (10 .66) 2 .66 10.7 (10 .66) 2 .66 10.7 (10 .66)/9 .953 2 .66/2 .488 10G ---> Quad 2 .5G 10.7 (10 .66) Quad-2.488 9.953 Quad-2 .66 10G ---> Quad 2 .5G e .g., Rx = 10G Weak, Tx = Quad 2 .5G Strong 9.953 9.953 Quad-2.488 9.953 9.953 2 .488 Quad-2 .488 2 .66 10G Quad 2 .5G GbE 10G Quad 2 .5G GbE 10G Quad 2 .5G 10G Quad 2 .5G Weak FEC-Regenerator 10G Quad 2 .5G Strong/Weak-Terminal 10G Quad 2 .5G Strong/Weak 10G -Regenerator Quad 2 .5G Digital Wrapper/Weak 10G -Terminal Quad 2 .5G Asymmetric Multiplex Mode 10G H Quad 2.5G Single 2 .5 Gbits/s Mode (16-Bit Line/System Interface) Asymmetric: Strong/Digital Wrapper with/without Weak Asymmetric-Weak Asymmetric-Tx/Rx Directions Transmit Interface Tx-System (Gbits/s) 9.953 9.953 2 .48 2 .48 10.312 10.312 Internal Loopback Internal Loopback Internal Loopback 10.7 (10.66) 10.7 (10 .66) 2 .66 2 .66 9.953 2.488 Loopback Loopback 9.953 2 .488 Loopback Loopback 9.953 2 .488 2.488 Tx-Line (Gbits/s) 10.7 (10 .66) 2 .66 11 .05 10.7 (10 .66) 2 .66 11 .05 10.7 (10 .66) 2 .66 Note : The number in parenthesis, when present, is the effectual rate due to no stuffing. 8 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 2.2 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) System Interface Overview . The system interface block has the three following modes of operation : -One group of 16 bits at 622 .08/666 .51/669 .32 Mbits/s for a 9.953 Gbits/s data rate. - Four groups of 4 bits at 622 .08/666 .51 Mbits/s for quad 2.488 Gbits/s . -One group of 16 bits at 155 .52/166 .63 Mbits/s . This interface allows transmit-to-receive loopback . Note : The system interface can run at other rates in strong FEC or digital wrapper mode. This rate is dependent on the system-side data rate, where this rate is 238/255 (14/15) or 237/255 (79/85) (10 Gbits/s mode with one fixed stuff column) of the line rate. 2.3 Section/Line Overhead Insert/Drop Overview (Figure 3) The section/line overhead blocks accept four clocks and four 32-bit data streams in quad 2.5 Gbits/s mode, one clock and one 32-bit data stream in single 2 .5 Gbits/s mode, or one clock and one 128-bit data bus in single STS-1 92/STM-64 mode. Serial TOAC channels for insert (4)/drop (4) of the transport overhead bytes are provided . The section/line overhead block (Figure 3, SONET/SDH Line/Section Overhead Processing with BCH-3 Capability, on page 10) performs framing-normal/enhanced (OOF, LOF), loss-of-signal detection (LOS), scrambling/descrambling, time-slot interchange (TSI) (if necessary) (STS-192/STM-64 only), alignment FIFO (asymmetric multiplex mode only), internal monitoring/insertion of select section and line overhead bytes (J0, 131, F1, B2, K1/K2 (AIS-L, RDI-L), B2, S1, M1), and FEC status correction (FSI) (BCH-3 processing) . Along with these monitoring/insert capabilities, the generation of AIS-L under hardware or software control is provided . Four BER algorithms are provided per stream (STS-48/STM-16 or STS-1 92/STM-64) to calculate signal fail (SF) and signal degrade (SD) conditions before and after BCH-3 error correction . The B1/B2 calculation (insert) monitor, scramble/descramble, transpose, alignment FIFO, BCH-3 encoder/decoder, and section/line overhead can all be bypassed independently per function and per STS-48/STS-192 stream . A PRBS generator and monitor are provided per STS-48 signal for continuity checking . This signal is placed into the STS-48 or within each STS-48 signal within a STS-192 payload with a pointer value of 522 . This fixed value allows monitoring at the receiver end without the need for a pointer interpreter. Note : The pointer is set by the incoming signal . Only when PRBS data is injected into the SONET frame is the pointer set, by the device, to 522 . Agere Systems Inc. 9 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 Operational Description July 2002 Device Overview (continued) 2.3 Section/Line Overhead Insert/Drop Overview (Figure 3) (continued) TRANSMIT DIRECTION T = TRANSPOSE BLOCK A = ALIGNMENT FIFO TOAC IN SERT (1 .728 Mbits/s OR 20 .736 Mbits/s) 0 I 131 CALL . I I SCR T I I PRBS ERR . INS I BCH-3 ENCODE I I B2 CALC . I J0, F1, APS, FSI (BCH-3) K2[2 :0]-RDI-L/AIS-L, S1, REI-INTERNAL INSERT SECTION/ LINE/ PRBS , AIS, INS. B2 MON T A DSCR I I I I W F- FRAMER, B1 MON . (OOF, LOF, LOS) W Z J FRAMER, 131 MON . (OOF, LOF, LOS) ] DSCR T BCH-3 MT B2 DECODE/ CORRECT, FSI MON B2 131 OR B2 RxREF (8 kHz) L__'~ BER SF/SD RECEIVE DIRECTION SECTION/ LINE TERM . (AIS INS) BCH STATS PRBS MON 4 BER SF/SD B2 CALC . T SCR B1 CALL . 131 MON, B2 MON, J0, F1, APS, S1, REI-INTERNAL MONITORS TOAC DROP (1 .728 Mbits/s OR 20.736 Mbits/s) Figure 3. SONET/SDH Line/Section Overhead Processing with BCH-3 Capability 2.4 TOAC Insert/Drop Channel Overview Four TOAC insert/drop functions are provided in quad STS-48/STM-16 mode and one function is provided in STS-192/STM-64 mode. These interfaces can operate in full TOAC drop/insert mode (Section 2.4.1) and in partial insert/drop mode (Section 2.4.2 on page 12) . 2.4.1 Mode 1-Full TOAC Drop/Insert Mode . The following signals are provided per channel: -One output clock at 20.736 MHz . -One output sync at 8 kHz coincident with the MSN (most significant nibble) of the first A1 byte. -One input enable signal (Tx only) active during the MSN (most significant nibble) and/or the LSN (least significant nibble) of each byte that may be inserted into the output stream . There is only one control signal per stream . This is an encoded signal programmed as follows : -11 = Insert TOAC data. -00 = Default . -01 = Pass data from incoming data stream . -10 = Software controlled data. -One set per STS-48/STM-16 frame input/output data bus (insert/drop-Tx/Rx direction, respectively)-4 bits/stream at 20.736 Mbits/s that transition at the rising edge of the clock (10,368 bits per STS-48/STM-16 SONET/SDH frame) . Each STS-48/STM-16 within the STS-192/STM-64 stream is output independently . 10 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) 2.4 TOAC Insert/Drop Channel Overview (continued) Table 2 shows the byte ordering for a STS-1 92/STM-64 signal in SONET/SDH byte ordering, and Table 3 on page 11 shows a STS-1 92/STM-64 in STS-48/STM-16 byte ordering . The TOAC channels output/accept the nibble data in STS-48/STM-16 byte order independent of the full drop/insert mode. Therefore, in STS-1 92/STM-64 mode, four TOAC channels are needed to drop/insert the entire transport overhead bytes. A byte is inserted into the transmit data stream through an external input that is sampled per clock cycle. Table 2. TOAC-STS-192 SONET/SDH Byte Ordering Time (Top to Bottom, then Left to Right) 4 => 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 I 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 I 97 100 103 106 109 112 115 118 121 124 127 130 133 136 139 142 I 145 148 151 154 157 160 163 166 169 172 175 178 181 184 187 190 II 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 I 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 I 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 I 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 II 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 I 51 54 57 60 63 66 69 72 75 78 81 84 87 90 93 96 I 99 102 105 108 111 114 117 120 123 126 129 132 135 138 141 144 I 147 150 153 156 159 162 165 168 171 174 177 180 183 186 189 192 STS-192 Number 1 Table 3. TOAC-STS-192 or STS-48 (Use STS-192 Numbers) in STS-48 Byte Ordering Time (Top to Bottom, then Left to Right for Each 1 2 14 13 25 37 26 38 4 16 28 40 5 17 29 41 7 19 31 43 8 20 32 44 10 22 34 46 11 23 35 47 74 49 61 73 85 50 62 86 52 64 76 88 53 65 77 89 55 67 79 91 56 68 80 92 58 70 82 94 59 71 83 95 121 110 122 134 97 109 133 98 100 112 124 136 101 113 125 137 103 115 127 139 104 116 128 140 106 118 130 142 107 119 131 143 145 157 181 146 170 182 169 158 148 160 172 184 149 161 173 185 151 163 175 187 152 164 176 188 154 1 166 1 178 1 190 II 155 I 167 1 179 1 191 I I Agere Systems Inc. STS-48 Channel) => 27 3 15 39 6 18 30 42 9 21 33 45 12 24 36 48 51 63 75 87 54 66 78 90 57 69 81 93 60 72 84 96 111 123 99 135 102 114 126 138 105 117 129 141 108 120 132 144 147 171 159 183 150 162 174 186 153 165 177 189 156 I 168 1 180 1 192 TOAC Pins RT0AC DATAO_4_[3 :0] RT0AC DATAO 3_[3:0] RTOAC DATAO 2_[3 :0] RT0AC DATAO_1 _[3 :0] 11 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 Device Overview (continued) 2.4 2.4.2 TOAC Insert/Drop Channel Overview (continued) Mode 2-Partial Insert/Drop Mode . The first STS-1/STM-0 (J0, E1, D1-D3, D4-D12, S1, E2, etc.), including the M1 byte, are accessible: -One output clock at 1 .728 MHz . -One output sync at 8 kHz coincident with the MSB (most significant bit) of the first A1 bit . -One input enable signal (Tx only) active during bit 7 (MSB) and/or bit 6 of each byte that may be inserted into the output stream . There is only one control signal per stream . This is an encoded signal which behaves as follows: -11 = Insert TOAC data. -00 = Default . -01 = Pass data from incoming data stream . -10 = Software controlled data. - One input/output data bit (insert/drop-Tx/Rx direction, respectively)-1 bit at 1 .728 Mbits/s that transitions at the rising edge of the clock (216 bits per STS-1 92/STM-64 or STS-48/STM-16 frame) . Table 4 summarizes the frame format in the STS-1 /STM-0 mode. Data is transmitted from left to right, then top to bottom, with A1 bit 7 being the first bit to be transmitted/received . Table 4. TOAC Insert/Drop Frame Format-STS-1/STM-0 Mode Row Section/RS Line/MS Column Numbers 1 2 3 1 A1 A2 2 3 4 5 6 7 131 D1 E1 D2 H1 B2 H2 K1 J0 F1 D3 H3 K2 D4 D7 8 9 D10 S1 D5 D8 D11 Mil D6 D9 D12 E2 I I I 1 . The Z2 byte is overwritten by the M1 value . 12 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 2.5 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) In-Band (Weak) FEC Overview (Bose-Chaudhuri-Hocquenghem (BCH-3)) The weak FEC operates on a quad STS-48/STM-16 and a single STS-192/STM-64 signal as per T1X1 .5/99-218R2 and G.707 standards . The bit-interleaved (x8) BCH-3 (4359, 4320) allows for triple error correction per block . In quad STS-48/STM-16 mode, 24 consecutive bit errors can be corrected . In STS-192/STM-64 mode, 96 consecutive bit errors can be corrected because the signal is encoded on a per-STS-48/STM-16 basis . The check bit locations, per row, are fixed per the standards. The decoder allows a hardware control of the decoder/error correction logic per stream or software control of the decoder/encoder correction logic. Either mode is provisionable through software . The modes are as follows : 1 . Hardware mode: transition between the two submodes is hitless and controlled by the FSI status bits: -Correct with data delay. -Do not correct with data delay. 2. Software control (independent of FSI status) : -FEC correction enabled . -FEC correction off with decoder delay. -FEC correction off without decoder delay. -FEC monitor mode without decoder delay. The raw bit error count/block count is provided to the software along with the number of uncorrectable blocks . These values are accumulated in individual saturating counters per STS-48/STM-1 6/STS-192/STM-64 stream. The encoder allows three modes of operation per stream entirely under software control . Transition between hardware mode and software control is hitless . 1 . FEC encoder on with delay. 2. FEC encoder off with delay. 3. FEC encoder off without delay. The total delay through the encoder or decoder is less than 15 ps each. Agere Systems Inc. 13 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 Operational Description July 2002 2.6 Device Overview (continued) Strong FEC (GL975) and Digital Wrapper (OTN) Processing Overview The strong FEC performs out-of-band forward error correction in quad STS-48/STM-16 mode or in single STS-1 92/STM-64 mode. For example, in quad STS-48/STM-16 mode, the payload rate (system interface) is 2 .488 Gbits/s while the line rate is 2 .66 Gbits/s . In single STS-192/STM-64 mode, the payload rate is 9.953 Gbits/s while the line rate is 10.66 (10 .7) Gbits/s (stuff) . Any line/system rates that satisfy the 15/14 (255/238) ratio or 85/79 (255/237) are acceptable inputs for the TFEC0410G device . The macro (Figure 4) consists of eight elastic stores (four Tx, four Rx), an FEC/DW frame create/monitor, an FEC/DW-DWAC (digital wrapper access channel) drop/insert block, an RS encoder/decoder, a scram bler/descrambler, an FEC/DW framer block, a byte interleaver, and a byte deinterleaver. DWAC INSERT TRANSMIT SIDE BYTE INTERLEAVE FEC/DW FRAME ELASTIC STORES 4 x 83 MHz OR 4 x 78 MHz TX ES 1 FEC/DW FRAME CREATE, RS ENCODER INS/ SCR I 10G AIS GEN TX ES 2 TX ES ~2$ tilts \V3 TxES4 TO/FROM LINE INTERFACE PRBS INS LB BYTE DLEAVE LB FEC/DW FRAME (OOF, LOF, LOS) DSCR RS DECODER OVERHEAD MONITOR, TO/FROM SONET/SDH OR SYSTEM INTERFACE LB LB Rx ES 1 10G R AIS MON/GEN RS STATS/BER RECEIVE SIDE PRBS MON 4 x 83 MHz DWAC DROP ES 2 ES 3 Rx ES 4 128 bits 4 x 78 MHz 4 x 83 MHz Figure 4. Digital Wrapper and Strong FEC Block Diagram 2 .6.1 Elastic Stores (ES) Four elastic stores per direction are provided to map/demap data to/from the FEC/DW frame format . Each elastic store functions independently in quad mode, while in single mode all four work together. They have no stuffing mechanism to accommodate sustained differences between the incoming and outgoing clocks. This requires the read and write clocks to be locked together using the on-board phase detector outputs (or equivalent circuitry) as inputs to external PLL logic. 14 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) 2.6 Strong FEC (GL975) and Digital Wrapper (OTN) Processing Overview (continued) 2.6.2 RS Encoder/Decoder and Digital Wrapper Basis Frame Format The strong FEC code used to protect the payload/overhead information against transmission errors is a Reed-Solomon code specified in ITU-T/G.975 and 6.709. The RS (255, 239) code block, shown in Figure 5, is a nonbinary code and belongs to the family of systematic linear cyclic block codes . DATA >) 64) )CKS Figure 5. 16-Way (or 64-Way) Interleaved RS (255, 239) Frame (FEC Frame) As can be seen, there is 1 overhead byte, 238 information bytes, and 16 check bytes per RS (255, 239) code block . In order to enhance the immunity of transmission system to the burst errors, 16 (or 64) RS (255, 239) code blocks are interleaved to form a FEC frame . Transmission order is column-by-column, i .e., after 16 (or 64) overhead bytes are transmitted, the first information byte of the second column will be transmitted . There are five different modes of operation, as shown in Table 5. Table 5. Modes of Operation FEC Payload Type Interleaving Depth Overhead Processing Quad 2488 Mbits/s 16 Single 9952 Mbits/s 16 FEC Frame Digital Wrapper (DW) Frame FEC Frame Digital Wrapper (DW) Frame Digital Wrapper (DW) Frame 64 Agere Systems Inc. I 15 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 2.6 Operational Description July 2002 Device Overview (continued) Strong FEC (GL975) and Digital Wrapper (OTN) Processing Overview (continued) In quad 2 .5 Gbits/s mode, the strong FEC macro processes four different 32-bit wide data streams at four different 83 MHz clocks. In 10 Gbits/s mode, the strong FEC macro processes a single 128-bit wide data stream at a single 83 MHz clock . 16-way or 64-way interleaving is programmable in 10 Gbits/s mode, while there is only 16-way interleaving in quad 2 .5 Gbits/s mode. The TFEC041 OG supports the following synchronous G.709 mappings : . (System Interface) CBR2G5 H OPU1 H ODU1 H OTU1 (Line Interface) (STS-48/STM-16, ATM, IP, Ethernet, etc.) . (System Interface) CBR10G H OPU2 H ODU2 H OTU2 (Line Interface) (STS-192/STM-64, ATM, IP, Ethernet, etc. ) The DW frame consists of four FEC frames, and each FEC frame consists of 16-way interleaving RS (255, 239) code blocks, as shown in Figure 6. In 16-way interleaving (dashed arrow), the overhead columns are spaced by 4064 bytes (254 x 16 rows/FEC frame), while in 64-way interleaving (solid arrow), all 64 overhead bytes are consecutively transmitted and repeated after 16256 bytes (4 x [254 x 16]). Each RS block can correct up to eight symbol errors. Therefore, with 16-way interleaving, 1024 (16 interleaving x 8 symbols x 8 bits/symbol) consecutive bit errors can be corrected ; while in 64-way interleaving, 1024 x 4 = 4096 consecutive bit errors can be corrected . The number of bit or block errors and uncorrected blocks are accumulated in saturating counters per stream . This information is used as the raw input to a BER algorithm . When the strong FEC is in digital wrapper mode, overhead definition and processing are different from those in FEC mode. ----------------------------------------OPTICAL CHANNEL OVERHEAD BYTES (64) ----------------------------I ob. . 'N 0H1 "n '. ". 4N(xl6) FEC FRAME #1 PARITY DATA OH2 FEC FRAME #2 PARITY DATA OH3 FEC FRAME #3 PARITY DATA FEC FRAME #4 PARITY DATA OH4 (x64) '(X16) Figure 6. Digital Wrapper-Optical Channel Overhead (16-Way/64-Way Interleaving) 16 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) 2.6 2.6.3 Strong FEC (GL975) and Digital Wrapper (OTN) Processing Overview (continued) FEC Overhead and Digital Wrapper Overhead Definition The entire overhead for both FEC and DW frames is programmable through the digital wrapper access channel (DWAC). This allows flexibility in its definition for future changes in the standards . Internally, 4 bytes can be monitored with continuous N-times detect (CNTD) monitors . These monitors can be combined in four different configurations . They can be grouped as four 1-byte monitors, two 2-byte monitors, one 3-byte and one 1-byte monitor, or one 4-byte monitor. The multiple bytes do not need to be continuous. 4 bytes can be inserted from an internal register per stream . Table 6 summarizes the overhead sources for each byte in the FEC or DW frame. The FEC overhead repeats every FEC frame . The position and location of the framing bytes are provisionable from a minimum of 2 bytes to a maximum of 16 bytes in steps of 2 bytes. All other bytes that have not been assigned as framing bytes can come from the four internal registers for each 2 .5 Gbits/s signal or from the DWAC. Backward error indications (BEI) and status indications (BDI) are provided on-chip . Table 6. FEC/Digital Wrapper Overhead Source 1 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Programmable Framing Bytes (LocationNalue-Internal), and Others from DWAC or Internal Registers (4 Max) Programmable Framing Bytes (LocationNalue-Internal), and Others from DWAC or Internal Registers (4 Max) Programmable Framing Bytes (LocationNalue-Internal), and Others from DWAC or Internal Registers (4 Max) Programmable Framing Bytes (LocationNalue-Internal), and Others from DWAC or Internal Registers (4 Max) 2 3 4 Notes : Any value not from an internal register or the DWAC channel is set to zero . Two (three) BIP-8 calculations are provided over the OPUk and payload bytes only; overhead and check bits are excluded from the calculation. The calculated values can be compared against a selected overhead byte . Errors are accumulated in saturating counters . A possible DW/OTM-0 signal overhead format is defined in Figure 7 on page 18. This format and many others are allowed and created from the internal and DWAC capabilities . Agere Systems Inc. 17 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 Device Overview (continued) 2.6 Strong FEC (GL975) and Digital Wrapper (OTN) Processing Overview (continued) ROW COLUMN 0 0 1 2 3 OTUkOVERHEAD 1516 OTUk PAYLOAD (4 x 3808 bytes) ,' 1 0 OTUk FEC (4 x 256 bytes) 2 3 4 -'----__ 5 FAS 1 RES 2 TCM3 3 I 4079 ROW # 0 FEC FRAME # 3823 GCC1 6 7 MFAS ACT GCC2 SM TCM6 TCM2 -7 8 9 10 11 GCCO TCM5 TCM1 APS/PCC TCM4 PM 12 13 14 15 RES FTFL MAPPING SPECIFIC EX P RES PT Note : Column and row are defined as row and frame, respectively, for register definitions . Figure 7. Possible Overhead Definition for OTUk Signals 2.6.4 FEC/DW-DWAC (Digital Wrapper Access Channel) Drop/Insert Block Four insert digital wrapper access channels (DWACs) are provided on-chip along with four drop DWACs. These channels provide most of the monitoring and insert capability for the FEC/DW overhead bytes. . The insert DWAC consists of the four following signals per channel (for a total of four DW access channels) : -One output clock at -10 .455 MHz (10 Gbits/s mode and quad 2.5 Gbits/s mode) . -One output superframe sync (-326.7 kHz/-81 .68 kHz-10 Gbits/s (FEC/DW), -81 .68 kHz/-20 .42 kHz-quad 2.5 Gbits/s (FEC/DW)) coincident with the MSB (most significant bit) of the first byte in frame 0, output on the rising edge of the clock. A double-wide pulse coincident with bit 6 (2.5 Gbits/s mode) or LSN (10 Gbits/s mode) indicates the corresponding frame contains an MFAS value of zero. -Input data: 4 bits in 10 Gbits/s mode and 1 bit per stream in quad 2.5 Gbits/s mode, sampled on the rising edge of the clock. -Input insert enable signal : active-high signal coincident with the MSB[7]-bit[6] of the byte to insert in quad 2.5 Gbits/s mode or coincident with the MSN and LSN in 10 Gbits/s mode. This is an encoded signal set as follows: -11 = insert DWAC data -00 = default -10 or 01 = pass data from incoming data stream . . The drop DWAC consists of the following three signals per channel (total of four DW access channels) : -One output clock at -10 .455 MHz (10 Gbits/s mode and quad 2.5 Gbits/s mode) . -One output superframe sync (-326.7 kHz/-81 .68 kHz-10 Gbits/s (FEC/DW), -81 .68 kHz/-20 .42 kHz-quad 2.5 Gbits/s (FEC/DW)) coincident with the MSB (most significant bit) of the first byte in frame 0, output on the rising edge of the DWAC clock. -Output data: 4 bits in 10 Gbits/s mode and 1 bit per stream in quad 2.5 Gbits/s mode, samples on the rising edge of the DWAC clock. 18 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) 2.6 Strong FEC (GL975) and Digital Wrapper (OTN) Processing Overview (continued) The data stream format to/from the device is shown in Figure 8. SYNC II ' ENABLE DATA OH1 OH2 OH3 OH4 OH5 OH6 OH7 OH8 OH9 OH10 OH11 OH12 [7 :0] OH13 OH14 OH15 OH16 TRANSMITTED SERIALLY OR NIBBLE WIDE Figure 8. DWAC Frame Definition 2.6.5 Receive/Transmit FEC/DW Framer An alpha/delta framer is provided to find the FEC/DW overhead framing pattern . The following parameters of the framer are programmable through software : - Number of framing pairs . -Framing values (0A1 /0A2). -Number of bytes examined to go in-frame. -Number of bytes examined to go out-of-frame . -Number of consecutive error-free framing patterns to declare in-frame. - Number of consecutive errored framing patterns to declare out-of-frame. The framer will detect a loss-of-frame (LOF) state and LOF parameters are programmable (number of frames to declare and number of frames to clear) . Under software or hardware control, an AIS signal will be generated (all-ones pattern in all overhead except the framing bytes). Data is optionally descrambled (Rx side only) using one of the two possible polynomials (x7 + x + 1 or x16 + x12 + x3 + x + 1) under user control . 2.7 Line Interface-MUX/DeMUX Overview . The line MUX/deMUX allows the three following modes of operation : -One group of 16 bits at 622 .08/666 .51/669 .32 Mbits/s-10 Gbits/s mode -One group of 16 bits at 155/166 Mbits/s-single 2.5 Gbits/s mode - Four groups of 4 bits at 622 .08/666 .51-quad 2 .5 Gbits/s mode. All modes support forward clocking only. These blocks perform parallel-to-parallel conversions from 128 bits H 16 bits, 32 bits H 16 bits, or 32 bits H 4 bits, respectively. Facility loopback and terminal loopback capabilities are provided at this interface for diagnostic purposes . This interface can run at other clock rates as long as the 15/14 (255/237) ratio between the system clock and line clock is maintained. Agere Systems Inc. 19 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 Operational Description July 2002 Device Overview (continued) 2.8 Alarm Status Output Signals Overview The status of the internal LOC, OOF, LOF, and LOS monitors per 2 .5 Gbits/s slice are accessible on eight external transmit and eight external receive pins (16 total-GPIO[15 :0]). The specified alarm output on each pin is programmable under software control . These outputs allow automatic actions to occur during certain failure conditions . (See the TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Hardware Register Map document for more information .) 2.9 Microprocessor Interface Overview The TFEC041 OG microprocessor interface architecture is configured for glueless interface to the Motorola(c) MPC860 and MC68360 microprocessors. The Intel (c) microcontrollers 8XC251 and 80C196 and the i960 microprocessor may also be utilized to interface to the TFEC0410G. However, provisions on the board need to be made to (de)multiplex the address and data bus . The state of the MPTYPE_IM input signal indicates to the device whether it interfaces to a Motorola microprocessor or an Intel microcontroller. Other microprocessors may be used if their timing requirements fit to one of the modes described . The TFEC041 OG has separate 16-bit wide address and data busses . The MPDB 8_16 input distinguishes between an 8-bit or 16-bit wide microprocessor data bus being used. In case of an 8-bit wide microprocessor data bus interface, the eight upper bits of the device data bus ports are not being used and are held 3-state . The microprocessor interface operates at the frequency of the microprocessor clock (PCLK) input which should be in the range of 10 MHz to 100 MHz . All internal counters are latched using an external or internal PM latch pulse that must occur once per second (programmable) to ensure all internal counters do not saturate. 2.9.1 Transfer Error Acknowledge (TEA N) (with MPC860 and MC68360 Only) The TFEC0410G contains a bus time-out counter. When this counter saturates, a bus error is generated to the external processor through the transfer error acknowledge (TEA N) signal . This feature must be considered with respect to the external ability of the processor to generate its own internal bus time-out. TEA_N will be asserted if an internal data acknowledgment is not received within 32 PCLK periods . This interval is used since all valid internal accesses to the device will be completed in significantly less than 32 PCLK periods . TEA_N is also asserted if the calculated parity value does not match the parity generated by the external microprocessor on a data transfer. 2.9.2 Interrupt Structure The interrupt structure of the TFEC0410G minimizes the effort for software/firmware to isolate the interrupt source. The interrupt structure is comprised of different registers depending on the consolidation level . At the lowest level (source level), there are two registers . The first is an alarm register (AR). An alarm register is typically of the write 1 clear (W1 C) type. The second is an interrupt mask (IM) register of the read/write (R/W) type. An alarm register latches a raw status alarm. This latched alarm may contribute to an interrupt if its corresponding interrupt mask bit is disabled . Individual latched alarms are consolidated into an interrupt status register (ISR) . If any of the latched alarms that are consolidated into a bit of an ISR are set and unmasked, the ISR bit is set . The ISR bit may contribute to an interrupt if its corresponding interrupt mask bit is disabled . ISRs may be consolidated into a higher-level ISR in a similar fashion until all alarms are consolidated into the chip-level ISR . The alarm register that causes an interrupt can be determined by traversing the tree of ISRs, starting at the chip-level ISR, until the source alarm is found. Note : Interrupts are disabled when the corresponding bit in the mask register is 0. If the mask register bit is 1, the interrupt is enabled. Two levels of alarms are provided : a high-interrupt output and a low-interrupt output from the device . 20 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 2 with Strong/Weak FEC and Digital Wrapper Device Overview (continued) 2.10 Clocking Overview The following diagrams show simplified pictures of the major clock domains within the TFEC041 OG in quad 2.5 Gbits/s and 10 Gbits/s strong/digital wrapper/weak SONET/SDH mode. In 10 Gbits/s mode, each block has one clock domain for a total of four transmission clocks along with one microprocessor clock . o i 590 r, WQ } OI OI ?n 1 UI LINE SIDE 0000 ~ _ o~I Z 0 Y Q W U U U UI J 0 0 0 0 SYSTEM SIDE :15 LINE INTERFACE FEGDW (RS) I Ft PHASE DET. ' 14 TX SYSTEM INTERFACE ES TCLKL0_[1-4] TDLO 413 :0] TDLO 313 :0] ~I > J I Tx SONET/SDH/BCH TDSI 43:0] TDSI 313:0] TDSI 2_[3:0] TDSI 1_[3:0] TCLKSI-[1-4] TDLO 213 :0] TDLO 113 :0] RDLI 4_[3 :0] Rx SONET/SDH/BCH ES BOF RDLI 33 :0] RDLI 2_[3 :0] RDLI 1_[3 :0] RXREF0_[1-4] RCLKLI-[1-4] RX SYSTEM INTERFACE RCLKS0-[1-4] RDSO RDSO RDSO RDSO i 4 up C~ 4[3 :0] 313 :0] 2_[3 :0] 13 :0] PHASE DET I 000 U}Q ~I 0of UI3:3 : OO I Y I _ . Y O I UI a UI ~ O U a a ~I O U O _y I d uil EL =I w 2 Ir Note : There are a total of 16 different transmission clocks and 1 microprocessor clock. Figure 9. Quad 2.5 Gbits/s Clocking Overview-Terminal Mode Agere Systems Inc. 21 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 2 Device Overview (continued) 2.10 Clocking Overview (continued) 0 ZHZ Y 01 O1 LINE SIDE ~ni 01 0000 LINE INTERFACE FEGDW (RS) J J d F- U U UU 0 0 0 o ~ F- SYSTEM SIDE ~85 OR :15 PHASE DET. . -79 OR :94 -Q TX SYSTEM INTERFACE ES TCLKL0-[1 ] (0 (0 EL EL Q W } J O O !A U ~ Tx SONET/SDH/BCH .--,- TDSI_[15 :0] TDL0_[15:0] TCLKSI[1] Rx SONET/SDH/BCH ES RDLI115:0] RX SYSTEM INTERFACE RCLKS0J1] RXREF0_[1] RDS0_[15 :0] RCLKLI-[1] 111 I~ 1 1 1 ITT TT2 z of C1of Cl OUQ ~IOI of U U Q O U a 0< -85 OR : 95 PHASE DET. '.790R .14 1 1 O d 71 ILK m :~EL f EL O H Note : There are a total of 4 different transmission clocks and 1 microprocessor clock . Figure 10. 10 Gbits/s Clocking Overview-Terminal Mode 22 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 3 with Strong/Weak FEC and Digital Wrapper Block Diagrams LINE SIDE DIGITAL WRAPPER OCH/STRONG FEC WITH OPTICAL CHANNEL/FRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 10.7 (9.953) Gbits/s OR QUAD 2 .66 (2.488) Gbits/s 10.7 (9.953) Gbits/s OR QUAD 2 .66 (2.488) Gbits/s I~ I RS INTERLEAVE HFNrnr OTN OH/ FRAME INSERT SONET/ FEC/DW I FRAM ERA DI-~N DE-INT OTN OH OONITOF SONET/ SDH I D rr SYSTEM SIDE SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) SDH BCH OH INSERT RX 9 .953 (10 .7) Gbits/s OR QUAD 2'488 (2 .66) Gbits/s TX I BCH-3 SONET/ I SDH FRAMER BCH DECODE/ r+noo~r+r I 9 .953 (10 .7) Gbits/s OR QUAD 2 .488 (2 .66) Gbits/s SON ET/ RS STATS I OTN STATS JBCH STATS uINSERT MICROPROCESSOR INTERFACE AND CONTROL SDH SECTION/ LINE MONITORING I Figure 11 . TFEC041OG Block Diagram STRONG FEC WITH FRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 10 .7 Gbits/s OR QUAD 2.66 Gbits/s 10 .7 Gbits/s OR QUAD 2.66 Gbits/s RS ENCODER TERLEAVE FEC FRAMER AND DE-INT H RS DECODE AND CORRECT RS STATS SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) OH/ FRAM E OH MONITOR 9.953 Gbits/s OR QUAD 2.488 Gbits/s 9.953 Gbits/s OR QUAD 2 .488 Gbits/s FRAME STATS MICROPROCESSOR INTERFACE AND CONTROL Figure 12. Strong FEC Application : Terminal Agere Systems Inc. 23 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 3 Operational Description July 2002 Block Diagrams (continued) STRONG FEC WITH FRAME SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) OVERHEAD PROCESSING (RS OUT-OF-BAND) 10 .7 Gbits/s OR QUAD 2.66 Gbits/s r-----, _ I I I 10 .7 Gbits/s I I OR QUAD 2.66 Gbits/s I RS FEC FRAMER A DE-INT D ,FE OH' rSERT 5H RS STATS I I JFSO- N ET/L SONET/ SDH SECTION/ LINE STATS MICROPROCESSOR INTERFACE AND CONTROL I Figure 13. Strong FEC Application : Regenerator (SONET/SDH Section Monitoring Possible) DIGITAL WRAPPER OCH WTH OPTICAL CHANNEL OVERHEAD PROCESSING (RS OUT-OF-BAND) 10 .7 Gbits/s OR QUAD 2.66 Gbits/s INTERLEAVE 10 .7 Gbits/s OR QUAD 2.66 Gbits/s DW FRAMER AND DE-INT I I RS ENCODER H I RS DECODE AND CORRECT IRS STATS I SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) OTN OH/ FRAME I NSERT 9. 953 Gbits/s OR QUAD 2. 488 Gbits/s OTN OH MONITOR 9. 953 Gbits/s OR QUAD 2. 488 Gbits/s STANS MICROPROCESSOR INTERFACE AND CONTROL I Figure 14. Digital Wrapper (OCh) Application : OTN Adapter 24 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 3 with Strong/Weak FEC and Digital Wrapper Block Diagrams (continued) DIGITAL WRAPPER OCH WITH OPTICAL CHANNEL OVERHEAD PROCESSING (RS OUT-OF-BAND) 10 .7 Gbits/s OR QUAD 2 .66 Gbfs/s 10 .7 Gbits/s OR QUAD 2 .66 Gbfs/s H OTIN OH/ FRAME INSERT RS ENCODER INTERLEAVE iiiEl DW FRAMER AND DE-INT SONET/SDH WITH WEAK FEC H 9.953 Gbits/s OR QUAD 2.488 Gbits/s OR RS DECODE OTIN OH AND MONITOR CORRECT IIM OTN TATS 10 .7 Gbits/s OR QUAD 2 .66 Gbits/s OTN SSTATS MICROPROCESSOR INTERFACE AND CONTROL rigure iu. uignai vvrapper kva.n) Hppucanvn : v I IN Regenerator DIGITAL WRAPPER OCH/STRONG FEC WITH OPTICAL CHANNEUFRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 10.7 Gbfs/s OR QUAD 2.66 Gbfs/s INTERLEAVE 10.7 Gbfs/s OR QUAD 2.66 Gbfs/s FEC/DW FRAMER AND DE-INT RS ENCODER FRAMER AND FRAME INSERT RS DECODE AND k CORRECT OTN OH MONITOR RS STATS SONET/SDH WITH WEAK FEC BCH-3 IN-BAND () D.7 Gbits/s OR QUAD 66 Gbfs/s 0 .7 Gbits/s OR QUAD .66 Gbits/s OTN STATS MICROPROCESSOR INTERFACE AND CONTROL Figure 16. Strong FEC or Digital Wrapper (OCh) with Strong FEC : Bidirectional Mode DIGITAL WRAPPER OCH/STRONG FEC WITH OPTICAL CHANNEUFRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 9.953 Gbits/s OR QUAD 2.488 Gbits/s SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) 9 .953 Gbits/s OR QUAD 2.488 Gbits/s SONETI TX SONETI BCH-3 11CH SDH OH SDH INSERT 1 ""~ FRAMER RX SONETI SDH FRAMER 9.953 Gbits/s OR QUAD 2.488 Gbits/s E I BCH DECODE/ CORRECT BCH STATS 53 Gbits/s OR UAD 2488 Gbits/s 99 SONETI SDH SECTION/ LINE MICROPROCESSOR INTERFACE AND CONTROL I Figure 17. Weak FEC Application : SONET/SDH Terminal Agere Systems Inc. 25 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 3 Block Diagrams (continued) DIGITAL WRAPPER OCH/STRONG FEC WITH OPTICAL CHANNEUFRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 9.953 Gbits/s OR QUAD 2.488 Gbits/s SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) SONET/ SDH BCH OH INSERT SO NET/ SDH 9.953 Gbits/s OR QUAD 2.488 Gbits/s TX SONET/ SDH FRAMEF BCH-3 9.953 Gbits/s OR QUAD 2.488 Gbits/s BCH DECODE/ BCH STATS I MICROPROCESSOR INTERFACE AND CONTROL I Figure 18. Weak FEC Application : SONET/SDH Regenerator STRONG FEC WITH FRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 10 .7 Gbits/s OR QUAD 2 .66 Gbits/s INTERLEAVE 10 .7 Gbits/s OR QUAD 2 .66 Gbits/s I FEC FRAMER AN DE-INT I _ RS ENCODER DECODE AND CORRECT RS STATS I I SONET/SDH WITH WEAK FEC (BCH-3 IN-BAN D) OH/ FRAME INSERT OH MONITOR SONET/ SDH BCH OH INSERT I SONET/ SDH FRAMER u BCH DECODE/ CORRECT FRAME STATS MICROPROCESSOR INTERFACE AND CONTROL BCH-3 BCH STATS I 9 .953 Gbits/s OR QUAD 2 .488 Gbits/s TX SONET/ SDH FRAMER 9 .953 Gbits/s OR QUAD 2 .488 Gbits/s SONET/ SDH SECTION/ LINE MONITORING I Figure 19. Strong/Weak FEC Application : SONET/SDH Terminal 26 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 3 with Strong/Weak FEC and Digital Wrapper Block Diagrams (continued) STRONG FEC WITH FRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 0 7 6btsl 0.7 Gbits/s OR QUAD 2.66 Gbits/s INTERLEAVE RS ENCODER FEC IRS DECO E FRAMER AND . OR QUAD 2.66 Gbits/s N DE-INT CORR OH/ FRAME INSERT SONET/ SDH BCH OH INSERT RX TOR T DEEC D' MO ON 0H OH NIT TOR RS STATS SONETI SDH FRAMER FRAME 'TATS BCH-3 BCH DECODE/ CORRECT TX SONET/ SDH FRAMER 9 .953 Gbits/s OR QUAD 2 .488 Gbits/s SDH 'M BCH ff SSONET' 0 T1 STATS LINE MICROPROCESSOR INTERFACE AND CONTROL I S-ECT"'ONI SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) I Figure 20. Strong/Weak FEC Application : SONET/SDH Regenerator SONET/SDH WITH WEAK FEC (BCH-3 IN-BAN D) WITH OPTICAL CHANNEL OVERHEAD PROCESSING (RS OUT-OF-BAND) 10 .7 Gbits/s OR QUAD 2 .66 Gbits/s INTERLEAVE RS ENCODER DW DECODE FRAMER AN DE-INT 10 .7 Gbits/s OR QUAD 2 .66 Gbits/s IRS OTN OH RX SONET/ SDH CORRECT RS STATS I _ OTN OHM FRAME INSERT SONET/ SD H BCH OH INSERT OTN STATS MICROPROCESSOR INTERFACE AND CONTROL BCH-3 ~J 9 .953 Gbits/s OR QUAD 2 .488 Gbits/s TX SONET/ SDH FRAMER BCH DECODE/ BCH STATS 1 SAT, SECTION/ NE 9 .953 Gbits/s O R QUAD 88 Gbis/s I Figure 21 . Digital Wrapper (OCh)/Weak FEC : OTN with SONET/SDH Termination Agere Systems Inc. 27 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 3 Block Diagrams (continued) SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) WITH OPTICAL CHANNEUFRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) 10 .7 Gbits/s OR 9.953 Gbits/s 10 .7 Gbits/s OR 9.953 Gbits/s INTERLEAVE RS ENCODER OTN OH/ FRAME INSERT SDH :BH SONET' INSERT C OH FEC/DW FRAMER AND DE-INT DECODE AND CORRECT OTN OH MONITOR 0Or RX NETI X SSDH : FRAMER SS T1 IRS STATS I I OTN I STATS BCH-3 I*- TX QUAD SONETI -2.488 Gbits/s SDH : FRAMER + BCH DECODE/ CORRECT BCH STATS QUAD 2 .488 Gbits/s SONET/ SDH SECTION/ I LINE MICROPROCESSOR INTERFACE AND CONTROL I Figure 22. Asymmetric Multiplex Mode: SONET/SDH Terminal with/without Strong/Weak FEC SONET/SDH WITH WEAK FEC (BCH-3 IN-BAND) DIGITAL WRAPPER OCH/STRONG FEC WITH OPTICAL CHANNEUFRAME OVERHEAD PROCESSING (RS OUT-OF-BAND) SINGLE 2 .488/2.66 Gbits/s OTN OH/ FRAME INSERT SONET/ SDH BCH OH INSERT _~ BCH-3 ~ I I SON ET/ SDH FRAMER BCH DECODE/ CORRECT (16 bits) INTERLEAVE RS ENCODER (16 bits) FEC/DW FRAMER AND DE-INT RS OTN OH DECODE AND MONITOR CORRECT SINGLE 2 .488/2.66 Gbits/s STATS I IRS I I SA"S MICROPROCESSOR INTERFACE AND CONTROL BCH STATS _ SINGLE 2'488/2'66 Gbits/s TX SONET/ SDH FRAMER (16 bits) (16 bits) SINGLE 2.488/2 .66 Gbits/s T/ S SDH SECTION/ LINE I Figure 23. Single 2.5 Gbits/s Mode: SONET/SDH, Terminal/Regenerator, with Strong or Weak FEC 28 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 4 4.1 with Strong/Weak FEC and Digital Wrapper Top-Level Overview Top-Level Functionality The top-level block outlines the following functionality in detail : . Top-level clock and data MUXes (Section 4.2) . . Loss-of-clock detectors (LOC) (Section 4.3 on page 31) . . Reset architecture (hardware/software) (Section 4.4 on page 32). . Loopback controls (Section 4.5 on page 33) . . Powerdown control functionality (Section 4.6 on page 33) . . Phase detectors (Section 4.7 on page 34) . . Line timing reference signal generation (Section 4.8 on page 35) . . Alarm status output signals through GPIO pins (Section 4.9 on page 36). 4.2 Top-Level Clocking Figure 24, Top-Level Clock and Datapath Overview (1 of 4 Slices), on page 30 shows a detailed picture of the major clock domains and datapaths within the TFEC0410G in quad 2 .5 Gbits/s strong/digital wrapper/weak SONET/SDH mode. In 10 Gbits/s mode, each block only has one clock domain for a total of four transmission clocks in addition to one microprocessor clock . Agere Systems Inc. 29 AdLib OCR Evaluation CD m O7 4 4.2 Top-Level Overview (continued) Top-Level Clocking (continued) SYSTEM SIDE N O -' NO 7 v N n N C1 rr O 7 TDSI-[1-4L[3 :0] TCLKSII1-4] m n O RDS011-4Lr3 :a1 RCLKS011-4] O0 G N rt O SL (q O rtC) O a 7 ~D 0 ,n 5 m_ Iv RCLKSI[1-4] CLOCK MULTIPLEXERS: (A) LINE TX-HS CLKMUX (B) LINE TX LS CLKMUX (C) LINE TXDWFEC CLKMUX (D) SYS TX_DWFEC CLKMUX (E) SYS TX SONFECCLKMUX (F) LINE RX DWFEC CLKMUX (G) SYS RXDWFEC CLKMUX (H) SYS RX_SONFECCLKMUX (I) SYS RXLS CLKMUX (J) SYSR)~_ HSCLKMUX o DATA MULTIPLEXERS : (K) LINE TX DMUX (L) DWFEC TX_DMUX (M)SONFEC TX DMUX (N) SONFEC RX DMUX (0)SONFECRX-BYP DMUX (P) SYS RX DMUX CLOCK SIGNALS: (1) LINE TX HSCLK (2) LINE TX LSCLK (3) LINE TX83CLK (4) DWFEC TX78CLK (5)SONFEC TX78CLK (6) LINE RX83CLK (7) DWFEC RX78CLK (8) SYS RX78CLK (9) SYSRX LSCLK (10) SYS RX HSCLK DATA SIGNALS: (11)LINE TXDATAO[127:0] (12) SONFEC-TXDATAO[l27 :0] (13) DWFEC TXDATAO[127:0] (14) DWFECTXDATAI[127 :0] (15) SYS TXDATAI[127:0] (16) SONFEC TXDATAI[127:0] (18) LINE RXDATAI[127:0] (19) DWFEC RXDATAO[127:0] (20) SONFEC RXDATAI[127:0] Figure 24. Top-Level Clock and Datapath Overview (1 of 4 Slices) (21) DWFEC RX83DATA[127 :0] (22) SONFECRXBYPDATA[127:0] (23) SONFEC RXDATAO[127:0] (24) SYS RXDATAO[127:0] nz 7 Q. 00 O (Q n AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 4 4.3 with Strong/Weak FEC and Digital Wrapper Top-Level Overview (continued) Top-Level Loss-of-Clock Detectors All high-speed input clocks have loss-of-clock (LOC) detectors . These detectors use the microprocessor clock as a reference and will not declare LOC if the MPU clock is lost. These detectors check for activity on the monitored signal . If the MPU clock is lost, the detectors will clear their LOC state and will not activate the respective LOC indicator until the MPU clock recovers . Table 7. Loss of Clock Registers Function Register Name (First Occurrence) Register Bits Qty., LOC Interrupt Alarm DEV LOC ALARM SO (W1 C) DEV LOC LINE TXCLK A DEV LOC LINE RXCLK A DEV LOC SYS TXCLK A DEV LOC SYS RXCLK A 4 4 0x14 0x14 DEV LOC LINE TXCLK M DEV LOC LINE RXCLK M 4 4 0x43 0x43 DEV LOC SYS TXCLK M DEV LOC SYS RXCLK M DEV LOC LINE TXCLK P DEV LOC LINE RXCLK P DEV LOC SYS TXCLK P 4 4 4 0x43 0x43 LOC Alarm Mask LOC Persistency LOC State DEV LOC MASK SO (R/W) DEV LOC PERSIST SO (RO) DEV LOC STATE SO (RO) 4 4 4 4 1st Addr2 (hex) 0x14 0x14 0x70 0x70 0x70 0x70 DEV LOC SYS RXCLK P DEV LOC LINE TXCLK 4 4 DEV LOC LINE RXCLK 4 0x90 0x90 DEV LOC SYS TXCLK DEV LOC SYS RXCLK 4 4 0x90 0x90 1 . Qty. refers to the number of registers that are similar to the one shown in the table . There maybe more registers to control different channels, or several registers of similar type used for a particular function . 2. 1st Addr (hex) refers to the address (in hex) of the first occurrence of this type of register. Agere Systems Inc. 31 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 4 4.4 Operational Description July 2002 Top-Level Overview (continued) Top-Level Reset Architecture (Hardware/Software) All slices are reset when the external reset signal is asserted . The device will not exit the reset state until a clock is provided to the MACRO block. The reset monitor registers indicate the reset status of each block. The datapath of each slice can be individually reset through a software register. In 10 Gbits/s mode, all slice resets must be written . The MPU blocks within the SONFEC supermacro and the DWFEC supermacro can be reset independently through software control . Table 8. Software Reset Registers Function MPU Reset Register Name (First Occurrence) Register Bits Qty. DEV MPUREG SWRST (R/W) DEV DWFEC MPU SWRST DEV_SONFEC_MPU_SWRST DEV_MPU_REG_SWRST DEV DWFEC DAT SWRST DEV_SONFEC_DAT_SWRST DWFEC_RX_RST_MON_S3 DWFEC RX RST MON S2 DWFEC_RX_RST_MON_S1 DWFEC_RX_RST_MON_SO DWFEC TX RST MON S3 DWFEC_TX_RST_MON_S2 DWFEC_TX_RST_MON_S1 DWFEC TX RST MON SO RX_RST_MON_S3 RX_RST_MON_S2 RX RST MON S1 RX_RST_MON_SO TX_RST_MON_S3 TX RST MON S2 TX_RST_MON_S1 TX RST MON SO 1 1 1 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Datapath Reset DEV DP SWRST SO (R/W) DWFEC Reset Monitor DWFEC RST_MON (RO) SONFEC Reset Monitor SONFEC RST MON (RO) 32 1st Addr (hex) 0x300 0x300 0x300 0x301 0x301 0x2001 0x2001 0x2001 0x2001 0x2001 0x2001 0x2001 0x2001 0x1001 Ox 1001 0x1001 Ox 1001 Ox 1001 0x1001 Ox 1001 0x1001 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 4 4.5 with Strong/Weak FEC and Digital Wrapper Top-Level Overview (continued) Top-Level Loopback Control Signals All loopback control signals are generated from the top MPU block (see Section 38, Microprocessor Interface, on page 167 for more details). Some loopback configurations are controlled by the internal data MUXes . Table 9. Loopback Control Signals Function Loopback Control 4.6 Register Name (First Occurrence) Register Bits Qty. 1 st Addr (hex) DEV CTL LPBK SO (R/W) DEV RSYS2TSYS LB DEV TLINE2RLINE LB DEV RDW2TDW LB DEV_TDW2RDW_LB DEV TRSEN2RRSDE LB 4 4 4 4 4 OxB0 OxB0 OxB0 OxB0 OxB0 Top-Level Powerup Control Registers The device allows the powerup of all LVDS and 3-statable input/output buffers on a per 2.5 Gbits/s basis through software control registers . The MPU clock to the SONFEC and DWFEC blocks can be inhibited. All I/O and transmission paths are in the powerdown state upon hardware and MPU software resets . Table 10. Powerup Control Registers Function Clock Inputs Data and Frame Inputs Output Data Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) DEV_PDN CLKIN SO (R/W) DEV_RCLKSI_PDN DEV RCLKLI PDN DEV_TCLKLI_PDN DEV_TCLKSI_PDN DEV TFRMLI PDN DEV TDSI PDN DEV_RDLI_PDN DEV TCLKLO PDN DEV_TDLO_PDN DEV_RCLKSO_PDN DEV RDSO PDN DEV_TTOAC_PDN DEV_RTOAC_CS_PDN DEV RTOAC DAT PDN DEV_RDW_CS_PDN DEV_RDW_DATO_PDN DEV TDW CS PDN DEV_DWFEC_PCLK_PDN DEV SONFEC PCLK PDN 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 1 0x160 0x160 0x160 0x160 0x164 0x164 0x164 0x168 0x168 0x168 0x168 0x16D 0x16D 0x16D 0x171 0x171 0x171 0x16C 0x16C DEV PDN IN S0 (R/W) DEV PDN OUT S0 (R/W) TOAC Clock/Sync/Data DEV_PDN TOACO S0 (R/W) DWAC Clock/Sync/Data DEV_PDN DWACO S0 (R/W) SONFEC/DWFEC MPU Powerup Agere Systems Inc. DEV_PDN ICLK (R/W) 33 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 4 4.7 Top-Level Overview (continued) Top-Level Phase Detectors The internal phase detector generates PUMP-UP and PUMP DN signals for locking the Tx 666/669 MHz line clock to the Tx 622 MHz system clock with external elements such as VCO and LPF (locking the Rx 622 MHz system clock to the Rx 666/669 MHz line clock) . For various applications, reference clock (REF-CLK) and variable clock (VAR-CLK) can be selected out of any four clocks : TCLKLI, TCLKSI, RCLKLI, and RCLKSI . Output polarity (PUMP UP, PUMP DN) can be controlled by software . 4.7.1 PD Engine The flip-flop based phase detector (PD) of the TFEC is used to detect the phase difference. The PD's detecting range is -2pi - +2pi. In its initial state, both flip-flops are cleared by RESETN, which is active-low. If REF-PHS is leading VAR PHS, then the up pulse is output until VAR-PHS's rising edge is received . This will result in making VAR CLK faster. If REF PHS is lagging VAR PHS, then the down pulse is output until VAR-PHS's rising edge is received . This will result in making VAR CLKslower. A timing diagram is shown in Figure 25. REF PHS VAR PHS UP DN Figure 25. Timing Diagram of Phase Detector Table 11 . Phase Detector Control Registers Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) Phase Detector Receive Direction Control Registers DEV_CTL_RX_PHDET-S0 (R/W) Phase Detector Transmit Direction Control Registers DEV_CTL_TX_PHDET-S0 (R/W) DEV-PHDET-RX-POL DEV-PHDET-RX-VARDIV DEV-PHDET-RX-REFDIV DEV-PHDET-RX-VARSEL DEV PHDET RX REFSEL DEV-PHDET-TX-POL DEV-PHDET-TX-VARDIV DEV PHDET TX REFDIV DEV-PHDET-TX-VARSEL DEV PHDET TX REFSEL 4 4 4 4 4 4 4 4 4 4 OxCC OxCC OxCC OxCC OxCC OxDO OxDO OxDO OxDO OxDO 34 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 4 4.8 with Strong/Weak FEC and Digital Wrapper Top-Level Overview (continued) Top-Level Line Timing Signal Reference One external pin per 2.5 Gbits/s interface is provided for line timing reference purposes (RXREFO[4-1]) . The source of these outputs is user controllable. The choices are summarized as follows : . Free-running 50% duty cycle at 8 kHz sync (toggle output after 4860 clock cycles) derived from the RCLKLI[4-1] input clocks. . Free-running 50% duty cycle at 8 kHz sync (toggle output after 5207 clock cycles) derived from the RCLKSI[4-1] input clocks . The reference signals are 8 kHz only with 622/666/669 MHz input clocks. Table 12. Line Timing Reference Select Register Function Line Timing Reference Agere Systems Inc. Register Name (First Occurrence) I DEV LTIM REF SEL SO (R/W) Register Bits I DEV LTIM REF SEL Qty. I 4 1st Addr (hex) I OxDC 35 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 4 4.9 Top-Level Overview (continued) Top-Level Alarm Status Output Signals (Through GPIO) Sixteen signals are provided, one per 2 .5 Gbits/s interface per transmit and receive direction accessible through the GPIO[15 :0] signals . The output of these signals is the ORing of the following alarms with their associated inhibit bits. The equations are summarized as follow : . RX_DW_ALM[4-1] = DEV LOC_LINE_RXCLK and NOT DEV_DWFEC RX_LOC INH or FRM_RXLOS and NOT DEV_DWFEC_RX_LOS_INH or FRM_RXOOF and NOT DEV_DWFEC_RX_OOF_INH or FRM RXLOF and NOT DEV DWFEC RX LOF INH . RX_SON_ALM[4-1] = DEV LOC_SYS_RXCLK and NOT DEV_SONFEC_RX_LOC INH or RX_LOS and NOT DEV_SONFEC_RX_LOS_INH or RX_SEF and NOT DEV_SONFEC_RX_OOF_INH or RX LOF and NOT DEV SONFEC RX LOF INH . TX_DW_ALM[4-1] = DEV LOC_LINE _TXCLK and NOT DEV_DWFEC_TX_LOC INH or FRM_TXLOS and NOT DEV_DWFEC_TX_LOS_INH or FRM_TXOOF and NOT DEV_DWFEC_TX_OOF_INH or FRM TXLOF and NOT DEV DWFEC TX LOF INH . TX-SON_ALM[4-1] = DEV LOC_SYS_TXCLK and NOT DEV_SONFEC_TX_LOC_INH or TX-LOS and NOT DEV_SONFEC_TX_LOS_INH or TX_SEF and NOT DEV_SONFEC_TX_OOF_INH or TX LOF and NOT DEV SONFEC TX LOF INH Table 13. Receive/Transmit Alarm Inhibit Registers Function Register Name (First Occurrence) Register Bits Qty. Receive Direction Alarm Inhibit Registers DEV_RX_ALRMSTAT_INH_SO (R/W) Transmit Direction Alarm Inhibit Registers DEV_TX_ALRMSTAT_INH_SO (R/W) DEV_DWFEC_RX_LOS_INH DEV_DWFEC_RX_LOF_INH DEV_DWFEC_RX_OOF_INH DEV DWFEC RX LOC INH DEV_SONFEC_RX_LOS_INH DEV_SONFEC_RX_LOF_INH DEV SONFEC RX OOF INH DEV_SONFEC_RX_LOC_INH DEV_DWFEC_TX_LOS_INH DEV_DWFEC_TX_LOF_INH DEV_DWFEC_TX_OOF_INH DEV DWFEC TX LOC INH DEV_SONFEC_TX_LOS_INH DEV_SONFEC_TX_LOF_INH DEV SONFEC TX OOF INH DEV SONFEC TX LOC INH 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 36 1st Addr (hex) OxD4 OxD4 OxD4 OxD4 OxD4 OxD4 OxD4 OxD4 OxD8 OxD8 OxD8 OxD8 OxD8 OxD8 0 D8 OxD8 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 5.1 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro Strong FEC Introduction This section provides the functional description of the strong FEC supermacro core: out-of-band . The functional description includes requirements that must be met, as derived from various specifications . The strong FEC supermacro core consists of the following : . Elastic store (78 MHz H 83 MHz) [ES] macro . . Digital wrapper with optical channel overhead processing [DW] macro. . Reed-Solomon (RS) macro. . FEC/DW framer (FRM) macro . . PRBS insert and monitor (PRBS) macro. . Byte interleave and deinterleave (INTLV) macro . This section contains the specifications and requirements for strong forward error correction (FEC). Agere Systems Inc. 37 AdLib OCR Evaluation 5 5.2 3 V1 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) Functional Description of Strong FEC The structure of strong FEC supermacro is shown in Figure 26. TOP_DWAC_TXDATA_EN[3:0] TOP_DWAC TXDATA[3:0] DWFEC_DWAC_TXCLKO[3:0] DWFEC_DWAC_TXSYNCr3:0] = Im LINE SIDE SYSTEM SIDE a LINE TX83CLK[3 :0] SYS TX78CLKr3:0] PRBS MON&INS PRBS(TX) LINE TX83RSTN[3 :0] DSPIFO (FROM OTUS) LINE TX83LOC[3:0] PRBSSPIF MPUMETA SYS TX78RSTN[3:0] SYS TX78ERSTN[3:0] FRAMER F F 1) FRM_DW_ TmATA[127:01 DW_TXSYNC[3:0] DIGITAL DWFEC_LINE TXDATA[127 :0] Is M RS_INTLV_TmATA[127:0] y IRS INTLV T)(SYNC[3:0] IFORIT NSE ONNL 'OR E' L y~ST I ;a K m M REEDSOLOMON ENCODER DW_RS_TXDATA[127:0] -DW IRS T)(SYNC[3:0] WIPER WITH OPTICAL CHANNEL OVERHEAD PROCESSING M INTLV(Tx) C M 10 DW ES TXn0kTA EN[3:0] DW ES TXSYNC[3:0] DWFEC RX83LOF[3 :0] AIS MONITOR N FRM:FAIWRE CONDITION (OOF/LOFILOS) R FECIDW FIRMRS RXDATN127 :0j FRAMER FIRM IRS RXSYNC[3:0] LINE-RX83CLKr3-.01 LINE RX83RSTN[3 :0] FRM(R~) DECODER 00% EW~T ?~T P2 DETECT DIGI WRAPPE 'ER WITH )PTICAL AIS CHANNEL TAL INS OVERHEAD P CESSING S. DW RXnOkTN127-.01 RS~DVVRXSYNC[3 :01 ,, 0 Om C ;0 z i DW( p VV_ESLRXDATA[127:0] DW_ESLRXDATAEN[3:01 LASTIC STO RE WFEC SONFEC RXDATA[ 127:0] 6 DVVES~R)(SYNC[3:0] IES(R~) SYS RX78CLIq3-.01 P) (PM_CL1C) SYS_RX78RSTN[3 :0] y MPUDW_RX_ESSYS[3:0] DWFEC_SYS_RX83DATA[127 :0] DWFEC_DWAC_RXCLKO[3 :0] DWFEC_DWAC_RXDATA[3:0] DWFEC_DWAC_RXSYNC[3 :0] Figure 26. Strong FEC Supermacro 00 AJSALARM CONDITION RSRX) LINE RX83ERSTNr3:0] w C C Faflum ODWition (OOF/LOF/LOS/LOC) a INTLV(Rx) DWFEC RX83LOSr3:0] LINE DWFECLRYDATA[127 :01 ES(TX) I LINE R)(83LOC[3-.01 DWFEC R)(830OF[3 :0] SONFEC_DWFEC_TXDATA[127:0] ES DW TXSYNCr3-.01 DW(Tx) K T Ic ELASTIC ES_DW_TXDATA[127:0] AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 with Strong/Weak FEC and Digital Wrapper 5.2 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.2.1 Functional Description of Strong FEC (continued) Strong FEC Mode Description All the strong forward error correction (FEC) code out-of-band features are supported in digital wrapper mode equipped with overhead byte insertion and monitor. The strong FEC code, used to protect the payload/overhead information against transmission errors, is a Reed-Solomon code specified in ITU-T/G.975: RS (255, 239). There is 1 overhead byte, 238 infomation bytes (payload and fix stuff), and 16 check bytes per RS (255, 239) code block. The 16 (or 64) RS (255, 239) code blocks are interleaved to form an FEC frame. Transmission order is column-by-column, i.e., after 16 (or 64) overhead bytes are transmitted, then the first information byte of the second column will be transmitted . The Reed-Solomon (RS) macro performs out-of-band forward error correction. The encoder generates check bytes of the quad 2488 Mbits/s signals or single 9952 Mbits/s signal . Error correction is performed in the decoder. The RS (255, 239) code shown in Figure 27 is a nonbinary code and belongs to the family of systematic linear cyclic block codes . DATA (16 bytes) FRAMING DATA (1 byte) 64) OCKS Figure 27. 16-Way (or 64-Way) Interleaved RS (255, 239) Frame There is 1 framing byte, 238 information bytes (payload and fix stuff), and 16 check bytes per RS (255, 239) code block . In order to enhance the immunity of transmission system to burst errors, 16 (or 64) RS (255, 239) code blocks are interleaved . Agere Systems Inc. 39 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 5 5.2 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) Functional Description of Strong FEC (continued) There are five different modes of operation, as shown in Table 14. Table 14. Modes of Operation FEC Payload Type (DWFEC TX 10G 2G5/ DWFEC RX-10G 2G5) Interleaving Depth (DWFEC TX 1664/ DWFEC RX-16 64) Quad 2488 Mbits/s 16 Single 9952 Mbits/s 16 64 I OH Processing (DWFEC TX FEC DW/ DWFEC RX-FEC DW) FEC Frame Digital Wrapper (DW) Frame FEC Frame Digital Wrapper (DW) Frame Digital Wrapper (DW) Frame Note : Digital wrapper (DW) frame mode is equivalent to four multiframe FEC frames . In quad 2 .5 Gbits/s mode, the strong FEC macro processes four different 32-bit wide data streams at four different 83 MHz clocks. In 10 Gbits/s mode, the strong FEC macro processes a single 128-bit wide data stream at a single 83 MHz clock. 16-way or 64-way interleaving is programmable in 10 Gbits/s mode, while there is only 16-way interleaving in quad 2.5 Gbits/s mode. The FEC function can be provided as a part of the digital wrapper (DW) frame. The DW frame consists of four FEC frames and each FEC frame consists of 16-way interleaving RS (255, 239) code blocks, as shown in Figure 28 . In 16-way interleaving (solid arrow), the overhead columns are spaced by 4064 bytes (254 x 16 rows/FEC frame), while in 64-way interleaving (dashed arrow), all 64 overhead bytes are consecutively transmitted and repeat after 16256 bytes (4 x [254 x 16]). When the strong FEC is in DW mode, overhead definition and processing are different from those in FEC mode. (See Table 7, Loss of Clock Registers, on page 31 .) OPTICAL OVERHEAD BYTES (16 PER ROW-TOTAL 64) (16 x 2 .5 Gbits/s/10 Gbits/s) OH1 OH2 ' " OH3 OH4 " ' - 0' (64 x 10 Gbits/s) FEC FRAME #1 PARITY DATA FEC FRAME #2 PARITY DATA FEC FRAME #3 PARITY DATA FEC FRAME #4 I PARITY DATA (x16) Figure 28. Digital Wrapper-Optical Channel Overhead (16-Way/64-Way Interleaving) Table 15 on page 41 shows a summary of the DWFEC MODE control registers . 40 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.2 Functional Description of Strong FEC (continued) Table 15. DWFEC MODE Register Summary Function Register Name (First Occurrence) Register Bits Qty., Transmit FEC Payload Type Indication (2.5 Gbits/s or 10 Gbits/s) Transmit Interleaving Depth Control (16-way or 64-way for 10 Gbits/s mode only) Transmit Frame Indication (FEC or DW mode) Receive FEC Payload Type Indication (2.5 Gbits/s or 10 Gbits/s) Receive Interleaving Depth Control (16-way or 64-way for 10 Gbits/s mode only) Receive Frame Indication (FEC or DW mode) DWFEC MODEO (R/W) DWFEC_TX_10G 2G5 1 1st Addrt (hex) Ox20F0 DWFEC MODEO (R/W) DWFEC-TX-16 64 1 Ox20F0 DWFEC_MODE1_SO (R/W) DWFEC MODEO (R/W) DWFEC_TX_FEC_DW 4 Ox20F1 DWFEC RX_10G 2G5 1 Ox20F0 DWFEC MODEO (R/W) DWFEC RX-16 64 1 Ox20F0 DWFEC_MODE1_SO (R/W) DWFEC_RX_FEC_DW 4 Ox20F1 1 . Qty. refers to the number of registers that are similar to the one shown in the table . There maybe more registers to control different channels, or several registers of similar type used for a particular function . t 1 st Addr (hex) refers to the address (in hex) of the first occurrence of this type of register. 5.2.2 Strong FEC Overhead and Digital Wrapper Overhead Definition The entire overhead for both FEC and DW frames is programmable through the DWAC. This allows flexibility in its definition for future changes in the standards . Internally, 4 bytes can be monitored with continuous N-times detect (CNTD) monitors . These monitors can be combined in four different configurations . They can be grouped as the following : -Four 1-byte monitors. -Two 2-byte monitors. -One 3-byte and one 1-byte monitor. -One 4-byte monitor. The multiple bytes do not need to be contiguous. Four bytes per stream can be inserted from internal registers . Table 16 on page 42 summarizes the overhead sources for each byte in the FEC or DW frame . The FEC overhead repeats every FEC frame . The position and location of the framing bytes are provisionable from a minimum of 2 bytes to a maximum of 16 bytes in steps of 2 bytes. All other bytes that have not been assigned as framing bytes can come from the four internal registers for each 2.5 Gbits/s signal or from the DWAC. This function can also be provided through software in conjunction with the DWAC insert channel . Agere Systems Inc. 41 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 5 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.2 Functional Description of Strong FEC (continued) Table 16. FEC/Digital Wrapper Overhead Source Row Number 1 2 3 4 5 Frame N Frame N + 1 Frame N + 2 Frame N + 3 FEC/DW Internal/DWAC Programmable framing bytes (location/value-internal), and others from DWAC or i n terna l reg i sters (4 MAX) . FEC (N)/DW Internal/DWAC Programmable framing bytes (location/value-intemal), and others from DWAC or i n terna l reg i sters (4 MAX) . FEC (N)/DW Internal/DWAC Programmable framing bytes (location/value-internal), and others from DWAC or i n terna l reg isters (4 MAX) . FEC (N)/DW Internal/DWAC Programmable framing bytes (location/value-internal), and others from DWAC or i n terna l reg isters (4 MAX) . 7 8 9 10 11 12 13 14 15 16 Notes : Any value not from an internal register or the DWAC is set to zero . Three BIP-8 calculations are provided over the OPUk overhead and payload bytes only; other overhead and check bits are excluded from the calculation. The calculated value can be compared against a selected overhead byte . Errors are accumulated in three different 27-bit saturating counters . The software and hardware overhead insert priority is defined in Table 17. 42 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 5.2 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) Functional Description of Strong FEC (continued) Table 17. Software/Hardware Overhead Insert Priority Priority (Highest = 1) 1 2 3 4 5 6 7 Feature OA1/OA2/MFAS byte (software) (Section 7 on page 55) . AIS, OCI, or other fixed pattern insert (software, hardware) . OH3 (software) . OH2 (software) . OH1 (software) . OHO (software) . BIP-8 insert (software). SM (131130) . PM (131131) . TCM (131132) . BEI, BDI, IAE, or STAT insert (software) . SM (BE10, BDIO, IAEO) . PM (BE11, BD11, STAT1) . TCM (BE12, BD12, STAT2) . DWAC insert (DWAC, default, passthrough). I Passthrough (see text on page 61). 8 9 10 Note : In 10 Gbits/s mode, only slice 0 is valid for digital wrapper overhead insert. An OTUk overhead format is defined in Figure 29. This format (and many others) are permitted (and created) from the internal and DWAC capabilities . COLUMN ROW 0 FEC FRAME # 1 4079 OTUk PAYLOAD (4 x 3808 bytes) OTUk FEC (4 x 256 bytes) ----_-__-- ~ 2 ~ 3 4 5 6 FAS 1 RES 2 TCM3 3 3823 ROW# ~ 0 1516 0 OTU4 0 1 2 3 GCC1 7 8 MFAS ACT GCC2 7 APS/PCC 10 SM TCM6 TCM2 9 GCCO TCM5 TCM1 F 11 TCM4 PM 12 13 14 15 RES FTFL MAPPING SPECIFIC EXP RES PT Note : Column and row are defined as row and frame, respectively, for register definitions . Figure 29. OTUk Overhead Frame Structure Agere Systems Inc. 43 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 5 5.3 Operational Description July 2002 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) Strong FEC Supermacro Clocking Domain Specification In quad 2 .5 Gbits/s mode, each slice is independent of the others. In loopback mode, clock selection is done in the top-level clock generation block . In 10 Gbits/s mode, slice 0 acts as the master slice and all other slices sync to its frame position . In loopback mode, clock selection is done in the top-level clock generation block. 5.4 Alarm Definition Table Table 18 summarizes all the service-affecting alarms in the device . Table 18. DWFEC Service-Affecting Alarm Summary Interface Receive Line Name Definition Loss-of-Clock (DEV LOC_LINE_RXCLK) Loss-of-Signal (FRM RXLOS) Out-of-Frame (FRM RXOOF) Loss-of-Frame (FRM RXLOF) BER Signal Degrade (RS_RXBER_SD_DET) BER Signal Fail (RS RXBER SF DET) SM Incoming Alignment Error (DW_RXIAEO DET and DW_TXAIS_TCMSTAT_IAEINHO) RxL-PM(TCMi) OCI/LCK/AIS PM (TCMi) STAT OCI/LCK/AIS Detected (DW RXOCI DET) Receive System RxS ES OVRFLW Elastic Store Overflow Indicator (ES RX OVERFLW A) RxS_ES_UNDRFLW Elastic Store Underflow Indicator (ES_RX_UNDRFLW_A) Transmit System TxS_ES_OVRFLW Elastic Store Overflow Indicator (ES_TX_OVERFLW_A) TxS ES UNDRFLW Elastic Store Underflow Indicator (ES TX UNDRFLW A) Transmit Line TxL_LOC Loss-of-Clock (DEV_LOC_LINE_TXCLK) TxL_LOS Loss-of-Signal (FRM_TXLOS) TxL OOF Out-of-Frame (FRM TXOOF) TxL LOF Loss-of-Frame (FRM TXLOF) 44 RxL_LOC RxL_LOS RxL OOF RxL_LOF RxL_BER_SD RxL BER SF RxL SM IAE Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.5 OTUk Overhead Generation Table 19. OTUk Overhead/Alarm Generation Equations Bytes Subfields FAS WAS SM TTI BIP BEI BDI IAE TTI BIP BEI BDI STAT PM PSI PT MSI TTIi BIPi BEIi BDli STATi GCCO-GCC2 TCMi (one at a time internally) FTFL EXP APS/PCC I - Generation Equation MPU/DWAC 0 to 255 Repeating Sequence DWAC Insert Calculated RxL_BIPl Errors OTUk_SF2 OTUk SF2 OR TxS CF3 DWAC Insert Calculated RxL_BIP' Errors OTUk SF2 AIS-OTUk-AIS OCI-MPU Control LCK-MPU Control DWAC Insert DWAC Insert DWAC Insert DWAC Insert Calculated RxL_BIP' Errors OTUk SF2 AIS-OTUk-AIS Gen OCI-MPU Control LCK-MPU Control MPU/DWAC MPU/DWAC I MPU/DWAC 1 . RxL_BIP = RX_POST_CVL_U or RX_POST_CVL_L or RX_PRE_CVL_U or RX_PRE_CVL_L . 2. OTUk_SF = RxL_LOC or RxL_LOS or RxL_OOF or RxL_LOF or RxL_BER_SF or RxL_BER_SD or RxL_PM_STAT_AIS or RxL_ TCMi_STAT AIS . 3. TxS CF (TxS Client Failure) = TxLOC . Agere Systems Inc. 45 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 5 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.5 OTUk Overhead Generation (continued) Table 20. Transmit OTUk Overhead Alarm Generation and Insert Control Registers Bytes Subfields Generation Equation Alarm Register Control Register Transmit Side FAS - MPU/DWAC Insert - WAS - - SM TTI BIP BEI BDI IAE 0 to 255 Repeating Sequence (available synchronization in loopback mode), MPU/DWAC Insert DWAC Insert Calculated RxL_BIP Errors OTUk_SF_TxL4 OTUk_IAE_TxL6 PSI PT MSI - DWAC Insert DWAC Insert DWAC Insert MPU/DWAC MPU/DWAC MPU/DWAC GCCO-2 FTFL EXP APS/PCC DW_TXBDIO_DET DW_TXIAEO DET - DW TXOA12_INS, DW TXOA1 VAL, DWTXOA2VAL, DWTXOA12 PAIRS DW_TXMFAS_INS, DW-TXOA12 MFAS OH_TxL1 BIP_TxL2 [0] BEI_TXL3 [0] BDI_TXL5 [0] DW TXIAEO_INS, DW TXIAEO_INH, DW_TXIAEO_LOFINH, DW_TXIAEO_OOFI NH OH_TxL1 OH_TxL1 OH_TxL1 OH_TxL1 OH_TxL1 OH TxL1 1 . OH TxL = DW TXOH[0-3LINS, DW TXOH[0-3LVAL, DW TXOH[0-3LFRM, DW TXOH[0-3LROW. 2. BIPTxL = DW TXBIP[0-2LINS, DW TXBIP[0-2LERRINS, DW TXBIP[0-2LFRM, DW TXBIP[0-2LROW . 3. BEI TxL = DW TXBEI[0-2LINS, DW TXBEI[0-2LERRINS, DW TXBII[0-2LFRM, DW TXBII[0-2LROW. 4. OTUk_SF TxL = RxL_LOC or RxL_LOS or RxL_OOF or RxL_LOF or RxL_BER_SF or RxL_BER_SD or RxL_PM_STAT_AIS or RxL_TCMi_STAT_AIS . 5 . BDI TxL = DW TXBDI[0-2LINS, DW TXBDI[0-2LINH, DW TXBDI[0-2LLOCINH, DW TXBDI[0-2LOOFINH, DW TXBDI[0-2LLOFINH, DW TXBDI[0-2LLOSINH, DW TXBDI[0-2LSFINH, DW TXBDI[0-2LSDINH, DW TXBDI[0-2LAISINH, DW TXBDI[0-2LOCIINH, DW TXBDI[0-2LFIXINH, DW TXBDI[0-2LTIMERINH . 6. OTUk IAE TxL = RxL OOF or RxL LOF . 46 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.5 OTUk Overhead Generation (continued) Table 20. Transmit OTUk Overhead Alarm Generation and Insert Control Registers (continued) Bytes Subfields PM TTI BIP BEI BDI STAT Generation Equation DWAC Insert Calculated RxL_BIP Errors OTUk SF TxL4 AIS-OTUk-AIS Generation : OTUk_AIS_TxL = FRM = TxL_LOC OR TxL_LOS OR TXL_OOF OR TxL_LOF ES or LB = TxL_LOC OR DW RXAIS COND7 OCI-MPU Control : DW RXOCI COND9 LCK-MPU Control : DW RXFIX_COND'O TCMi TTIi BIPi BEIi BDli STATi DWAC Insert Calculated RxL_BIP Errors OTUk SF TxL4 AIS-OTUk-AIS Generation OCI-MPU Control LCK-MPU Control Alarm Register Control Register OH_TxL1 BIP_TxL2 [1] BEI_TxL3 [1] DW TXBDI1 DET BDI TxL5 [1] DW_TXB111_STAT INS, DW_TXAIS_INS, DW_TXOA12_MFAS, DW_TXLOC_AISINH, DW_TXOOF_AISINH, DW TXLOF_AISINH, DW TXLOS_AISINH, DW_TXRXCOND_AISINH, FTFL/TCM/GCC/APS Inhibits DW_TXOCI_INS, DW_TXRXCOND _OCIINH, FTFL/TCM/GCC/APS Inhibits DW_TXFIX_INS, DW TXLCK_FIX, DW TXFIX VAL, DW_TXRXCOND_FIXINH, FTFL/TCM/GCC/APS Inhibits OH_TxL1 BIP_TXL2 [2] BEI_TxL3 [2] DW TXBD12 DET BDI TxL5 [2] DW_TXBII2_STAT_INS, FTFL/TCM/GCC/APS Inhibits FTFL/TCM/GCC/APS Inhibits I I FTFL/TCM/GCC/APS Inhibits 1 . OH TxL = DW TXOH[0-3LINS, DW TXOH[0-3LVAL, DW TXOH[0-3LFRM, DW TXOH[0-3LROW. 2 . BIP TxL = DW TXBIP[0-2]INS, DW TXBIP[0-2LERRINS, DW TXBIP[0-2LFRM, DW TXBIP[0-2LROW . 3 . BEI TxL = DW TXBEI[0-2]INS, DW TXBEI[0-2LERRINS, DW TXBII[0-2] FRM, DW TXBII[0-2LROW. 4. OTUk_SF TxL= RxL_LOC or RxL_LOS or RxL_OOF or RxL_LOF or RxL_BER_SF or RxL_BER_SD or RxL_PM_STAT_AIS or RxL_TCMi_STAT_AIS . 5 . BDI TxL = DW TXBDI[0-2]INS, DW TXBDI[0-2LINH, DW TXBDI[0-2LLOCINH, DW TXBDI[0-2LOOFINH, DW TXBDI[0-2LLOFINH, DW TXBDI[0-2LLOSINH, DW TXBDI[0-2LSFINH, DW TXBDI[0-2LSDINH, DWTXBDI[0-2LAISINH, DW TXBDI[0-2LOCIINH, DW TXBDI[0-2LFIXINH, DW TXBDI[0-2LTIMERINH . 6. OTUk_IAE_TxL = RxL_OOF or RxL_LOF . 7. DW_RXAIS_COND = RxL_LOC or RxL_LOS or RxL_OOF or RxL_LOF or RxL_BER_SF or RxL_BER_SD or RxL_PM_STAT_AIS or RxL_TCMi STAT_AIS or RxL_AIS_BYTE . 8 . DW TXAIS FTFLINH, DW TXAIS TCMINH, DW TXAIS GCCINH, DW TXAIS APSINH . 9. DW_RXOCI_COND = RxL_PM_STAT_OCI or RxL_TCMi STAT_OCI or RxL_OCI_BYTE . 10 . DW RXFIX COND = RxL PM STAT LCK or RxL TCMi STAT LCK or RxL FIX BYTE. Agere Systems Inc. 47 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 5 Operational Description July 2002 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.5 OTUk Overhead Generation (continued) Table 21 . Receive OTUk Overhead Alarm Generation and Insert Control Registers Bytes Subfields Generation Equation Alarm/Report Register Control Register Received Side FAS WAS SM TTI BIP BEI BDI IAE 1 . OH 2. BIP 3. BEI 4. OH 48 MPU/DWAC Drop MPU/DWAC Drop Continuous N-Time Detect, MPU/DWAC Drop Calculated RxL BIP Errors Overwritten Before DWAC Drop (with current calculated BIP error per frame value) Continuous N-Time Detect, MPU/DWAC Overwritten Before DWAC Drop (with DW TXBDIO DET) Continuous N-Time Detect, MPU/DWAC Overwritten Before DWAC Drop (with DW TXIAEO DET) OH_ALARM RxL4 DW-RXBIP01-ECNT DW RXBE101 ECNT - DW RXBDIO DET DW_RXIAEO DET - DW-RXOA12-MFAS OH RxL1 BIP_RxL2 [0] BEI RxL3 [0] DWAC_RXBE10_OVWR DW_RXBDIO CNTD DWAC_RXBDIO_OVWR DW_RXIAEO CNTD DWAC_RXIAEO_OVWR RxL = DW_RXOH0123 GRP, DW RXOH[0-3] CNTD, DW RXOH[0-3LFRM, DW RXOH[0-3]ROW . RxL= DW_RXBIP[0-2LDISABLE, DW_RXBIP[0-2LBIT BLK, DW RXBIP[0-2] FRM, DW TXBIP[0-2LROW . RxL = DW_RXBEI[0-2LDISABLE, DW_RXBEI[0-2]BIT BLK, DW RXBII[0-2LFRM, DW TXBII[0-2LROW. ALARM RxL = DW RXOH[0-3LDET, DW RXOH[0-3]VAL. Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.5 OTUk Overhead Generation (continued) Table 21 . Receive OTUk Overhead Alarm Generation and Insert Control Registers (continued) Bytes Subfields PM TTI BIP BEI BDI STAT PSI GCCO-2I PT MSI - Generation Equation Alarm/Report Register Control Register Continuous N-Time Detect, OH_ALARM RxL4 OH RxL1 MPU/DWAC Drop Calculated DW-RXBIP11-ECNT BIP_RxL2 [1] RxL BIP Errors DW RXBEI11 ECNT BEI RxL3 [1] Overwritten Before DWAC DWAC-RXBE11-OVWR Drop (with current calculated BIP error per frame value) Continuous N-Time Detect, DW RXBD11-DET DW-RXBD11 CNTD MPU/DWAC Overwritten Before DWAC DWAC-RXBD11-OVWR Drop (with DW TXBDI1 DET) Continuous N-Time Detect, DW_RX_BII1_STAT_NEW_A, DW_RXB111_STAT_CNTD, OTUk_AIS_ RxL MPU DW_ RX_ BI11 _STAT, DW_RXAIS_SETCNTD, Insert and Monitor/DWAC DW_RXAIS DET5 DW_RXAIS_CLRCNTD, Drop DW_RXAIS_ROW, DW_RXAIS_FRM, DW_RXAIS_I NS, DW_RXAIS DETINH, DW_RXLOC AISINH, DW_RXOOFAISINH, DW_RXLOF AISINH, DW_RXLOSAISINH, DW_RXSF AISINH, DW_RXSDAISINH, _ FTFL/TCM/GCC/APS Inhibit6 OTUk_OCI_RxL DW_RXOCI DET7 DW_RXOCI_INS, MPU Insert and DW_RXOCI_ DETINH, Monitor/DWAC Drop FTFL/TCM/GCC/APS Inhibit? OTUk_ LCK_ RxL DW RXFIX_DET8 DW_RXFIX_VAL, MPU Insert and FTFL/TCM/GCC/APS Inhibit? Monitor/DWAC Drop DWAC Drop DWAC Drop I DWAC Drop I OH ALARM RxL4 I OH RxL1 1 . OH RxL = DW RXOH0123 GRP, DW RXOH[0-3LCNTD, DW RXOH[0-3LFRM, DW RXOH[0-3LROW. 2. BIP RxL = DW_RXBIP[0-2LDISABLE, DW RXBIP[0-2LBIT BLK, DW RXBIP[0-2] FRM, DW TXBIP[0-2LROW . 3. BEI RxL = DW_RXBEI[0-2LDISABLE, DWRXBEI[0-2LBITBLK, DW RXBII[0-2] FRM, DW TXBII[0-2LROW. 4. OH ALARM_RxL = DW_RXOH[0-3] DET, DW_RXOH[0-3LVAL. 5. DW RXAIS DET = RxL_PM_STAT_AIS or RxL TCMi_STAT_AIS or RxL AIS_BYTE . 6 . DW RXAIS FTFLINH, DW RXAIS TCMINH, DW RXAIS GCCINH, DW RXAIS APSINH . 7. DW_RXOCI_DET = RxL_PM_STAT_OCI or RxL_TCMi STAT_OCI or RxL_OCI_BYTE . 8. DW RXFIX DET = RxL PM STAT LCK or RxL TCMi STAT LCK or RxL FIX BYTE . Agere Systems Inc. 49 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 5 Operational Description July 2002 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.5 OTUk Overhead Generation (continued) Table 21 . Receive OTUk Overhead Alarm Generation and Insert Control Registers (continued) Bytes Subfields Generation Equation Alarm/Report Register TCMi TTI Continuous N-Time Detect, MPU/DWAC Drop Calculated RxL BIP Errors Overwritten Before DWAC Drop (with current calculated BIP error per frame value) Continuous N-Time Detect, MPU/DWAC Overwritten Before DWAC Drop (with DW TXBDI2 DET) OH ALARM RxL4 BIP BEI BDI STAT FTFL EXP APS/PCCI - Control Register OH RxL1 DW-RXBIP21-ECNT BIP_RxL2 [2] DW RXBEI21 ECNT - BEI RxL3 [2] DWAC-RXBE12-OVWR DW RXBD12 DET - Continuous N-Time Detect, DW- RX-BI12_STAT_NEW_A, OTUk_AIS_ RxL MPU DW_ RX_ B112_STAT, Insert and Monitor/DWAC DW_RXAIS_DET6 Drop OTUk_OCI_RxL DW_RXOCI_DET7 MPU Insert and Monitor/DWAC Drop OTUk_LCK_RxL DW_RXFIX_DET8 MPU Insert and Monitor/DWAC Drop MPU/DWAC Drop MPU/DWAC Drop I MPU/DWAC Drop I OH ALARM RxL4 DW-RXBD12 CNTD DWAC-RXBD12-OVWR DW_RXB112_STAT_CNTD, FTFL/TCM/GCC/APS Inhibit? FTFL/TCM/GCC/APS Inhibit? FTFL/TCM/GCC/APS Inhibit? OH OH I OH RxL1 1 . OH RxL = DW_RXOH0123 GRP, DW RXOH[0-3] CNTD, DW RXOH[0-3LFRM, DW RXOH[0-3]ROW. 2. BIP RxL= DW_RXBIP[0-2LDISABLE, DW_RXBIP[0-2LBIT BLK, DW RXBIP[0-2] FRM, DW TXBIP[0-2LROW . 3. BEI RxL = DW_RXBEI[0-2LDISABLE, DW_RXBEI[0-2]BIT BLK, DW RXBII[0-2LFRM, DW TXBII[0-2LROW. 4. OH ALARM_RxL = DW RXOH[0-3LDET, DW RXOH[0-3] VAL. 5. DW RXAIS DET = RxL_PM_STAT_AIS or RxL TCMi_STAT_AIS or RxL_AIS_BYTE . 6 . DW RXAIS FTFLINH, DW_RXAIS TCMINH, DW RXAIS GCCINH, DW_RXAIS APSINH . 7. DW_RXOCI_DET = RxL_PM_STAT_OCI or RxL_TCMi STAT_OCI or RxL_OCI_BYTE . 8. DW RXFIX DET = RxL PM STAT LCK or RxL TCMi STAT LCK or RxL FIX BYTE . 50 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 5.6 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) Strong FEC Alarm Actions Table 22. Alarm Actions Interface Receive Line (OTUk input data interface) Name RxL_LOC RxL_LOS RxL OOF RxL_LOF RxL_BER_SF RxL BER SD RxL IAE RxL_TCMi_STAT_AIS RxL_TCMi_STAT_OCI RxL_TCMi_STAT_LCK RxL_PM_STAT_AIS RxL_PM_STAT_OCI RxL_PM_STAT_LCK RxS_ES_OVRFLW RxS_ES_UNDRFLW Receive System (client output data interface) Transmit System TxS_ES_OVRFLW (client input data TxS ES UNDRFLW interface) Transmit Line TxL_LOC (OTUk Output TxL_OOF (bidirectional mode only) data interface) TxL LOF (bidirectional mode only) TxL LOS (bidirectional mode only) Agere Systems Inc. Action on Detection Monitoring (All Modes) Maintence Signal Generation (Terminal/Regenerator/ Bidirectional Modes) Disable All Monitoring Disable All Monitoring Disable All Monitoring Disable All Monitoring Allow Monitoring Allow Monitoring Allow Monitoring Disable All Monitoring ODUk-AIS if Enabled ODUk-AIS if Enabled ODUk-AIS if Enabled ODUk-AIS if Enabled ODUk-AIS if Enabled ODUk-AIS if Enabled No Action Regenerate ODUk-X Maintenance Signal if Enabled Disable All Monitoring Regenerate ODUk-X Maintenance Signal if Enabled NA NA No Action No Action NA NA No Action No Action NA NA NA NA ODUk-AIS ODUk-AIS ODUk-AIS ODUk-AIS if if if if Enabled Enabled Enabled Enabled 51 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 5 Operational Description July 2002 Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.7 5.7.1 Overview, General Functional Description, and Block Diagram of Strong FEC Supermacro Submacros Elastic Store (ES) Macro The ES macro performs rate conversion between two different clocks . One clock (83 MHz) is faster than the other (78 MHz), but the effective clock rates are the same because the faster clock has overhead bytes; therefore, there is no stuffing mechanism . The transmit ES buffers system rate data and outputs gapped line rate data to create space for FEC/DW overhead and FEC check bytes . Data arrives at the transmit ES grouped as 32 bits in each slice. Each group of 32 bits is written into the associated ES location (128 locations x 32 bits). In 2.5 Gbits/s mode, data is read from the ES by 238 clock cycles per 255 clock cycles. In 10 Gbits/s mode, data can either be read by 237 or 238 clock cycles per 255 clock cycles depending on the phase detector divide ratio settings. The receive ES buffers gapped data at the line rate and outputs data at the system rate to absorb clock gapping of the FEC/DW overhead and FEC check bytes . Data arrives to the receive ES grouped as 32 bits in each slice. Each group of 32 bits is written into the associated ES location (128 locations x 32 bits) by 238 clock cycles (for 2.5 Gbits/s mode) or 237/238 clock cycles (depending on the phase detector divide ratio settings for 10 Gbits/s FEC/DW frame) per 255 clock cycles per the system rate clock . An optional fixed stuff row can be placed in row 120 of 255 in 10 Gbits/s mode. 5.7.2 DW Macro This block controls the creation of the FEC/DW frame by controlling the read/write pointers to the elastic store . This control allows gap to be inserted into the outgoing frame for overhead, stuff column, and check byte insertion . The overhead is provisionable through internal registers or through the DWAC channel . 5.7.3 Reed-Solomon (RS) Macro The RS macro performs out-of-band forward error correction using the RS (255, 239) code. The RS encoder accepts 239 bytes of payload and overhead data followed by 16 bytes of all-zero check bytes, and generates 16 bytes of check data. The RS decoder detects and corrects transmission errors, then calculates and reports the incoming BER based on the exact number of corrected bits. 5.7.4 Scrambler/Descrambler Macro The scrambler/descrambier optionall~r scrambles/descrambles data. The scrambling sequence can be selected between two different polynomials : x + x + 1 or x16 + x12 + x3 + x + 1 . Once a scram bling/descrambling pattern is requested, the entire frame (with the exception of the framing bytes) is scram bled/descrambled by the selected polynomial, starting at each frame on the first bit which follows the last framing byte. 52 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 5 with Strong/Weak FEC and Digital Wrapper Strong FEC (Reed-Solomon and Digital Wrapper) Supermacro (continued) 5.7 5.7.5 Overview, General Functional Description, and Block Diagram of Strong FEC Supermacro Submacros (continued) Error Insert Macro The error insert macro inserts various types of errors for RS codec testing . Errors can be inserted in 32-bit format in quad 2.5 Gbits/s mode, or in 128-bit format in 10 Gbits/s mode. 5.7.6 Framer Macro Data arrives to the FEC/DW framer grouped as 4 slices of 4 bytes (32 bits) in quad 2 .5 Gbits/s mode, and 16 bytes (128 bits) in single 10 Gbits/s mode. The FEC/DW framer performs the following : . Framing . Detects LOS, OOF, LOF . Descrambles the data . Inserts AIS In 10 Gbits/s mode, a single FEC/DW framer works on a 128-bit wide data bus . In quad 2.5 Gbits/s mode, a separate FEC/DW framer works on each 32-bit wide data bus ; therefore, there are four separate FEC/DW framers for four different slices . 5.7.7 Interleaver/Deinterleaver Macro The RS encoder/decoder performs byte interleaving/deinterleaving of code blocks in order to enhance the immunity of transmission system to burst errors (in byte manner) . Agere Systems Inc. 53 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 6 6.1 Strong FEC Supermacro Elastic Store (Transmit Direction) Elastic Store (Tx) Functional Description The transmit ES buffers system rate data and outputs gapped line rate data to allocate space for FEC/DW overhead and FEC check bytes . It is assumed that the effective clocks of both write and read are the same; therefore, there is no stuffing mechanism . Data arrives to the transmit ES grouped as 32 bits in each slice. Each group of 32 bits is always written into the associated ES location (128 locations x 32 bits), even if the ES will overflow/underflow. Data is read from the ES by the line rate clock for 238 or 237 out of 255 clock cycles for each FEC frame . The relationship between read and write address is controlled in order to simultaneously minimize signal delay and to guarantee data integrity. At the initial state, or after overflow/underflow, the read address is automatically reset to the predefined position (32 locations ahead of the write address), when the first sync pulse is received . In 10 Gbits/s mode, all four elastic stores work in synchronization. In some applications, the transmit ES is disabled and data is bypassed. In this case, the overflow/underflow alarm is not declared. The ES can be forced to restart by software control . Table 23. Elastic Store (Tx) Register Summary Function Tx ES Overflowing Interrupt Alarm Tx ES Underflowing Interrupt Alarm Tx ES Overflowing Interrupt Alarm Mask Tx ES Underflowing Interrupt Alarm Mask Tx ES Forced Restart 54 I Register Name (First Occurrence) Register Bits Qty. ES_ALARM SO (W1 C) ES_TX_OVERFLW_A 4 Ox201 C ES-ALARM -SO (W1 C) ES_TX_UNDRFLW_A 4 Ox201C ES MASK_SO (R/W) ES_TX_OVERFLW_M 4 0x2058 ES MASK_SO (R/W) ES TX_UNDRFLW M 4 0x2058 4 I 0x2130 ES CTL SO (R/W) I ES TX RESTART I 1st Addr (hex) Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 7 with Strong/Weak FEC and Digital Wrapper 7.1 Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF) Functional Description of FEC/DW Framer The FEC/DW framer consists of three subblocks : a loss-of-signal (LOS) detector, FEC/DW framer (0A1 and OA2), and a frame state machine (for detection of OOF and LOF). The LOS detector monitors the data for loss of signal (fixed all-zeros pattern over a programmable time interval) . The FEC/DW framer block allows the framing on a DW or FEC frame based on a programmable value/number of OA1 and OA2 bytes. The LOF detector monitors the OOF state for a continuous in-frame or out-of-frame state . 7.1 .1 Loss-of-Signal (LOS) Detector The data is monitored by the LOS detector macro for loss of signal (LOS) . In 10 Gbits/s mode, there is a single LOS detector. In quad 2 .5 Gbits/s mode, there is a separate LOS detector on each quad input. On powerup, an LOS defect is declared if all-zeros data is received continuously for a programmable time threshold . This time threshold is provisionable through the loss-of-signal (LOS) threshold register (FRM_TX_CTL LOSDET, 0x22134) for each slice. The default value is 0 (disabled). Assuming that the client signal is operating at SONET or SDH clock rates, the threshold can be set to any value from 0 ps (i.e., LOS detection disabled) to 98.32 ps, with a resolution of 96.02 ns. In the event that other line clock rates are used, the resolution of the threshold is determined by multiplying the period of the line clock by 64. An LOS defect is subsequently cleared when two successive valid framing patterns are received with no period of all zeros exceeding the time threshold . Detection of an LOS defect is indicated by a latched alarm status bit and a persistency bit. Four LOS detectors are implemented, corresponding to each slice. In quad 2.5 Gbits/s mode, all the LOS detectors function independently on 32 bits of data. In 10 Gbits/s mode, the slice 0 LOS detector functions on 128 bits of data and the other LOS detectors are disabled . If the LOS detect threshold is set to zero, LOS detection is disabled and LOS and LOS_PM outputs are deasserted regardless of the LOS condition . The slice 0 LOS detector pin description is given in Table 24. If an optical transponder is connected to the receive line interface, the most appropriate method to declare LOS is by monitoring the power level monitor of the received signal from the transponder. In some transponders, the amplifier gain is high enough to cause the LVDS receive data lines to move above zero, even when there is no optical output . If this should occur, the TFEC0410G may not indicate an LOS defect. This is not a deficiency of the device, but a characteristic of the LOS detection methods . If an optical transponder is used, the LOS detector of the TFEC0410G monitors the connection from the transponder to the receive line interface . The LOS detector in the TFEC0410G is appropriate for electrical monitoring of LOS . Table 24. LOS Detector Register Summary Function LOS Detect Time Threshold LOS Interrupt Alarm LOS Alarm Mask LOS Persistency LOS State Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1stAddr (hex) FRM_TX_CTL LOSDET S0 (R/W) FRM_TXLOS DET 4 0x22134 FRM_ALARM_SO (W1 C) FRM_MASK_S0 (R/W) FRM PERSIST SO (RO) FRM STATE SO (RO) FRM_TXLOS_A FRM_TXLOS_M FRM TXLOS P FRM TXLOS 4 4 4 4 Ox202C 0x2068 Ox209C Ox20CC 55 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 7 Operational Description July 2002 Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF) (continued) 7.1 Functional Description of FEC/DW Framer (continued) 7.1 .2 Framer (A1 and A2) In 10 Gbits/s mode, framing is performed on a single channel . In quad 2 .5 Gbits/s mode, framing is performed on four independent channels . The frame alignment is found by searching for the OA1 and OA2 bytes contained in the FEC/DW (OCh) signal . The framing pattern searched for, or checked, may be a subset of the OA1 and OA2 bytes contained in the FEC/DW (OCh) signal . The framed signal is continuously checked with the presumed frame start position for the alignment . If in the in-frame state (OOF = 0), the maximum out-of-frame (OOF) detection time will be equal to a programmable period of FEC/DW (OCh) frames (superframes) . If in the OOF state, the maximum frame alignment time will be equal to a programmable number of the FEC/DW (OCh) frame (superframe) periods of an error-free signal with no emulated framing patterns . The number of OA1 and OA2 bytes are programmable independently while in the in-frame state and out-of-frame state . The framer outputs frame-aligned data and an 8 kHz sync and reference (free-running) signals . The OA1 pattern cannot be aliased within the OA1 and OA2 pattern boundary. Also, under no circumstances can the two patterns, OA1 and OA2, be the same. Four framers are implemented, corresponding to each slice. In quad 2 .5 Gbits/s mode, all framers function independently on 32 bits of data . In 10 Gbits/s mode, the slice 0 framer functions on 128 bits of data and the other framers are disabled. If the FRM_DIS signal is asserted, framing is disabled . In loopback mode, the framer outputs are disabled and the output sync follows the incoming sync. 7.1 .2.1 Frame State Machine (FSM) The FSM is responsible for bit/byte rotation and for determining the out-of-frame state (OOF) and loss-of-frame (LOF) alarms for each channel. The FSM comes out of reset in the OOF state with the OOF and LOF alarms active . The framining parameters are summarized below : 1 . 0A1, OA2 programmable value per slice (MPU DW_FRM OA1_VAL[3-0][7 :0], MPU DW FRM OA2 VAL[3-0][7 :0]). 2. Number of framing pattern pairs (0A1 /0A2) in the FEC/DW (OCh) frame (MPU_DW FRM OA12 PAIRS[3-0][2:0] ; see Table 25) . 3. Number of framing pattern pairs (0A1 /0A2) used to transition between out-of-frame to in-frame state (OOF, 1 => 0), MPU_DW FRM OA12-PAIRCLR[3-0][2 :0] . 4. Number of framing pattern pairs (OA1/OA2) used to transition between in-frame to out-of-frame state (OOF, 0 => 1), MPU_DW FRM OA12 PAIRSET[3-0][2 :0] . 5. Number of valid consecutive framing pairs (0A1 /0A2) required to transition from out-of-frame to the in-frame state (MPU DW_FRM_OOF CLR[3-0][4:0]). When a portion of the frame alignment word is used, the pattern is always equally centered around the OA1/OA2 border. 6. Number of valid consecutive framing patterns (OA1/OA2) required to transition from in-frame to the out-of-frame state (MPU DW FRM OOF_SET[3-0][4 :0]). When a portion of the frame alignment word is used, the pattern is always equally centered around the OA1/OA2 border. 56 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 7 with Strong/Weak FEC and Digital Wrapper Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF) (continued) 7.1 Functional Description of FEC/DW Framer (continued) Table 25. Frame Alignment (0A1, OA2) Pattern Positions Value (pairs) 1 2 3 4 0x0 (1)' Ox1 (2) Ox2 (3)2 Ox3 (4) Ox4 (5) Ox5 (6) Ox6 (7) 0x7 (8) OM OM OM OM OM OM OM I OM I OA2 OM OM OM OM OM OM OM OA2 OM OM OM OM OM OM OA2 OA2 OM OM OM OM I OM 5 OA2 OA2 OM OM OM I OM 6 OA2 OA2 OA2 OM OM I OM 7 OA2 OA2 OA2 OM I OM 8 9 OA2 OA2 OA2 OA2 OM I OA2 OA2 OA2 OA2 10 11 12 13 OA2 OA2 OA2 OA2 OA2 OA2 OA2 OA2 I OA2 I OA2 I OA2 I OA2 I 14 15 16 OA2 OA2 I OA2 I OA2 1 . 0x0 (1) is the default value. 2. 0x2 (3) is defined by ITU-T/G .709 . The following example defines a frame pattern that contains three OM and three OA2 frame alignment words (A in Figure 30, Framing Algorithm with Example, on page 58) with values OxF6 and 0x28 (B, C), respectively. All six framing values are required to be error free for two consecutive frames for transition from the out-of-frame state to the in-frame state (D). After six consecutive mismatches (E), the out-of-frame state is entered . Only two of the frame alignment words (containing the OA1/OA2 border) are tested for mismatches. Note that the framer will not generate sync pulses during the OOF state . Note : The minimum OOF set value is 0x2 . If OOF SET is programmed to 0x0 or 0x1, OOF will be declared after two consecutive mismatches. Agere Systems Inc. 57 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 7 7.1 Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF) (continued) Functional Description of FEC/DW Framer (continued) (A) MPU DW FRM OA12 PAIRS[2 :0] = 0x2 (B) MPU DWFRM OA1 VAL[7:0] = OxF6 (C) MPU DW FRMOA2VAL[7 :0] = 0x28 (D) MPUDW FRM OOFCLR[4 :0] = 0x1 (E) MPU DW FRM OOF SET[4 :0] = 0x6 MPU DW FRM_OA12 PAIRCLR[2 :0] = 0x2 MPU DWFRM_OA12PAIRSET[2 :0] = 0x0 MPU DW FRM DISABLE = 0 \ IN FRAME FRAMING PATTERN CONFIRMED PROGRAMMABLE CONSECUTIVE FRAMING ERRORS FRAME CONFIRM FRAMING PATTERN NOT COMFIRMED FRAMING PATTERN FOUND OOF RESET Figure 30. Framing Algorithm with Example 58 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 7 7.1 with Strong/Weak FEC and Digital Wrapper Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF) (continued) Functional Description of FEC/DW Framer (continued) Table 26. Framer Control Register Summary Function Register Name (First Occurrence) Register Bits Qty. FRM TX CTL OOF 3 SO FRM TX DISABLE 4 1st Addr (hex) Ox22C0 FRM-TX-CTL OA12 SO (R/W) FRM-TX-CTL OA12 SO (R/W) FRM_TX_CTL_OA12- PAT-3-SO (R/W) FRM-TXOA1 VAL FRM-TXOA2 VAL FRM-TXOA12-PAIRS 4 4 4 0x22138 0x22138 Ox22BC FRM_TX_CTL_OA12- PAT-3-SO (R/W) FRM TXOA12 PAIRCLR 4 Ox22BC FRM_TX_CTL_OA12- PAT-3-SO (R/W) FRM-TXOA12-PAIRSET 4 Ox22BC FRM TX CTL OOF 3 SO FRM TXOOF SET 4 Ox22C0 FRM TX CTL OOF 3 SO FRM TXOOF CLR 4 Ox22C0 Interrupt FRM-ALARM SO (W1C) FRM_TXOOF A 4 Ox202C Interrupt FRM MASK_SO (R/W) FRM_TXOOF M 4 0x2068 FRM_PERSIST-SO (RO) FRM STATE SO (RO) FRM_TXOOF_P FRM TXOOF 4 4 Ox209C Ox20CC Framer Disable OA1 Frame Byte Value OA2 Frame Byte Value Number of Repeat OA1 Bytes (same as OA2) Ex: 0 = One OA1, one OA2s 7 = Eight OA1s, eight OA2s See Table 25 on Page 57 Number of Framing Pattern Pairs (OA1/OA2) Used to Transition Between Out-of-Frame to In-Frame State (OOF, 1 ---> 0) Number of Framing Pattern Pairs (OA1/OA2) Used to Transition Between In-Frame to Out-of-Frame State (OOF, 0 ---> 1) Out-of-Frame Set Out-of-Frame Clear Out-of-Frame Alarm Out-of-Frame Alarm Mask Out-of-Frame Out-of-Frame Persistency State Agere Systems Inc. 59 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 7 Operational Description July 2002 Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF) (continued) 7.1 7.1 .3 Functional Description of FEC/DW Framer (continued) Loss-of-Frame (LOF) Detector The LOF alarm is asserted if OOF persists for a programmable number of frames. The LOF alarm is terminated a programmable number of frames after the OOF alarm is terminated . An interrupt alarm, persistency, and state are provided per slice. Table 27. Loss-of-Frame Control Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) Loss-of-Frame Set FRM RX CTL LOF 2 SO FRM TXLOF SET 4 Ox22C4 Loss-of-Frame Clear FRM RX CTL LOF 2 SO FRM TXLOF CLR 4 Ox22C4 Interrupt Alarm Interrupt Alarm FRM-ALARM _S0 (W1 C) FRM-MASK-SO (R/W) FRM-TXLOF-A FRM TXLOF M 4 4 Ox202C 0x2068 Persistency State FRM_PERSIST_S0 (RO) FRM STATE SO (RO) FRM-TXLOF_P FRM TXLOF 4 4 Ox209C Ox20CC Loss-of-Frame Loss-of-Frame Mask Loss-of-Frame Loss-of-Frame 7.1 .4 Provisioning and Alarm Operation in 10 Gbits/s Mode Only slice 0 alarms and control parameters are valid in 10 Gbits/s mode. All other slice information is ignored and all alarms from slice 1, slice 2, and slice 3 are disabled. 60 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert Functional Description of Digital Wrapper Insert The digital wrapper insert is used for overhead processing before the Reed-Solomon (RS) encoder (check byte insert) . All overhead and data can be retimed and passed through by enabling the control bit, DW_TX_PASSTHRU . Passthrough mode is only available when the data is coming from the transmit framer or is looped back from the receive direction . See Table 17, Software/Hardware Overhead Insert Priority, on page 43 and Figure 26, Strong FEC Supermacro, on page 38 for more information . Table 28. Digital Wrapper Input MUX Control Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) Transmit input MUX. The DW insert block will take the following data to process : 0 = ES_DW_TXDATA (from Tx ES). 1 = FRM_DW_TXDATA (from Tx framer) . Transmit overhead passthrough mode: 0 = Disable . 1 = Enable. DWFEC MUX_S0 (R/W) DW_TX_ES FRM 4 Ox20F5 DW_TX_CTL_TOP 2 S0 (R/W) DW_TX_PASSTHRU 4 0x2178 Overhead passthrough should only be enabled when data is coming from the Tx framer or from the Rx direction loopback (RDW2TDW LB). All FEC/DW frame overhead insert functions supported by the DW in the transmit direction are summarized as follows: . Frame bytes insert. . Multiframe byte (free-running) insert. . Internal FEC overhead bytes insert. . BIP-8 calculation . . BEI/BDI insert and monitor. . IAE/STAT insert and monitor . . AIS, OCI, or other pattern insert. . DWAC insert. . PRBS payload insert. . Check bits insert. . Fixed stuff column enable/disable . The 128-bit input data can be selected from either ES DW_TXDATA[127 :0] or FRM-DW-TXDATA[l 27 :0] via the microprocessor. In loopback mode, the 128-bit input data can be selected from the output of the receive direction (DW_ES RXDATA) to pass through to the digital wrapper insert, which is controlled by the top-level input pin (MPU DW R2T LB) . The digital wrapper insert should synchronize its frame by monitoring DW ES RXSYNC . Agere Systems Inc. 61 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 8.1 Digital Wrapper Insert (continued) 8.1 .1 Functional Description of Digital Wrapper Insert (continued) Framing Bytes Insert The DW macro allows programmable framing bytes (0A1, OA2) in both FEC frame and DW (multiframe) mode. For 6.709 compliance, the framing bytes should be set as follows: . Set the OM byte to OxF6. . Set the OA2 byte to 0x28. . Set the insertion count to 0x2. . Set the number of MFAS bytes to 0x1 . In the transmit direction, a free-running counter generates the MFAS bytes. In loopback or bidirectional mode, the MFAS counter is synchronized to the incoming MFAS . The DWAC sync output is asserted for two DWAC clock cycles wide to indicate that the current overhead is for MFAS 0x0 . (See Figure 40 on Page 79.) All framing bytes can be inserted by either the DWAC insert channel or by one or all of the overhead (OHx) insert bytes. When neither OM nor OA2 is inserted, either the DWAC insert byte, overhead (OHx) insert bytes, or default will be inserted . DW_TXDEFAULT will set all overhead bytes to a default value of all 1s or Os if no specific overhead insertion is enabled. Table 29. Framing Byte (0A1 and OA2) Insert Control Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OM OA2 Frame Byte Insert Enable OM Frame Byte Value OA2 Frame Byte Value Number of Repeat OM and OA2 Byte Pairs (see Table 25 on Page 57) Insert Free-Running MFAS Counter Default Value for Overhead Bytes (all Os or all 1 s) Sync MFAS Counter to Incoming MFAS Value Enable DW TX_CTL TOP 2 S0 (R/W) DW-TXOA12 INS 4 0x2178 DW TX CTL OA12 S0 (R/W) DW_TX_CTL OA12 S0 (R/W) DW_TX_CTL_OA12 PAT S0 (R/W) DW TXOA1 VAL DW_TXOA2 VAL DW_TXOA12 PAIRS 4 4 4 Ox217C Ox217C 0x2180 DW_TX_CTL_TOP_V2 S0 (R/W) DW_TXMFAS_INS 4 0x2514 DW_TX_CTL TOP 2 S0 (R/W) DW_TXDEFAULT 4 0x2178 DW_TX_CTL_TOP_V2 S0 (R/W) DW_TXMFAS SYNC 4 0x2514 62 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) 8.1 8.1 .2 Functional Description of Digital Wrapper Insert (continued) Internal FEC Overhead Byte Insert (OHO to OH3) There are four internal programmable bytes (0H0, OH1, OH2, OH3) that can be inserted or overwritten in digital wrapper overhead locations for each slice. Each overhead (OHx) can be inserted by programming its 8-bit wide value. The location of the overhead byte can be specified by using frame location and row location. EXAMPLE : INSERT OHO VALUE 0X20 INTO GCC1, BYTE 0 ; OH LOCATION IS FRM 3, ROW 1 DW_OHO INS[0] = 1 DW_TXOH0 VAL[0][7 :0] = 0X20 DW TXOHO FRM[0][1 :0] = 01 (0X1) DW TXOHO ROW[0]03 :0] = 0100 (0X4) ROW # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 FEC FRAME # 1 2 3 Note : Column and row are defined as row and frame, respectively, for register definitions . Figure 31 . Internal DWFEC Overhead Byte Insert Programmable Location Example Agere Systems Inc. 63 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 8.1 Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) Table 30. Transmit DW OHO to OH3 Bytes Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) Overhead Byte Insertion Enable Overhead Byte Insertion Value Overhead Byte Insertion Frame Location (DW mode only) Overhead Byte Insertion Row Location Overhead Byte Insertion Enable Overhead Byte Insertion Value Overhead Byte Insertion Frame Location (DW mode only) Overhead Byte Insertion Row Location Overhead Byte Insertion Enable Overhead Byte Insertion Value Overhead Byte Insertion Frame Location (DW mode only) Overhead Byte Insertion Row Location Overhead Byte Insertion Enable Overhead Byte Insertion Value Overhead Byte Insertion Frame Location (DW mode only) Overhead Byte Insertion Row Location DW_TX_CTL TOP 2 SO (R/W) DW_TXOHO INS 4 0x2178 DW_TX_CTL OHO 2 SO (R/W) DW_TXOHO_VAL 4 0x2184 DW_TX_CTL OHO 2 SO (R/W) DW_TXOHO FRM 4 0x2184 DW_TX_CTL OHO 2 SO (R/W) DW_TXOHO ROW 4 0x2184 DW_TX_CTL TOP 2 SO (R/W) DW_TXOH1 INS 4 0x2178 DW_TX_CTL OH1 2 SO (R/W) DW_TXOH1_VAL 4 0x2188 DW_TX_CTL OH1 2 SO (R/W) DW_TXOH1 FRM 4 0x2188 DW_TX_CTL OH1 2 SO (R/W) DW_TXOH1 ROW 4 0x2188 DW_TX_CTL TOP 2 SO (R/W) DW_TXOH2 INS 4 0x2178 DW_TX_CTL OH2 2 SO (R/W) DW_TXOH2_VAL 4 0x218C DW_TX_CTL OH2 2 SO (R/W) DW_TXOH2 FRM 4 0x218C DW_TX_CTL OH2 2 SO (R/W) DW_TXOH2 ROW 4 0x218C DW_TX_CTL TOP 2 SO (R/W) DW_TXOH3 INS 4 0x2178 DW_TX_CTL OH3 2 SO (R/W) DW_TXOH3_VAL 4 0x2190 DW_TX_CTL OH3 2 SO (R/W) DW_TXOH3 FRM 4 0x2190 DW_TX_CTL OH3 2 SO (R/W) DW_TXOH3 ROW 4 0x2190 Note : Refer to Table 12 on page 35 for the priority of overhead byte insert. In FEC frame, only row location control registers are used . 64 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) 8.1 8.1 .3 Functional Description of Digital Wrapper Insert (continued) BIP-8 Calculation Three BIP-8 calculations are provided every frame (OPU overhead (row 14-15), payload, and fix stuff; other bytes are excluded from calculation) . The bit interleaved parity code (BIP-8) byte is even parity, which is placed in the BIP byte of the second frame following the frame as shown in Figure 32 . 13 1415 16 3823 4079 bytes 0 w PAYLOAD 2 3 _ + .- w 0 1 2 BI P8 3 + - w 0 1 2 3 Note : Refer to Table 17 on page 43 for the priority of overhead byte insert. In FEC frame, only row location control registers are used . Figure 32. 6.709 BIP-8 Computation and Transport for One Connection Monitoring Level The BIP-8 byte can be inserted via microprocessor control . The BIP-8 byte can be inserted in both FEC and DW frames by specifying the location (time slot) of any frame. This is identical to the example in Figure 32. BIP-8 insert is suggested to be inserted at the corresponding locations of the SM/TCM and PM bytes. Agere Systems Inc. 65 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 Digital Wrapper Insert (continued) 8.1 8.1 .4 Functional Description of Digital Wrapper Insert (continued) General Definition of BEI, BDI, and IAE Insert and Monitor Three BII bytes can be inserted in every frame . A BII byte includes BEI (the number of BIP errors per frame in the receive direction) and BDI interrupt alarm state . The BEI value is between 0 to 8 in each frame. When BEI insert is disabled, BEI location is set to zero. When BEI error insert is enabled, BEI location is set to a nonzero fixed value . BI10 BYTE BDI IAE XX BEI (BIP ERROR PER FRAME) Bill/B112 BYTE STAT BDI Figure 33. BII Byte Description Each BDI-failure (DW TXBDIO_INS, DW_TXBD11_INS, and DW_TXBD12 INS) contributes to a state bit . Transmit BDI-failure is inserted into the data signal using the following equation : . DW_TXBDI_DET = (LINE_RX83LOC and not (DW_TXBDI_LOCINH)) or-input loss of clock (FRM RXLOS and not (DW TXBDI_LOSINH)) or-loss-of-signal (FRM RXOOF and not (DW TXBDI_OOFINH)) or-out-of-frame (FRMRXLOF and not (DW TXBDI_LOFINH)) or-loss-of-frame (RS_RXBER_SF_DET and not (DW_TXBDI_SFINH)) or-BER signal fail (RS_RXBER_SD_DET and not (DW-TXBDI-SDINH)) or-BER signal degrade (DW-RXAIS COND and not (DW TXBDI_AISINH)) or-PM-AIS or TCM-AIS (DW-RXOCI COND and not (DWTXBDI_OCIINH)) or-PM-OCI or TCM-OCI (DW-RXFIX_COND and not (DW TXBDI_FIXINH)) or-PM-FIX/LCK or TCM-LCK (TIMER20Frames and not (DW_TXBDI-TIMERINH)) or-20 frame timer (DW TXBDI INS)-software insert Only receive alarms can contribute to transmit BDI failure generation . Transmit framer alarms and loss-of-transmit clock do not contribute to transmit BDI . Note : Refer to Table 17, Software/Hardware Overhead Insert Priority, on page 43 for the priority of overhead byte insert. In FEC frame mode, only row location control registers are used. For BEI error insert, set BEI to a value of 0x3 regardless of the number of receive direction BIP errors per frame. BEI and BDI can be passthrough or inserted indepedently by using the DWAC insert. If BDI is inserted for a BDI overwritten byte in DWAC drop in the receive direction, and it is not desired to generate BDI in the transmit direction, the BII byte location can be programmed to an invalid location ; BEI insert is also disabled . SONET/SDH equipment has the ability to generate an RDI-P alarm for a minimum number of frames. The 20-frame timer allows for a similar function in BDI generation . This may be inhibited through software if not desired . 66 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) A single-bit IAE is also generated in the transmit direction . It is generated under OOF/LOF conditions in the receive direction . Only receive alarms can contribute to transmit IAE failure generation . Transmit framer alarms do not contribute to transmit IAE. . DW TXIAE_DET = (FIRM RXOOF and NOT (DW TXIAE_OOFINH)) or-out-of-frame (FIRM RXLOF and NOT (DW TXIAE LOFINH)) or-loss-of-frame (DW TXIAE-INS)-software insert BDI/BEI/IAE are controlled individually by the corresponding SM/PM and TCM control signals described in Section 8.1 .5 on page 68 through Section 8.1 .9 on page 76. Table 31 . BDI/IAE Overhead Insert Priority Priority (Highest = 1) Feature 1 2 Software BDI/IAE Insert (ex., DW_TXBDIO_INS is set high) Hardware BDI/IAE Detect = DW_TXBDIO_DET (ex., DW_TXBDIO_INH or DW_TXIAEO_INH is set low) DWAC Insert Passthrough 3 4 Figure 34 shows the BDI and IAE alarm detection and insertion structure . LINE-RX83LOC DW TXBDI LOCINH FRM_RXLOS DW TXBDI LOSINH FRM_RXLOF DW_TXBDI_LOFINH FRM_RXOOF DW_TXBDI_OOFINH DW TXBDI DET RS-SF DW TXBDI SFINH RS_SD DW_TXBDI_SDINH DW_RXAIS_CON D DW_TXBDI_AISINH DW_RXOCI_COND DW_TXBDI_OCIINH (BDI OVERHEAD BIT INSERT) DW TXBDI INH DW TXBDI INS DW_RXFIX_COND DW TXBDI FIXINH FRM_RXOOF DW TXIAE OOFINH DW TXIAE DET FRM_RXLOF DW TXIAE LOFINH DW TXIAE INS (IAE OVERHEAD BIT INSERT) DW TXIAE INH DW TXIAE INS Figure 34. BDI and IAE Alarm Structure (per Slice) Agere Systems Inc. 67 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 Digital Wrapper Insert (continued) 8.1 Functional Description of Digital Wrapper Insert (continued) Table 32 . ODUk TCM-STAT Overhead Interpretation If (AIS COND-INSERT = 1), then : STAT[2 :0] 000 001 010 011 100 101 110 111 Status No Source TC In Use without IAE Condition (normal or OTUk-AIS1) In Use with IAE Condition (DW_TXIAEO DET and not DW TXAIS TCMSTAT IAEINH) Reserved for Future International Standardization Reserved for Future International Standardization Maintenance Signal: ODUk-LCK Maintenance Signal : ODUk-OCI I Maintenance Signal: ODUk-AIS 1 . During OTUk-AIS, DW TXAIS TCMSTAT_IAEINH is set high . 8.1 .5 OTU Section Monitoring (SM) One field of section monitoring overhead (SM) is defined in FEC frame 0, rows 7 to 9, to support section monitoring . The SM field contains the following subfields (Figure 35) . These bytes will use the BIPO set of register bits (DW TXBIPO INS, etc.) in the insert control registers . . Bit interleaved parity (BIP-8) . . Backward defect indication (BDI) . . Backward error indication (BEI). . Incoming alignment error overhead (IAE). . Reserved for future international standardization (RES) . 1 TTI 0 ' 15 16 SM 2 3 BIP-8 7 SAPI DAPI 6 BEI 5 4 3 m SM-3 ~ 2 1 Q RES 0 31 32 OPERATOR SPECIFIC 63 Figure 35. 6.709 ODUk Section Monitor Overhead 68 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) 8.1 .5.1 SM Bit Interleaved Parity (BIP-8) One BIP-8 calculation is provided in the section monitoring (SM) field (over payload and OPU overhead, check bits are excluded from calculation of the frames) ; see Figure 32 . The section (even parity) bit interleaved (BIP-8) byte's value is calculated over the entire OPU signal in the nth frame and then inserted in the BIP byte of the n + 2nd frame as shown in Figure 32 on Page 65. The computed BIP-8 byte can then be error inserted (bits are inverted) via microprocessor control . Table 33. Transmit SM BIP Byte Insertion Register Summary Function BIP Byte Insertion Enable BIP Byte Error Insertion Enable BIP Byte Insertion Frame Location BIP Byte Insertion Row Location 8.1 .5.2 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) DW TX CTL BIP SO (R/W) DW_TX_CTL BIP SO (R/W) DW TXBIP0 INS DW_TXBIP0 ERRINS 4 4 0x2198 0x2198 DW_TX_CTL BIP SO (R/W) DW_TXBIPO FRM 4 0x2198 DW_TX_CTL BIP SO (R/W) DW_TXBIP0 ROW 4 0x2198 SM Backward Error Indication (BEI) The BEI (BIP errors per frame in the receive direction) can be inserted in every frame to indicate to the far end the received BIP errors . The valid BEI value is between 0 and 8 in each frame; invalid values that are greater than 0x8 are set as zero. When BEI insert is disabled, BEI value is set to zero. When BEI error insert is enabled, BEI value is set to a 0x3 regardless of the number of received BI P errors per frame . Table 34. Transmit SM BEI Insertion Register Summary Function BEI Insertion Enable BEI Error Insertion Enable BII Byte Insertion Frame Location BII Byte Insertion Row Location Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) DW TX CTL BII SO (R/W) DW_TX_CTL BII_SO (R/W) DW_TX_CTL BII-SO (R/W) DW TXBE10 INS DW_TXBE10 ERRINS DW_TXBI10 FRM 4 4 4 0x219C 0x219C 0x219C DW_TX_CTL BII SO (R/W) DW_TXBII0_ROW 4 0x219C 69 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 8.1 Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) 8.1 .5.3 SM Backward Defect Indication (BDI) Transmit BDI is inserted into the OTU frame under the same conditions described in Section 8.1 .4, General Definition of BEI, BDI, and IAE Insert and Monitor, on page 66. If a BDI insertion condition occurs, software can program BDI to be inserted for twenty consecutive frames regardless of BDI conditions. Table 35. Transmit SM BDI Insertion Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) BDI Failure Interrupt Alarm BDI Failure Interrupt Alarm Mask BDI Failure Persistency BDI Failure State BDI Failure Condition Not Detect when Detect LOC Inhibit BDI Failure Condition Not Detect when Detect OOF Inhibit BDI Failure Condition Not Detect when Detect LOF Inhibit BDI Failure Condition Not Detect when Detect LOS Inhibit BDI Failure Condition Not Detect when Detect SF Inhibit BDI Failure Condition Not Detect when Detect SD Inhibit BDI Failure Condition Not Detect when Detect AIS Inhibit BDI Failure Condition Not Detect when Detect OCI Inhibit BDI Failure Condition Not Detect when Detected FIX Pattern Inhibit BDI Failure Condition Not Detect After at Least 20 Frames Inhibit BDI Detect Inhibit DW-ALARM _S0 (W1 C) DW-MASK-SO (R/W) DW-TXBDIO-DET-A DW-TXBDIO-DET M 4 4 0x2020 Ox205C DW-PERSIST-2-SO (RO) DW-STATE-2-SO (RO) DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TXBDIO-DET-P DW-TXBDIO-DET DW-TXBDIO-LOCINH 4 4 4 0x2090 Ox20C0 Ox21A0 DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TXBDIO-OOFINH 4 Ox21A0 DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TXBDIO-LOFINH 4 Ox21A0 DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TXBDIO-LOSINH 4 Ox21A0 DW-TX-CTL-BDIOINH-2-SO (R/W) DW_TX_CTL-BDIOINH-2-SO (R/W) DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TXBDIO-SFINH 4 Ox21A0 DW-TXBDIO-SDINH 4 Ox21A0 DW-TXBDIO-AISINH 4 Ox21A0 DW-TXBDIO-OCIINH 4 Ox21A0 DW-TXBDIO-FIXINH 4 Ox21A0 DW-TX-CTL-BDIOINH-2-SO (R/W) DW-TXBDIO-TIMERINH 4 Ox21A0 DW TX CTL BDIOINH 2 SO DW TXBDIO INH 4 Ox21A0 DW TX CTL BDIOINH 2 SO DW TXBDIO INS 4 Ox21A0 BDI Insertion Enable 70 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) 8.1 .5.4 SM Incoming Alignment Error Overhead (IAE) Transmit IAE is inserted into the OTU frame under the same conditions described in Section 8.1 .4 on page 66. Table 36. Transmit IAE Insertion Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) IAE Insertion Enable IAE Detect Inhibit IAE Insert Inhibit Due to Rx LOF Condition IAE Insert Inhibit Due to Rx OOF Condition IAE Failure Interrupt Alarm IAE Failure Interrupt Alarm Mask IAE Failure Persistency IAE Failure State DW TX CTL TOP V2 SO (R/W) DW TX CTL TOP V2 SO (R/W) DW_TX_CTL_TOP_V2 SO (R/W) DW TXIAEO INS DW TXIAEO INH DW_TXIAEO_LOFINH 4 4 4 0x2514 0x2514 0x2514 DW_TX_CTL_TOP_V2 SO (R/W) DW_TXIAEO OOFINH 4 0x2514 DW ALARM V2 SO (W1 C) DW MASK V2 SO (R/W) DW PERSIST V2 SO (RO) DW STATE V2 SO (RO) DW TXIAEO DET A DW TXIAEO DET M DW TXIAEO DET P DW TXIAEO DET 4 4 4 4 0x2030 Ox206C Ox20A0 Ox20D0 Agere Systems Inc. 71 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 Digital Wrapper Insert (continued) 8.1 Functional Description of Digital Wrapper Insert (continued) 8.1 .6 Path Monitoring Insert (PM) The path monitoring bytes have identical functionality as the SM byte with (3-bit) STAT available . These bytes will use the BIP1 set of register bits (DW TXBIP1 INS, etc .) in the insert control registers . 8.1 .6.1 PM-Bit Interleaved Parity (BIP-8) The BI P-8 byte is processed identically to the SM-BI P8 byte (see Section 8.1 .5.1 on page 69) . Table 37. Transmit PM BIP Byte Insertion Register Summary Function BIP Byte Insertion Enable BIP Byte Error Insertion BIP Byte Insertion Frame Location BIP Byte Insertion Row Location 8.1 .6.2 Register Name (First Occurrence) Register Bits Qty. 1stAddr (hex) DW_TX_CTL_BIP_SO (R/W) DW_TX_CTL BIP SO (R/W) DW_TX_CTL BIP SO (R/W) DW_TXBIP1_INS DW_TXBIP1_ERRINS DW_TXBIP1 FRM 4 4 4 0x2198 0x2198 0x2198 DW_TX_CTL BIP SO (R/W) DW_TXBIP1-ROW 4 0x2198 PM-Backward Error Indication (BEI) The BEI bits are processed identically to the SM-BEI bits (see Section 8.1 .5.2 on page 69) . Table 38. Transmit PM BEI Insertion Register Summary Function BEI Insertion Enable BEI Error Insertion BII Byte Insertion Frame Location BII Byte Insertion Row Location 72 Register Name (First Occurrence) DW_TX_CTL_BII_SO (R/W) DW_TX_CTL BII_SO (R/W) DW_TX_CTL BII-SO (R/W) Register Bits Qty. DW_TXBE11_INS DW_TXBE11_ERRINS DW-TXB111 FRM 4 4 4 1st Addr (hex) Ox219C Ox219C Ox219C DW_TX_CTL BII SO (R/W) DW-TXB111 ROW 4 Ox219C Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) 8.1 .6.3 PM-Backward Defect Indication (BDI) The BDI bit is processed identically to the SM-BDI bit (see Section 8.1 .5.3 on page 70) . Table 39. Transmit PM BDI Insertion Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) BDI Failure Interrupt Alarm BDI Failure Interrupt Alarm Mask BDI Failure Persistency BDI Failure State BDI Failure Condition Not Detect when Detect LOC Inhibit BDI Failure Condition Not Detect when Detect OOF Inhibit BDI Failure Condition Not Detect when Detect LOF Inhibit BDI Failure Condition Not Detect when Detect LOS Inhibit BDI Failure Condition Not Detect when Detect SF Inhibit BDI Failure Condition Not Detect when Detect SD Inhibit BDI Failure Condition Not Detect when Detect AIS Inhibit BDI Failure Condition Not Detect when Detect OCI Inhibit BDI Failure Condition Not Detect when Detected FIX Pattern Inhibit BDI Failure Condition Not Detect After at Least 20 Frames Inhibit BDI Detect Inhibit DW ALARM SO (W1 C) DW-MASK-SO (R/W) DW TXBDI1 DET A DW-TXBDI1-DET M 4 4 0x2020 Ox205C DW-PERSIST-2_SO (RO) DW STATE 2 SO (RO) DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-DET-P DW TXBDI1 DET DW-TXBDI1-LOCINH 4 4 4 0x2090 Ox20C0 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-OOFINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-LOFINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-LOSINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBD11-SFINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBD11-SDINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-AISINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-OCIINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-FIXINH 4 0x2518 DW-TX-CTL-BDIlINH-V2-SO (R/W) DW-TXBDI1-TIMERINH 4 0x2518 DW TX CTL BDIl INH V2 SO DW TXBDI1 INH 4 0x2518 DW TX CTL BDIlINH V2 SO DW TXBDI1 INS 4 0x2518 BDI Insertion Enable Agere Systems Inc. 73 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 Digital Wrapper Insert (continued) 8.1 Functional Description of Digital Wrapper Insert (continued) 8.1 .7 PM Statistics The STAT bits are set to 0x1 to indicate normal data signal and are overwritten under AIS/OCI and LCK conditions . The generation of these maintenance signals is described in Section 8.1 .10 on page 76. Table 40. Transmit PM AIS, OCI, and LCK Insert Register Summary Function STAT 0x1 Insert Enable (if no error) 8.1 .8 Register Name Register Bits Qty. DW_TX_CTL_TOP_V2_SO (R/W) DW-TXB111-STAT-INS 4 1st Addr (hex) 0x2514 Tandem Connection Insert (TCMi) There are 6 TCM bytes in an OTUk frame . The software can program any one of the TCM bytes to be processed in the transmit direction . The processing of the selected TCM bytes is identical to the PM bytes. These bytes will use the BIP3 set of register bits (DW TXBIP2 INS, etc .) in the insert control registers . 8.1 .8.1 TCMi-Bit Interleaved Parity (BIP-8) The BI P-8 byte is processed identically to the SM-BI P8 byte (see Section 8.1 .5.1 on page 69) . Table 41 . Transmit TCM BIP Byte Insertion Register Summary Function BIP Byte Insertion Enable BIP Byte Error Insertion BIP Byte Insertion Frame Location BIP Byte Insertion Row Location 8.1 .8.2 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) DW_TX_CTL_BIP_V2_SO (R/W) DW_TX_CTL_BIP_V2_SO (R/W) DW_TX_CTL BIP V2 SO (R/W) DW_TXBIP2_INS DW_TXBIP2_ERRINS DW_TXBIP2 FRM 4 4 4 0x2524 0x2524 0x2524 DW_TX_CTL BIP V2 SO (R/W) DW_TXBIP2 ROW 4 0x2524 TCMi-Backward Error Indication (BEI) The BEI bits are processed identically to the SM-BEI bits (see Section 8.1 .5.2 on page 69) . Table 42. Transmit TCM BEI Insertion Register Summary Function BEI Insertion Enable BEI Error Insertion BII Byte Insertion Frame Location BII Byte Insertion Row Location 74 Register Name (First Occurrence) Register Bits Qty. DW_TX_CTL_BII_V2_SO (R/W) DW_TX_CTL_BII_V2_SO (R/W) DW_TX_CTL BII_V2 SO (R/W) DW-TXBE12-INS DW-TXBE12 ERRINS DW-TXB112 FRM 4 4 4 1st Addr (hex) 0x2520 0x2520 0x2520 DW_TX_CTL BII_V2 SO (R/W) DW-TXB112 ROW 4 0x2520 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) 8.1 .8.3 TCMi-Backward Defect Indication (BDI) The BDI bit is processed identically to the SM-BDI bit (see Section 8.1 .5.3 on page 70) . Table 43. Transmit TCM BDI Insertion Register Summary Function BDI Failure Interrupt Alarm BDI Failure Interrupt Alarm Mask BDI Failure Persistency BDI Failure State BDI Failure Condition Not Detect when Detect LOC Inhibit BDI Failure Condition Not Detect when Detect OOF Inhibit BDI Failure Condition Not Detect when Detect LOF Inhibit BDI Failure Condition Not Detect when Detect LOS Inhibit BDI Failure Condition Not Detect when Detect SF Inhibit BDI Failure Condition Not Detect when Detect SD Inhibit BDI Failure Condition Not Detect when Detect AIS Inhibit BDI Failure Condition Not Detect when Detect OCI Inhibit BDI Failure Condition Not Detect when Detected FIX Pattern Inhibit BDI Failure Condition Not Detect After at Least 20 Frames Inhibit BDI Detect Inhibit BDI Insertion Enable Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1stAddr (hex) DW ALARM SO (W1 C) DW-MASK-SO (R/W) DW TXBD12 DET A DW-TXBD12 DET M 4 4 0x2020 Ox205C DW-PERSIST-2_SO (RO) DW STATE 2 SO (RO) DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-DET-P DW TXBD12 DET DW-TXBD12-LOCINH 4 4 4 0x2090 Ox20C0 Ox251C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12_OOFINH 4 Ox251C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-LOFINH 4 Ox251C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-LOSINH 4 0x251 C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-SFINH 4 0x251 C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-SDINH 4 Ox251C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-AISINH 4 Ox251C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBDI2-OCIINH 4 Ox251C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-FIXINH 4 0x251 C DW-TX-CTL-BD121NH-V2-SO (R/W) DW-TXBD12-TIMERINH 4 Ox251C DW TX CTL BD121NH V2 SO DW TXBDI2 INH 4 Ox251C DW TX CTL BD121NH V2 SO DW TXBD12 INS 4 Ox251C 75 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 Digital Wrapper Insert (continued) 8.1 8.1 .9 Functional Description of Digital Wrapper Insert (continued) TCM Statistics The STAT bits are set to 0x0 to indicate no TC signal and are overwritten under AIS/OCI and LCK conditions. The generation of these maintenance signals is described in later sections. Table 44. Transmit TCM AIS, OCI, and LCK Insert Register Summary Function STAT 0x1 Insert Enable (if no error) 8.1 .10 Register Name (First Occurrence) Register Bits Qty. DW_TX_CTL_TOP V2 SO (RW) DW-TXBI12 STAT-INS 4 1st Addr (hex) 0x2514 Alarm Indication Signal (AIS), Open Connection Indication (OCI), Locked (LCK), and Fixed Pattern Insert The macro automatically generates hardware AIS in transmit direction insert when the alarms (i.e., LOC, LOS, OOF, or LOF state bits) are active and the appropriate inhibit signals are inactive or software insert is active . The AIS, OCI, LCK, or other pattern insert priority is defined in Table 45. Table 45. AIS, OCI, Locked (LCK), and Fixed Pattern Insert Priority Priority (Highest = 1) 1 2 3 4 5 6 AIS, OCI, or Other Pattern AIS Insert (Software) OCI Insert (Software) Fixed Pattern Insert (Software) AIS Insert (Hardware) FRM (Tx) ES (Tx) or LB (Rx to Tx) (LINE TX83LOC and not (LINE TX83LOC and not (DW TXLOC AISINH)) (DW TXLOC AISINH)) or or (FRM DW_TXLOS and not (DW RXAIS_COND and not (DW TXLOS AISINH)) (DWTXRXCOND AISINH)) or OCI Insert (Hardware) (FRM DW TXOOF and not (DW RXOCI COND and not (DWTXOOF AISINH)) (DWTXRXCOND OCIINH) Locked or Fixed Pattern Insert (Hardware) (FRM DW_TXLOF and not (DW RXFIX_COND and not (DW TXLOF AISINH)) (DWTXRXCOND FIXINH)) Note : See page 107 for description of DW RXAIS COND, DW RXOCI COND, and DW RXFIX COND. All frames are generated with a valid FEC/DW framing pattern, OTUk overhead, and the remaining frame bytes set to OxFF for AIS insert, 0x66 for OCI insert, or all fixed pattern (0x55-OTUk-LCK). At programmable WAS location bytes, overhead insert (such as DWAC insert or OHO) in the OTU OH field, is valid and is not overwritten by the AIS generator. TCMO-TCM5, GCCO-GCC2, and APS/PCC inhibits are available . 76 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) The frame structures for AIS, OCI, and LCK are shown below. OVERHEAD (0 TO 15) FA CH OTU OH TCM6 TCM3 PAYLOAD (16 TO 3823) TCM2 TCM5 TCM4 OxFF TCM1 IGCC1IGCC2I APS/PCC FTFL Figure 36. ODUk-AIS (TCMi, GCC1, GCC2, APS/PCC Can Be Modified/Monitored) aOVERHEAD (0 TO 15) FA CH TCM6 TCM3 PAYLOAD (16 TO 3823) OTU OH TCM2 TCM5 TCM4 0x66 TCM1 IGCC1IGCC2I APS/PCC FTFL Figure 37. ODUk-OCI (TCMi, GCC1, GCC2, APS/PCC Can Be Modified/Monitored) aOVERHEAD (0 TO 15) FA CH OTU OH TCM6 TCM3 PAYLOAD (16 TO 3823) TCM2 TCM5 TCM4 0x55 TCM1 IGCC1IGCC2I APS/PCC FTFL Figure 38. ODUk-LCK (TCMi, GCC1, GCC2, APS/PCC Can Be Modified/Monitored) Figure 39 is an example of WAS, SM, FTFL, TCM2, GCC1, and GCC2 when inhibited during ODUk-AIS . OVERHEAD [0 TO 15] FA OH PAYLOAD [16 TO 3823] OH OxFF TCM2 IGCC1I GCC2 I I FTFL Example : DW TXOA12 PAIR = 0x2, DW TXOA12 WAS = 0x4, DW RXAIS FTFLINH = 0x1, DW RXAIS GCCINH = 0x6, DW TXAIS TCMINH = 0x2, and DW TXAIS APSINH = 0x0 . Figure 39. ODUk-AIS (MFAS, SM, FTFL, TCM2, GCC1, and GCC2 are Inhibited) Agere Systems Inc. 77 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 8.1 Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) An AIS signal is generated in case of a layer defect or an open connection . Table 46. Digital Wrapper AIS Insert Byte Register Summary Function AIS Insertion Enable . OCI Insertion Enable . Fixed Pattern Byte Insertion Enable. Locked or Fixed Signal Pattern to Be Inserted : 0 = Locked . 1 = Fixed. Fixed Pattern Byte : 0x00 = Open Connection Indication/AI I Os . OxFF = Layer Defect/Al1 1 s (default). Number of Multiframe (MFAS) Bytes After OA2 (see Table 25 on Page 57). Loss-of-Clock AIS Inhibit. When Set to Logic 1, the AIS Insert is Inhibited in Case of Loss-of-Clock (LINE TX83LOC) . Out-of-Frame AIS Inhibit. When Set to Logic 1, the AIS Insert is Inhibited in Case of Out-of-Frame (FRM TXOOF) . Loss-of-Frame AIS Inhibit. When Set to Logic 1, the AIS Insert is Inhibited in Case of Loss-of-Frame (FRM TXLOF) . Loss-of-Signal AIS Inhibit. When Set to Logic 1, the AIS Insert is Inhibited in Case of Loss-of-Signal (FRM TXLOS). Receive AIS Condition Inhibit. Receive OCI Condition Inhibit. Receive Other Fixed Pattern Condition Inhibit. FTFL Inhibit during AIS. Inhibit TCMO-TCM5 overwritten by AIS/OCI/LCK1 . Inhibit GCCO-GCC2 overwritten by AIS/OCI/LCK. Inhibit APS/PCC inhibit overwritten by AIS/OCI/LCK. Inhibit TCMO-TCM5 overwritten by AIS/OCI/LCK1 Inhibit. Register Name (First Occurrence) Register Bits Qty. (R/W) (R/W) (R/W) SO DW-TXAIS_INS DW-TXOCI_INS DW-TXFIX_INS DW-TXLCK-FIX 4 4 4 4 0X2178 0X2178 0X2178 0X2514 DW_TX_CTL AIS 2 SO (R/W) DW-TXFIX-VAL 4 0X2194 DW TX_CTL OA12 PAT-SO (R/W) DW_TX_CTL_AIS_2 SO (R/W) DW-TXOA12 MFAS 4 0X2180 DW-TXLOC_AISINH 4 0X2194 DW_TX_CTL_AIS 2 SO (R/W) DW-TXOOF_AISINH 4 0X2194 DW_TX_CTL_AIS_2 SO (R/W) DW-TXLOF_AISINH 4 0X2194 DW_TX_CTL_AIS_2 SO (R/W) DW_TXLOS_AISINH 4 0X2194 DW-TX-CTL-AIS-2 SO (R/W) DW_TX_CTL_AIS 2 SO (R/W) DW_TX_CTL_AIS 2 SO (R/W) DW TXRXCOND_AISINH DW TXRXCOND OCIINH DW-TXRXCOND FIXINH 4 4 4 0X2194 0X2194 0X2194 DW TX CTL AIS V2 SO DW TXAIS FTFLINH 4 0X2528 DW_TX_CTL_AIS_V2 (R/W) DW_TX_CTL-AIS-V2 (R/W) DW_TX_CTL-AIS-V2 (R/W) DW_TX_CTL-AIS-V2 (R/W) SO DW-TXAIS TCMINH 4 0X2528 SO DW-TXAIS GCCINH 4 0X2528 SO DW-TXAIS_APSINH 4 0X2528 SO DW_TXAIS-TCMSTAT_ IAEINH 4 0X2514 DW_TX_CTL_TOP_2_SO DW-TX_CTL TOP_2 SO DW-TX-CTL TOP_2 SO DW_TX CTL-TOP-V2 (RNV) 1st Addr (hex) 1 . If TCM insert during AIS/OCI/LCK, STAT [2 :0] will be inserted 001 for normal operation mode . (IAE in-use is not available .) 78 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) 8.1 Functional Description of Digital Wrapper Insert (continued) 8.1 .11 DWAC Insert Four insert digital wrapper access channels (DWAC) are provided on chip along with four drop DWACs. These channels provide most of the monitoring and insert capabilities for the FEC/DW overhead bytes. The insert DWAC consists of four signals per channel (total of four DWAC channels) : -Output clock at -10 .455 MHz (10 Gbits/s mode (slice 0 only) and quad 2 .5 Gbits/s mode). -Output superframe sync (-326.7/-81 .68 kHz-10 Gbits/s (FEC/DW), -81 .68/-20 .42 kHz-quad 2.5 Gbits/s (FEC/DW)) coincident with the MSB (most significant bit) in quad 2.5 Gbits/s mode, or MSN (most significant nibble) in 10 Gbits/s mode of the first byte in frame 0. The sync pulse is provided on the rising edge of DWAC clock . At WAS = 0x00, sync pulse is set high for two clock cycles. - Input data: 4 bits (a nibble) in 10 Gbits/s mode and 1 bit per stream in quad 2.5 Gbits/s mode. - Input insert enable signal : active-high signal coincident with the first two MSB[7:6] of the byte to insert in quad 2.5 Gbits/s mode or coincident with the two MSNs in 10 Gbits/s mode. See Table 28 on page 61 . All the DWAC bytes insertion control is described below. The data stream format from the device is identical to Figure 33 on page 66. SYNC ENABLE DATA TRANSMITTED SERIALLY OR NIBBLE WIDE ------------------------------- " ,, DW DWAC TXCLKO DW DWAC TXSYNC DWAC DW TXDATA[3:0] . OH1 [7] _ OH1 [6] . . . . .' _ OH1 [7 :4] OH1 [3_0] --------- -------------------------- ~------ DWAC DW TXDATA EN[0] i Note : See the Timing Characteristics section in the Hardware Design Guide for the Transmit Transport Overhead Access Channel section . Figure 40. Transmit DWAC Frame Definition Table 47. DWAC Byte Insertion Control DWAC Enable Data Value DWAC-DW-TXDATA-EN[3 :0]/[0] Sampled at [MSB], [MSB - 1]/[MSN], [MSN - 1] Positions Only. 11 00 01/10 Agere Systems Inc. Description Insert data from the serial DWAC input. Default standards . Passthrough (if enabled, otherwise default standard is inserted) . 79 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 Operational Description July 2002 Digital Wrapper Insert (continued) 8.1 Functional Description of Digital Wrapper Insert (continued) Table 48. Transmit DWAC Insertion Register Summary Function Register Name (First Occurrence) DWAC Byte Insertion Enable I DW DWAC TX CTL SO (R/W) 8.1 .12 Register Bits I Qty. DWAC TXINS I 4 1st Addr (hex) I Ox21C4 PRBS Insert and Monitor A pseudorandom sequence (PRBS : 229 _ 1 or 231 _ 1) data can be inserted into payload locations (exclude overhead and check bits locations). When the pseudorandom sequence is inserted, a 229 _ 1 or a 231 _ 1 sequence is used in the payload data bytes with the pattern starting after each of the overhead bytes. In addition, all overhead bytes function normally. The pseudorandom pattern uses either a 229 _ 1 (536, 870, 911 bits), or a 231 _ 1 (2, 147, 483, 647 bits) pattern length specified in 0.150. The 229 _ 1 sequence is generated by a 29-stage shift register whose twenty-seventh and twenty-ninth stage outputs are added and fed back to the first stage. The output of the last stage can be inverted (which yields a sequence with up to 29 zeros) . The 231 _ 1 sequence is generated by a 31-stage shift register whose twenty-eighth and thirty-first stage outputs are added and fed back to the first stage. The output of the last stage can be inverted (which yields a sequence with up to 31 zeros). In quad 2 .5 Gbits/s mode, the PRBS macro generates four independent 32-bit PN sequences . In 10 Gbits/s mode, all 128 bits are generated as one PN sequence . The PRBS pattern can be inverted by setting a single control bit. Only the slice 0 control bit is valid in 10 Gbits/s mode. A single-bit error can be inserted. The PRBS generator injects a single error bit at the MSB in the test pattern . The most significant bit (MSB) of each slice is inverted . For example, in quad 2 .5 Gbits/s, the 127th (slice 3), 95th (slice 2), 64th (slice 1), and 31th (slice 0) are used. In 10 Gbits/s mode, only the 127th is used. Table 49. PRBS Insert Control Bit Register Summary Function Register Name (First Occurrence) Register Bits Qty. Transmit PRBS Pattern (Payload Only) Insertion Enable Transmit PRBS Pattern Sequence Selection : 0=229_1 1=231_1 Transmit PRBS Inverted Pattern (Payload Only) Insertion Enable Transmit PRBS Error Insert Bit (1 error bit per 128 bits in 10 Gbits/s mode, and 1 bit per 32 bits in 2.5 Gbits/s mode) DW_TX_CTL_TOP_2_SO (R/W) DW_TXPRBS_INS 4 0x2178 DW PRBS CTL SO (R/W) DW_TXPRBS 29 31_PAT 4 0x21 EO DW PRBS CTL SO (R/W) DW_TXPRBS INV 4 Ox21E0 DW PRBS CTL SO (R/W) DW_TXPRBS_1 BERRINS 4 0x21 EO 80 1st Addr (hex) Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 8 8.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Insert (continued) Functional Description of Digital Wrapper Insert (continued) PRBS data in payload locations (exclude overhead and check bytes location) can be monitored by the PRBS monitor at the input pins. A pseudorandom sequence pattern (either 231 - 1 or 229 - 1) can be detected . When 32 consecutive bits match the pattern, the pattern sync state declares itself in-sync. If eight or more consecutive mismatches are in the payload sequence, the corresponding pattern sync state declares itself out-of-sync . In 10 Gbits/s mode, the payload goes into sync if the most up-to-date 32 bits (LSB) are matched, and declares out-of-sync if the most up-to-date of the last 32 bits (LSB) has eight or more consecutive mismatches in the payload sequence . Note : If 32 bits match and/or eight mismatches occur in less up-to-date patterns [127:32], sync state will be ignored . The pattern sync state also provides an interrupt alarm and persistency. The PRBS can also monitor for an inverted pattern via the microprocessor. Any bit error occurring after the monitor is in the in-sync state is reported by an 8-bit counter. This counter (DW_TXPRBS ECNT) will contain the number of bit errors (clear-on-read toggle from the microprocessor) . Table 50. PRBS Monitor Register Summary Function Register Name (First Occurrence) Register Bits Qty. Transmit PRBS Monitor Pattern (payload only) Monitor is Expected to be Inverted When Set Transmit PRBS Monitor Pattern Sequence Selection : 0=229-1 1 =231-1 Monitored PRBS Pattern Sync Interrupt Alarm Bit Monitored PRBS Pattern Sync Mask Bit DW_PRBS_CTL_V2 S0 (RW) DW_TXPRBS_MON INV 4 1st Addr (hex) 0x2530 DW_PRBS_CTL_V2_S0 (RW) DW_TXPRBS_MON_29_ 31 - PAT 4 0x2530 DW_ALARM_V2 S0 (W1 C) DW_MASK_V2 S0 (RW) DW_TXPRBS SYNC_A 4 0x2030 DW-TXPRBS SYNC M 4 Ox206C Monitored PRBS Pattern Sync Persistency Bit When the PRBS Pattern (Payload Only) Detects 32 Matches in a Row, It Declares Itself In-Sync and the Error Detector is Enabled . If the Device Detects Eight Consecutive Mismatches, the Test Pattern Detector Declares Itself Out-of-Sync and Starts Searching Again. 0 = In-Sync . 1 = Out-of-Sync. Monitored PRBS Error Pattern Counter. The PRBS Monitor Counts the number of Times the Input Data Differs from the Expected Value in an 8-Bit Counter that Holds its Count when it Reaches the Maximum Value of 255 . This Counter is Reset when Ready by the Microprocessor, and is not Affected by the PM RST Signal (clear-on-read). DW_PERSIST_V2 SO (RO) DW_STATE_V2 S0 (RO) DW_TXPRBS SYNC P 4 Ox20A0 DW_TXPRBS SYNC 4 Ox20D0 DW_TX_CNT_PRBS_ V2 S0 (COR) DW_TXPRBS_ECNT 4 0x2604 Agere Systems Inc. 81 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 8 Digital Wrapper Insert (continued) 8.1 Functional Description of Digital Wrapper Insert (continued) 8.1 .13 Digital Wrapper Check Byte Insert The check bits location can be set to pass through its value by setting a control bit . Otherwise, all check bits are set to zero. Check byte passthrough is not available when the transmit data is generated from the transmit elastic store. Table 51 . DW Insert Check Byte Insertion Register Summary Function Transmit Check Bits Location Zero Insertion : 0 = Check Bits are Set to Zero 1 = Check Bits Pass Through . Transmit No Fix Stuff Enable (10 Gbits/s DW mode only) i .e., 119th of 0-254 Columns is Reserved for a Stuff Column 9 9.1 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) DW_TX_CTL_TOP_2_S0 (R/W) DW_TX_CBPASS 4 0x2178 DW_TX_CTL_TOP_V2_S0 (RW) DW_TX_NO_FS 4 0x2514 Strong FEC Supermacro Reed-Solomon (RS) Encoder Functional Description of RS Encoder The RS encoder calculates and inserts check bytes which are remainders after polynomial division of the payload by generating polynomial, g(z) = (z + 1) (z + al) . . . (z + a15), where a is a root of the binary primitive polynomial Xs+X4+X3+X2+1 . Data arrives to the RS encoder grouped as four slices of 32 bits. Each slice has four independent check byte calculators. Each calculator accepts 239 bytes of payload data followed by 16 bytes of all-zeros data, and generates 16 bytes of check data. The check bytes replace all 16 incoming zero bytes unless the RS encoder is in bypass mode. Table 52. RS Encoder Register Summary Function RS Encoder Mode Control : 0 = Normal . 1 = Bypass . 82 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) RS_TX_CTL TOP S0 (R/W) RS_TX_ENC 4 Ox221A Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 10 with Strong/Weak FEC and Digital Wrapper Strong FEC Supermacro Scrambler 10.1 Functional Description of Strong FEC Supermacro Scrambler The scrambler optionally scrambles incoming data. The scrambling sequence can be selected between two different polynomials : x7 + x + 1 and x16 + Xl2 + X3 + X + 1 . When scrambling is enabled, the whole FEC/DW frame is scrambled, with the exception of the framing byte, by a selected polynomial (x7 + x + 1 or X16 + X12 + X3 + X + 1). Scrambling is initiated at each frame on the first bit which follows the framing byte. The first bit sequence of the scrambler is all 1 s. DATA IN DQI-L-i DQH-i DQH-i DQH-i DQH-i DQH~DQ X7+x+1 SCRAMBLED DATA OUT CLOCK Figure 41 . x7 + x + 1 Frame Synchronous Scrambler (6.975) DATA IN DQ DQ t t DQ DQ DQ t DQ DQ DQ DQ low t X16+x12+x3+x+1 SCRAMBLED DATA OUT CLOCK Figure 42. X1s + X12 + X3 + x + 1 Frame Synchronous Scrambler (6.709) Table 53 . Scrambler Register Summary Function Scrambling Control : 0 = Off. 1 = On . Scrambling Sequence Select : 0 = 7-bit (X7 + X + 1). 1=16-bit(X16+X12+X3+X+1) . Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) RS TX_CTL_TOP SO (R/W) RS TX_SCR 4 Ox221A RS TX_ CTL_TOP SO (R/W) RS_TX_SCR_7-16 POL 4 Ox221A 83 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 11 11 .1 Operational Description July 2002 Strong FEC Supermacro Error Insert Functional Description of Error Insert The error insert inserts various types of errors for RS code testing . For each slice, an error insert block accepts 32 bits of data. There is a total of four slices instantiated to make the 128-bit wide data for 16-way and 64-way 10 Gbits/s mode. A 32-bit mask register corresponds to the 32-bit wide data bus for the error insertion . When the mask bit is set to logic 1, the corresponding data bit is inverted. The number of skipping clock cycles can be programmed through the microprocessor. Error bits combining with the number of skipping clock cycles can be repeated by using a control bit bus . The first column of error can be chosen via the microprocessor. The stream of errors start when there is a 0 => 1 transition . See Figure 43, Example of Error Insert Setup Diagram, on page 85 . Ensure the inserted error bits are within the range as noted in Table 54. Table 54. Error Insert Register Summary Function Mask for the Error Insertion on the 32-Bit Data Bus Number of Skipping Clock Cycles Between 32-Bit Error Pattern Number of Repeating Clock Cycles Between 32-Bit Error Pattern Start Column (Note : In 16x2.5G mode, 0-1019 ; 16x10G mode, 0-254; 64x10G mode, 0-1019 . Out of range values default to 0.) Error Start Control Bit Error Insert Finish Alarm Error Insert Finish Mask Error Insert Finish State 84 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 0x2226/ 0x2227 RS-TX-CTL-ERRMSK1-SO/ RS-TX-CTL-ERRMSK0-S0 (R/W) RS_TX_CTL_ERRSKIP S0 (R/W) RS_TXERR1_MASK/ RS-TXERRO-MASK 4 RS-TXERR-SKIP 4 0x221 E RS_TX_CTL-ERRREPT-SO (R/W) RS-TXERR-REPEAT 4 0x2222 RS TX_CTL-ERRCOL SO (R/W) RS-TXERR-COL 4 Ox222F RS_TX_CTL_TOP_SO (R/W) RS-ALARM SO (W1C) RS_MASK_2_S0 (R/W) RS STATE SO (RO) RS-TXERR-START RS-TXERR-A RS-TXERR-M RS TXERR 4 4 4 4 Ox221A 0x2028 0x2064 Ox20C8 Agere Systems Inc. AdLib OCR Evaluation 11 C-O Strong FEC Supermacro Error Insert (continued) 11 .1 Functional Description of Error Insert (continued) N O -' NO 7 COLUMN (CLOCK CYCLE) 0 n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 v (D . . N C1 0 1 rt_ O 7 2 3 4 m 5 II M 7 8 9 10 II 0 11 12 13 H_ m 14 n O O a m 0 O 27 rt O SL (q O rtC) O a 7 28 29 30 31 RS TXERR START Example : ( O -n 5' m cw nz RS TXERR SKIP[7:0] = 0x2 RSTXERRREPEAT[9 :0] = 0x4 RS_TXERR COL[11 :0] = 0x4 RS_TXERR1_MASK = 0x0 RS TXERRO MASK = 0x0065 a 5' to Figure 43. Example of Error Insert Setup Diagram 0 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 12 12.1 Operational Description July 2002 Interleaver Functional Description of Interleaver The RS encoder performs interleaving of code blocks in order to enhance the immunity of a transmission system to burst errors, in byte manner. In 10 Gbits/s mode, all four interleavers work in synchronization . The read/write addresses of slice 1, slice 2, and slice 3 are synchronized with slice 0, which is a master slice. 13 13.1 Deinterleaver Functional Description of Deinterleaver The RS decoder performs deinterleaving of code blocks in order to enhance the immunity of the transmission system to burst errors, in byte manner. In 10 Gbits/s mode, all four deinterleavers work in synchronization. The read/write addresses of slice 1, slice 2, and slice 3 are synchronized with slice 0, which is a master slice. 14 Framer Receive Direction Requirements The framer functionality of the receive direction is identical to the transmit direction in Section 7, Strong FEC Supermacro FEC/DW Framer (LOS, OOF, LOF), on page 55. Table 55. LOS Register Summary Function LOS Detect Time Threshold LOS Interrupt Alarm LOS Alarm Mask LOS Persistency LOS State 86 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) FRM RX_CTL LOSDET SO (R/W) FRM RXLOS_DET 4 Ox22A0 FRM ALARM S0 (W1 C) FRM_MASK_SO (R/W) FRM_PERSIST_SO (RO) FRM STATE SO (RO) FRM RXLOS A FRM_RXLOS_M FRM_RXLOS_P FRM RXLOS 4 4 4 4 Ox202C 0x2068 Ox209C Ox20CC Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 14 with Strong/Weak FEC and Digital Wrapper Framer Receive Direction Requirements (continued) Table 56. Framer Register Summary Function Framer Disable OA1 Frame Byte Value OA2 Frame Byte Value Number of Repeat OA1 Byte (same as OA2): 0 = One OA1's, One OA2's 7 = Eight OA1's, Eight OA2's See Table 25 on Page 57 Number of Framing Pattern Pairs (OA1/OA2) Used to Transition Between Out-of-Frame to In-Frame State (OOF, 1 => 0) Number of Framing Pattern Pairs (OA1/OA2) Used to Transition Between In-Frame to Out-of-Frame State (OOF, 0 => 1) Out-of-Frame Set Out-of-Frame Clear Out-of-Frame Interrupt Alarm Out-of-Frame Interrupt Alarm Mask Out-of-Frame Persistency Out-of-Frame State Agere Systems Inc. I Register Name (First Occurrence) Register Bits Qty. FRM RX CTL OOF 3 SO FRM RX DISABLE 4 1st Addr (hex) Ox22AC FRM_RX_CTL OA12 SO (R/W) FRM_RX_CTL OA12 SO (R/W) FRM RX_CTL-OA12 PAT-3 SO (R/W) FRM_RXOA1 VAL FRM_RXOA2 VAL FRM RXOA12 PAIRS 4 4 4 Ox22A4 Ox22A4 Ox22A8 FRM RX_CTL-OA12 PAT-3 SO (R/W) FRM-RXOA12 PAIRCLR 4 Ox22A8 FRM RX_CTL-OA12 PAT-3 SO (R/W) FRM RXOA12 PAIRSET 4 Ox22A8 FRM RX CTL OOF 3 SO FRM RXOOF SET 4 Ox22AC FRM RX CTL OOF 3 SO FRM RXOOF CLR 4 Ox22AC FRM_ALARM SO (W1 C) FRM RXOOF_A 4 Ox202C FRM MASK_SO (R/W) FRM-RXOOF M 4 0x2068 FRM PERSIST-SO (RO) FRM-RXOOF P 4 Ox209C FRM STATE SO (RO) I FRM-RXOOF I 4 I Ox20CC 87 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 14 Framer Receive Direction Requirements (continued) Table 57. Loss-of-Frame Control Register Summary Function Loss-of-Frame Loss-of-Frame Loss-of-Frame Alarm Loss-of-Frame Alarm Mask Loss-of-Frame Loss-of-Frame 15 15.1 Register Name (First Occurrence) Register Bits Qty. Set Clear Interrupt FRM_RX_CTL_LOF_2_SO (R/W) FRM_RX_CTL_LOF_2_SO (R/W) FRM_ALARM SO (W1 C) FRM_RXLOF_SET FRM RXLOF_CLR FRM RXLOF_A 4 4 4 1st Addr (hex) 0x22130 0x22130 Ox202C Interrupt FRM MASK SO (R/W) FRM RXLOF M 4 0x2068 FRM_PERSIST_SO (RO) FRM STATE SO (RO) FRM_RXLOF_P FRM RXLOF 4 4 Ox209C Ox20CC Persistency State Strong FEC Supermacro Descrambler Functional Description of Descrambler The descrambler optionally descrambles incoming data. The scrambling sequence can be selected between two different polynomials : x7 +x+ 1 or x16 +X12+ X3 +X+ 1 . Once descrambling is requested, the whole FEC/DW frame is descrambled, with the exception of the framing byte, by a selected polynomial initiated at each frame on the first bit which follows the framing byte. The first bit sequence of the descrambler is all ones. Table 58. Descrambler Register Summary Function Rx Descrambling Control : 0 = Off. 1 = On . Rx Descrambling Sequence Select : 0 = 7-bit (X7 + X + 1). 1 = 16-bit (X16 + X12 + X3 + X + 1) . 88 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) RS RX_CTL_TOP SO (R/W) RS RX_DSCR 4 0x2200 RS RX_ CTL_TOP SO (R/W) RS_ RX_DSCR_7- 16 POL 4 0x2200 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 16 16.1 with Strong/Weak FEC and Digital Wrapper Reed-Solomon (RS) Decoder Functional Description of RS Decoder The RS decoder detects and corrects transmission errors, and calculates and reports incoming BER based on the exact number of corrected bits. When the FEC/DW framer is in the OOF, LOF, or LOS state, the associated decoder is disabled. 16.1.1 Error Detect and Correct Data arrives to the RS decoder grouped as four slices of 32 bits. Each slice has four independent error detect-and-correct blocks. Each block accepts 8-bit wide RS code blocks, and outputs 8-bit wide corrected code blocks . The number of corrected bits and the number of uncorrectable blocks are counted and reported to the BER monitor block, per slice. If uncorrectable errors are detected, correction operation is turned off automatically on a block-by-block basis and the number of corrected bit errors is not counted . There are four operational decoding modes . Monitor . Shutdown . Decode Only . Correct When the RS decoder is set to the monitoring mode, the error is detected and monitored, but data is not corrected without delay. When set to shut-down mode, the decoding function is disabled and data is bypassed without delay. When set to decode-only mode, the error is detected and monitored, but data is not corrected with delay. When set to correct mode, the error is detected and corrected . The transition between decode-only and correct are hitless. Table 59. RS Decoder Register Summary Function RS Decoder Mode Control 16.1.2 Register Name (First Occurrence) I RS RX-CTL TOP SO (R/W) Register Bits I RS RX-DEC I Qty. 1stAddr (hex) 4 I 0x2200 BER Monitor The Reed Solomon statistics count correctable errors that are detected and corrected in the RS decoder. The monitoring of the line BER before correction can be done through the knowledge of the exact number of corrected bits. The errors that remain uncorrected after forward error correction can be considered negligible in the computation of BER, for low error rates. Agere Systems Inc. 89 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 16 Operational Description July 2002 Reed-Solomon (RS) Decoder (continued) 16.1 Functional Description of RS Decoder (continued) 16.1.3 Error Count The corrected bits and the uncorrectable blocks are accumulated per slice in 16-bit saturating counters based on either bit or block errors . In bit mode, each corrected error (or uncorrectable block) causes the counter to increment. If block error is selected, each FEC/DW frame which has a corrected error (or uncorrectable block) causes the counter to increment by only one . The counter stops at the maximum value and will not roll over, and is cleared by the PMRST signal . Table 60. RS Error Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) RS Error Count Control RS Rx 0 => 1 Corrected Bit Counter RS Rx 1 => 0 Corrected Bit Counter RS Rx Corrected Bit Counter RS Rx Uncorrectable Block Counter RS RX_CTL_TOP SO (R/W) RS_ERR_BITBLK 4 0x2200 RS_RX_CNT_OT01_ERRBITO_SO/ RS_RX_CNT_OT01_ERRBIT1_SO (RO) RS_RX_CNT_1T00_ERRBITO_SO/ RS_RX_CNT_1T00_ERRBIT1_SO (RO) RS_RX_CNT_ERRBITO_SO/ RS_RX_CNT_ERRBIT1_SO (RO) RS_RX_CNT_ERRBLKO_SO/ RS RX_CNT ERRBLK1 SO (RO) RS_RX_ERR00_OT01_BITCNT/ RS_RX_ERR01_OT01_BITCNT 4 Ox254A/ Ox254B RS_RX_ERRO_1T00_BITCNT/ RS_RX_ERR1_1T00_BITCNT 4 0x2553/ 0x2554 RS_RX_ERRO_BITCNT/ RS_RX_ERR1_BITCNT RS RX_UNCO_BLKCNT/ RS RX_UNC1-BLKCNT 4 Ox234C/ Ox234D 0x2355/ 0x2356 16.1.3.1 4 BER Detecting and Reporting The corrected errors are used to detect SF and SD conditions. The BER threshold for each defect is separately provisionable for each slice over a range of 1 x 10-N values, where N = 3 to 9. The detection times and error limits used to detect and clear both defects are dependent on the provisioned BER threshold, as shown in Table 61 . The values shown in Table 61 are the powerup defaults and are dependent on the mode selected (2.5 Gbits/s or 16-way/64-way 10 Gbits/s). These values can be changed through the corresponding registers and are common to all slices. The clearing BER threshold for each defect is always one-tenth of the detection threshold . As can be seen in Table 61, the range of possible detect threshold are 1 x 10-3 to 1 x 10-9, which results in clear thresholds of 1 x 10-4 to 1 x 10-10 . For example, to detect SD at 1 x 10-5 BER in 2 .5 Gbits/s mode, the detection time is 3.2 ms and the detect error limit is 83. The clearing would take place at 1 x 10-6 BER, with a clearing time of 51 .2 ms and a clearing error limit of 665 . Figure 44 on page 91 illustrates SD detection and clearing using the default values . 90 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 16 with Strong/Weak FEC and Digital Wrapper Reed-Solomon (RS) Decoder (continued) 16.1 Functional Description of RS Decoder (continued) Table 61 . BER Threshold Time and Error Limits for Line SD and SF Detection Provisioned BER Threshold Detection Time 2.5 Gbits/s 10 Gbits/s 2.5 Gbits/s 10 Gbits/s 2.5 Gbits/s 10 Gbits/s 1 x 10-3 1 x 10-4 1 x10-5 1 x 10-6 1 x 10-7 1 x 10-8 1 x 10-9 1 x 10--10 0.4 ms 0.4 ms 3.2 ms 51 .2 ms 409 .6 ms 3200 ms 52.4s 419.4s 0.1 ms 0.1 ms 0.8 ms 10.3 ms 102 .4 ms 800 ms 10.6s 104 .8s 1044 104 83 133 106 85 136 - 1044 104 83 133 106 85 136 - 520 415 665 530 425 680 545 520 415 665 530 425 680 545 I I Detect Error Limit I I Clear Error Limit I I 665 U O w m 0 w g U U Q p U 83 i IN i 14 01 SD DETECTION WINDOW SD CLEARING WINDOW TIME (MS) Figure 44. Example of SD Detection (10-5 BER) and Clearing (10-6 BER) In 10 Gbits/s mode, the thresholds are compared against the sum of the four slice SF and SD counts . A detected SF or SD defect causes a corresponding maskable interrupt status bit to be set . The SD/SF BER control bits select the bit error rate for a particular slice. These control bits then select the detection time, the detect error limit, and the clear error limits for each slice. The detect error limit and the clear error limit registers contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper bit for a time unit specifier. For the detection time register, the value contained in the lower 15 bits is either specified in 0.1 ms units (upper bit = 0) or in 0.1 s units (upper bit = 1). Note that the receive sync pulse is used as the timing reference . Agere Systems Inc. 91 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 16 16.1 Operational Description July 2002 Reed-Solomon (RS) Decoder (continued) Functional Description of RS Decoder (continued) A fixed windowing scheme is used for SD/SF detection . The window size is determined by the value in the detection time register for the specified bit error rate. An SD or SF alarm is declared immediately when the accumulated error count exceeds the value specified in the detect error limit register. If this error limit is not reached by the end of the window, then the accumulated error count is reset to zero. When an SD or SF alarm is declared, the accumulated error count resets and clearing begins using the bit error rate threshold that is one-tenth of the specified value, along with the corresponding detection time registers . Clearing of the SD or SF alarm only occurs at the end of the window when the accumulated error count is less than the value specified in the clear error limit register. The RS decoder reports current BER so the customer knows which is a current BER . For this, seven BERs are monitored at the same time. Once a certain level BER is detected, lower-level BERs are ignored and the highest-level of BER is reported as a current BER, i .e., when 1 x 10-4 BER is detected, BERs from 1 x 10-5 to 1 x 10-9 are ignored and 1 x 10--4 is reported as a current BER . SD THRESHOLD SD DETECT CORRECTED BITS - CURRENT BER SF DETECT SF THRESHOLD Figure 45. RS Decoder Block Diagram 92 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 16 16.1 with Strong/Weak FEC and Digital Wrapper Reed-Solomon (RS) Decoder (continued) Functional Description of RS Decoder (continued) Table 62. RS Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) RS SD Threshold Select RS RX_CTL_TOP S0 (R/W) 4 0x2200 RS SF Threshold Select RS RX_CTL TOP S0 (R/W) RS_RXBER_SDTHRESHOLD RS_RXBER_SF_ THRESHOLD RS RXBER SD DET A RS_RXBER_SF_DET_A RS_RXBER_SD_DET_M RS RXBER SF DET M RS_RXBER_SD_DET_P RS_RXBER_SF_DET_P RS RXBER SD DET RS_RXBER_SF_DET RS RXBER_REPORT 4 0x2200 4 4 4 4 4 4 4 4 4 0x2028 0x2028 0x2064 0x2064 0x2098 0x2098 Ox20C8 Ox20C8 Ox235E RS RXBER DETTIMEO RS_RXBER_DETTIME1 RS_RXBER_DETTIME2 RS RXBER DETTIME3 RS_RXBER_DETTIME4 RS_RXBER_DETTIME5 RS RXBER DETTIME6 RS_RXBER_DETTIME7 RS_RXBER_SETO RS RXBER SET1 RS_RXBER_SET2 RS_RXBER_SET3 RS RXBER SET4 RS_RXBER_SET5 RS_RXBER_SET6 RS RXBER CLRO RS_RXBER_CLR1 RS_RXBER_CLR2 RS RXBER CLR3 RS_RXBER_CLR4 RS_RXBER_CLR5 RS RXBER CLR6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x2204 0x2205 0x2206 0x2207 0x2208 0x2209 Ox220A 0x22013 Ox220C Ox220E 0x2210 0x2212 0x2214 0x2216 0x2218 Ox220D Ox220F 0x2211 0x2213 0x2215 0x2217 0x2219 RS RS RS RS RS RS RS RS RS SD Detect Interrupt Alarm SF Detect Interrupt Alarm SD Detect Mask SF Detect Mask SD Detect Persistence SF Detect Persistence SD Detect State SF Detect State BER Report RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS BER-3 Detection Time BER-4 Detection Time BER-5 Detection Time BER-6 Detection Time BER-7 Detection Time BER-8 Detection Time BER-9 Detection Time BER-10 Detection Time BER-3 Detect Error Limit BER-4 Detect Error Limit BER-5 Detect Error Limit BER-6 Detect Error Limit BER-7 Detect Error Limit BER-8 Detect Error Limit BER-9 Detect Error Limit BER-4 Clear Error Limit BER-5 Clear Error Limit BER-6 Clear Error Limit BER-7 Clear Error Limit BER-8 Clear Error Limit BER-9 Clear Error Limit BER-10 Clear Error Limit Agere Systems Inc. RS ALARM SO (W1 C) RS_ALARM_S0 (W1 C) RS-MASK-2_SO (R/W) RS-MASK-2 SO (R/W) RS-PERSIST_SO (RO) RS-PERSIST_SO (RO) RS STATE SO (R0) RS-STATE_SO (RO) RS RX_CNT_BERREP SO (RO) RS RX CTL BERDTO (R/W) RS_RX_CTL_BERDT1 (R/W) RS_RX_CTL_BERDT2 (R/W) RS RX CTL BERDT3 (R/W) RS_RX_CTL_BERDT4 (R/W) RS_RX_CTL_BERDT5 (R/W) RS RX CTL BERDT6 (R/W) RS_RX_CTL_BERDT7 (R/W) RS_RX_CTL_BERSETO (R/W) RS RX CTL BERSET1 (R/W) RS_RX_CTL_BERSET2 (R/W) RS_RX_CTL_BERSET3 (R/W) RS RX CTL BERSET4 (R/W) RS_RX_CTL_BERSET5 (R/W) RS_RX_CTL_BERSET6 (R/W) RS RX CTL BERCLRO (R/W) RS_RX_CTL_BERCLR1 (R/W) RS_RX_CTL_BERCLR2 (R/W) RS RX CTL BERCLR3 (R/W) RS_RX_CTL_BERCLR4 (R/W) RS_RX_CTL_BERCLR5 (R/W) RS RX CTL BERCLR6 (R/W) 93 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 17.1 Operational Description July 2002 Digital Wrapper Drop Functional Description of Digital Wrapper Drop The digital wrapper drop is used for overhead monitoring after the RS decoder (checkbyte calculate and correct) . For each slice, the digital wrapper drop block accepts 32 bits of data. There is a total of four slices instantiated to create a 128-bit wide block for 16-way and 64-way 10 Gbits/s mode. . All FEC/DW frame overhead dropping and monitoring functions supported by the DW in the receive direction are summarized in the following list: -Internal FEC overhead bytes monitor. -BIP-8 monitor (also has an available TCM byte) . -1311 monitor, BDI detect, IAE detect, and BEI monitor (also has an available TCM byte) . -AIS, OCI, or other fixed pattern detect (STAT monitor in TCMi and PM bytes). -DWAC drop. - Insertion of AIS, OCI, or other fixed pattern . -PRBS monitor (also provides insert) . All monitors are disabled if the receive direction, loss-of-signal, loss-of-clock, and out-of-frame alarms are disabled. In the loss-of-frame case, the monitor continues functioning if its associate AIS inhibit is set . Whenever the continuous N-times detect (CNTD) signals are defined, they require not only that the monitored signal be consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the status can be updated . N can range from 1 to 15. Programming a CNTD block with a value of 0 turns off the CNTD detection . In the receive direction, 128-bit input data will be retimed and passed through without any processing to either DW ES RXDATA[127 :0] or DWFEC SYS RX83DATA[127 :0] . (Note that AIS insertion may need to be inhibited .) In a loopback mode, the 128-bit input data can be selected from DW RS TXDATA[127 :0] . 17.1.1 Internal FEC Overhead Bytes Monitor (OHO to OH3) There are up to four overhead bytes per FEC or DW frame which can be detected and reported via the microprocessor. The provisioning location is programmable and operates identically to the digital wrapper OHO to OH3 insert. See Section 8 .1, Functional Description of Digital Wrapper Insert, on page 61 for the programming example . . The monitored overhead byte is updated via a microprocessor after N consecutive consistent occurrences (frames) of a new pattern overhead byte is received . They can be grouped as the following : -Four 1-byte monitors. -Two 2-byte monitors. -One 3-byte and one 1-byte monitor. -One 4-byte monitor. Multiple bytes do not need to be contiguous. Four bytes can be inserted from internal register per stream . Table 63. OHO-OH3 Monitor Byte Group Indication Summary Control Bits DW RXOH0123 GRP[1 :0] 00 01 10 11 Description Valid CNTD Control Value Four 1-Byte Group Two 2-Byte Groups One 1-Byte and One 3-Byte Group I One 4-Byte Group I OH3, OH2, OH1, OHO OH2, OHO OH1, OHO OHO Any changes to the receive overhead byte state must be reported to its interrupt alarm and persistency register bit . The interrupt alarm mask bit is also provided. 94 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 17.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) Table 64. Internal FEC Overhead Byte Monitor Register Summary Function Overhead Byte Monitor Group Indication : 00 = Four 1-byte . 01 = Two 2-byte. 10 = One 1-byte and one 3-byte. 11 = One 4-byte. Overhead Byte Monitor Interrupt Alarm . Overhead Byte Monitor Interrupt Alarm Mask. Overhead Byte Monitor Value. Continuous N-Times Detect for Receive Overhead Byte (OHO) . (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) Overhead Byte Monitor Frame Location (DW Mode Only). Overhead Byte Monitor Row Location . Overhead Byte Monitor Interrupt Alarm . Overhead Byte Monitor Interrupt Alarm Mask. Overhead Byte Monitor Value. Continuous N-Times Detect for Receive Overhead Byte (0H1) . (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) Overhead Byte Monitor Frame Location (DW Mode Only). Overhead Byte Monitor Row Location . Overhead Byte Monitor Interrupt Alarm . Overhead Byte Monitor Interrupt Alarm Mask. Overhead Byte Monitor Value. Agere Systems Inc. Register Name (First Occurrence) DW RX_CTL_TOP SO (R/W) Register Bits Qty. DW-RXOH0123 GRP 4 1st Addr (hex) 0x2150 DW_ALARM SO (W1 C) DW_RXOHO DET_A 4 0x2020 DW MASK_SO (R/W) DW_RXOHO DET_M 4 Ox205C DW RX_VAL_OH01 SO (RO) DW_RX_CTL_OHO_2_SO (R/W) DW_RXOHO_VAL 4 0x2320 DW_RXOHO_CNTD 4 0x2154 DW_RXOHO FRM 4 0x2154 DW_RX_CTL_OHO 2 SO (R/W) DW_RX_CTL_OHO 2 SO (R/W) DW_ALARM SO (W1 C) DW_RXOHO ROW 4 0x2154 DW_RXOH1 DET_A 4 0x2020 DW MASK_SO (R/W) DW_RXOH1 DET_M 4 Ox205C DW RX_VAL_OH01 SO (RO) DW_RX_CTL_OH1_2_SO (R/W) DW_RXOH1_VAL 4 0x2320 DW_RXOH1_CNTD 4 0x2158 DW_RXOH1 FRM 4 0x2158 DW_RX_CTL_OH1 2 SO (R/W) DW_RX_CTL_OH 1 2 SO (R/W) DW_ALARM SO (W1 C) DW_RXOH 1 ROW 4 0x2158 DW_RXOH2 DET_A 4 0x2020 DW MASK_SO (R/W) DW_RXOH2 DET_M 4 Ox205C DW RX_VAL_OH23 SO (RO) DW_RXOH2_VAL 4 0x2324 95 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 17.1 Operational Description July 2002 Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) Table 64. Internal FEC Overhead Byte Monitor Register Summary (continued) Function Continuous N-Times Detect for Receive Overhead Byte (0H2) . (The valid range for this register is 0x1-OxF. 0x0 is used to turn-off the monitor.) Overhead Byte Monitor Frame Location (DW Mode Only). Overhead Byte Monitor Row Location . Overhead Byte Monitor Interrupt Alarm . Overhead Byte Monitor Interrupt Alarm Mask. Overhead Byte Monitor Value. Continuous N-Times Detect for Receive Overhead Byte (0H3) . (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) Overhead Byte Monitor Frame Location (DW Mode Only). Overhead Byte Monitor Row Location . 17.1.2 Register Name (First Occurrence) DW_RX_CTL_OH2_2_S0 (R/W) Register Bits Qty. DW-RXOH2-CNTD 4 1st Addr (hex) Ox215C DW-RXOH2-FRM 4 Ox215C DW_RX_CTL_OH2 2 S0 (R/W) DW_RX_CTL_OH2 2 S0 (R/W) DW-ALARM SO (W1 C) DW-RXOH2 ROW 4 Ox215C DW RXOH3-DET-A 4 0x2020 DW_MASK_S0 (R/W) DW-RXOH3 DET-M 4 Ox205C DW-RX-VAL-OH23 SO (RO) DW_RX_CTL_OH3_2_S0 (R/W) DW_RXOH3_VAL 4 0x2324 DW-RXOH3-CNTD 4 0x2160 DW-RXOH3 FRM 4 0x2160 DW-RXOH3 ROW 4 0x2160 DW_RX_CTL_OH3 2 S0 (R/W) DW_RX_CTL_OH3 2 S0 (R/W) BIP-8 Monitor (See Figure 32 on Page 65) For each FEC or DW frame, up to three single BIP-8 bytes per slice, even parity, is computed over the i - 2 frame (overhead and check bytes) . In every FEC or DW frame, the received BIP-8 value is extracted and compared to the calculated BI P-8 byte for the previous frame . Three per-slice BIP-8 bytes' locations for monitoring are programmable . In FEC frame, only the row location is used. Errors in the BIP-8 code are tabulated in an internal 27-bit counter based on either bit or block errors, as provisioned for each slice through the BIP-8 mode control bit . In bit mode (selected by default), each BIP-8 bit in error causes the counter to increment . If block error is selected, each BIP-8 code in error causes the counter to increment only once. Regardless of which mode is selected, the value in the counter is transferred to maintenance register on the rising edge of the performance monitoring clock, at which point the counter is cleared . The counter will stop at the maximum value and will not roll over. Twelve BIP-8 monitoring blocks are implemented, corresponding to each slice. In quad 2 .5 Gbits/s mode, all these blocks function independently on 32 bits of data. In 10 Gbits/s mode, the slice 0 block functions on 128 bits of data and the other blocks are disabled. 96 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) 17.1 17.1.3 Functional Description of Digital Wrapper Drop (continued) BII Monitor-BDI Detect and BEI Monitor BDI can be detected via microprocessor control . There are 3 BDI bits per slice, for a total of 12 bits of BDI indication bytes, which can be detected by specifying the location of the frame and the row. In FEC frame mode, only the row location is used. See Figure 33 on Page 66 for BEI and BDI locations in the BII byte. BEI (BIP error per frame) will be accumulated in a counter. BDI bit detect is declared when the monitored BDI bit is set after a number of N consecutive consistent occurrences (frames) . Three sets of BI I byte can be monitored . 17.1.4 OTU Section Monitoring (SM) The following subfields in the SM bytes are monitored . These bytes will use the BIPO set of register bits (DW RXBIPO-DI SABLE, etc .) in the monitor control registers . 17.1.4.1 SM-BIP-8 The BIP-8 is computed over all the bytes of OPUk (overhead and payload) in the nth frame and is compared against the received BIP in the n + 2 frame. The BIP errors (if any) are reported to the transmit overhead processor for insertion of BEI in the corresponding transmit SM byte. These bit errors are also accumulated in an internal register. The content of this internal register is transferred to the corresponding reporting register on performance monitoring reset. The internal accumulating register is then cleared . The internal accumulating counter can be set to count the number of bits (0x0) or blocks (0x1) in error. Table 65. SM BIP-8 Monitor Register Summary Function BIP Calculation Disable. BIP Byte Counter Mode: 0 = Bit Count Mode. 1 = Block Count Mode. BIP Byte Monitor Frame Location (DW mode only) : 00 = Frame N. 01= Frame N+1 . 10= Frame N+2 . 11 =Frame N+3 . BIP Monitor Byte Row Location . DW BIP-8 Error Counter. Agere Systems Inc. Register Name (First Occurrence) DW_RX_CTL_TOP (R/W) -SO Register Bits Qty. 1stAddr (hex) 4 0x2150 DW-RXBIPO-DISABLE DW RX_CTL_BIP SO (R/W) DW_RXBIPO BIT BLK 4 Ox216C DW RX_CTL_BIP SO (R/W) DW RXBIPO_FRM 4 Ox216C DW_RX_CTL_BIP SO (R/W) DW_RXBIPO_ROW 4 Ox216C DW_RX_CNT_BIP00_SO/ DW-RX-CNT_BIP01-SO (RO) DW_RXBIP00_ECNT/ DW-RXBIP01-ECNT 4 0x2328/ 0x2329 97 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 17.1 Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) 17.1.4.2 SM-Backward Error Indication (BEI) These bits indicate the BIP errors in the far end and are accumulated in an internal register. The content of this internal register is transferred to the corresponding reporting register on performance monitoring reset. The internal accumulating register is then cleared . The internal accumulating counter can be set to count the number of bits (0x0) or blocks (0x1) in error. Table 66. SM BEI Monitor Register Summary Function BEI Calculation Disable. BEI Counter Mode: 0 = Bit Count Mode. 1 = Block Count Mode. BII Byte Monitor Frame Location (DW Mode Only): 00 = Frame N. 01= Frame N+1 . 10= Frame N+2 . 11 =Frame N+3 . BII Monitor Byte Row Location. DW BEI Error Counter. 17.1.4 .3 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) DW RX_CTL_TOP_SO (R/W) DW RX_CTL-BII S0 (R/W) DW_RXBE10 DISABLE DW_RXBE10 BIT_BLK 4 4 0x2150 0x2170 DW RX_CTL-BII S0 (R/W) DW RXBI10 FRM 4 0x2170 DW RX_CTL-BII S0 (R/W) DW_RXBI10 ROW 4 0x2170 DW_RX_CNT_BE100_S0/ DW RX CNT BE101 SO (RO) DW_RXBEI00_ECNT/ DW RXBE101 ECNT 4 Ox233A/ Ox233B SM-Backward Defect Indication (BDI) This bit is captured in the corresponding register. A new value is only validated after it has been received for a programmable N consecutive frames. Table 67. SM BDI Monitor Register Summary Function Register Name (First Occurrence) Register Bits BDI Bit Monitor Interrupt Alarm. BDI Bit Monitor Interrupt Alarm Mask. BDI Bit Monitor Persistency. BDI Bit Monitor State. Continuous N-Times Detect and Clear BDI Monitor Byte Detect Condition . (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) DW_ALARM_S0 (W1 C) DW_MASK_S0 (R/W) DW_RXBDIO_DET_A DW RXBDIO DET_M 4 4 0x2020 Ox205C DW_PERSIST_2_SO (RO) DW_STATE_2_SO (RO) DW_RX_CTL_BIICNTD_SO (R/W) DW_RXBDIO_DET_P DW_RXBDI0_DET DW_RXBDIO_CNTD 4 4 4 0x2090 Ox20C0 0x2174 98 Qty. 1stAddr (hex) Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) 17.1 Functional Description of Digital Wrapper Drop (continued) 17.1.4.4 SM-Incoming Alignment Error (IAE) This bit indicates the alignment error in the far end and is captured in the corresponding register. A new value is only validated after it has been received for a programmable N consecutive frames. The bit location for the IAE value is fixed in the SM byte at row 0, column 9, bit 2 . Table 68. SM IAE Monitor Register Summary Function IAE Bit Monitor Interrupt Alarm IAE Bit Monitor Interrupt Alarm Mask IAE Bit Monitor Persistency IAE Bit Monitor State Continuous N-Times Detect and Clear IAE Monitor Byte Detect Condition (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) 17.1.5 Register Name (First Occurrence) DW_ALARM_V2_SO (W1 C) DW_MASK_V2 SO (R/W) DW_PERSIST_V2_SO (RO) DW_STATE_V2_SO (RO) DW_RX_CTL_V2_SO (R/W) Register Bits Qty. 1stAddr (hex) DW_RXIAEO_DET_A DW_RXIAEO DET_M 4 4 0x2030 Ox206C DW_RXIAEO_DET_P DW_RXIAEO_DET DW_RXIAEO_CNTD 4 4 4 Ox20A0 Ox20D0 0x2500 ODU Path Monitoring (PM) The PM bytes are processed identically to the SM/TCM byte (see Section 7.1 .4 on page 60) . These bytes will use the BIP1 set of register bits (DW RXBIP1 DISABLE, etc .) in the monitor control registers . 17.1.5.1 PM-BIP-8 Table 69. PM BIP-8 Monitor Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) BIP Calculation Disable BIP Byte Counter Mode: 0 = Bit Count Mode. 1 = Block Count Mode. BIP Byte Monitor Frame Location (DW Mode Only): 00 = Frame N. 01= Frame N+1 . 10= Frame N+2 . 11 =Frame N+3 . BIP Monitor Byte Row Location DW BIP-8 Error Counter DW_RX_CTL TOP_SO (R/W) DW_RX_CTL BIP SO (R/W) DW RXBIP1-DISABLE DW RXBIP1-BIT_BLK 4 4 0x2150 Ox216C DW RX_CTL BIP SO (R/W) DW_RXBIP1 FRM 4 Ox216C DW RX_CTL BIP SO (R/W) DW_RXBIP1 ROW 4 Ox216C DW_RX_CNT_BIP10_SO/ DW RX CNT BIP11 SO (RO) DW_RXBIP10_ECNT/ DW RXBIP11 ECNT 4 0x2331/ 0x2332 Agere Systems Inc. 99 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 17.1 Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) 17.1 .5.2 PM-Backward Error Indication (BEI) Table 70. PM BEI Monitor Register Summary Function Register Name (First Occurrence) Register Bits Qty. DW RX CTL TOP SO DW RXBE11 DISABLE 4 0x2150 DW-RX-CTL BII SO (R/W) DW_RXBE11 BIT BLK 4 0x2170 DW_RX_CTL BII SO (R/W) DW RXBI11 FRM 4 0x2170 DW-RX-CTL-BII SO (R/W) DW-RXB111 ROW 4 0x2170 DW-RX-CNT-BE110-SO/ DW-RX CNT-BEI11-SO - (Roy DW-RXBE110_ECNT/ DW-RXBE111-ECNT 4 0x2343/ 0x2344 BEI Calculation Disable BEI Counter Mode: 0 = Bit Count Mode. 1 = Block Count Mode. BII Byte Monitor Frame Location (DW Mode Only) : 00 = Frame N. 01= Frame N+1 . 10= Frame N+2 . 11 =Frame N+3 . BII Monitor Byte Row Location DW BEI Error Counter 17.1 .5.3 1st Addr (hex) PM-Backward Defect Indication (BDI) Table 71 . PM BDI Monitor Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) BDI Bit Monitor Interrupt Alarm. BDI Bit Monitor Interrupt Alarm Mask. BDI Bit Monitor Persistency. BDI Bit Monitor State. Continuous N-Times Detect and Clear BDI Monitor Byte Detect Condition . (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) DW-ALARM _S0 (W1 C) DW-MASK-SO (R/W) DW_RXBD11_DET_A DW RXBD11 DET-M 4 4 0x2020 Ox205C DW-PERSIST-2-SO (RO) DW-STATE_2_SO (RO) DW-RX-CTL-BIICNTD-SO (R/W) DW_RXBD11_DET_P DW_RXBD11_DET DW-RXBD11-CNTD 4 4 4 0x2090 Ox20C0 0x2174 100 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) 17.1 Functional Description of Digital Wrapper Drop (continued) 17.1.5.4 PM-Status (STAT) Table 72. STAT Bits Monitoring MS Value Maintenance Signal 0x66 0x55 OxFF ODUk-OCI ODUk-LCK ODUk-AIS I AIS, OCI, or other fixed patterns can be detected via microprocessor control . One indication byte can be detected by specifying the frame location, row location, and expected value . In FEC frame mode, only the row location is used. The AIS, OCI, or other pattern byte detect is declared when the monitored byte is AIS (all 1 s), OCI (all 6s), or other fixed pattern byte pattern after setting a number of N consecutive consistent occurrences (frames). The AIS, OCI, or other pattern byte detect is cleared when the monitored byte is found to be a mismatch from AIS (all 1 s), OCI (all 6s), or other pattern byte for a clearing number of N consecutive consistent occurrences (frames) . AIS, OCI, or other pattern byte detects report the interrupt alarm, persistency, and state bit via the microprocessor. Agere Systems Inc. 101 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 17.1 Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) Table 73. PM STAT Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (Hex) AIS Monitor Byte Detect Condition Interrupt Alarm AIS Monitor Byte Detect Condition Interrupt Alarm Mask AIS Monitor Byte Detect Condition Persistence AIS Monitor Byte Detect Condition State OCI Monitor Byte Detect Condition Interrupt Alarm OCI Monitor Byte Detect Condition Interrupt Alarm Mask OCI Monitor Byte Detect Condition Persistence OCI Monitor Byte Detect Condition State FIX Monitor Byte Detect Condition Interrupt Alarm FIX Monitor Byte Detect Condition Interrupt Alarm Mask FIX Monitor Byte Detect Condition Persistence FIX Monitor Byte Detect Condition State Fixed Pattern Monitor And Insert Byte Value Continuous N-Times Detect for Setting AIS, OCI, or Other Fixed Pattern Monitor Byte Detect Condition . (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) DW_ALARM SO (W1 C) DW RXAIS DET_A 4 0x2020 DW_MASK_SO (R/W) DW_RXAIS DET M 4 Ox205C DW_PERSIST 2 SO (RO) DW_RXAIS DET_P 4 0x2090 DW_STATE 2 SO (RO) DW RXAIS DET1 4 Ox20C0 DW_ALARM SO (W1 C) DW_RXOCI DET_A 4 0x2020 DW_MASK_SO (R/W) DW RXOCI DET_M 4 Ox205C DW_PERSIST 2 SO (RO) DW_RXOCI DET_P 4 0x2090 DW_STATE 2 SO (RO) DW RXOCI-DET2 4 Ox20C0 DW_ALARM SO (W1 C) DW RXFIX_DET_A 4 0x2020 DW_MASK_SO (R/W) DW_RXFIX_DET_M 4 Ox205C DW_PERSIST 2 SO (RO) DW RXFIX_DET_P 4 0x2090 DW_STATE 2 SO (RO) DW_RXFIX_DET3 4 Ox20C0 DW_RX_CTL_AISBYTE_SO (R/W) DW_RX_CTL_AIS_2_SO (R/W) DW_RXFIX_VAL 4 0x2168 DW_RXAIS_SETCNTD 4 0x2164 1 . DW RXAIS DET is when AIS byte or PM-STAT or TCM-STAT detected AIS . 2. DWRXOCIDET is when AIS byte or PM-STAT or TCM-STAT detected OCI . 3. DW RXFIX DET is when AIS byte or PM-STAT or TCM-STAT detected LCK or fixed pattern is detected . 102 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 17.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) Table 73. PM STAT Register Summary (continued) Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (Hex) Continuous N-Times Detect for Clearing AIS, OCI, or Other Fixed Pattern Monitor Byte Detect Condition . (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) AIS, OCI, or Other Fixed Pattern Byte Monitor Frame Location (DW Mode Only) : 00 = Frame N. 01= Frame N+1 . 10= Frame N+2 . 11 =Frame N+3 . AIS, OCI, or Other Fixed Pattern Monitor Byte Row Location STAT N-Time DW-RX-CTL-AIS_2_SO (R/W) DW-RXAIS-CLRCNTD 4 0x2164 DW RX-CTL-AIS 2 SO (R/W) DW RXAIS FRM 4 0x2164 DW RX-CTL-AIS 2 SO (R/W) DW RXAIS ROW 4 0x2164 DW-RX-CTL-OH -V2 -SO (RW) DW-ALARM-V2 SO (RO) DW-RXBI11-STAT-CNTD 4 0x2504 DW-RX-Bill STAT-NEW-A 4 0x2030 DW-MASK-V2 SO (RO) DW RX-Bill STAT-NEW M 4 Ox206C DW-PERSIST-V2 SO (RO) DW-RX-Bill STAT-NEW P 4 Ox20A0 New Validated STAT Value Interrupt Alarm New Validated STAT Value Persistency Mask New Validated STAT Value Persistency STAT Value I DW RX-MON V2 SO (RO) I DW-RX Bill STAT I 4 I 0x2546 1 . DW RXAIS DET is when AIS byte or PM-STAT or TCM-STAT detected AIS . 2. DW RXOCI DET is when AIS byte or PM-STAT or TCM-STAT detected OCI . 3. DW RXFIX DET is when AIS byte or PM-STAT or TCM-STAT detected LCK or fixed pattern is detected . Agere Systems Inc. 103 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 Digital Wrapper Drop (continued) 17.1 Functional Description of Digital Wrapper Drop (continued) 17.1 .6 ODUk Tandem Connection Monitoring (TCM) There are 6 TCM bytes in an OTU frame . Any one of these 6 TCM bytes can be monitored by selecting it via the microprocessor. The selected TCM bytes are then processed identically to the SM byte (Section 7.1 .4 on page 60) . These bytes will use the BIP2 set of register bits (DW RXBIP2 DISABLE, etc.) in the monitor control registers 17.1 .6.1 TCMi-BIP-8 Table 74. TCM BIP-8 Monitor Register Summary Function BIP Calculation Disable BIP Byte Counter Mode: 0 = Bit Count Mode. 1 = Block Count Mode. BIP Byte Monitor Frame Location (DW Mode Only): 00 = Frame N. 01= Frame N+1 . 10= Frame N+2 . 11 =Frame N+3 . BIP Monitor Byte Row Location DW BIP-8 Error Counter 17.1.6.2 Register Name (First Occurrence) DW RX-CTL-V2_SO (R/W) DW RX-CTL V2 SO (R/W) Register Bits DW RX-BIP2 DISABLE DW RX-BIP2 BIT BLK Qty. 1stAddr (hex) 4 0x2500 4 0x2500 DW-RX-CTL-Bll2-V2 2 SO (R/W) DW RXBIP2 FRM 4 0x2508 DW-RX-CTL Bll2-V2 2 SO (~) DW RXBIP2 ROW 4 0x2508 DW_RX_CNT_BIP20_V2_SO/ DW-RX-CNT-BIP21-V2-SO (RO) DW_RXBIP20_ECNT/ DW-RXBIP21-ECNT 4 0x2534/ 0x2535 TCMi-Backward Error Indication (BEI) Table 75. TCM BEI Monitor Register Summary Function BEI Calculation Disable BEI Counter Mode: 0 = Bit Count Mode. 1 = Block Count Mode. BII Byte Monitor Frame Location (DW Mode Only) : 00 = Frame N. 01 = Frame N + 1 . 10= Frame N+2 . 11 =Frame N+3 . BII Monitor Byte Row Location DW BEI Error Counter 104 Register Name (First Occurrence) DW RX-CTL-V2_SO (R/W) DW RX-CTL-V2 SO (R/W) Register Bits DW-RX-BE12-DISABLE DW-RX-BE12-BIT-BLK Qty. 1stAddr (hex) 4 0x2500 4 0x2500 DW-RX-CTL-B112-V2 2 SO (R/W) Used for BEI, BDI, and STAT Locations DW-RXB112 FRM 4 0x2508 DW-RX-CTL-B112-V2 2 SO (R/W) Used for BEI, BDI, and STAT Locations DW-RX-CNT-BE120-V2-SO/ DW-RX-CNT-BE121 -V2 -SO (RO) DW-RXB112 ROW 4 0x2508 DW-RXBE120-ECNT/ DW-RXBE121-ECNT 4 Ox253D/ Ox253E Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 17.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) 17.1.6.3 TCMi-Backward Defect Indication (BDI) Table 76. TCM BDI Monitor Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) BDI Bit Monitor Interrupt Alarm BDI Bit Monitor Interrupt Alarm Mask BDI Bit Monitor Persistency BDI Bit Monitor State Continuous N-Times Detect and Clear BDI Monitor Byte Detect Condition (The valid range for this register is 0x1-OxF. 0x0 is used to turn off the monitor.) DW-ALARM-V2 SO (W1 C) DW RXBD12 DET-A 4 0x2030 DW-MASK-V2 SO (R/W) DW RXBD12 DET-M 4 Ox206C DW-PERSIST-V2_SO (RO) DW-STATE-V2-SO (RO) DW-RX-CTL-CNTD-V2-SO (R/W) DW-RXBD12-DET-P DW-RXBD12-DET DW-RXBD12-CNTD 4 4 4 Ox20A0 Ox20D0 0x2510 17.1.6.4 Status (STAT) Table 77. STAT Bits Monitoring MS Value Maintenance Signal 0x66 0x55 OxFF ODUk-OCI ODUk-LCK ODUk-AIS I Table 78. TCM STAT Register Summary Function STAT N-Time New Validated STAT Value Interrupt Alarm New Validated STAT Value Persistency Mask New Validated STAT Value Persistency STAT Value I Agere Systems Inc. Register Name Register Bits Qty. 1st Addr (Hex) DW-RX-CTL-CNTD-V2-SO (RW) DW-ALARM-V2 SO (RO) DW-RXB112-STAT-CNTD 4 0x2510 DW-RX-BI12 STAT-NEW-A 4 0x2030 DW-MASK-V2 SO (RO) DW-RX-B112 STAT NEW M 4 Ox206C DW-PERSIST-V2 SO (RO) DW-RX-B112 STAT-NEW-P 4 Ox20A0 4 I 0x2546 DW RX-MON V2 SO (RO) I DW RX-BI12 STAT I 105 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 Digital Wrapper Drop (continued) 17.1 Functional Description of Digital Wrapper Drop (continued) 17.1.7 DWAC Drop The drop DWAC consists of the following three signals per channel (total of four DWAC channels) : -Output clock at -10 .455 MHz (10 Gbits/s mode and quad 2 .5 Gbits/s mode). -Output superframe sync (-326.7/-81 .68 kHz-10 Gbits/s (FEC/DW), -81 .68/-20 .42 kHz-quad 2 .5 Gbits/s (FEC/DW)) coincident with the MSB (most significant bit) of the first byte in frame 0. -Output data: 4 bits in 10 Gbits/s mode and 1 bit per stream in quad 2 .5 Gbits/s mode. SYNC ENABLE DATA I [7 :0] I L -------------------------------------------- TRANSMITTED SERIALLY ORNIBBLE WIDE . DW DWAC RXCLKO DW DWAC RXSYNC DWAC DW RXDATA[3 :0] _ _0H1 [7] _ OH1 [6] OH1 17 :471 OH1 [3 :0] ---------------------------------~----- Note : See the Timing Characteristics section in the Hardware Design Guide for the Transmit Transport Overhead Access Channel section . DW DWAC RXCLKO is not 50% duty cycle . Figure 46. Receive DWAC Frame Definition Three BII bytes can be overwritten to BII byte locations using monitored 131 P-8 error per frame and DW_TXBDI_DET information (signal from transmit direction) . The BII overwritten byte capability is provided for a regenerator mode. Table 79. Receive DWAC Drop Register Summary Function BDI (Tx Detect) Overwritten to DWAC Drop (SM-BDI) BEI (Tx Detect) Overwritten to DWAC Drop (SM-BEI) IAE (Tx Detect) Overwritten to DWAC Drop (SM-IAE) BDI (Tx Detect) Overwritten to DWAC Drop (PM-BDI) BEI (Tx Detect) Overwritten to DWAC Drop (PM-BEI) BDI (Tx Detect) Overwritten to DWAC Drop (TCM-BDI) BEI (Tx Detect) Overwritten to DWAC Drop (TCM-BEI) Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) DW_DWAC_RX_CTL S0 (R/W) DW_DWAC_RX_CTL S0 (R/W) DW_DWAC_RX_CTL_V2 S0 (R/W) DW_DWAC_RX_CTL S0 (R/W) DW_DWAC_RX_CTL S0 (R/W) DW_DWAC_RX_CTL_V2 S0 (R/W) DW_DWAC_RX_CTL_V2 S0 (R/W) DWAC RXBDIO OVWR 4 0x21 CO DWAC RXBE10 OVWR 4 Ox21CO DWAC RXIAEO OVWR 4 Ox252C DWAC RXBD11 OVWR 4 0x21 CO DWAC RXBE11 OVWR 4 Ox21CO DWAC RXBD12 OVWR 4 Ox252C DWAC RXBE12 OVWR 4 Ox252C Note : BDI/BEI/IAE value are calculated, processed, and overwritten at the corresponding location. Ex., BEI calculated value can be inserted at SM-BEI before being dropped by the DWAC . 106 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) 17.1 17.1.8 Functional Description of Digital Wrapper Drop (continued) Insertion of AIS, OCI, and Other Fixed Patterns The macro will automatically generate AIS, OCI, and other fixed pattern bytes with valid framing byte patterns by alarms (hardware) or software insert. The AIS, OCI, or other pattern insert priorities are defined in Table 23 on page 54. Table 80. AIS, OCI, and Fixed Pattern Insert Priority Priority (Highest = 1, Lowest = 6) AIS, OCI, or Other Pattern 1 AIS Insert (Software) (DW RXAIS INS) OCI Insert (Software) (DW-RXOCI INS) LCK or Fixed Pattern Insert (Software) (DW RXFIX INS) AIS Alarm Detect (Hardware) (LINE-RX83LOC and not (DW RXLOC AISINH)) or (FRM DW-RX_LOS and not (DW RXLOS AISINH)) or (FRM DW-RX_OOF and not (DW RXOOF AISINH)) or (FRM DW RX_LOF and not (DW RXLOF AISINH)) or (RS BER SD and not (DW RXSD AISINH)) or (RS BER SD and not (DW RXSD AISINH)) or (DW RXAIS DET') and not (DW-RXAIS DETINH) OCI Alarm Detect (Hardware) (DW RXOCI DET2 and not (DW RXOCI DETINH)) Other Fixed Pattern Alarm Detect (Hardware) (DW RXFIX DET3 and not (DW RXFIX DETINH)) 2 3 4 5 6 1 . DW RXAIS DET is when AIS byte or PM-STAT or TCM-STAT detected AIS . 2. DW RXOCI DET is when AIS byte or PM-STAT or TCM-STAT detected OCI . 3. DW RXFIX DET is when AIS byte or PM-STAT or TCM-STAT detected LCK or fixed pattern is detected . . DW RXAIS COND is active-high (output) if AIS pattern in STAT1 or STAT2 is detected and inserted . . DW RXOCI COND is active-high (output) if OCI pattern in STAT1 or STAT2 is detected. . DW RXFIX COND is active-high (output) if fixed or LCK pattern in STAT1 or STAT2 is detected. When DW_RXAIS COND is set to logic 1, a default pattern of all 1s will be inserted . When the DW_RXOCI_DET alarm is in detect mode (active), an OCI (0x66) pattern will be inserted . When the DW_RXFIX_DET alarm is detected, all LCK (0x55) or fixed patterns in DW_RXFIX_VAL will be inserted via the microprocessor. AIS, OCI, or other fixed patterns can be inserted . AIS/OCI/LOCk signals are generated as per Table 77 on page 105 . The DW_RXAIS_COND is also an output to an elastic store (Rx). At programmable MFAS location bytes, overhead in the OTU OH field is valid and is not overwritten by AIS generator. TCMO-TCM5, GCCO-GCC2, and APS/PCC inhibit are available. In 10 Gbits/s mode, only slice 0 is valid. Agere Systems Inc. 107 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 17.1 Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) Table 81 . Insertion of AIS Register Summary Function Register Name (First Occurrence) AIS Insert Control Bit (when DW RX_CTL TOP SO (R/W) set to logic 1, AIS condition will be inserted) OCI Insert Control Bit. DW RX_CTL TOP SO (R/W) Fixed Pattern Insert DW RX_CTL TOP SO (R/W) Control Bit DW_RX_CTL_OH_V2_SO Number of Multiframe (MFAS) Bytes After OA2 (R/W) (see Table 25 on Page 57) Loss-of-Clock AIS Inhibit DW RX_CTL TOP SO (R/W) (When set to logic 1, the AIS insert will be inhibited in case of loss-of-clock (LINE RX83LOC)) DW_RX_CTL TOP SO (R/W) Out-of-Frame AIS Inhibit (When set to logic 1, the AIS insert will be inhibited in case of out-of-frame (FRM RXOOF)) DW RX_CTL TOP SO (R/W) Loss-of-Frame AIS Inhibit (When set to logic 1, the AIS insert will be inhibited in case of loss-of-frame (FRM RXLOF)) Loss-of-Signal AIS Inhibit DW RX_CTL TOP SO (R/W) (When set to logic 1, the AIS insert will be inhibited in case of loss-of-signal (FRM RXLOS)) AIS Failure Condition when DW_RX_CTL_AIS_V2_SO (R/W) Detect SF Inhibit AIS Failure Condition when DW_RX_CTL_AIS_V2_SO Detect SD Inhibit (R/W) AIS Detect, AIS Pattern DW RX_CTL TOP SO (R/W) Insert Inhibit DW RX_CTL TOP SO (R/W) OCI Detect, OCI Pattern Insert Inhibit Fixed Pattern Detect, Fixed DW RX_CTL TOP SO (R/W) Pattern Insert Inhibit Choose Insert Pattern of LCK DW RX_CTL_V2 SO (RW) (0x55) or FIX Value FTFL Inhibit During AIS DW RX CTL AIS V2 SO (RW)I 108 Register Bits Qty. DW_RXAIS INS 4 0x2150 DW_RXOCI_INS DW_RXFIX_INS 4 4 0x2150 0x2150 DW-RXOA12-MFAS 4 0x2504 DW RXLOC_AISINH 4 0x2150 DW_RXOOF_AISINH 4 0x2150 DW RXLOF_AISINH 4 0x2150 DW_RXLOS AISINH 4 0x2150 DW_RXSF_AISINH 4 Ox250C DW_RXSD_AISINH 4 Ox250C DW_RXAIS DETINH 4 0x2150 DW RXOCI DETINH 4 0x2150 DW_RXFIX_DETINH 4 0x2150 DW RXLCK_FIX 4 0x2500 DW RXAIS FTFLINH I 1st Addr (hex) 4 I Ox250C1 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 17.1 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) Table 81 . Insertion of AIS Register Summary (continued) Function Register Name (First Occurrence) TCMO to TCM5 Insert During DW RX_CTL AIS_V2 S0 AIS/OCI/LCK' GCCO to GCC2 Inhibit During DW RX_CTL AIS_V2 S0 AIS/OCI/LCK APS/PCC Inhibit During DW RX_CTL AIS_V2 S0 AIS/OCI/LCK TCMO to TCM5 Insert During DW RX_CTL OH V2 S0 AIS/OCI/LCK' Inhibit Register Bits Qty. 1st Addr (hex) (RW) DW_RXAIS_TCMINH 4 Ox250C (RW) DW_RXAIS GCCINH 4 Ox250C (RW) DW_RXAIS_APSINH 4 Ox250C 4 0x2504 (RW) DW_RXAIS TCMSTAT_IAEINH 1 . If TCM insert during AIS/OCI/LCK, STAT [2 :0] will be inserted 001 for normal operation mode . (IAE in-use is not available .) The following figure shows the alarm structure of the AIS/OCI/FIX detection and insertion . AIS_CNTD_DET AIS STAT1 (PMAIS) AIS STAT1 (TCMAIS) DW RXAIS INH DW RXAIS DET SYS-RX83LOC DW RXLOC AISINH FRM_DW_RX_LOS DW_RXLOS_AISINH FRM_DW_RX_LOF DW RXLOF AISINH DW_RXAIS_COND (AIS PATTERN INSERT) FRM_DW_RX_OOF DW RXOOF AISINH RS-SF DW RXSF AISINH RS_SD DW RXSD AISINH OCI_CNTD_DET OCI STAT1 (PMAIS) OCI STAT1 (TCMAIS) DW RXOCI DET DW RXOCI COND DW RXOCI INH (0C1 PATTERN INSERT) DW RXOCI INS FIX_CNTD_DET FIX STAT1 (PMAIS) FIX STAT1 (TCMAIS) DW RXFIX DET DW RXFIX COND DW RXFIX INH (FIX PATTERN INSERT) DW RXFIX INS Figure 47. AIS/OCI/FIX Alarm Structure (per Slice) Agere Systems Inc. 109 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 17 17.1 17.1 .9 Digital Wrapper Drop (continued) Functional Description of Digital Wrapper Drop (continued) PRBS Monitor PRBS data in payload locations (excluding overhead and check bytes location) can be monitored by the PRBS monitor at the output pins (DW_RXPRBSDATA[127 :0] and DW_RXPRBSDATA-EN[3 :0]). A pseudorandom sequence pattern (either 231 - 1 or 229 - 1) can be detected. When 32 consecutive bits matches in its pattern, the pattern sync state declares itself in-sync . If eight or more consecutive mismatches are in the payload sequence, the corresponding pattern sync state declares itself out-of-sync . In 10 Gbits/s mode, the payload goes into sync if the most up-to-date 32 bits (LSB) are a match, and declares itself out-of-sync if the most up-to-date of the last 32 bits (LSB) has eight or more consecutive mismatches in the payload sequence . Note : If 32 bits match and/or eight mismatches occur in a less up-to-date pattern [127:32], it will be ignored . The pattern sync state also provides interrupt alarm and persistence . The PRBS can also monitor for inverted patterns via the microprocessor. For any bit errors occurring after the monitor is in the in-sync state, an 8-bit counter reports the number of bit errors using clear-on-read toggle from the microprocessor. Table 82. PRBS Monitor Register Summary Function Receive PRBS Pattern (Payload Only) Monifor is Expected to be Inverted When Set Receive PRBS Pattern Sequence Selection : 0 = 229 - 1 . 1 =231-1 . Receive PRBS Error Pattern Counter. The PRBS monitor counts the number of times the input data differs from the expected value in an 8-bit counter that holds its count when it reaches the maximum value of 255 . This counter is reset when ready by the microprocessor, and is not affected by the PMRST signal . (clear-on-read) Receive PRBS Pattern Sync Interrupt Alarm Bit Receive PRBS Pattern Sync Mask Bit Register Name (First Occurrence) Qty. 4 1st Addr (hex) 0x21 EO 4 0x21 EO DW-RXPRBS-ECNT 4 0x2600 DW RXPRBS SYNC-A 4 0x2024 DW-RXPRBS SYNC M 4 0x2060 DW RXPRBS SYNC P 4 0x2094 DW-RXPRBS SYNC 4 0x2024 DW-RXPRBS SYNC 4 Ox20C4 DW-PRBS-CTL SO DW-RXPRBS INV (R/W) DW PRBS CTL SO DW-RXPRBS 29 31 PAT - (R/W) DW-RX-CNTPRBS SO (COR) DW-PRBS_ ALARM SO (W1 C) DW-PRBS_MASKSO (R/W) PRBS Bit DW-PRBS_ Receive Pattern Sync Persistency PERSIST SO (RO) Receive PRBS Pattern Sync Alarm Bit DW-PRBS_ ALARM SO (W1 C) When the PRBS pattern (payload only) DW-PRBS_STATE_ detects 32 matches in a row, it declares itself SO (RO) in-sync and the error detector is enabled. if the device detects eight consecutive mismatches, the test pattern detector declares itself out-of-sync and starts searching again . 0 = In-sync . 1 = Out-of-sync. 110 Register Bits Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 17 with Strong/Weak FEC and Digital Wrapper Digital Wrapper Drop (continued) 17.1 17.1.10 Functional Description of Digital Wrapper Drop (continued) PRBS Insert Table 83. PRBS Insert Register Summary Function PRBS Pattern (payload only) Insert PRBS Inverted Pattern Insert (payload only) Insert PRBS Pattern Sequence Insert Selection : 0=229_1 1=231_1 Received PRBS Error Insert Bit (1 error bit per 128 bits in 10 Gbits/s mode, and 1 bit per 32 bits in 2 .5 Gbits/s mode) 17.1.11 Register Name (First Occurrence) Register Bits Qty. DW_PRBS_CTL_V2 SO (R/W) DW_PRBS_CTL_V2_SO (R/W) DW_PRBS_CTL_V2 SO (R/W) DW_RXPRBS INS 4 1st Addr (hex) 0x2530 DW_RXPRBS_INS_INV 4 0x2530 DW RXPRBS INS-29-31 PAT 4 0x2530 DW_RXPRBS_INS_1BERRINS 4 0x2530 1st Addr (hex) 0x2500 DW_PRBS_CTL_V2_SO (R/W) No Fix Stuff Mode A register bit can be enabled to disable the fix stuff column . Table 84. Receive Data No Fix Stuff Mode Register Summary Function Fix Column Disable (119th column is reserved for fixed stuff, 10 Gbits/s mode only) Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. DW_RX_CTL_V2 SO (RW) DW_RX_NO_FS 1 111 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 18 18.1 Elastic Store (Receive Direction) Functional Description of Elastic Store Receive Direction The receive elastic store (ES) buffers gapped 83 MHz data and outputs 78 MHz data to absorb clock gapping of the FEC/DW overheads and FEC check bytes. Data arrives to the receive ES grouped as 32 bits in each slice. Each group of 32 bits is written into the associated ES location (128 locations x 32 bits) by 237/238 clock cycles (payload region of the FEC/DW frame) out of 255 clock cycles (whole FEC/DW frame) in the 83 MHz clock . Data is read from the ES by a 78 MHz clock. The relationship between read and write addresses is controlled in order to minimize signal delay and to guarantee data integrity at the same time. In the initial state, or after over/underflow, the write address is automatically reset to the predefined position (32 locations ahead of the read address), when the first sync pulse is received . In 10 Gbits/s mode, all four elastic stores should work in synchronization . In some applications, the receive ES is disabled and data is bypassed. In this case, the overflow/underflow alarm is not declared. By software control, the elastic store is forced to restart. Table 85. Elastic Store (Rx) Register Summary Function Rx ES Overflowing Interrupt Alarm Rx ES Underflowing Interrupt Alarm Rx ES Overflowing Interrupt Alarm Mask Rx ES Underflowing Interrupt Alarm Mask Rx ES Forced Restart 112 I Register Name (First Occurrence) ES-ALARM-SO (W1 C) Register Bits Qty. ES RX_OVERFLW_A 4 ES-ALARM-SO (W1 C) ES RX_UNDRFLW_A 4 Ox201C ES MASK_SO (R/W) ES RX_OVERFLW M 4 0x2058 ES MASK_SO (R/W) ES_RX_UNDRFLW_M 4 0x2058 4 I 0x2130 ES CTL SO (R/W) I ES RX-RESTART I 1stAddr (hex) Ox201 C Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 19 19.1 with Strong/Weak FEC and Digital Wrapper SONET FEC (BCH Weak/in Band) Supermacro SONFEC (BCH Weak/in Band) Introduction The following sections provide the functional description of the SONET weak FEC supermacro core: in-band . The functional description includes requirements that must be met, as derived from various specifications . The weak FEC supermacro core consists of the following : -SONET STS-192/Quad STS-48 BCH Macro Core -SONET STS-192/Quad STS-48 Framer -SONET STS-192/Quad STS-48 B1 Monitoring -SONET STS-192/Quad STS-48 Descrambler -SONET STS-192/Quad STS-48 Alignment FIFO (transmit only) -SONET STS-192/Quad STS-48 Transpose Demultiplexer -SONET STS-192/Quad STS-48 B2 Monitoring -SONET Overhead/PRBS Payload Insert Processing -SONET Overhead/PRBS Payload Monitor Processing -SONET STS-192/Quad STS-48 B2 Computing -SONET STS-192/Quad STS-48 Transpose Multiplexer -SONET STS-192/Quad STS-48 Scrambler -SONET STS-192/Quad STS-48 B1 Computing 19.2 Functional Description of SONET FEC (BCH Weak/in Band) Supermacro The SONET FEC (SONFEC) supermacro incorporates all the SONET-related functions of the TFEC041OG device . It performs the BCH encoding of the incoming STS data in the transmit direction and BCH decoding in the receive direction . In both directions, all the blocks that modify/monitor the data can be disabled . In the transmit direction, the incoming data is framed, optionally descrambled, and monitored for B1 BIP errors . If loss of frame, loss of signal, or RDI/AIS is detected, then the AIS frames are generated and all the functions are disabled (including BCH encoding) . If no AIS conditions exist, or no AIS data is received, then the data is passed on to the overhead processing macro. The overhead processor inserts the provisioned overhead bytes (software, TOAC, default, or data as received) . The complete SONET frame is then BCH encoded and optionally scrambled before being sent out from this macro. In the receive direction, the incoming data is framed, optionally descrambled, and monitored for B1 BIP errors . If loss of frame, loss of signal, or RDI/AIS is detected, then AIS frames are generated and all the functions are disabled (including BCH decoding) . If no AIS conditions exist, or no AIS data is received, then the data is error corrected by the BCH decoder (if within its error correction capability) and then is passed on to the overhead processing macro. The overhead processor drops the overhead bytes on the TOAC channel and performs overhead byte analysis on individual bytes, if enabled. The complete SONET frame is then optionally scrambled before being sent out from this macro. In the receive direction, software can monitor the error correction performance through the BIP error counts provided both before and after BCH decoding . The B1 or B2 BIP errors can be monitored before BCH decoding for SD/SF detection . The B2 errors can be monitored before or after BCH decoding for SD/SF detection . The SONET supermacro also supports two loopback modes: one on the line side and the other on the system side. Individual disable controls for all the blocks allow operational flexibility within the device. As an example, in loopback mode, one of the framers (of the two in the loop) can be disabled as the other one performs the framing . This avoids redundancy of alarm signals as well as reduces the delay in framing . Since individual macros are independently controlled by software, care must be taken to program the mode (10 Gbits/s mode/2 .5 Gbits/s mode) of each block . In virtual 10 Gbits/s mode (in the transmit direction only), the incoming four 2.5 Gbits/s mode STS-48 signals are frame aligned at the alignment FIFO and then multiplexed to form one single 10 Gbits/s mode STS-192 signal . The structure of SONET weak FEC supermacro is shown in Figure 48 on page 114. Agere Systems Inc. 113 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 19 19.2 SONET FEC (BCH Weak/in Band) Supermacro (continued) Functional Description of SONET FEC (BCH Weak/in Band) Supermacro (continued) l~ 1 0 Figure 48. SONET Weak FEC Supermacro Functional Block Diagram 114 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 19 with Strong/Weak FEC and Digital Wrapper 19.3 SONET FEC (BCH Weak/in Band) Supermacro (continued) 19.3.1 SONFEC AIS/RDI Generation SONFEC (BCH Weak/in Band) Overview In SONFEC, both transmit and receive overhead processors can generate AIS . If loss of clock or loss of signal is detected, AIS is generated and software cannot disable the AIS generation (no internal frame generation) . Once the AIS condition is cleared, a subsequent one or two frames may be corrupt (131 Ps) . 19.3.2 Transmit AIS The SONFEC supermacro generates AIS in the transmit direction under the following conditions : . Loss of clock . . Loss of signal . . Severely errored frame (SEF) and SEF AIS generation is software enabled (TX SEF AIS DIS). . Loss of frame (LOF) and LOF AIS generation is software enabled (TX LOF AIS DIS). . Line-AIS frame is detected and line AIS generation upon detection is software enabled (TX LINE AIS DIS). . Line-AIS frame generation is software enabled (TX LINE AIS INS). Table 86. Transmit AIS Control Register Summary Register Name Register Bits OHP_TX_AIS RDI TX_SEF AIS DIS TX_LOF_AIS DIS TX_LINE_AIS_DIS TX_LINE_AIS_INS Agere Systems Inc. Function AIS generation due to SEF condition disable . 0 = AIS generated under SEF. 1 = AIS generation under SEF disabled . AIS generation due to LOF condition disable . 0 = AIS generated under LOF. 1 = AIS generation under LOF disabled . AIS generation due to AIS detect disable . 0 = AIS generated under AIS . 1 = AIS generation under AIS disabled. AIS generation . 0 = AIS generated. 1 = AIS generation disabled . 115 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 19 Operational Description July 2002 19.3 SONET FEC (BCH Weak/in Band) Supermacro (continued) 19.3.3 SONFEC AIS/RDI Generation (continued) Receive AIS The SONFEC supermacro generates AIS in the receive direction under the following conditions: . Loss of clock . . Loss of signal . . Severely errored frame (SEF) and SEF AIS generation is software enabled (RX SEF AIS DIS). . Loss of frame (LOF) and LOF AIS generation is software enabled (RX LOF AIS DIS). . Signal fail at post B2 monitoring and SF AIS generation is software enabled (RX SF AIS DIS). . Section trace-JO mismatch and JO mismatch AIS generation is software enabled (RX TIM L AIS DIS). . Line-AIS frame is detected and line AIS generation upon detection is software enabled (RX LINE AIS_DIS) . . Line-AIS frame generation is software enabled (RX LINE AIS_INS) . Table 87. Receive AIS Control Register Summary Register Name OHP RX_AIS RDI Register Bits RX_SEF_AIS DIS RX_LOF AIS DIS RX_LINE_AIS DIS RX_TIM L AIS DIS RX_SF_AIS DIS RX_LINE_AIS INS 116 Function AIS generation due to SEF condition disable . 0 = AIS generation due to SEF enabled. 1 = AIS generation due to SEF disabled . AIS generation due to LOF condition disable . 0 = AIS generation due to LOF enabled. 1 = AIS generation due to LOF disabled . AIS generation due to AIS detection disable . 0 = AIS generation due to AIS detect enabled. 1 = AIS generation due to ASI detect disabled . AIS generation due to JO mismatch disable . 0 = AIS generation due to JO mismatch enabled. 1 = AIS generation due to JO mismatch disabled . AIS generation due to SF condition disable . 0 = AIS generation due to SF condition enabled . 1 = AIS generation due to SF condition disabled. AIS generation . 0 = AIS generation disabled. 1 = AIS generated . Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 19 with Strong/Weak FEC and Digital Wrapper SONET FEC (BCH Weak/in Band) Supermacro (continued) 19.3 SONFEC AIS/RDI Generation (continued) 19.3.4 Transmit RDI Generation The SONFEC supermacro generates RDI in the transmit direction whenever there is a hardware AIS condition in the receive direction . Once the receive direction detects any one of the RDI generation events, K2 bytes in the transmit direction are modified under all conditions (except in the case of software bypass) . If no hardware RDI generation events are present, then the lower 3 bits of the software programmed K2 byte are inserted if software insert is enabled. Once RDI is inserted, the duration can be software controlled for either 20 consecutive frames or the duration of the RDI event. Both RDI and AIS conditions are controlled by the same set of register bits. Optionally, software can be programmed to bypass the received K1/K2 . Table 88. Transmit RDI Insertion Control Register Summary 19.4 Register Name Register Bits Function OHP_TX_AIS_RDI TX-20FRM-RDI-DIS OHP_TX_MAINT TX_RDI L SELECT 0HP_TX_K1 K2 TX_K2 BYTE[3 :0] RDI insertion disable . 0 = Enable RDI insertion on 20 frames . 1 = Disable RDI insertion on 20 frames. RDI insertion from the programmed K2 byte enable. 0 = RDI insertion disabled . 1 = RDI insertion enabled. If software enabled, then the last three bits of K2 are inserted in RDI . SONFEC Interrupt Structure The interrupt structure is comprised of different registers depending on the consolidation level . The structure depicts only that of the SONFEC macro. Individual interrupts sourced within the SONFEC supermacro cause the corresponding bits to be set in the interrupt service register (ALARM registers (W1 C)) . If the corresponding interrupt mask register bit is set (MASK registers (R/W)), then these interrupts cause the submacro level interrupt bit to be set . These submacro level interrupts are grouped into two: overhead processor and BCH . When the mask bits corresponding to these submacro interrupts are set, they cause an interrupt to be sourced from the SONFEC supermacro . The interrupt summary is given the TFEC041OG Hardware Register Map document . Agere Systems Inc. 117 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 20 20.1 Operational Description July 2002 BCH Macro Functional Description of BCH Macro The BCH (Bose-Chaudhuri-Hocquenghem) macro performs in-band forward error correction (FEC) . The code used for in-band FEC is a shortened, systematic binary BCH (4359, 4320) code derived from a (8191, 8162) parent code which belongs to the family of systematic linear cyclic block codes . The code block consists of 4320 information bits and 39 check bits. In order to enhance the immunity of the transmission system to the burst errors, eight code blocks are bit-interleaved . CODE BLOCKS Figure 49. 8-Way Bit Interleaved BCH (4359, 4320) Frame The 39 check bits are the remainder after polynomial division of the information polynomial by generating polynomialG(x)=G1(x)xG3(x)xG5(x)where G1(x)=X13+X4+X3+X +1,G3(x)=X13+X1+X9+X7+X5+X4+1, and G5(x) = X13 + X11 + X8 + X7 + x4 + x + 1 . Sufficient check bits are generated to support triple error correction . The 8-way bit interleaving in conjunction with BCH-3 provides 24-bit burst error correction capability per frame. One row of an STM-16 (STS-48), which is 4320 bytes, forms the information of the BCH frame (i.e., the BCH macro encodes and decodes the STM-16 (STS-48) on a row-by-row basis) . The code block definition for an STM-64 (STS-196) is identical to that for an STM-16 (STS-48). However, there are four block groups, i .e., 32 code blocks . Conceptually, the FEC function falls below the multiplexing section (MS) layer and provides a correction service to the MS layer, and uses overhead bytes from the MSOH (multiplexing section overhead) and RSOH (regenerator section overhead) as shown in Figure 50 on page 119. Although check bytes are transported in information byte positions, they are not included in information . From this, all RSOH bytes (including undefined RSOH bytes) and all FEC check bytes are not included in the coding of the FEC and are replaced with zeros. Note that the Q1 bytes (FSI-FEC status indication bytes) are covered by the FEC, and are therefore included in the coding of the FEC . 118 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 20 20.1 with Strong/Weak FEC and Digital Wrapper BCH Macro (continued) Functional Description of BCH Macro (continued) Ws Ws FEC 1 FEC 2 FEC 3 FEC 4 FEC 5 FEC 6 FEC 7 FEC 8 FEC 9 ROW =2, GROUP =1 ROW =2, GROUP =4 ROW =2, GROUP =6 ROW =3, GROUP =1 ROW =3, GROUP =4 ROW =3, GROUP =6 ROW =3, GROUP =7 ROW =3, GROUP =8 111 ROW =3, GROUP =9 ROW =5, GROUP =4 ROW =5, GROUP =5 ROW =5, GROUP =6 ROW =5, GROUP =7 ROW =5, GROUP =8 ROW =5, GROUP =9 ROW =6, GROUP =7 ROW =6, GROUP =8 ROW =6, GROUP =9 ROW =7, GROUP =7 ROW =7, GROUP =8 ROW =7, GROUP =9 ROW =8, GROUP =7 ROW =8, GROUP =8 ROW =8, GROUP =9 ROW =9, GROUP =1 ROW =9, GROUP =2 ROW =9, GROUP =2 BYTE NO. 1 2 3 Q1 BYTE 4 5 6 7 8 9 1011 121314 15 16 1 bit 8 bits _ I 8-bit INTERLEAVED CHECK DATA #0 8-bit INTERLEAVED CHECK DATA #12 Figure 50. FEC Check Byte Allocation in STM-16 (STS-48) Agere Systems Inc. 119 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 20 Operational Description July 2002 BCH Macro (continued) 20.1 Functional Description of BCH Macro (continued) In Figure 44 on page 91, each set of FEC bytes represents a set of FEC check bits. The number indicates the row of the payload to which each set of FEC check bytes pertains . The Q1 byte is an FEC status indicator (FSI) . This is used at the FEC decoding point to determine whether FEC information is present for error correction to take place. Table 89 and Table 90 give the exact check byte locations for STM-16 and STM-64 signals . Table 89. Location of FEC Check Bits for STM-64 (STS-192) The numbers in the table represent row number, group number, and byte number, respectively . FEC Row #1 1 2 3 4 5 6 7 8 9 Check Bits Set #1 (#38 - #26) 2,1,4-2,1,16 2, 1, 20 - 2, 1, 32 2, 1, 36 - 2, 1, 48 2,1,52-2,1,64 3,1,4-3,1,16 3, 1, 20 - 3, 1, 32 3, 1, 36 - 3, 1, 48 3, 1, 52 - 3, 1, 64 3, 7, 4 - 3, 7,16 3, 7, 20 - 3, 7, 32 3, 7, 36 - 3, 7, 48 3, 7, 52 - 3, 7, 64 5, 4, 4 - 5, 4,16 5, 4,20 - 5, 4, 32 5, 4, 36 - 5, 4, 48 5, 4, 52 - 5, 4, 64 5, 7, 4 - 5, 7,16 5, 7, 20 - 5, 7, 32 5, 7, 36 - 5, 7, 48 5, 7, 52 - 5, 7, 64 6, 7, 4 - 6, 7,16 6, 7, 20 - 6, 7, 32 6, 7, 36 - 6, 7, 48 6, 7, 52 - 6, 7, 64 7, 7, 4 - 7, 7,16 7, 7, 20 - 7, 7, 32 7, 7, 36 - 7, 7, 48 7, 7, 52 - 7, 7, 64 8, 7, 4 - 8, 7,16 8, 7, 20 - 8, 7, 32 8, 7, 36 - 8, 7, 48 8, 7, 52 - 8, 7, 64 9,1,4-9,1,16 9, 1, 20 - 9, 1, 32 9, 1, 36 - 9, 1, 48 9,1,52-9,1,64 I Check Bits Set #2 (#25 - #13) 2,4,4-2,4,16 2, 4, 20 - 2, 4, 32 2, 4, 36 - 2, 4, 48 2,4,52-2,4,64 3,4,4-3,4,16 3, 4,20 - 3, 4, 32 3, 4, 36 - 3, 4, 48 3, 4, 52 - 3, 4, 64 3, 8, 4 - 3, 8, 16 3, 8, 20 - 3, 8, 32 3, 8, 36 - 3, 8, 48 3, 8, 52 - 3, 8, 64 5, 5, 4 - 5, 5, 16 5, 5, 20 - 5, 5, 32 5, 5, 36 - 5, 5, 48 5, 5, 52 - 5, 5, 64 5, 8, 4 - 5, 8, 16 5, 8, 20 - 5, 8, 32 5, 8, 36 - 5, 8, 48 5, 8, 52 - 5, 8, 64 6, 8, 4 - 6, 8, 16 6, 8, 20 - 6, 8, 32 6, 8, 36 - 6, 8, 48 6, 8, 52 - 6, 8, 64 7, 8, 4 - 7, 8, 16 7, 8, 20 - 7, 8, 32 7, 8, 36 - 7, 8, 48 7, 8, 52 - 7, 8, 64 8, 8, 4 - 8, 8, 16 8, 8, 20 - 8, 8, 32 8, 8, 36 - 8, 8, 48 8, 8, 52 - 8, 8, 64 9,2,4-9,2,16 9, 2, 20 - 9, 2, 32 9, 2, 36 - 9, 2, 48 9,2,52-9,2,64 I Check Bits Set #3 (#12 - #0) 2,6,4-2,6,16 2, 6, 20 - 2, 6, 32 2, 6, 36 - 2, 6, 48 2,6,52-2,6,64 3,6,4-3,6,16 3, 6, 20 - 3, 6, 32 3, 6, 36 - 3, 6, 48 3, 6, 52 - 3, 6, 64 3, 9, 4 - 3, 9,16 3, 9, 20 - 3, 9, 32 3, 9, 36 - 3, 9, 48 3, 9, 52 - 3, 9, 64 5, 6, 4 - 5, 6, 16 5, 6, 20 - 5, 6, 32 5, 6, 36 - 5, 6, 48 5, 6, 52 - 5, 6, 64 5, 9, 4 - 5, 9, 16 5, 9, 20 - 5, 9, 32 5, 9, 36 - 5, 9, 48 5, 9, 52 - 5, 9, 64 6, 9, 4 - 6, 9, 16 6, 9, 20 - 6, 9, 32 6, 9, 36 - 6, 9, 48 6, 9, 52 - 6, 9, 64 7, 9, 4 - 7, 9, 16 7, 9, 20 - 7, 9, 32 7, 9, 36 - 7, 9, 48 7, 9, 52 - 7, 9, 64 8, 9, 4 - 8, 9,16 8, 9, 20 - 8, 9, 32 8, 9, 36 - 8, 9, 48 8, 9, 52 - 8, 9, 64 9,3,4-9,3,16 9, 3, 20 - 9, 3, 32 9, 3, 36 - 9, 3, 48 9,3,52-9,3,64 01 Byte - 3, 9, 3 (FSI) 3, 9,19 (OOH) 3, 9, 35 (OOH) 3, 9, 51 (OOH) - - 1 . See Figure 50, FEC Check Byte Allocation in STM-16 (STS-48), on page 119 for details on FEC rows. 120 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 20 with Strong/Weak FEC and Digital Wrapper BCH Macro (continued) 20.1 Functional Description of BCH Macro (continued) Table 90. Location of FEC Check Bits for STM-16 (STS-48) FEC Row #1 1 2 3 4 5 6 7 8 9 I Check Bits Set #1 (#38 - #26) 2,1,4-2,1,16 3, 1, 4 - 3, 1, 16 3, 7, 4 - 3, 7,16 5, 4, 4 - 5, 4,16 5, 7, 4 - 5, 7,16 6, 7, 4 - 6, 7,16 7, 7, 4 - 7, 7,16 8, 7, 4 - 8, 7,16 9, 1, 4 - 9, 1, 16 1 Check Bits Set #2 (#25 - #13) 2,4,4-2,4,16 3, 4, 4 - 3, 4,16 3, 8, 4 - 3, 8,16 5, 5, 4 - 5, 5,16 5, 8, 4 - 5, 8,16 6, 8, 4 - 6, 8,16 7, 8, 4 - 7, 8,16 8, 8, 4 - 8, 8,16 912, 4 - 9, 2, 16 Check Bits Set #3 (#12 - #0) 2,6,4-2,6,16 3, 6, 4 - 3, 6,16 3, 9, 4 - 3, 9,16 5, 6, 4 - 5, 6,16 5, 9, 4 - 5, 9,16 6, 9, 4 - 6, 9,16 7, 9, 4 - 7, 9,16 8, 9, 4 - 8, 9,16 9, 3, 4 - 9, 3,16 I 01 Byte 3, 9, 3 - 1 . See Figure 50, FEC Check Byte Allocation in STM-16 (STS-48), on page 119 for details on FEC rows . 20.1.1 BCH Encoder The BCH encoder generates and inserts check bits of STM-16/STM-64 (STS-48/STS-192) signals . Data arrives to the BCH encoder grouped as four slices of 32 bits. Because the code block definition for an STM-64 (STS-192) is identical to that for an STM-16 (STS-48), and the transpose demultiplexer (TDMX) reorders the data so that the STM-64 (STS-192) is divided into its four constituent STS-48 data streams, each slice can operate independently even in STM-64 (STS-192) mode. The only difference between STM-16 (STS-48) mode and STM-64 (STS-192) is Q1 byte insertion, which is explained in the next section (Section 20.1 .1 .1) . 20.1.1 .1 FSI Bit Insert The FEC encoder is required to generate the FEC status indication (FSI) bits to enable downstream decoders . This is to prevent downstream decoders from causing miscorrection when FEC encoding is not present. The Q1 byte is located in row 3, as shown in Figure 49 on page 118. The FSI carrying byte is located in the first Q1 byte, i.e., the Q1 byte of the first block group (which contains FSI and Q1 bytes in the remaining block groups) is unassigned and the transmitted default value is OOH in STM-64 (STS-192) mode. The FSI bits are the bits (7 and 8) of the FSI byte, as shown in Figure 51 . The remaining bits in the FSI byte are reserved, but are covered by the FEC . The transmitted default value for these remaining 6 bits is zero. RESERVED 1 2 3 4 FSI 5 6 7 8 Figure 51 . FEC Status Indication Byte (FSI) The value of the FSI bits is encoded according to encoder states, and there are three operational encoder states : FEC-ON, FEC-OFF with encoder delay, and FEC-OFF without encoder delay. The encoder operational state is controlled by software . When the encoder is in the FEC-ON state, FSI = 01 is transmitted . When the encoder is in the FEC-OFF with encoder delay state, all Q1 bytes are set to 0x00 . When the encoder is in the FEC-OFF without encoder delay state, they are bypassed. Note : 10 or 11 is not a valid encoder transmission value. Agere Systems Inc. 121 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 20 20.1 Operational Description July 2002 BCH Macro (continued) Functional Description of BCH Macro (continued) Table 91 . BCH Macro Register Summary Function BCH Encoder Status Control I Register Name (First Occurrence) BCH PROV SO (R/W) Register Bits I BCH ENC MODE Qty. I 4 1st Addr (hex) I 0x1144 Note : When configuring the BCH encoder in OC-192 mode, ensure that all slices are enabled . To ensure all slices are active before the FSI byte is generated, write 0X1147 last. 20.1.1 .2 FEC Payload Generate All RSOH bytes (including undefined RSOH bytes) of incoming STMA6 (STS-48) signals are not included in the encoding of the FEC and are replaced with zeros before the check bit calculation . All Q1 bytes are included in the FEC block for correction before retransmission by correcting regenerators, and therefore are added to the incoming STM-16 (STS-48) signal for the encoding of the FEC . 20.1 .1 .3 Check Bit Generate Data arrives to the BCH encoder grouped as four slices of 32 bits. The BCH encoder generates check bits in 8-way bit interleaving mode. Therefore, there are 4 bits of data which belong to the same code block at every clock cycle . Each slice has eight independent check bit calculators . Each calculator accepts 4 bits of information data which belong to same code block during 1080 clock cycles (i.e., accepts 4320 information bits). After 1080 times polynomial division of the information data, each calculator outputs 39 bits check data, which is a remainder of the polynomial division . Since the in-band FEC code blocks are designed to cover a single row of the STMA6 (STS-48), the starting of polynomial division is the same as starting each row of the STM-16 (STS-48). 20.1 .1 .4 Check Bit Insert The check bits are inserted into designated locations as shown in Figure 44 on page 91 . The check bit data is available after polynomial division of the associated information data, but FEC-3, FEC-5, FEC-6, FEC-7, FEC-8, and FEC-9 are located in the middle of the rows to which the check bit data pertains . For this reason, information data is delayed before check bit inserting . As mentioned previously, there are three operational encoding states . The FEC insert works in synchronization with the encoding state . When the encoder operates in the FEC-OFF without encoder delay state, the information data is transmitted without delay. In order to permit synchronized decoder switching at the receiver, the FEC insert is turned off (on) starting with the first row of the eighth frame after the FSI change. For flexible operation, check bits are inserted either MSB first or LSB first. This is configured by software . Table 92. BCH FEC Insert Register Summary Function BCH FEC Insert Control 122 I Register Name (First Occurrence) BCH PROV SO (R/W) Register Bits I BCH ENC_INSERT Qty. I 4 1st Addr (hex) I 0x1144 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 20 20.1 with Strong/Weak FEC and Digital Wrapper BCH Macro (continued) Functional Description of BCH Macro (continued) 20.1.1 .5 B2 Compensate Since the FEC function uses overhead bytes from the MSOH and consequently overwrites bytes currently covered by B2, the BCH encoder compensates B2 appropriately to reflect the change in the FEC MSOH bytes; the FEC check bits cover the B2 byte. The FEC check bytes and FSI byte in the RSOH are not included in B2 compensation ; only the FEC check bytes in the MSOH are included in B2 compensation . This ensures backward compatibility of B1 and B2 calculation for nonFEC equipment . 20.1.1 .6 Error Insert Various types of errors can be inserted for BCH code testing . The error insert inserts various types of errors for BCH code testing . For each slice, an error insert block accepts 32 bits of data. There are a total of 4 slices instantiated to create the 128-bit wide data for 16-way and 64-way 10 Gbits/s mode. A 32-bit mask register corresponds to the 32-bit wide data bus for the error insertion . When the mask bit is set to logic 1, the corresponding data bit is inverted. The number of skipping clock cycles can be programmed through the microprocessor. Error bits combining with the number of skipping clock cycles can be repeated by using a control bit bus . The first column of error can be chosen via the microprocessor. The stream of errors start when there is a 0 => 1 transition on the error control bit . Note : To ensure all errors are inserted within the valid range, the following equation can be used: (skip + 1) x (repeat - 1) + row x 1080 + column < 9 x 1080 Table 93. BCH Error Insert Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) Mask for Error Insertion on the 32-bit Data Bus Number of Skipping Clock Cycles Between the 32-bit Error Patterns (valid range is 0-1023) Number of Repeating Clock Cycles Between the 32-bit Error Patterns (valid range is 0 (no error)-255) Start Row (valid range is 0-8) Start Column (valid range is 0-1079) Error Start Control Bit Error Insert Finish State Error Insert Finish Alarm Error Insert Finish Mask Error Insert Finish Persist BCH_TXERR-MASKL_SO/ BCH-TXERR-MASKU_SO (R/W) BCH_TXERR-SKIP SO (R/W) BCH-TXERR-MASK-L/ BCH-TXERR-MASK-U BCH-TXERR-SKIP 4 4 0x1148/ Ox114C 0x1158 BCH-TXERR-REPEAT-SO (R/W) BCH-TXERR-REPEAT 4 0x1154 BCH-TXERR-ROWCOL SO (R/W) BCH_TXERR-ROW 4 0x1150 BCH-TXERR-ROWCOL SO (R/W) BCH TXERR-COL 4 0x1150 BCH_TXERR-START-SO (R/W) BCH_TX_STATE_SO (RO) BCH TX ALARM SO (W1C) BCH_TX_MASK_SO (R/W) BCH TX PERSIST SO (RO) BCH-TXERR-START BCH-TXERR-FINISH BCH TXERR FINISH A BCH-TXERR-FINISH-M BCH TXERR FINISH P 4 4 4 4 4 0x1158 Ox10E4 0x1020 Ox106C Ox10B4 Agere Systems Inc. 123 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 20 Operational Description July 2002 BCH Macro (continued) 20.1 Functional Description of BCH Macro (continued) 20.1 .2 BCH Decoder The BCH decoder detects and corrects transmission errors of STM-16/STM-64 (STS-48/STS-192) signals . Data arrives to the BCH decoder grouped as four slices of 32 bits. Because the code block definition for an STM-64 (STS-192) is identical to that of an STMA6 (STS-48), and the transpose demultiplexer (TDMX) reorders the data so that the STM-64 (STS-192) is divided into its four constituent STS-48 data streams, each slice can operate independently even in STM-64 (STS-192) mode . One difference between STM-16 (STS-48) mode and STM-64 (STS-192) is Q1 byte interpretation, which will be explained in Section 20.1 .2 .3 on page 125 . When defects (LOC/LOS/OOF/LOF/MS-AIS) are found, the associated BCH decoder is disabled . The diagram of the BCH decoder, in each slice, is shown in Figure 48 on page 114 . 20.1 .2.1 FEC Frame Generate All RSOH bytes (including undefined RSOH bytes) of incoming STMA6 (STS-48) signals are not included in the decoding of the FEC and are replaced with zeros before error detection . All Q1 bytes are corrected before retransmission by correcting regenerators, and therefore are included in the decoding of the FEC . For flexible operation, check bits are extracted in either MSB first or LSB first. This is configured by software . Table 94. BCH Frame Generate Register Summary Function BCH FEC Extract Control 20.1.2.2 I Register Name (First Occurrence) BCH-RXPROV S0 (R/W) Register Bits I BCH DEC EXTRACT I Qty. 4 I 1st Addr (hex) 0x1140 Error Detect Each slice has eight independent error detect blocks and each detect block consists of three subblocks : syndrome calculate, BMA (Berlekamp-Massey algorithm), and chien (time-domain error location) search . Uncorrectable errors are detected and reported to the BCH stat as well as corrected bits, per slice. 124 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 20 20.1 with Strong/Weak FEC and Digital Wrapper BCH Macro (continued) Functional Description of BCH Macro (continued) 20.1.2.3 FSI Bit Interpret In hardware mode, the FEC decoder is required to interpret the FEC status indication (FSI) bits to enable correcting function. This is to prevent miscorrection when FEC encoding is not present . The Q1 byte locations and FSI bits information are the same as those of the encoder. When the BCH decoder operates in STM-64 (STS-192) mode, the FSI carrying byte is located in the first Q1 byte, and therefore, decoding states of the slices which have the second, third, and fourth Q1 bytes follow that of the master slice, which has the first Q1 byte. The decoding state transition according to the received FSI is as follows . The decoding state can be changed from FEC-ON to FEC-OFF with encoder delay upon receipt of third consecutive NON-01, and from FEC-OFF with encoder delay to FEC-ON upon receipt of the ninth consecutive FSI value 01 . Table 95. BCH FSI Register Summary Function BCH BCH BCH BCH Correction Correction Correction Correction 20.1.2.4 Status Status Interrupt Alarm Status Interrupt Mask Status Persistency Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) BCH RX STATE SO (RO) BCH_RX_ALARM_SO (W1 C) BCH_RX_MASK_SO (R/W) BCH RX PERSIST SO (RO) BCH DEC FSI BCH_DEC_FSI_A BCH_DEC_FSI_M BCH DEC FSI P 4 4 4 4 Ox 10E0 0x101 C 0x1068 Ox 10B0 Error Correct The received data is delayed before being corrected, while transmission errors are detected. There are two ways of controlling decoding states. The first is by hardware (FSI controlled) and the second is by software . When the BCH decoder is set to hardware mode, the correcting function will follow the FSI as mentioned above . The state transition between FEC-ON and FEC-OFF is hitless . In software mode, there are the four following decoding states . Two are the same as hardware mode, and monitoring and shutdown modes are added: -FEC-ON . -FEC-OFF with decoder delay. - Monitoring (error detect and count but not correct without decoder delay). -Shutdown (no error detect nor correct) . In monitoring and shut-down modes, the received data is transmitted downstream without delay. Table 96. BCH Decoding Register Summary Function BCH Decoding Mode Select 20.1.3 Register Name (First Occurrence) I BCH-RXPROV SO (R/W) Register Bits I BCH DEC MODE Qty. I 4 1 st Addr (hex) I 0x1140 BCH Statistics (BCH-Stat) The BCH-stat counts correctable errors that are detected and corrected in the BCH decoder. The monitoring of the line BER before correction can be done through the knowledge of the exact number of corrected bits. The errors that remain uncorrected after forward error correction can be considered negligible in the computation of BER for low error rates. Agere Systems Inc. 125 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 20 Operational Description July 2002 BCH Macro (continued) 20.1 Functional Description of BCH Macro (continued) 20.1.3.1 Error Count The corrected bits and the uncorrectable blocks are accumulated per slice in 16-bit saturating counters based on either bit or block errors . In bit mode, each corrected error (or uncorrectable block) causes the counter to increment. If block error is selected, each BCH frame which has a corrected error (or uncorrectable block) causes the counter to increment by one . The counter will stop at the maximum value, will not roll over, and is cleared by the PMRST signal . Table 97 . BCH Error Count Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) BCH Error Count Control BCH Rx Corrected Bit Counter BCH Rx Uncorrectable Block Counter BCH ERR_PROV_SO (R/W) BCH ERR_BITBLK 4 Ox115C BCH_ERR_BITCNT_L_SO/ BCH ERR BITCNT U SO (RO) BCH_ERR_BLKCNT_L_SO/ BCH ERR_BLKCNT U SO (RO) BCH_ERR_BITCNT_L/ BCH ERR BITCNT U BCH UNC BLKCNT_L/ BCH UNC BLKCNT_U 4 0x1165/ 0x1164 Ox116E/ Ox116D 20.1.3.2 4 BER Monitor The corrected errors are used to detect SF and SD conditions. The BER threshold for each defect is separately provisionable for each slice over a range of 1x10-N values, where N = 3 to 9. The BER algorithm is the same as that of the RS decoder (refer to Section 16.1 .2, BER Monitor, on page 89 for a detailed description) . Table 98. BER Threshold Time and Error Limits for Line SD and SF Detection BER Threshold 1 x 10-3 1 x 10-4 1 x 10-5 1 x 10-6 1 x 10-7 1 x 10-8 1 x 10-9 1 x 10-10 Detection Time II Detect Error Limit Clear Error Limit STS-48/ STM-16 STS-192/ STM-64 STS-48/ STM-16 STS-192/ STM-64 STS-48/ STM-16 STS-192/ STM-64 1 .0 ms 1 .0 ms 4 .0 ms 32 .0 ms 128 .0 ms 1 s 8.2s 65.6s 0.25 ms 0.25 ms 1 .0 ms 8.0 ms 32.0 ms 250 ms 2.1 s 16.4s 992 248 99 79 63 50 40 - 992 248 99 79 63 50 40 - - - 496 495 395 315 250 200 160 496 495 395 315 250 200 160 I II I II I The SD/SF BER control bits select the bit error rate for a particular slice. These control bits then select the detection time, detect error limit, and clear error limit for each slice. The detect error limit and the clear error limit registers contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper bit for a time unit specifier. For the detection time register, the value contained in the lower 15 bits is either specified in 0.125 ms units (upper bit = 0) or in 0.128 s units (upper bit = 1). Note : The receive sync pulse is used as the timing reference . 126 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 20 20.1 with Strong/Weak FEC and Digital Wrapper BCH Macro (continued) Functional Description of BCH Macro (continued) Table 99. BCH BER Monitor Register Summary BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH Function Register Name (First Occurrence) Register Bits Qty. SD Threshold Select SF Threshold Select SD Detect SF Detect SD Detect Alarm SF Detect Alarm SD Detect Mask SF Detect Mask SD Detect Persistency SF Detect Persistency BER Report BER-3 Detection Time BCH_ERR_PROV_SO (R/W) BCH_ERR_PROV_SO (R/W) BCH-STATE_S0 (RO) BCH-STATE_S0 (RO) BCH-ALARM. SO (W1 C) BCH-ALARM_S0 (W1 C) BCH_MASK_SO (R/W) BCH_MASK_SO (R/W) BCH-PERSIST_S0 (RO) BCH-PERSIST_S0 (RO) BCH_ERR_RPT_SO (RO) BCH BERDT3 (R/W) BCH_RX_BER_SD BCH_RX_BER_SF BCH_RX_BER_SD_DET BCH_RX_BER_SF_DET BCH_RX_BER_SD_DET_A BCH_RX_BER_SF_DET_A BCH_RX_BER_SD_DET_M BCH_RX_BER_SF_DET_M BCH_RX_BER_SD_DET_P BCH_RX_BER_SF_DET_P BCH_BER_REPORT BCH_BER_DT_UNIT_3/ BCH_BER_DT_VAL_3 BCH_BER_DT_UNIT_4/ BCH_BER_DT_VAL_4 BCH_BER_DT_UNIT_5/ BCH_BER_DT_VAL_5 BCH_BER_DT_UNIT_6/ BCH_BER_DT_VAL_6 BCH_BER_DT_UNIT_7/ BCH_BER_DT_VAL_7 BCH_BER_DT_UNIT_8/ BCH_BER_DT_VAL_8 BCH_BER_DT_UNIT_9/ BCH_BER_DT_VAL_9 BCH_BER_DT_UNIT_10/ BCH_BER_DT_VAL_10 BCH_BER_SET_LIMIT_3 BCH_BER_SET_LIMIT_4 BCH_BER_SET_LIMIT_5 BCH_BER_SET_LIMIT_6 BCH_BER_SET_LIMIT_7 BCH_BER_SET_LIMIT_8 BCH_BER_SET_LIMIT_9 BCH_BER_CLR_LIMIT_4 BCH_BER_CLR_LIMIT_5 BCH_BER_CLR_LIMIT_6 BCH_BER_CLR_LIMIT_7 BCH_BER_CLR_LIMIT_8 BCH_BER_CLR_LIMIT_9 BCH BER CLR LIMIT 10 4 4 4 4 4 4 4 4 4 4 4 1 1st Addr (hex) Ox115C Ox115C Ox10E0 Ox10E0 0x101 C Ox101C 0x1168 0x1168 Ox10B0 Ox10B0 0x1160 0x1190 1 0x1191 1 0x1192 1 0x1193 1 0x1194 1 0x1195 1 0x1196 1 0x1197 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Ox11C0 Ox11C1 Ox11C2 Ox11C3 Ox11C4 Ox11C5 Ox11C6 0x11 FO 0x11 F1 0x11 F2 0x11 F3 0x11 F4 0x11 F5 0x11 F6 BCH BER-4 Detection Time BCH BERDT4 (R/W) BCH BER-5 Detection Time BCH BERDT5 (R/W) BCH BER-6 Detection Time BCH BERDT6 (R/W) BCH BER-7 Detection Time BCH BERDT7 (R/W) BCH BER-8 Detection Time BCH BERDT8 (R/W) BCH BER-9 Detection Time BCH BERDT9 (R/W) BCH BER-10 Detection Time BCH BERDT10 (R/W) BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH BCH_BERSET3 (R/W) BCH_BERSET4 (R/W) BCH_BERSET5 (R/W) BCH_BERSET6 (R/W) BCH_BERSET7 (R/W) BCH_BERSET8 (R/W) BCH_BERSET9 (R/W) BCH_BERCLR4 (R/W) BCH_BERCLR5 (R/W) BCH_BERCLR6 (R/W) BCH_BERCLR7 (R/W) BCH_BERCLR8 (R/W) BCH_BERCLR9 (R/W) BCH BERCLR10 (R/W) BER-3 Detect Error Limit BER-4 Detect Error Limit BER-5 Detect Error Limit BER-6 Detect Error Limit BER-7 Detect Error Limit BER-8 Detect Error Limit BER-9 Detect Error Limit BER-4 Clear Error Limit BER-5 Clear Error Limit BER-6 Clear Error Limit BER-7 Clear Error Limit BER-8 Clear Error Limit BER-9 Clear Error Limit BER-10 Clear Error Limit Agere Systems Inc. 127 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 21 Operational Description July 2002 21 .1 SONFEC Input MUX and Output MUX Functional Description of SONEC Input MUX and Output MUX The SONFEC input MUX and output MUX transfer data across the slices depending upon their mode of operation . In 2 .5 Gbits/s mode, they bypass the data received . In 10 Gbits/s mode, they transfer data across slices to/from four aggregate 32 bits of data on each of the slice clocks. The input MUX also performs the loopback functionality in SONFEC. 22 22.1 Loss-of-Signal (LOS) Detector and Framer Functional Description of LOS Detector and Framer The LOS detector monitors the data for loss of signal . The framer macro generates the frame sync and loss-offrame outputs . These functions can be optionally disabled, allowing data to pass through unchanged . The framer also generates an 8 kHz reference output . 22.1.1 Loss-of-Signal (LOS) Detector The data is monitored by the LOS detector macro for loss of signal (LOS) . In STS-192 mode, there is a single LOS detector. In STS-48 mode, there is a separate LOS detector on each STS-48 input . On powerup, an LOS defect is declared if all zeros data is received continuously for a programmable time threshold . This time threshold is provisional through the loss-of-signal (LOS) threshold register for each channel, and can be set to any value from 0 gs (i .e., LOS detection disabled) to 105 gs, with a resolution of 102 .88 ns (64 times the period of the 622 .08 MHz clock) . The LOS defect is subsequently cleared when two successive valid framing patterns are received with no period of all zeros exceeding the time threshold . Detection of an LOS defect is indicated by a latched alarm status bit, a persistency bit, and a 1 s PM bit being set in the corresponding LTE receive channel registers . In addition, LOS causes alarm indication signal (AIS) generation by the overhead processor block in all STS-48 or STS-192 affected . Both the transmit and receive LOS detectors are identical. 22.1.2 Framer (A1 and A2) In STS-192 mode, framing is performed on a single channel. In STS-48 mode, framing is performed on four independent channels. The framer also supports enhanced framing, where every other A1 byte and A2 byte is inverted to better maintain do balance on the optical line. A1_A1A1_A1 . . . A1_A1 = F609F609 . . . F609. A2A2A2A2 . . . A2A2 = 28D728D7 . . . 28D7 . The STS framing bytes are present in all STS-1 time slots of the STS-48 or STS-192 . When normal framing is selected, the A1 bytes are set to OxF6, while the A2 bytes are set to 0x28. If enhanced framing is selected, using the framing mode control bit, the A1 and A2 bytes contain normal framing in odd STS-1 time slots and the inverse value in even STS-1 time slots. The framer outputs frame-aligned data and the 8 kHz reference (free-running) signal. The STS-192 framer is described in the following sections. The STS-48 framer is similar. 128 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 22 with Strong/Weak FEC and Digital Wrapper Loss-of-Signal (LOS) Detector and Framer (continued) 22.1 22.1.2.1 Functional Description of LOS Detector and Framer (continued) Framer FSM The framer finite state machine (FSM) is responsible for determining the severely errored framing (SEF) and lossof-framing (LOF) SONET framing alarms for each channel. The framer FSM is shown in Figure 52. The FSM comes out of reset in the SEF state with the SEF and LOF alarms active . The framing pattern used is the 16-bit word consisting of the last A1 byte and the first A2 byte. The first occurrence of the framing pattern transfers the FSM to the frame confirm state. Frame timing is also synchronized . Another framing pattern that matches coincident with the expected frame timing transfers the state to in-frame (i.e., it takes two consecutive valid framing patterns to frame to an incoming signal) . Outside the SEF and frame confirm states, the SEF alarm output is inactive . As shown in the FSM, when in-frame, four consecutive framing errors are required to be transferred back to the SEF state. The LOF alarm is asserted if SEF persists for 24 frames (3 ms). The LOF alarm is terminated eight frames (1 ms) after the SEF alarm is terminated (i.e., eight frames after the FSM enters the in-frame state), provided the SEF state is not reentered (as per SONET objectives) . The framing pattern is a subset of the A1A2 STS-N pattern . This design uses the 16-bit A1A2 boundary as the framing pattern which evaluates to an average SEF defect occurrence time of 31 .79 min ., assuming a Poisson bit error rate (BER) of 10-3. This is greater than the minimum average SONET requirement of 6 min . The SEF alarm is reported by a latched register bit in the LTE receive nonservice-affecting alarm register for the respective channel . The LOF alarm is reported by a latched register bit in the LTE receive service-affecting alarm register for the respective channel . In addition, a persistency bit for LOF exists in the LTE receive service-affecting persistency register. Detection of LOF and SEF defects are also indicated by the LTE receive last-second PM register. Detected LOF defect detection causes AIS to be inserted in all affected STS-48 or STS-192 . This AIS insertion is disabled by default after reset and can be enabled using the LOF AIS disable control register bit for each channel, or replaced by insertion upon SEF detection using the SEF AIS disable control bit . Another control bit is the enhanced framing mode bit. These control bits are part of the LTE provisioning register for the respective channel . FRAMING PATTERN CONFIRMED FRAME CONFIRM FRAMING PATTERN FOUND IN FRAME FOUR CONSECUTIVE FRAMING ERRORS FRAMING PATTERN NOT COMFIRMED SEF RESET Figure 52. Framer FSM Agere Systems Inc. 129 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 22 22.1 Loss-of-Signal (LOS) Detector and Framer (continued) Functional Description of LOS Detector and Framer (continued) Table 100 . Framer Register Summary Function Framer Disable Control Framer Mode Control Enhanced Framing Enable AIS Insertion on SEF AIS Insertion on LOF LOF State SEF State LOF Alarm SEF Alarm LOF Alarm Mask SEF Alarm Mask LOF Persistency SEF Persistency LOF PM SEF PM Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC RX BYPASS SO (R/W) SONFEC RX MODE (R/W) OHP RX_PROV_SO (R/W) OHP RX FRM DIS RX FRM MODE 4 1 RX_ENH FRMG_ENB 4 0x1115 0x1110 0x1310 RX SEF AIS DIS 4 RX LOF AIS DIS RX LOF 4 4 RX SEF RX LOF A 4 4 RX SEF A RX LOF M 4 4 RX SEF M RX LOF P 4 4 RX SEF P RX LOF PM 4 4 RX SEF PM 4 OHP RX PROV SO (R/W) OHP RX PROV SO (R/W) OHP RX SA STATE SO (RO) OHP RX NSA 0 STATE SO (RO) OHP RX SA ALARM SO (W1C) OHP RX NSA 0 ALARM SO (W1 C) OHP RX SA MASK SO (R/W) OHP RX NSA 0 MASK SO (R/W) OHP RX SA PERSIST SO (RO) OHP RX NSA 0 PERSIST SO (RO) OHP RX PM SO (RO) OHP RX PM SO (RO) 0x1314 0x1314 Ox10E8 Ox 10EC 0x1024 Ox102C 0x1070 0x1078 Ox10B8 Ox 10BC Ox132C Ox132C Table 101 . LOS Detector Register Summary Function LOS Detection Mode Control LOS Detect Time Threshold LOS LOS LOS LOS LOS 130 State Alarm Alarm Mask Persistency PM Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC RX_MODE (R/W) RX_LOS MODE 1 0x1110 OHP RX_LOS SO (R/W) RX_LOS THRESHOLD 4 0x1324 OHP RX SA STATE SO (RO) OHP RX SA ALARM SO (W1 C) OHP RX SA MASK SO (R/W) OHP RX SA PERSIST SO (RO) OHP RX PM SO (RO) RX LOS RX LOS A 4 4 Ox 10E8 0x1024 0x1070 0x10138 Ox132C RX LOS M RX LOS P RX LOS PM 4 4 4 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 23 23.1 with Strong/Weak FEC and Digital Wrapper Transmit Alignment FIFO Functional Description of Transmit Alignment FIFO The alignment FIFO block will align four independent 2 .5 Gbits/s data channels into one 10 Gbits/s data channel . Elastic buffers (FIFOs) are used to align each incoming 2.5 Gbits/s stream (slice 1, slice 2, and slice 3) to the master 77.76 MHz clock (slice 0). These FIFOs will absorb delay variations of up to 1000 ns between the first and the last incoming 2.5 Gbits/s streams, given that the four streams are byte-synchronous (on the byte boundary). Each input 2.5 Gbits/s data channel may be inhibited from contributing to the overall alignment by setting the corresponding inhibit bit (ALGN_INH) high. When one particular channel is inhibited from being aligned with the rest, the frame pulse for that channel is aligned with the aligned frame pulses of the rest of the channels and the data is brought out as all ones. The FIFO depths can be monitored to give an indication of the individual operating depths (write address-read address). In addition, an overflow bit, when set using FIFO MIN and FIFO MAX values, will indicate the FIFO fullness or emptiness for each channel. The global resync signal will align all the channels when there is a 0 to 1 transition on the GLBL_RESYNC input. There is an alarm bit which will indicate if the alignment is not correct for a particular channel . If the alarm bit for a particular channel is high (indicating that the channel did not get aligned), the frame pulse for that channel is aligned with the pseudoframe pulse and the data is all ones. The pseudoframe pulse is the output of a free-running counter when there is no alignment performed . After alignment, the pseudoframe pulse occurs at the same position as the frame pulses from aligned channels. Note : The global resync signal must be asserted if the original delay increases between the streams. The BYPASS input signal will cause the alignment to be bypassed and the data streams will be brought out as if it came in on time. (The input bits MPU_SONFEC_TX_10G_2G5, V10G_MODE N, and BYPASS should all be set to zeros in order for the alignment to take place. This block also supports short-frame mode.) To use the alignment FIFO on Tx side, all four groups of four bits (16 bits total) must be frequency and phase aligned on arrival . Internally, only the slice 0 clock is used (this is related to virtual 10 Gbits/s mode). In this instance, it is important to understand that the alignment FIFO in the SONFEC block is used to frame align the four streams. The FIFO alarm bit indicates if a stream is not correctly aligned with the other frames. A global resync is needed for alignment if the original delay increases between the inputs . While the delay between the inputs is less than the original delay, the device absorbs the delay variation automatically and no global resync is needed. Agere Systems Inc. 131 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 24 24.1 Operational Description July 2002 131 Monitoring Functional Description of 131 Monitoring The section BI P-8 byte is located in the first STS-1 of the STS-48 or STS-192 only, and carries the even parity of the scrambled data in the previous STS-48 or STS-192 frame . In every frame, the received B1 value is extracted and compared to the calculated BI P-8 for the previous frame . Errors in the BI P-8 code are tabulated in an internal 16-bit counter based on either bit or block errors, as provisioned for each channel through the B1 BIP mode control bit . In bit mode (selected by default), each BIP-8 bit in error causes the counter to increment . If block error is selected, each BIP-8 code in error causes the counter to increment only once. Regardless of which mode is selected, the value in the counter is transferred to the section coding violation (CV-S) register on the rising edge of the performance monitoring clock, at which point the counter is cleared . The counter will stop at the maximum value and will not roll over. Table 102 . B1 Monitoring Register Summary Function B1 Monitoring Disable B1 Monitoring Mode Bit/Block Error Control Last Second Coding Violations Count 25 25.1 Register Name (First Occurrence) Register Bits Qty. SONFEC RX BYPASS SO (R/W) SONFEC_RX_MODE (R/W) OHP_RX_PROV_SO (R/W) OHP-RX_CVS PM SO (RO) OHP RX B1MON DIS RX_B1MON_MODE RX_B1BIP_MODE RX_CVS 4 1 4 4 1st Addr (hex) 0x1115 0x1110 0x1310 0x1353 Descrambler Functional Description of the Descrambler The data from the framer is optionally descrambled using the SONET/SDH standard generator polynomial : 1 + x6 + x7 . The descrambling can be disabled through the DESCRM DIS bit in the LTE receive channel provisioning register for each channel . Table 103 . Descrambler Register Summary Function Descrambling Control Descrambling Mode 132 I Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC_RX_BYPASS SO (R/W) OHP RX-DESCR-DIS 4 0x1115 1 I 0x1110 SONFEC RX-MODE (R/W) I RX-DESCR MODE I Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 26 26.1 with Strong/Weak FEC and Digital Wrapper Transpose Demultiplexer Functional Description of the Transpose Demultiplexer (TDMX) The TDMX macro receives the STS-192 stream in 16-byte blocks. Each set of 16 bytes belongs to one of the four possible STS-48 output channels. The macro then outputs bytes for each of the STS-48 channels every clock period. For STS-192 data, the input stream must be demultiplexed to create four STS-48 data streams for further processing . The transpose demultiplexer reorders the data so that the STS-192 is divided into its four constituent STS-48 data streams. The byte ordering of the individual STS-1s, or STS-1 components of an STS-Nc that comprise the STS-192 as it enters the TDMX and after the TDMX (STS-48 byte ordering), and the details of the STS-192 to STS-48 demultiplexing, can be found in GR-253-CORE Section 5-1, Network Element Architectural Features (Multiplexing Procedure) page 5-1 . If the device is in STS-48 mode, the data is received on all four channels and the TDMX should be bypassed. Table 104 . Transpose Demultiplexer Register Summary Function Transpose Demultiplexer Disable Control Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC RX_TP BYPASS (R/W) RX_TDMX_DIS 1 0x1112 133 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 27 27.1 RDI/AIS Detection Functional Description of RDI/AIS Detection The RDI/AIS detector in the receive direction detects AIS frames prior to BCH decoding . If AIS is detected, then BCH decoding is disabled . In the transmit direction, it detects AIS before overhead processing and, if detected, disables BCH encoding . RDI in the receive direction is done during overhead processing . Table 105 . RDI/AIS Detector Register Summary Function AIS Detection Disable Control AIS Detection Mode Control AIS State AIS Alarm AIS Alarm Mask AIS Persistency AIS PM RDI State (Tx Only) RDI Alarm (Tx Only) RDI Alarm Mask (Tx Only) RDI Persistency (Tx Only) RDI PM (Tx Only) I Register Name (First Occurrence) Register Bits Qty. SONFEC RX_BYPASS SO (R/W) OHP RX_AISD DIS 4 0x1115 SONFEC RX_MODE (R/W) RX_AISD MODE 1 0x1110 OHP_RX_SA_STATE_S0 (RO) OHP_RX_SA_ALARM_SO (W1C) OHP_RX_SA_MASK_SO (R/W) OHP_RX_SA_PERSIST_S0 (RO) OHP RX PM S0 (RO) OHP TX NSA STATE S0 (RO) OHP_TX_NSA_ALARM_SO (W1C) OHP_TX_NSA_MASK_S0 (R/W) RX_AIS_L RX_AIS_L_A RX_AIS_L_M RX_AIS_L_P RX LINE AIS PM TX_LINE_RDI TX_LINE_RDI_A TX_LINE-RDI M 4 4 4 4 4 4 4 4 0x10E8 0x1024 0x1070 0x10B8 0x132C 0x10F4 0x1034 0x1080 OHP_TX_NSA_PERSIST S0 (RO) TX_LINE RDI P 4 Ox 10C4 4 I 0x1394 OHP TX PM S0 (RO) I TX LINE-RDI PM I 1st Addr (hex) Note : In 10 Gbits/s mode, the master slice (that processes the STS-48 #1 in a STS-192) is slice 3 . Therefore, though all the rest of the 10 Gbits/s alarms are reported in slice 0, in the RDI/AIS detector, the alarms in 10 Gbits/s are reported at slice 3 registers. Following the same reason, regardless of 10 Gbits/s or 2 .5 Gbits/s mode of operation, all the slices are to be programmed . 134 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 28 28.1 with Strong/Weak FEC and Digital Wrapper 132 Monitoring Functional Description of 132 Monitoring The line BIP-8 is located in each STS-1 of the STS-48, or STS-192, and carries the even parity for the line overhead and SPE data within the previous STS-1 frame. The N-line BIP-8 bytes in an STS-N are intended to provide a single error monitoring facility for the entire STS-N signal . Thus, each B2 monitor block is used to check the 48 line BIP-8 codes, whether in STS-48 or STS-192 mode. Each BIP-8 bit found to be in error causes an internal 22-bit counter to increment. The value in the counter is transferred to the line coding violation (CV-L) registers on the positive edge of the performance monitoring clock, at which point the counter is cleared . The counter will stop at the maximum value and will not roll over. When in STS-192 mode, a read of the STS-48 slice 0 CV-L registers returns the 24-bit sum of the four constituent STS-48 channel CV-L counts . Therefore, though the registers are 24-bit, in 2.5 Gbits/s mode, only the lower 22 bits are valid . In 10 Gbits/s mode, only slice 0's 24 bits are valid, though the maximum count is OxFFFFFC. During AIS insertion due to LOS, LOF, SEF, or line AIS, processing of the B2 byte is inhibited. It takes five frames of line AIS before the actual line AIS alarm is declared. Once AIS insertion is removed, processing of the B2 byte is delayed for two frames. A single B2 controller block collects all the B2 errors and sums up to a single register for 10 Gbits/s mode of operation. Both transmit and receive B2 monitors are identical . In the receive direction, two B2 monitors are implemented before and after BCH decoding. These two B2 monitors can be used to compute the coding gain of the decoder. Table 106 . B2 Register Summary Function B2 Monitoring Disable (Rx Only) B2 Monitoring Mode (Rx Only) Coding Violations Count (Rx Only) B2 Monitoring Disable (Rx Only) B2 Monitoring Mode (Rx Only) Coding Violations Count (Rx Only) B2 Monitoring Disable (Tx Only) B2 Monitoring Mode (Tx Only) Coding Violations Count (Tx Only) Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1 st Addr (hex) SONFEC RX_BYPASS SO (R/W) OHP-RX_PRE B2MON DIS 4 0x1115 SONFEC RX_MODE (R/W) RX_PRE B2MON MODE 1 0x1110 OHP RX_PRE_CVL_L_PM_SO/ OHP RX-PRE_CVL U PM SO (RO) SONFEC RX_BYPASS SO (R/W) RX_PRE_CVL L/ RX_PRE CVL U OHP RX_POST B2MON-DIS 4 4 Ox 134B/ Ox 134A 0x1115 SONFEC RX_MODE (R/W) RX_POST B2MON MODE 1 0x1110 OHP RX_POST_CVL L_PM_SO/ OHP RX-POST CVL U PM SO (RO) SONFEC_TX_BYPASS SO (R/W) RX_POST CVL L/ RX_POST CVL U OHP_TX_B2MON DIS 4 4 0x1342/ 0x1341 0x1119 SONFEC_TX_MODE (R/W) TX_B2MON-MODE 1 0x1111 OHP TX CVL L-PM SO/ OHPTX CVL LPM SO (RO) TX CVL L/ TXCVL U 4 Ox139D/ Ox139C 135 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 29 Operational Description July 2002 BER-SD/SF Detection 29.1 Functional Description of BER-SD/SF Detection The line/section BIP-8 errors can also be tracked in 16-bit signal fail (SF) and signal degrade (SD) counters. These counters are used to detect SF (signal fail) and SD (signal degrade) conditions for protection switching . The BER threshold for each defect is separately provisionable for each channel over a range of 1 x 10-N values, where N = 3 to 5 for SF and N = 5 to 9 for SD . The detection times and error limits used to detect and clear both defects are dependent on the provisioned BER threshold, as shown in Table 107 . The STS-192 values shown in the table are the powerup defaults. These values can be changed through the corresponding registers and are common to all channels. The clearing BER threshold for each defect is always 1/10th of the detection threshold . As can be seen in Table 107, the range of possible detect thresholds is 1 x 10-3 to 1 x 10-9, which results in clear thresholds of 1 x 10-4 to 1 x 10-10 . For example, to detect SD at 1 x 10-5 BER in an STS-192, the detection time is 4 ms and the detect error limit is 358 . The clearing would take place at 1 x 10-6 BER, with a clearing time of 6.5 ms and a clearing error limit of 77. Figure 53 on page 137 illustrates SD detection and clearing using the default STS-192 values specified in Table 107. SD thresholds of 1 x 10-10 to 1 x 10-15 are supported through software . Table 107 . BER Threshold Time and Error Limits for Line SD and SF Detection BER Threshold 1 x 10-3 1 x 10-4 1 x 10--5 1 x 10--6 1 x 10--7 1 x 10-8 1 x 10-9 1 x 10--10 Detection Time I Detect Error Limit Clear Error Limit STS-48 STS-192 STS-48 STS-192 STS-48 STS-192 4 ms 4 ms 4 ms 31 ms 312 .5 ms 2600 ms 21 s 170s 4 ms 4 ms 4 ms 6.5 ms 65 ms 650 ms 5250 ms 41 s 4818 862 81 62 62 51 40 - 19453 3543 358 51 51 51 40 - 957 114 91 91 77 63 52 3734 423 77 77 77 63 51 I I I I I In STS-192 mode, the thresholds are compared against the sum of the four STS-48 channel SF and SD counts . A detected SF or SD defect causes a corresponding maskable interrupt status bit to be set in the LTE receive slice N service-affecting alarm register. The SD/SF BER control bits in the LTE receive channel N maintenance register select the bit error rate for a particular channel. These control bits then select the detection time, detect error limit, and clear error limits for each channel from the LTE receive SD/SF registers. The detect error limit and the clear error limit registers contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper 1 bit for a time unit specifier. For the detection time register, the value contained in the lower 15 bits is either specified in 0.5 ms units (upper bit = 0) or in seconds (upper bit = 1). Note that the performance monitoring clock input to the device is used as the timing reference when the detection time is expressed in seconds . The SD/SF BER select control bits are described in Table 108 and Table 109 on page 138. A fixed windowing scheme is used for SD/SF detection . The window size is determined by the value in the detection time register for the specified bit error rate. An SD or SF alarm is declared immediately when the accumulated error count exceeds the value specified in the detect error limit register. In the detection process, when the error count equals the threshold, the window is prematurely ended and clearing process starts immediately. If this error limit is not reached by the end of the window, then the accumulated error count is reset to zero. When an SD or SF alarm is declared, the accumulated error count resets and clearing begins using the bit error rate threshold that is 1/10th of the specified value along with the corresponding detection time registers . Clearing of the SD or SF alarm only occurs at the end of the window when the accumulated error count is less than the value specified in the clear error limit register. 136 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 29 with Strong/Weak FEC and Digital Wrapper BER-SD/SF Detection (continued) 29.1 Functional Description of BER-SD/SF Detection (continued) The SONFEC incorporates two SD/SF detectors in the receive direction . These two monitors can be used as a measurement for the coding gain. The pre-SD/SF detector monitors the B1 or B2 errors for SD/SF detection before BCH decoding. The post-SD/SF detector monitors the B2 errors after BCH decoding. U 358 O W N m D W g U U Q D U 77 SD DETECTION WINDOW SD CLEARING WINDOW TIME (ms) Figure 53. Example of STS-192 SD Detection (10-5 BER) and Clearing (10-6 BER) During AIS, insertion due to LOS, LOF, SEF, or line AIS, processing of the B2 byte is inhibited and the internal SF/SD counters are reset back to zero. It takes 5 frames of line AIS before the actual line AIS alarm is declared; it is likely that the signal degrade alarm will also be triggered . Due to this fact, once AIS insertion is removed, processing of the SD/SF is delayed for 2 frames. Table 108 . SD BER Select Control Register Bits Value RX_PRE SD BER SEL/ RX-POST SD BER SEL 000 001 010 011 100 Others Description Select Select Select Select Select I Select BER BER BER BER BER BER 1 1 1 1 1 1 x x x x x x 10-5. 10-6. 10-7. 10-8. 10-9. 10-5. Note : See Table 110, 132 Register Summary, on page 138 for RX_PRE SD BER SEL and for RX_POST SD BER SEL descriptions . Agere Systems Inc. 137 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 29 BER-SD/SF Detection (continued) 29.1 Functional Description of BER-SD/SF Detection (continued) Table 109 . SF BER Select Control Register Bits Value RX_PRE SF_BER SEL/ RX-POST SF-BER SEL 00 01 10 Others Description Select Select Select I Select BER 1 x 10-3. BER 1 x 10-4. BER 1 x 10-5. BER 1 x 10--3. Note : See Table 110 for RX_PRE SF BER SEL and for RX_POST SF BER SEL descriptions . Table 110. B2 Register Summary Function Register Name (First Occurrence) Register Bits Qty. SD/SF Detection Time (1 x 10-3)1 SD/SF Detect Error Limit (1 x 10-3)1 SD/SF Clear Error Limit (1 x 10-4)1 PRE SD/SF BIP Select SD/SF Threshold Selection SD/SF Interrupt Alarms SD/SF Interrupt Masks SD/SF State 1st Addr (hex) OHP RX_SDSF DT3(R/W) 8 0x1220 OHP- RX SDSF SET3 (R/W) RX_SDSF_ DT_ UNIT_3 RX SDSF DT VAL 3 RX SDSF SET LIMIT 3 7 0x1250 OHP- RX_SDSF CLR4 (R/W) RX_SDSF CLR_LIMIT_4 7 0x1280 OHP RX_MAINT_SO (R/W) RX_PRE SD SF BIPSEL 4 0x1318 OHP RX_MAINT_SO (R/W) RX_PRE_SD_BER_SEL RX_PRE_SF_BER_SEL RX_PRE_SD_A RX PRE SF A RX_PRE_SD_M RX_PRE_SF_M RX_PRE_SD RX_PRE_SF RX_PRE_SD_P RX PRE SF P 4 0x1318 4 0x1024 4 0x1070 4 0x10E8 4 0x10138 SD/SF Persistency OH P RX_SA_ALARM SO (W1 C) OHP RX_SA_MASK_S0 (R/W) OHP RX_SA_STATE SO (RO) OHP RX_SA_PERSIST SO (RO) 1 . These registers are the highest BER . Lower bar configuration registers directly follow these, in secession . 30 30.1 Receive Transport Overhead Processing Functional Description of the Receive Transport Overhead Processing This block terminates the transport overhead and incorporates four identical STS-48 overhead processing blocks . Each block accepts the frame and byte-aligned data for one STS-48 channel and extracts the transport section and line overhead . The extracted overhead is then either stored internally or provided externally on a serial output, and may also be further processed for alarm or performance monitoring purposes . The received overhead bytes can also be allowed to pass through unchanged . The definition and associated storage or processing of each byte is detailed in the following subsections . All processing of overhead bytes is inhibited under AIS conditions. An AIS frame can be generated either by hardware or software . 138 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 30 30.1 with Strong/Weak FEC and Digital Wrapper Receive Transport Overhead Processing (continued) Functional Description of the Receive Transport Overhead Processing (continued) Table 111 . Hardware AIS Generation Summary (Receive) AIS Generation Alarms AIS Generation Disables RX_LOC_A RX_LOS_A RX SEF A RX_LOF_A RX_AIS_L_A RX JO MISMATCH A RX POST SF A RX SEF AIS DIS RX_LOF_AIS_DIS RX_LINE_AIS_DIS RX TIM L AIS DIS RX SF AIS DIS Description Loss of clock . Loss of signal . Detected severely errored frame. Detected loss of frame. Detected line AIS frame . Detected JO mismatch. Detected signal fail . In addition to the individual storage or external availability of the overhead bytes described below, the transport overhead bytes for each STS-48 (individual or part of STS-192) are serialized and output on the TOAC pins of the device . There are four sets of TOAC data pins available for each STS-48 channel . This TOAC interface can operate in two modest . In full TOAC drop mode, the full set of transport overhead bytes for each STS-48 channel (1296 bytes) is output on the TOAC pins. In partial TOAC drop mode, only the transport overhead bytes of the first STS-1 of each STS-48 channel (27 bytes) are output on the TOAC pins. The bytes are output, MSN (most significant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the TOAC clock (20 .736 MHz (full)/ 1 .728 MHz (partial)). The location of the MSN of the first A1 byte is identified by the TOAC sync output going high. In STS-48 mode, each of the TOAC data pins transmits the transport overhead for an STS-48 channel . In STS-192 (full TOAC) mode, the four pairs of the TOAC data pins transmit the STS-192 overhead (5184 bytes), where the TOAC data #1 pins transmit STS channels 1 through 48, and the TOAC data #2, TOAC data #3, and TOAC data #4 pins transmit STS channels 49 through 96, 97 through 144, and 145 through 192, respectively. The receive TOAC drop is described in detail in Section 32.1 on page 160 . Note : In SONFEC, four overhead processors capable of processing an entire STS-48 are implemented . In 2.5 Gbits/s mode, each functions independently. However, in 10 Gbits/s mode, only one slice (that process the STS-48 #1 in a STS-192) functions as master slice and the others function very minimally. In OHP, this master slice is slice 3. Therefore, though all the rest of the 10 Gbits/s alarms are reported in slice 0, in OHP, the alarms in 10 Gbits/s are reported in the slice 3 registers . Following the same reason, regardless of 10 Gbits/s or 2.5 Gbits/s mode of operation, all the overhead processing slices are to be programmed . 30.1.1 Global Overhead Byte Processing Insertion of AIS on the receive side can be either due to hardware or software . If hardware AIS is detected, then the overhead bytes, except A1 and A2, are set to OxFF. A1 bytes and A2 bytes will have the inserted framing pattern. In the following sections, the term rx hw insert ais is used to indicate a hardware controlled AIS condition . The register bit receive SDH mode controls the default values of overhead bytes. If set to 1, the default overhead values are set to OxFF (SDH mode); otherwise, it is set to 0x00 (SONET mode) . Table 112. Receive Overhead Processor General Register Summary Function SONET/SDH Mode OHP Mode Control AIS-L Insert Control Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP_RX_PROV_SO (R/W) SONFEC_RX_MODE (R/W) OHP RX MAINT SO (R/W) RX_SDH_MODE RX_OHP_MODE RX LINE AIS INS 4 1 4 0x1310 0x1110 0x1314 1 . For more information on the two TOAC modes, see Section 2.4, TOAC Insert/Drop Channel Overview, on page 10 . Agere Systems Inc. 139 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 30 Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) 30.1 .1 .1 Default All Undefined Bytes in Section Overhead For all the bytes that are not specified in the following sections, and default bytes in other STS-1 (s) in a STS-48 or STS-192, processing is done as follows : if NOT (rx hw_insert ais) Section Undefined_Byte = Received-Line-Data ; else Section Undefined_Byte = Default SONET_SDH ; end 30.1 .1 .2 Default All Undefined Bytes in Line Overhead For all the bytes that are not specified in the following sections, and default bytes in other STS-1 (s) in a STS-48 or STS-192, processing is done as follows : if (RX_LINE_AIS_INS) or (rx_hw insert_ais) Line Undefined Byte = OxFF; else Line Undefined Byte = Received-Line-Data ; end 30.1.1 .3 Framing Byte (A1) The framing byte A1 is overwritten if not inhibited by software . If normal framing is selected, the A1 bytes are set to OxF6, while the A2 bytes are set to 0x28. If enhanced framing is selected, using the framing mode control bit, the A1 bytes and A2 bytes contain normal framing (OxF6 and 0x28) in odd STS-1 time slots and the inverse value (0x09 and OxD7) in even STS-1 time slots. if (RX_A1A2_INH) and NOT (rx_hw insert_ais) A1 = Received-Line_Data; else if (RX_ENH_FRMG_INS) A1 = Enhanced Framing A1 ; else A1 = Normal Framing A1 ; end Table 113 . A1 Register Summary (Receive) Function A1 Insertion Enable Enhanced Framing 140 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP RX_PROV_SO (R/W) RX_A1A2_INH RX ENH FRMG INS 4 4 0x1310 0x1310 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 30 with Strong/Weak FEC and Digital Wrapper Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) 30.1.1 .4 Framing Byte (A2) The framing byte A2 is overwritten if not inhibited by software . If normal framing is selected, the A1 bytes are set to OxF6, while the A2 bytes are set to 0x28. If enhanced framing is selected using the framing mode control bit, the A1 bytes and A2 bytes contain normal framing (OxF6 and 0x28) in odd STS-1 time slots and the inverse value (0x09 and OxD7) in even STS-1 time slots. if (RX_A1A2_INH) and NOT (rx_hw insert_ais) A2 = Received-Line-Data ; else if (RX-ENH_FRMG_INS) A2 = Enhanced Framing A2 ; else A2 = Normal Framing A2; end Table 114. A2 Register Summary (Receive) Function A2 Insertion Enable Enhanced Framing 30.1.1 .5 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP RX PROV SO (R/W) RX A1A2 INH RX ENH FRMG INS 4 4 0x1310 0x1310 Section Trace (JO) The section trace byte is present in the first STS-1 of the STS-48 or STS-192 only. Specified by the JO message type control bit, the TOH processor supports extraction of either SONET 64-byte (ASCII, <CR><LF> terminated) or SDH 16-byte (E.164) section trace messages which are stored in internal memory. Processing of the received message then depends on the JO message mode control bit . The content of the message is either monitored for a mismatch from a provisioned expected message, or monitored for a sustained change (validation) in the received message . Table 115. JO Message Control Register Bits (Receive) Register Bits Value RX_JO TYPE 0 1 01 10 11/00 RX JO MODE Description SONET format (64 byte) . SDH format (16 byte) . Provisioned (expected value). Validated (sustaining value). I Undefined. Note : See Table 116 for RX_JO TYPE and RX_JO MODE descriptions. If the JO message mode control bit is set to the provisioned mode, then the incoming message is compared against the software programmed expected message . The expected message is stored in the internal memory for each STS-48 channel. A mismatch is declared if a consistent received message differs from the expected message for ten consecutive messages . The mismatch clears when four out of five received messages match the expected message (fixed windowing is used for clearing) . This mismatch state is reflected in the JO message mismatch alarm bit . If JO mismatch is detected, it can optionally generate AIS frames if software enabled. Agere Systems Inc. 141 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 30 Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) When the JO message mode control bit is set to the validated mode, the incoming message is monitored for a sustained change . A sustained change is detected when the received message differs from the last stable message for ten consecutive messages . The new message then becomes the stable message, is stored in internal memory, and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained change). The JO new message alarm bit is set when a sustained change is detected. Selection of the message type, SONET or SDH format, and the content monitoring mode (provisioned or validated), are provisionable on a per STS-48 channel basis through a corresponding LTE receive channel maintenance register. The associated alarms for the two modes are reported in the corresponding LTE receive channel nonsernrice affecting interrupt alarm register. The expected messages for all channels are provisioned through the microprocessor interface using the 64-byte JO access expected message buffer. The sustained or captured messages for all channels are available through the microprocessor interface, using the 64-byte JO access received message buffer. if NOT (rx_hw insert ais) JO = Received-Line-Data ; else JO = OxFF ; end Table 116 . JO Register Summary (Receive) Function Message Type Control Message Mismatch Alarm New Message Alarm Message Mismatch Alarm Mask New Message Alarm Mask Message Mismatch State Message Mismatch Persistency JO Access Expected Message Buffer JO Access Sustained Message Buffer 142 Register Name (First Occurrence) Register Bits Qty. OHP RX_MAINT_SO (R/W) 4 OHP RX_NSA_0_ALARM SO (W1C) RX_JO TYPE RX JO MODE RX_JO MISMATCH_A 4 Ox102C OHP RX_NSA_1 ALARM_SO (W1C) OHP RX_NSA_0 MASK_SO (R/W) RX_JO_NEW_A RX_JO_MISMATCH M 4 4 0x1028 0x1078 OHP RX_NSA_1 MASK_SO (R/W) RX_JO NEW_M 4 0x1074 OHP RX_NSA_0 STATE SO (RO) RX_JO_MISMATCH 4 Ox10EC OHP RX_NSA_0 PERSIST_SO (RO) RX_JO MISMATCH P 4 Ox10BC 4 0x1800 Ox 181 F 4 0x1880 Ox 189F OHP_RX_JOEXPO_SO OHP RX JOEXP31 SO (R/W) OHP_RX_JOSUSO_SO OHP RX JOSUS31 SO (RO) RX_JO_EXP_0 RX JO-EXP 31 [32] RX_JO_SUS_0 RX JO-SUS 31 [32] r 1st Addr (hex) 1318 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 30 with Strong/Weak FEC and Digital Wrapper Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) 30.1.1 .6 Section Growth (ZO) No receive function has been defined for the section growth byte present in the remaining STS-1 locations of the STS-48 or STS-192 JO byte. In the receive direction, these bytes are transferred to the system interface or TOAC drop without modification . if NOT (rx_hw insert ais) ZO = Received-Line-Data ; else ZO = OxFF; end 30.1.1 .7 Section BIP-8 (B1) The section BIP-8 131 byte is located in the first STS-1 of the STS-48 or STS-192 only. The computed 131 is inserted on the first STS-1 131 byte location . The other STS-1 131 bytes are transferred to the system interface or TOAC drop without modification . Optionally, 131 can be corrupted by enabling the 131 corrupt enable bit. 131 insertion is controlled by 131 compute block . The overhead processor bypasses the received 131 . 30.1.1 .8 Local Orderwire (E1) The local orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only and provides a 64 kHz channel for voice communications between regenerators, hubs, and remote terminals . These bytes are transferred to the system interface or TOAC drop without modification . if NOT (rx_hw insert ais) E1 = Received-Line-Data ; else E1 = OxFF; end Agere Systems Inc. 143 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 30 Operational Description July 2002 Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) 30.1 .1 .9 Section User Channel (F1) The section user channel byte is located in the first STS-1 of the STS-48 or STS-192 only and provides a 64 kHz channel for use by the network provider. The byte is extracted from each frame . A new value is only validated and stored in the F1 byte after it has been received for the programmed N consecutive times. Detection of a new validated byte is indicated by the F1 new byte alarm bit. The alarm is only generated when the value of the new validated byte is different from the value of the last validated byte. The other STS-1 F1 bytes are transferred to the system interface or TOAC drop without modification . if NOT (rx_hw insert ais) F1 = Received-Line-Data ; else F1 = OxFF ; end Table 117. Section User Channel (F1) Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) New Validated F1 Alarm New Validated F1 Alarm Mask New Validated F1 Value Validated F1 N-Time Detect OH P_RX_NSA_1-ALARM_SO (W1C) OHP RX NSA 1 MASK SO (R/W) OHP_RX_F1S1BYTE_SO (RO) OHP RX F1S1DET SO (R/W) RX_F1_NEW_A RX F1 NEW M RX_F1_BYTE RX F1 NDET 4 4 4 4 0x1028 0x1074 0x1334 0x1328 30.1 .1 .10 Section Data Communications Channel (D1, D2, and 103) The section data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only and are used as one 192 kHz message-based channel for operations, administration, and maintenance (OA&M) communication . These bytes are transferred to the system interface or TOAC drop without modification . if NOT (rx_hw insert ais) D1 To D3 = Received-Line-Data ; else D1 To_D3 = OxFF ; end 30.1 .1 .11 Line BIP-8 (B2) The line 131 P-8 B2 byte is provided in all the STS-1s of the STS-48 or STS-192 . The computed B2 is inserted in these locations . Optionally, B2 can be corrupted by enabling the B2 corrupt enable bit. if (RX_LINE_AIS INS) or (rx_hw insert_ais) B2 = OxFF; else B2 = Computed B2; end 144 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 30 with Strong/Weak FEC and Digital Wrapper Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) 30.1.1 .12 STS Payload Pointer (H1, H2, and H3) The STS pointers are passed through unchanged . If PRBS payload monitoring is enabled, these pointer values are set to 5221. These bytes are transferred to the system interface or TOAC drop without modification . if (RX_LINE_AIS_INS) or (rx_hw insert ais) H1 To_H3 = OxFF; else H1_To H3 = Received-Line-Data ; end 30.1.1 .13 Receive APS Channel (K1 and K2) The APS channels' bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are used for automatic protection switching (APS) signaling to coordinate line-level protection switching . In addition, the K2 byte is also used to carry line AIS (AIS-L) and line RDI (RDI-L) signals . The other STS-1 K1/K2 bytes are transferred to the system interface or TOAC drop without modification . A new value in either byte is only validated after it has been received N times consecutively, where N is provisionable to 3 or 5 using the K1 K2 validate select control bit. When a K1 or K2 byte is validated, the value is stored in the K byte status register and the K1 K2 new byte alarm bit is set . These two alarms are only generated when the value of the new validated K1 or K2 byte is different from the value of the last validated byte . Validation of the K1 and K2 bytes, and the generation of the alarms, is not affected by the line AIS status . The validated K1 and K2 bytes are further processed for the following defects : Protection switching byte. This defect occurs when either an inconsistent APS byte or an invalid code is detected . An inconsistent APS byte occurs when no N consecutive K1 bytes of the last twelve successive frames are identical, starting with the last frame containing a previously consistent byte. An invalid code occurs when the incoming K1 byte contains an unused code or a code irrelevant for the specific switching operation in three consecutive frames. An invalid code also occurs when the incoming K1 byte contains an invalid channel number in three consecutive frames. Because invalid code detection requires information not readily available to hardware, it must be detected by software polling of the validated K1 byte value. An inconsistent APS byte defect is detected by hardware and will cause an alarm status bit to be set in the corresponding LTE receive channel nonservice-affecting interrupt alarm register. It is cleared when a K1 byte is received and validated . An inconsistent APS byte defect is neither detected nor terminated during an AIS-L defect. Processing of the inconsistent APS byte defect is also inhibited when the validated K1 byte has a value of OxFF and bits 2-0 of the validated K2 byte have a value of 111 (line AIS). This additional feature prevents a change in the inconsistent APS defect state just before line AIS is declared . Channel mismatch . This defect occurs when the channel numbers in the transmitted K1 byte (bits 3-0) and the validated received K2 byte (bits 7-4) are not identical . Detection of a channel mismatch defect causes a latched alarm status bit to be set in the corresponding LTE receive channel nonservice-affecting interrupt alarm register. A channel mismatch defect is neither detected nor terminated during an AIS-L defect. Processing of the channel mismatch defect is also inhibited when the validated K2 byte has a value of 1111x111 binary. This additional feature prevents a change in the channel mismatch defect state just before line AIS is declared. 1. The pointer is set by the incoming signal . Only when PRBS data is injected into the SONET frame is the pointer set, by the device, to 522. Agere Systems Inc. 145 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 30 Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) In addition, the currently received K2 byte is processed for the following defects : . Line AIS (AIS-L) . Declared when bits 2-0 of K2 contain 111 for five consecutive frames . Cleared when any other pattern is received for five consecutive frames. Detection of a line AIS defect is indicated by an alarm status bit, a persistency bit, and a 1 s PM bit being set in the registers for the affected channel. . Line RDI (RD I-L). Declared when bits 2-0 of K2 contain 110 (binary) for five consecutive frames . Cleared when any other pattern is received for five consecutive frames. Detection of a line RDI defect is indicated by a latched alarm status bit and a 1 s PM bit being set in the registers for the affected channel . if (RX_LINE_AIS_INS) or (rx_hw insert_ais) K1 To K2 = OxFF; else K1_To K2 = Received-Line-Data ; end Table 118 . APS Channel (K1 and K2) Register Summary (Receive) Function Register Name (First Occurrence) Register Bits Qty. K1 K2 Validation Length Select (3 or 5) Validated K1 K2 Storage New Validated K1 K2 Alarm Inconsistent APS Alarm Channel Mismatch Alarm New Validated K1 K2 Alarm Mask Inconsistent APS Alarm Mask Channel Mismatch Alarm Mask RDI-L Alarm RDI-L Alarm Mask Last Second RDI-L PM Inconsistent APS State Channel Mismatch State Inconsistent APS Persistency Channel Mismatch Persistency RDI-L State RDI-L Persistency OHP RX_PROV_SO(R/W) RX_K_VAL LIMIT_SEL 4 0x1310 OHP RX_K1 K2BYTE SO (R0) 4 0x1330 4 0x1028 OHP RX_NSA_0_ALARM SO (W1C) RX K1_BYTE RX-K2_BYTE RX_K1_NEW_A RX_K2_N EW_A RX_INCONSISTENT_APS_A 4 Ox 102C OHP RX_NSA_0_ALARM SO (W1C) RX_K1K2CH MISMATCH A 4 Ox 102C OHP RX_NSA_1 MASK_SO (W1C) 4 0x1074 OHP RX_NSA 0_MASK_SO (R/W) RX_K1_NEW_M RX_K2_NEW_M RX_INCONSISTENT_APS_M 4 0x1078 OHP RX_NSA_0 MASK_SO (R/W) RX_K1K2CH MISMATCH M 4 0x1078 OHP_RX_NSA 0_ALARM_SO (W1C) OHP RX NSA 0 MASK SO (R/W) OHP_RX_PM_SO (RO) OHP RX NSA 0 STATE SO (RO) OHP RX_NSA_0 STATE SO (RO) RX_LINE_RDI_A RX LINE RDI M RX_LINE_RDI_PM RX INCONSISTENT APS RX_K1K2CH MISMATCH 4 4 4 4 4 Ox102C 0x1078 Ox132C Ox10EC Ox 10EC OHP-RX_NSA_0 PERSIST_SO (RO) RX_INCONSISTENT_APS P 4 Ox10EC OHP-RX_NSA_0 PERSIST_SO (RO) RX_K1K2CH MISMATCH-P 4 Ox10BC OHP_RX_NSA_0_STATE_SO (RO) OHP RX NSA 0 PERSIST SO (RO) RX_LINE_RDI RX LINE RDI P 4 4 Ox10EC Ox10BC 146 OHP RX_NSA_1 ALARM SO (W1C) 1st Addr (hex) Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 30 with Strong/Weak FEC and Digital Wrapper Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) 30.1.1 .14 Line Data Communication Channel (104-1012) The line data communication channel bytes are located in the first STS-1 of the STS-48 or STS-192 only and are used as one 576 kHz message-based channel for operations, administration, and maintenance communication (OA & M). These bytes are transferred to the system interface or TOAC drop without modification . if (RX LINE_AIS INS) or (rx_hw insert ais) D4 To_D12 = OxFF; else D4_To D12 = Received Line_Data; end 30.1.1 .15 Synchronization Status (S1) The synchronization status byte is located in the first STS-1 of the STS-48 or STS-192 only and is used to convey the synchronization status of a network element. The byte is extracted from each frame. A new value is only validated and stored in the S1 byte after it has been received for the programmed N consecutive times. Detection of a new validated byte is indicated by the S1 new byte alarm bit . The alarm is only generated when the value of the new validated byte is different from the value of the last validated byte. The other STS-1 S1 bytes are transferred to the system interface or TOAC drop without modification . if (RX_LINE_AIS INS) or (rx_hw insert ais) S1 = OXFF; else S1 = Received-Line-Data ; end Table 119. Receive Synchronization Status (S1) Register Summary Function New Validated S1 Alarm New Validated S1 Alarm Mask New Validated S1 Value Validated S1 N-Time Detect Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP RX_NSA_1_ALARM_SO (W1C) OHP RX_NSA_1 MASK_SO (R/W) RX_S1_NEW_A RX_S1 NEW_M 4 4 0x1028 0x1074 0HP_RX_F1S1BYTE_SO (RO) OHP RX F1S1DET SO (R/W) RX_S1_BYTE RX S1 NDET 4 4 0x1334 0x1328 147 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 30 Operational Description July 2002 Receive Transport Overhead Processing (continued) 30.1 Functional Description of the Receive Transport Overhead Processing (continued) 30.1 .1 .16 Line Remote Error Indication (M1) The line remote error indication (REI-L) byte is located in the third STS-1 of the STS-48 or STS-192 only (in order of appearance in the STS-192 signal) and is used to convey to the far end the number of errors detected using the line BIP-8 bytes (truncated at 255). The byte is extracted from each frame and the value added to an internal 21-bit counter. The value in the counter is transferred to the REI-L registers on the positive edge of the performance monitoring (PM) clock input, at which point the counter is cleared . The counter will stop at the maximum value and will not roll over. The other STS-1 M1 bytes are transferred to the system interface or TOAC drop without modification . if (RX_LINE_AIS INS) or (rx_hw insert_ais) M1 = OXFF; else M1 = Received-Line-Data ; end Table 120 . Line REI (M1) Register Summary Function Last Second REI-L Count 30.1 .1 .17 Register Name (First Occurrence) OHP_RX_REI_L_PM_SO OHP RX REI U PM SO (RO) Register Bits Qty. 1st Addr (hex) RX_REIL_U RX REIL L 4 4 0x1338 0x1339 Express Orderwire (E2) The express orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only and provides a 64 kHz channel for voice communications between line entities . The other STS-1 E2 bytes are transferred to the system interface or TOAC drop without modification . if (RX_LINE_AIS INS) or (rx_hw insert_ais) E2 = OxFF; else E2 = Received-Line-Data ; end 31 31 .1 Transmit Transport Overhead (TOH) Processor Functional Description of TOH Processor This block inserts the transport overhead and incorporates four identical STS-48 overhead processing blocks . Each block accepts the data for one STS-48 channel from the transmit payload add interface and inserts the transport section and line overhead . The inserted overhead is either sourced internally or provided externally on serial inputs . If sourced internally, the overhead may be from registers in the microprocessor interface, or derived . The received overhead bytes can also be allowed to pass through unchanged . In STS-48 mode, each channel carries complete transport overhead . In STS-192 mode, only the first STS-48 channel carries complete transport overhead, while the other channels only cant' framing (A1, A2), Z0, and line BIP-8 . In addition, the line overhead bytes can all be overwritten with all ones (along with all of the payload SPE bytes) by enabling line AIS insertion . If software is disabled, the transmit overhead processing is disabled . Software can disable either the line overhead bytes processing, section overhead bytes processing, or both. All processing of overhead bytes is inhibited under AIS conditions. An AIS frame can be generated either by hardware or software . 148 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 31 with Strong/Weak FEC and Digital Wrapper Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) Table 121 . Hardware AIS Generation Summary (Transmit) AIS Generation Alarms AIS Generation Disables TX_LOC_A TX_LOS_A TX SEF A TX_LOF_A TX AIS L A TX SEF AIS DIS TX_LOF_AIS_DIS TX LINE AIS DIS Description Loss of clock . Loss of signal . Detected severely errored frame . Detected loss of frame. Detected line AIS frame. In addition to the individual storage or external availability of the overhead bytes described, the transport overhead bytes for each STS-48 (individual or part of STS-192) can be sourced serially using the TOAC data pins. This TOAC interface can operate in two modes' . In full TOAC drop mode, the full set of transport overhead bytes for each STS-48 channel (1296 bytes) can be sourced on the TOAC pins. In partial TOAC drop mode, only the transport overhead bytes of the first STS-1 of each STS-48 channel (27 bytes) can be sourced on the TOAC pins. Insertion must be globally enabled through software using the TOH data insert control bit, and then enabled on a perbyte basis by strobing the TOAC enable pin high during the LSB of the byte to insert (the state of the TOAC enable is ignored during the other bits) . The bytes are received, MSN (most significant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the TOAC clock (20 .736 MHz (full)/1 .728 MHz (partial)). The location of the MSN (most significant nibble) bit of the first A1 byte is identified by the TOAC sync output going high. For B2, the value received is actually used as an XOR corruption mask for the internally calculated values . In STS-48 mode, the individual TOAC data pins, along with the TOAC enable pin, capture the transport overhead for that STS-48 channel. In STS-192 mode, the four pairs of TOAC data pins, along with their respective TOAC enable pins, capture the entire STS-192 overhead (5184 bytes), where the TOAC data #1 pins capture STS channels 1 through 48, and the TOAC data #2, TOAC data #3, and TOAC data #4 pins capture STS channels 49 through 96, 97 through 144, and 145 through 192, respectively. The TOAC insert functionality is described in detail later in this section . Note : In SONFEC, four overhead processors capable of processing an entire STS-48 are implemented . In 2.5 Gbits/s mode, each functions independently. However, in 10 Gbits/s mode, only one slice (that process the STS-48 #1 in an STS-192) functions as a master slice and all others functions are very minimal . In OHP, the master slice is slice 3. Therefore, though all the rest of the 10 Gbits/s alarms are reported in slice 0, in overhead processor, the alarms in 10 Gbits/s are reported at slice 3 registers . Following the same reason, regardless of 10 Gbits/s or 2.5 Gbits/s mode of operation, all the overhead processing slices are to be programmed. 1 . For more information on the two TOAC modes, see Section 2.4 on page 10 . Agere Systems Inc. 149 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 31 Transmit Transport Overhead (TOH) Processor (continued) 31 .1 31 .1.1 Functional Description of TOH Processor (continued) Global Overhead Byte Insertion If TOAC insertion is enabled, the first 2 bits (MSB and MSB - 1 positions of the data) of the TOAC data enable input control the overhead byte insertion . Table 122 . TOAC Byte Insertion Control TOAC Enable Data TX_TOAC_ENB (Pin) Sampled at [MSB], [MSB - 1] Positions Only Description Value 11 00 01 10 Insert data from the serial TOAC input . Default data. Bypass data. I Software controlled data. In the following sections, the term TOAC_Controlled Data is used to indicate the data inserted in the overhead byte position, depending on the TOAC enable pin. If AIS is detected, then all the line overhead bytes are set to OxFF. Insertion of AIS can be either due to hardware or software . In the following sections, the term tx hw insert_ais is used to indicate a hardware-controlled AIS condition . The register bit transmit SDH mode controls the default values of overhead bytes. If set to 1, the default value is set to either OxFF (SDH mode) or 0x00 (SONET mode). Table 123 . Transmit Overhead Processor General Register Summary Function OHP (SOH) Disable Control OHP (LOH) Disable Control Global TOAC Byte Insert Control SONET/SDH Mode OHP Mode Control AIS-L Insert Control 31 .1.1 .1 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC TX BYPASS S0 (R/W) SONFEC TX BYPASS S0 (R/W) OHP TX PROV S0 (R/W) OHP TX SOH PROC DIS OHP TX LOH PROC DIS TX_TOAC ENB 4 4 4 0x1119 0x1119 0x1370 OHP TX PROV S0 (R/W) SONFEC_TX_MODE (R/W) OHP TX MAINT SO (R/W) TX SDH MODE TX_OHP_MODE TX LINE AIS INS 4 1 4 0x1370 0x1111 0x1374 Default All Undefined Bytes in Section Overhead For all the bytes that are not specified in the following sections and default bytes in other STS-1 (s) in an STS-48 or STS-192, processing is done as follows : if (TX TOAC ENB) Section_UndefinedByte = TOAC Controlled Data; else if (OHP_TX_SOH_PROC_DIS) and NOT (tx_hw_insert_ais) Section Undefined_Byte = Received System Data ; else Section Undefined_Byte = Default SONET_SDH ; end 150 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 31 with Strong/Weak FEC and Digital Wrapper Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) 31 .1.1 .2 Default All Undefined Bytes in Line Overhead For all the bytes that are not specified in the following sections and default bytes in other STS-1 (s) in an STS-48 or STS-192, processing is done as follows : if (TX_LINE_AIS_INS) or (tx_hw insert_ais) Line-Undefined Byte = OxFF; else if (TX TOAC ENB) Line-Undefined Byte = TOAC Controlled-Data ; else if (OHP TX_LOH_PROC DIS) Line-Undefined Byte = Received System_Data ; else Line Undefined Byte = Default SONET_SDH ; end 31 .1.1 .3 Framing Byte (A1) The framing byte A1 is overwritten if not inhibited by software . If normal framing is selected, the A1 bytes are set to OxF6, while the A2 bytes are set to 0x28. If enhanced framing is selected using the framing mode control bit, the A1 bytes and A2 bytes contain normal framing (OxF6 and 0x28) in odd STS-1 time slots and the inverse value (0x09 and OxD7) in even STS-1 time slots. if (TX TOAC_ENB) A1 = TOAC_Controlled_Data; else if (TX_A1A2 INH) and NOT (tx_hw_insert_ais) A1 = Received System Data; else if (TX ENH_FRMG_INS) A1 = Enhanced Framing A1 ; else A1 = Normal Framing A1 ; end Table 124 . A1 Register Summary (Transmit) Function A1 Insertion Enable Enhanced Framing Agere Systems Inc. Register Name (First Occurrence) Register Bits Qty. 1 st Addr (hex) OHP_TX_PROV_SO (R/W) TX_A1A2_INH TX ENH FRMG INS 4 4 0x1370 0x1370 151 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 31 Operational Description July 2002 Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) 31 .1.1 .4 Framing Byte (A2) The framing byte A2 is overwritten if not inhibited by software . If normal framing is selected, the A1 bytes are set to OxF6, while the A2 bytes are set to 0x28. If enhanced framing is selected using the framing mode control bit, the A1 bytes and A2 bytes contain normal framing (OxF6 and 0x28) in odd STS-1 time slots and the inverse value (0x09 and OxD7) in even STS-1 time slots. Alternatively, errors can be inserted in A2 bytes by setting the corresponding TX A2_ERR_INS bit for each slice. The errors are inserted by inverting every fourth A2 byte out of the 192 A2 bytes starting with the first byte. Also, during A2 error insertion, normal framing is always used even if TX ENH FRMG INS is set to 1 . if (TX TOAC_ENB) A2 = TOAC_Controlled_Data; else if (TX A2 ERR INS) A2 = Errored A2 ; else if (TX_A1A2 INH) and NOT (tx_hw_insert_ais) A2 = Received System Data; else if (TX ENH_FRMG_INS) A2 = Enhanced Framing A2 ; else A2 = Normal Framing A2; end Table 125 . A2 Register Summary (Transmit) Function A2 Insertion Enable Enhanced Framing A2 Error Control 31 .1.1 .5 Register Name (First Occurrence) OHP_TX_PROV_SO (R/W) OHP TX PROV SO (R/W) OHP TX MAINT SO (R/W) Register Bits TX_A1A2_INH TX ENH FRMG INS TX A2 ERR INS Qty. 4 4 4 1st Addr (hex) 0x1370 0x1370 0x1378 Section Trace (JO) The section trace byte is present in the first STS-1 of the STS-48 or STS-192 only. The TOH processor supports insertion of either SONET 64-byte (ASCII, <CR><LF> terminated) or SDH 16-byte (E.164) section trace messages. The message is stored in internal memory and should be repeated four times if a 16-byte SDH message is to be sent. The message is provisioned by software using the section trace access registers . After the message is provisioned, insertion of the message must be enabled through the JO message insert control bit . If insertion is not enabled, the JO byte is instead sent as 0x01 for STS-48/STS-192 mode. if (TX TOAC_ENB) JO = TOAC_Controlled_Data ; else if (TX JO INS) JO = MPU_Programmed J0 ; else if (OHP_TX SOH_PROC DIS) and NOT (tx_hw insert_ais) JO = Received System Data; else JO = 0x01 ; end 152 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 31 with Strong/Weak FEC and Digital Wrapper Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) Table 126 . JO Register Summary (Transmit) Function Message Insert Control JO Provisioned Message Buffer 31 .1.1 .6 Register Name (First Occurrence) Register Bits Qty. 1stAddr (hex) OHP_TX_MAINT_SO (R/W) OHP_TX_JOBYTEO_SO OHP TX JOBYTE31 SO (R/W) TX-JO-INS TX_JO_EXP_0 TX JO_EXP 31 4 4 0x1378 0x1900 Ox191F Section Growth (ZO) The section growth bytes are present in the STS-1 locations, excluding the first STS-1 of the STS-48 or STS-192 . They are set to the fixed pattern OxCC in STS-192 mode, or to an increasing binary count (2 to 48, corresponding to order of appearance) in STS-48 mode. if (TX TOAC_ENB) ZO = TOAC_Controlled_Data; else if (OHP_TX SOH_PROC_DIS and NOT (tx_hw_insert ais) ZO = Received System Data; else if (TX OHP_MODE equals 2G5) ZO = 0x02 to 0x48; else ZO = OXCC; end 31 .1.1 .7 Section BIP-8 (B1) The section BI P-8 B1 byte is located only in the first STS-1 of the STS-48 or STS-192 . The computed B1 is inserted on the first STS-1 B1 byte location . Optionally, B1 can be corrupted by enabling the B1 corrupt enable bit . if (TX TOAC_ENB) B1 = TOAC_Controlled_Data; else if (OHP_TX SOH_PROC_DIS) and NOT (tx_hw insert_ais) B1 = Received System Data; else B1 = Default SONET_SDH ; end Agere Systems Inc. 153 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 31 Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) 31 .1.1 .8 Local Orderwire (E1) The local orderwire byte is located only in the first STS-1 of the STS-48 or STS-192, and provides a 64 kHz channel for voice communications between regenerators, hubs, and remote terminals . if (TX TOAC_ENB) E1 = TOAC_Controlled_Data; else if (OHP_TX SOH_PROC_DIS) and NOT (tx_hw insert_ais) E1 = Received System Data; else E1 = Default SONET_SDH ; end 31 .1.1 .9 Section User Channel (F1) The section user channel byte is located only in the first STS-1 of the STS-48 or STS-192 and provides a 64 kHz channel for use by the network provider. The byte is inserted in each frame using either a value provisioned in the F1 byte control register or from a value received on the TOAC data input . if (TX TOAC_ENB) F1 = TOAC_ControlledData ; else if (TX F1 INS) F1 = MPU_Programmed F1 ; else if (OHP_TX SOH_PROC_DIS) and NOT (tx_hw insert_ais) F1 = Received System Data; else F1 = Default SONET_SDH ; end Table 127 . Transmit F1 Register Summary Function Byte Insert Control Provisioned F1 Byte 154 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP TX MAINT_SO (R/W) OHP TX F1S1BYTE SO (R/W) TX_F1_INS TX F1 BYTE 4 4 0x1378 0x1388 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 31 with Strong/Weak FEC and Digital Wrapper Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) 31 .1.1 .10 Section Data Communications Channel (D1, D2, and 103) The section data communications channel bytes are located only in the first STS-1 of the STS-48 or STS-192, and are used as one 192 kHz message-based channel for operations, administration, and maintenance (OA & M) communication. if (TX TOAC_ENB) D1-To-D3 = TOAC_ControlledData ; else if (OHP_TX_SOH_PROC_DIS) and NOT (tx_hw insert_ais) D1 To D3 = Received System-Data ; else D1 To_D3 = Default SONET SDH; end 31 .1.1 .11 Line BIP-8 (B2) The line BI P-8 B2 byte is provided in all the STS-1s of the STS-48 or STS-192 . The computed B2 is inserted in these locations . If B2 calculation and TOAC insertion are enabled, the computed B2 value is XORed with the received TOAC B2 byte value (if TOAC data enable is asserted on the MSB of B2 byte) . Optionally, B2 can be corrupted by enabling the B2 corrupt enable bit . if (TX_LINE_AIS INS) or (tx_hw_insert_ais) B2 = OXFF; else if (TOAC Mode) if (TOAC Enable Mode is 11) B2 = Computed B2 xor TOAC Data; else B2 = bypass, default, or software controlled depending on TOAC enable mode 01, 00, or 10; end if else if (OHP TX B2_BYPASS) B2 = Received System Data; else B2 = Computed B2; end Agere Systems Inc. 155 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 31 Operational Description July 2002 Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) 31 .1.1 .12 STS Payload Pointer (H1/H2/H3) The STS payload pointer bytes are normally set to the values received at the system interface. These values are overwritten under the following conditions (in order of precedence from highest to lowest) : If the H1, H2, or H3 pointers are changed, then no other overhead processing is done. TOAC or software controls are ignored . . Software/hardware AIS insertion : if enabled, overwrites the pointer bytes for the channel with OxFFFFFF. . Unequipped signal insertion : if enabled, overwrites the pointer bytes for the channel with 0x600000 . . PRBS payload insertion : if enabled, overwrites the pointer bytes for the channel with Ox620A00. . Invalid pointer insertion : if enabled, overwrites the pointer bytes for the channel with 0x633300. . NDF pointer insertion : if enabled, overwrites the pointer bytes for the channel with Ox920A00. . TOAC data insertion : controlled by TOAC. if (TX_LINE_AIS INS) or (tx_hw_insert_ais) H1 = OxFF; H2 = OxFF; H3 = OxFF; else if (TX LINE UNEQ INS) H1 = 0x60; H2 = 0x00; H3 = 0x00; else if (TX PRBS ENB) H1 = 0x62 ; H2 = MA; H3 = 0x00; else if (TX INV PTR_INS) H1 = 0x63; H2 = 0x33; H3 = 0x00; else if (TX NDF INS) H1 = 0x92 ; H2 = MA; H3 = 0x00; else if (TX TOAC_ENB) if (TX_LINE_AIS_INS OR tx_hw_insert ais) H1 = Non TOAC Functionality H2 = Non TOAC Functionality H3 = Non TOAC Functionality else H 1 = TOAC_Controlled_Data; H2 = TOAC Controlled Data; H3 = TOAC Controlled Data; else H1 = Received System Data; H2 = ReceivedSystem Data; H3 = Received System Data; end 156 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 31 with Strong/Weak FEC and Digital Wrapper Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) Table 128 . Transmit STS Payload Pointer Register Summary Function NDF Insert Control Invalid Pointer Insert Control UNEQ-L Insert Control 31 .1.1 .13 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP_TX_MAINT_S0 (R/W) TX_NDF_INS TX_INV_PTR_INS TX LINE UNEQ INS 4 4 4 0x1378 0x1378 0x1378 APS Channel (K1 and K2) The APS channel bytes are located only in the first STS-1 of the STS-48 or STS-192 and are used for automatic protection switching (APS) signaling to coordinate line level protection switching . In addition, the K2 byte is also used to carry line AIS and line RDI signals . Both bytes are inserted during each frame, normally using values stored in the K-byte register. In addition, the value of bits 2-0 in K2 can optionally be automatically overwritten by 110 (RDI-L) when AIS-L, LOS, SEF, or LOF (SEF and LOF only if AIS insertion is enabled) are detected for the receive STS-48 or STS-192 . This insertion is controlled by the RDI-L select bit in the LTE transmit channel maintenance register. When RDI-L is triggered, it will be inserted for a minimum of 20 consecutive frames, if not software disabled. if (TX_LINE_AIS INS) or (tx_hw_insert_ais) K1 = OXFF; K2 = OxFF; else if (TX TOAC_ENB) K1 = TOAC_Controlled_Data; if (TX_RDI_L SEL) and (tx_hw_insert rdi) K2 = K2[7:3] & "110"; else if (TX RDI L SEL) K2 = TOAC Controlled_Data ; end else if (APS BYPASS) K1 = By Pass Data; K2 = By Pass Data; else K1 = MPU_Programmed_K1 ; if (TX_RDI_L SEL) and (tx_hw_insert rdi) K2 = K2[7:3] & "110"; else if (TX RDI L SEL) K2 = TOAC Controlled_Data ; end end Agere Systems Inc. 157 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 31 Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) Table 129 . Transmit APS Channel (K1 K2) Register Summary Function K1 K2 Software Insert Control K1 K2 Software Insert Value RDI-L Duration Control RDI-L Insert Control 31 .1.1 .14 Register Name (First Occurrence) OHP_TX_MAINT S0 (R/W) OHP_TX_K1 K2BYTE S0 (R/W) OHP_TX_AIS_RDI_SO (R/W) OHP TX MAINT S0 (R/W) Register Bits Qty. 1stAddr (hex) TX_K1 K2-BYPASS 4 TX_K1_BYTE TX_K2_BYTE TX-20FRM-RDI-DIS TX RDI L SEL 4 Ox138C 4 4 0x1374 0x1378 0x1378 Line Data Communication Channel (104-1012) The line data communications channel bytes are located only in the first STS-1 of the STS-48 or STS-192, and are used as one 576 kHz message-based channel for operations, administration, and maintenance communication . if (TX_LINE_AIS INS) or (tx_hw_insert_ais) D4_To D12 = OxFF; else if (TX TOAC_ENB) D4_To_D12 = TOAC_Controlled_Data; else if (OHP TX_LOH_PROC_DIS) 104_To D12 = Received System Data; else D4_To_D12 = Default SONET SDH ; end 31 .1.1 .15 Synchronization Status (S1) The synchronization status byte is located only in the first STS-1 of the STS-48 or STS-192 and is used to convey the synchronization status of a network element. The byte is inserted in each frame using either a value provisioned in the S1 byte control register or from a value received on the TOAC data input . if (TX_LINE_AIS INS) or (tx_hw_insert_ais) S1 = OXFF; else if (TX TOAC_ENB) S1 = TOAC_Controlled_Data; else if (TX S1 INS) S1 = MPU_Programmed S1 ; else if (OHP TX LOH_PROC_DIS) S1 = Received System Data; else S1 = Default SONET_SDH ; end Table 130 . Transmit Synchronization Status (S1) Register Summary Function Byte Insert Control Provisioned S1 Byte 158 Register Name (First Occurrence) Register Bits Qty. OHP TX MAINT SO (R/W) OHP TX F1S1BYTE SO (R/W) TX S1 INS TX S1 BYTE 4 4 1st Addr (hex) 0x1378 0x1388 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 31 with Strong/Weak FEC and Digital Wrapper Transmit Transport Overhead (TOH) Processor (continued) 31 .1 Functional Description of TOH Processor (continued) 31 .1.1 .16 STS-192 Line Remote Error Indication (M1) The line remote error indication (REI-L) byte is located only in the third STS-1 of the STS-48 or STS-192 (in order of appearance in the STS-192 signal) and is used to convey to the far end the number of errors detected in the receive direction using the line 131 P-8 bytes. The byte is inserted each frame with a binary value indicating the number of line BI P-8 errors (truncated at 255) detected in the previous receive frame for the entire STS-48 or STS-192 . The value of the byte can be fully corrupted (by setting all bits) on a per STS-48 channel basis using the M1 corrupt enable control bit . The duration of the corruption is defined in frames per second, up to a maximum of 8000 frames (1 second), and corruption starts with the next frame after the rising edge of performance monitoring clock. The M1 corrupt frame count register specifies this duration. if (TX_LINE_AIS INS) or (tx_hw_insert_ais) M1 = OxFF; else if (TX TOAC_ENB) M1 = TOAC_Controlled_Data ; else if (TX M1CORRUPT_EN) M1 = OxFF; else if (TX M1 INS) M1 = Monitored-B2-Error-Count ; else if (OHP TX_LOH_PROC_DIS) M1 = Received-System-Data; else M 1 = 0x00; end Table 131 . Transmit M1 Register Summary Function Byte Insert Control M1 Corrupt Enable M1 Corrupt Duration Control 31 .1.1 .17 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP TX MAINT SO (R/W) OHP_TX_PROV_SO (R/W) OHP_TX_M1CORRUPT_S0 (R/W) TX M1 INS TX_M1CORRUPT_ENB TX_M1CORRUPT FRM CNT 4 4 4 0x1378 0x1370 0x1384 Express Orderwire (E2) The express orderwire byte is located only in the first STS-1 of the STS-48 or STS-192 and provides a 64 kHz channel for voice communications between line entities . if (TX_LINE_AIS INS) or (tx_hw_insert_ais) E2 = OXFF; else if (TX TOAC_ENB) E2 = TOAC_Controlled_Data; else if (OHP TX LOH_PROC_DIS) E2 = Received System Data; else E2 = Default SONET_SDH ; end Agere Systems Inc. 159 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 32 Operational Description July 2002 Receive TOAC Drop/Transmit TOAC Insert Four TOAC insert/drop functions are provided in quad STS-48/STM-16 mode and one in STS-1 92/STM-64 mode. 32.1 Receive TOAC Drop In the receive direction (TOAC drop), each transport overhead byte is extracted in each frame, buffered, and output MSN (most significant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the TOAC clock (20 .736 MHz (full)/1 .728 MHz (partial)) . During AIS insertion, due to LOS, LOF, or SEF (provisionable), OxFF is constantly output. The location of the MSN of the first A1 byte is identified by the TOAC sync output going high . In STS-48 mode, each of the four TOAC data pins per STS-48 frame transmits the transport overhead for an STS-48 channel. In STS-192 mode, four sets of four TOAC data pins transmit the entire STS-192 overhead (5184 bytes), where the fourth set of four TOAC data pins transmit STS channels 1 through 48, the third set of four TOAC data pins transmit STS channels 49 through 96, the second set of four TOAC data pins transmit channels 97 through 144, and the first set of four TOAC data pins transmit channels 145 through 192 . Internally, a memory is used for each channel in order to buffer the data and transfer it between the internal processing rate and the external data rate. This allows for the data to be transmitted in a nongapped manner. The operation of the memory is monitored using parity and any errors are reported using the TOAC data parity error alarm bit. This alarm bit is present in the corresponding LTE receive channel nonservice-affecting interrupt alarm register and is valid regardless of the mode (STS-48/STM-16 or STS-1 92/STM-48) of the device . 32.2 Transmit TOAC Insert In the transmit direction (TOAC insert), each transport overhead byte for each STS-48 (individual or part of an STS-192) can be sourced serially using the four TOAC data pins allocated per STS-48 channel . Insertion of these received bytes is controlled through a global TOAC insert enable bit in the transmit provisioning register. The insertion is then enabled on a per-byte basis by strobing the TOAC data enable pin high during the entire period of the byte to insert. The bytes are received MSN (most significant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the TOAC clock (20 .736 MHz (full)/1 .728 MHz (partial)). The location of the MSN (most significant nibble) bit of the first A1 byte is identified by the TOAC sync output going high . For B2, the value received is actually used as an XOR corruption mask for the internally calculated values . In STS-48 mode, the individual TOAC data pins, along with the TOAC enable pin, capture the transport overhead for that STS-48 channel . In STS-192 mode, the four sets of four TOAC data pins, along with their respective TOAC enable pins, capture the entire STS-192 overhead (5184 bytes), where the fourth set of four TOAC data pins capture STS channels 1 through 48, the third set of four TOAC data pins capture STS channels 49 through 96, the second set of four TOAC data pins capture channels 97 through 144, and the first set of four TOAC data pins capture channels 145 through 192. Internally, a memory is used for each channel to buffer the data and transfer it between the external data rate and the internal data rate. The operation of the memory is monitored using parity and any errors are reported using the TOAC data parity error alarm bit . This alarm bit is present in the LTE transmit interrupt alarm register and is valid regardless of the mode (STS-48 or STS-192) in which the device is operating . When enabled, the overhead serial link takes precedence over all other overhead sources, with the exception of bytes that are software enabled . 160 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 32 with Strong/Weak FEC and Digital Wrapper 32.3 Transmit Transport Overhead (TOH) Processor (continued) TOAC Modes Both the receive TOAC drop and transmit TOAC insert interfaces can operate in two modes: full TOAC insert/drop mode and partial insert/drop mode (see Section 32.3.1 and Section 32 .3.2 on page 161). 32.3.1 Full TOAC Insert/Drop Mode . TOAC clock output at 20.736 MHz . . TOAC sync output 8 kHz coincide with the MSN (most significant nibble) of the first A1 nibble . . TOAC data enable input (Tx only) active during the MSN (most significant nibble) of each byte to be inserted into the output stream . . TOAC data bus (transmit insert input/receive drop output) : -In STS-48 mode, four bits/stream at 20.736 Mbits/s that transition at the rising edge of the clock (10,368 bits per STS-48/STM-16 SON ET/SDH frame) . -In STS-192 mode, sixteen bits at 20.736 Mbits/s that transition at the rising edge of the clock ([10368 x 4] = 41472 bits per STS-1 92/STM-64 SONET/SDH frame) . The byte ordering of the individual STS-1 s or STS-1 components of an STS-Nc that comprise the STS-192 and the details of the STS-192 to STS-48 demultiplexing can be found in GR-253-CORE Section 5-1, Network Element Architectural Features (Multiplexing Procedure), page 5-1 . The TOAC channels output/accept the nibble data in STS-48/STM-16 byte ordering independent of the full drop/insert mode. Therefore, in STS-1 92/STM-64 mode, four TOAC channels are needed to drop/insert the entire transport overhead bytes. A byte is inserted into the transmit data stream through an external input that is sampled per clock cycle . If the signal is active (high) during the MSB/ MSN (most significant bit/nibble), the byte is inserted into the transmitted overhead stream . 32.3.2 Partial TOAC Insert/Drop Mode First STS-1/STM-0 (J0, E1, D1-D3, D4-D12, S1, E2, including the M1 byte accessible) : . TOAC clock output at 1 .728 MHz (in 10 Gbits/s mode, only RTOAC CLKO_4, RTOAC SYNCO_4, and RTOAC_DATAO 4 are used). . TOAC sync output at 8 kHz coincide with the MSN (most significant nibble) of the first A1 nibble . . TOAC data enable input (Tx only) active during the MSN (most significant nibble) of each byte to be inserted into the output stream . . TOAC data bus (transmit insert input/receive drop output) : -One bit/stream at 1 .728 Mbits/s that transitions at the rising edge of the clock (216 bits per STS-1 92/STM-64 or STS-48/STM-16 frame). Agere Systems Inc. 161 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 32 Receive TOAC Drop/Transmit TOAC Insert (continued) 32.3 TOAC Modes (continued) Table 132 summarizes the frame format in the STS-1 /STM-0 mode. Data is transmitted from left to right, then top to bottom with A1 bit 7 being the first bit to be transmitted/received. Table 132 . TOAC Insert/Drop Frame Format-STS-1/STM-0 Mode Row Column Numbers 1 2 3 4 5 6 7 8 9 Section/RS Line/MS I 1 2 A1 B1 D1 H1 B2 D4 D7 D10 S1 A2 E1 D2 H2 K1 D5 D8 D11 Mil I 3 I J0 F1 D3 H3 K2 D6 D9 D12 E2 1 . The Z2 byte is overwritten by the M1 value. Table 133 . Receive Overhead Serial Links Register Summary Function TOAC Byte Drop Control Register Name (First Occurrence) I OHP RX-PROV SO (R/W) Register Bits I RX-TOAC MODE I Qty. 1st Addr (hex) 4 I 0x13101 Table 134 . Transmit Overhead Serial Links Register Summary Function Global TOAC Byte Insert Control 33 33.1 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) OHP TX PROV SO (R/W) TX_TOAC ENB TX TOAC MODE 4 0x1370 Receive/Transmit Payload Processing Receive Payload Processing In the receive direction, optionally, the payload data of an STS-192c/STS-48c can be monitored with a PRBS analyzer. This PRBS monitor is provided per STS-48 for continuity checking . The pointer value of the receive STS-48c signal must be 5221 . This allows monitoring without the need for a pointer interpreter. Three different PRBS monitoring sequences are supported : PRBS15, PRBS20, and PRBS23 . Additionally, each of the PRBS data received can be programmed to be inverted before monitoring . Monitoring can be done in two modes. In full SPE monitoring, the complete payload as well as POH bytes contains PRBS data. In normal SPE monitoring, only the payload bytes contain the PRBS data; POH bytes and stuff bytes are ignored . 1. The pointer is set by the incoming signal . Only when PRBS data is injected into the SONET frame is the pointer set, by the device, to 522. 162 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 33 with Strong/Weak FEC and Digital Wrapper Receive/Transmit Payload Processing (continued) 33.1 Receive Payload Processing (continued) Table 135 . Receive PRBS Payload Type Register Bits Value Description RX_PRBS_TYPE 01 10 00,11 PRBS15 PRBS20 PRBS23 Table 136 . Receive PRBS Register Summary Function PRBS Out-of-Sync Alarm PRBS Out-of-Sync Alarm Mask PRBS Out-of-Sync State PRBS Out-of-Sync Persistency PRBS Data Inversion Enable PRBS Data Type PRBS Mode PRBS Data Monitoring Enable PRBS BER Count 33.2 I Register Name (First Occurrence) Register Bits Qty. 1st Add r (hex) OHP RX_NSA_0 ALARM_SO (W1C) OHP RX_NSA_0 MASK_SO (R/W) RX-PRBS_OOS_A RX_PRBS OOS M 4 4 Ox102C 0x1078 OHP_RX-NSA 0-STATE SO (RO) OHP RX_NSA_0 PERSIST SO (RO) RX_PRBS_OOS RX-PRBS OOS_P 4 4 Ox10EC Ox10BC OHP RX_PROV_SO (R/W) RX_PRBS INV 4 0x1310 OHP_RX_PROV_SO (R/W) OHP RX_PROV_SO (R/W) OHP RX_PROV_SO (R/W) RX_PRBS_TYPE RX_PRBS_MODE RX_PRBS_ENB 4 4 4 0x1310 0x1310 0x1310 OHP RX-PRBS BER SO (COR) I RX-PRBS BER CNTOI 4 I 0x1600 Transmit Payload Processing In the transmit direction, optionally, internally generated PRBS data can be inserted as the STS-192c/STS-48c payload . This PRBS generator is provided per STS-48 for continuity checking . Four STS-48 PRBS signals are inserted in an STS-192 signal for 10 Gbits/s mode. The PRBS generated signal is placed in the STS-192c/STS-48c payload with a fixed pointer value of 5221 . Three different PRBS generation sequences are supported : PRBS15, PRBS20, and PRBS23 . Additionally, each of the PRBS data transmitted can be programmed to be inverted before monitoring. Insertion can be done in two modes . In full SPE insertion, the complete payload as well as POH bytes contains PRBS data. In normal SPE insertion, only the payload bytes contain the PRBS data; POH bytes and the STS-48c/STS-192c stuff bytes are ignored . Table 137 . Transmit PRBS Payload Type Register Bits TX PRBS TYPE Value 01 10 00,11 I Description PRBS15 PRBS20 PRBS23 1. The pointer is set by the incoming signal . Only when PRBS data is injected into the SONET frame is the pointer set, by the device, to 522. Agere Systems Inc. 163 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 33 Receive/Transmit Payload Processing (continued) 33.2 Transmit Payload Processing (continued) Table 138 . Transmit PRBS Register Summary Function PRBS PRBS PRBS PRBS 34 34 .1 Data Inversion Enable Data Type Mode Data Insertion Enable Register Name (First Occurrence) Register Bits Qty. OHP TX PROV SO (R/W) TX PRBS INV TX_PRBS_TYPE TX_PRBS_MODE TX PRBS ENB 4 4 4 4 1st Addr (hex) 0x1370 0x1370 0x1370 0x1370 132 Computing Functional Description of 132 Computing The line BI P-8 is located in each STS-1 of the STS-48 or STS-192 and carries the even parity for the line overhead and SPE data in the previous STS-1 frame. Since the B2 byte is calculated for each STS-1 independent of the other STS-1 s, the device mode (STS-48 or STS-192) does not affect the operation of this block. The B2 values in all STS-1s in an STS-48 channel can be fully corrupted (by inverting all the bits) on a per STS-48 basis, using the B2 corrupt enable control bit. The duration of the corruption is defined in frames per second, up to a maximum of 8000 frames (1 second) between rising edges of the performance monitoring clock . The B2 corrupt frame count register specifies this duration . Table 139 . B2 Register Summary Function B2 Calculation Disable B2 Corrupt Enable B2 Corrupt Duration Control 164 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC_RX_BYPASS-SO (R/W) OHP RX PROV SO (R/W) OHP RX_B2CORRUPT_SO (R/W) OHP_RX_B2CAL_DIS 4 0x1115 RX B2CORRUPT ENB RX_B2CORRUPT FRM CNT 4 4 0x1310 0x1320 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 35 35.1 with Strong/Weak FEC and Digital Wrapper Transpose Multiplexer (TMX) Functional Description of the TMX In STS-192 mode, the bytes in the four STS-48 channels need to be combined and reordered to create an STS-192 data stream. This is performed by the transpose multiplexer (TMX) . The byte ordering of the individual STS-1 s, or STS-1 components of an STS-Nc, that comprise the STS-48 as it enters the TDMX and after the TDMX (STS-192 byte ordering) and the details of the STS-48 to STS-192 multiplexing can be found in GR-253-CORE Section 5-1, Network Element Architectural Features (Multiplexing Procedure), page 5-1 . If the device is in STS-48 mode, the data is received on all four channels and the TMX is bypassed. The module receives individual STS-48 bytes every clock period from each STS-48 and will output 16 bytes on the STS-192 . Because SONET interleaving causes each STS-48 bandwidth to be multiplexed into an STS-192 16 bytes at a time, each STS-48 must have 16 bytes stored and then output every fourth clock on the 16-byte wide STS-192 output. That is, each STS-48 must source all 16 bytes in the STS-192 word once every four clocks. Table 140 . Transpose Multiplexer Register Summary Function Transpose Multiplexer Disable Control 36 36.1 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC RX-TP BYPASS (RNV) RX-TMX-DIS 1 0x1112 Scrambler Functional Description of the Scrambler in the Transpose Multiplexer The data stream is optionally scrambled using the standard generator polynomial 1 + x6 + x7. The scrambling can be disabled by the corresponding scrambler disable bit of the LTE channel N provisioning register. Table 141 . Scrambler Register Summary Function Scrambler Disable Control Scrambler Mode Control Agere Systems Inc. I Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC RX BYPASS SO OHP RX SCRM DIS 4 0x1115 SONFEC-RX MODE (R/W) I RX-SCR-MODE I 1 I 0x1110 165 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 37 37.1 Operational Description July 2002 131 Computing Functional Description of 131 Computing The section BIP-8 byte is located only in the first STS-1 of the STS-48 or STS-192 and carries the even parity of the scrambled data in the previous STS-192 frame . In every frame, the calculated BIP-8 for the previous frame is inserted in the 131 byte of the current frame prior to scrambling . The 131 value can be fully corrupted (by inverting all bits) on a per-channel basis using the 131 corrupt enable control bit . The duration of the corruption is defined in frames per second, up to a maximum of 8000 frames (1 second) between rising edges of performance monitoring clock . The 131 corrupt frame count register specifies this duration . Table 142 . B1 Computing Register Summary Function 131 Calculation Disable 131 Calculation Mode 131 Corrupt Enable 131 Corrupt Duration Control 166 Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) SONFEC RX_BYPASS SO (R/W) OHP RX_B1CAL DIS 4 0x1115 SONFEC RX_MODE (R/W) RX_B1CALC MODE 1 0x1110 OHP_RX_PROV_SO (R/W) OHP RX_B1CORRUPT_SO (R/W) RX_B1CORRUPT_ENB RX B1CORRUPT FRM CNT 4 4 0x1310 Ox131C Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 38 with Strong/Weak FEC and Digital Wrapper Microprocessor Interface 38.1 Microprocessor Interface Overview The TFEC041 OG microprocessor interface architecture is configured for glueless interface to the Motorola MPC860 and MC68360 microprocessors . The Intel microcontrollers 8XC251 and 80C196 and the i960 microprocessor may also be utilized to interface to the TFEC0410G. However, provisions on the board need to be made to (de)multiplex the address and data bus . The state of the MPTYPE_IM input signal indicates to the device whether it interfaces to a Motorola microprocessor or an Intel microcontroller. Other microprocessors may be used if their timing requirements fit to one of the modes described . The TFEC0410G has separate 16-bit wide address and data buses . The MPDB-8-16 input distinguishes between an 8-bit or 16-bit wide microprocessor data bus being used. In case of an 8-bit wide microprocessor data bus interface, the eight upper bits of the device data bus ports are not being used and are held 3-state . The microprocessor interface operates at the frequency of the microprocessor clock (PCLK) input, which should be in the range of 10 MHz to 100 MHz . Depending on the state of the MPMODE_As input signal, the interface to the 80960SX microprocessor is synchronous, while the interface to the 8XC251 and 80C196 microcontrollers is asynchronous . Similarly, with the MPC860 or MC68360 microprocessors being used, the state of the MPMODE_As input signal determines whether bus transfers are synchronous or asynchronous, respectively. In this case, the microprocessor interface also generates an external processor bus error if an internal data acknowledgment is not received in a predetermined period of time, or on parity errors if the MPPAREN input is enabled. All internal counters are latched using an external or internal performance monitor (PM) latch pulse that must occur once per second to ensure all internal counters do not saturate . Persistency alarm registers are used in conjunction with the interrupt alarm registers to indicate whether alarms are persistent. The TFEC041OG contains 48 general purpose inputs/outputs (GPIOs), which can be used to monitor signals on the board . 38.2 Subblock Address Space Assignment The 16-bit address space is assigned to the subblocks of the device, as shown in Table 143 . Table 143 . Subblock Address Space Assignment Base Address 0x0000 0x1000 0x2000 0x3000 Block Microprocessor interface/top level . DWFEC macro . SONFEC macro . ( Unused . Agere Systems Inc. Block Name I MPU DWFEC SONFEC - 167 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 38 38.2 Operational Description July 2002 Microprocessor Interface (continued) Microprocessor Interface Overview (continued) Table 144 . MPU General Register Summary Function Version Control Device Identification Device Identification Device Identification Device Identification Device Identification Scratch 38.3 0 1 2 3 4 Register Name (First Occurrence) Register Bits Qty. DEV VER (R0) DEV_ID0 (RO) DEV_ID1 (RO) DEV ID2 (RO) DEV_ID3 (RO) DEV_ID4 (RO) DEV SCRATCH (R/W) DEV VER DEV_ID0 DEV_ID1 DEV ID2 DEV_ID3 DEV_ID4 DEV SCRATCH 1 1 1 1 1 1 1 1st Addr (hex) 0x0 0x1 0x2 0x3 0x4 0x5 0x200 Microprocessor Interface Modes Table 145 highlights the four microprocessor modes controlled by the MPTYPE-IM and MPMODE AS inputs . Table 145 . Microprocessor Configuration Modes Mode MPTYPE IM MPMODE AS MODE 1 1 1 MODE 2 1 0 MODE 3 0 1 MODE 4 0 0 38.4 Description Typical Application Synchronous interface ; handshake using data acknowledge . Asynchronous interface ; handshake using data acknowledge . Synchronous interface ; handshake through inserted wait states ; asynchronous address latching. Asynchronous interface ; handshake through inserted wait states ; asynchronous address latching. MPC860 MC68360, MC68HC16X i960 (80960SX) 80c196, 8XC251 Microprocessor Interface Pinout Descriptions The MODE[1 -4] specific pin definitions are given in Table 146 . Note that the microprocessor interface uses the same set of pins in all modes. 168 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 38 with Strong/Weak FEC and Digital Wrapper Microprocessor Interface (continued) 38.4 Microprocessor Interface Pinout Descriptions (continued) Table 146 . MODE[1-4] Microprocessor Pin Definitions Configuration Device Pin Name Microprocessor Pin Name Pin Type Assertion Sense MODE 1 CS- N CS Input Active-low Chip select . TS-N RW_N TS R/W Input Input Active-low Transfer start. Read/write : RW_N = 1 for read. RW N = 0 for write . ADDRESS DATA PARITY A D DP Input I/O - Address bus. Data bus. I/O - Parity bus (odd parity supported only) . TAN TA TEA Output TEA- N INTH_N/ INTL N MODE 2 CS- N TS-N RW_N CS TS R/W Input DS- N DS +Input ADDRESS DATA A D Input I/O PARITY TAN PRTY DSACK* BERR I/O Output TEA_ N INTH_N/ INTL N MODE 3 Agere Systems Inc. IRQ* Output Output Input Input IRQ* Output Output CS- N TS-N RW_N - Input ALE W/R Input Input DS- N AS Input ADDRESS DATA AD AD Input I/O TAN INTH_N/ INTL N READY INT* Output Output Function Active-low Transfer acknowledge . Active-low Transfer error acknowledge . Active-low Interrupt. Active-low Chip select . Active-low Transfer start. - Read/write : RW_N = 1 for read. RW N = 0 for write . Active-low Data strobe . - Address bus. Data bus. Parity bus . Active-low Transfer acknowledge . Active-low Bus error. Active-low Interrupt. Active-low Chip select . Active-high Address latch enable. - Write/read: RW_N = 0 for read. RW N = 1 for write . Active-low Address strobe . - Address bus. Data bus. Active-low Ready signal . Active-low Interrupt. 169 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 38 Operational Description July 2002 Microprocessor Interface (continued) 38.4 Microprocessor Interface Pinout Descriptions (continued) Table 146 . MODE[1-4] Microprocessor Pin Definitions (continued) Configuration Device Pin Name Microprocessor Pin Name Pin Type Assertion Sense MODE 4 CS- N TS-N RW N CSx ALE RD Input Active-low Chip select . Active-high Address latch enable. DS- N ADDRESS WR AD Input Input DATA TAN AD, D READY, WAIT INT* I/O INTH_N/ INTL N 38.5 Input Input Output Output Function Active-low Read enable. Active-low Write enable . - Address bus. Data bus. Active-low Ready, wait signal . Active-low Interrupt. Reset Behavior The microprocessor interface can be reset by driving the pin RST_N active-low. It will take about 5 clock cycles of PCLK after the reset gets negated until the microprocessor interface is fully functional . The software reset registers (0x300-0x304) can be used to reset parts of the device . Those registers themselves can only be reset by the hardware reset, i .e., by pulling RST N active low. After a reset of the MPU macro, the MPU registers within the SONFEC and DWFEC macro are powered down and held in reset. They can be put back to function by enabling the bits DEV_SONFEC_PCLK_PDN and DEV_DWFEC_PCLK_PDN in the DEV_PDN_ICLK register. Note that all previously programmed values in the MPU registers of SONFEC and DWFEC will be lost during powerdown . Similarly, the clock MUXing control register DEV_CTL_CLKMUX[0:4] S[0 :3] will disable the internal functional clocks upon a reset of the MPU macro. All registers that rely on a functional clock to write or return data will not be accessible before those clocks are enabled . This affects the PRBS counter registers OHP_RX_PRBS_BER_S[0 :3] in the SONFEC macro and DW_RX_CNT_PRBS S[0 :3] in the DWFEC macro . An attempt to access those registers in this case will cause the microprocessor interface to get stuck waiting for an internal acknowledge . In mode 1 and mode 2, the interface will time-out itself and generate a processor bus error (see Section 38.7, Transfer Error Acknowledge (Mode 1 and Mode 2 Only), on page 171). In mode 3 and mode 4, the microprocessor interface can be reset from this state by negating and asserting CS N. In general, the microprocessor interface will terminate any access after detecting CS_N being negated . 170 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 38 38.6 with Strong/Weak FEC and Digital Wrapper Microprocessor Interface (continued) Microprocessor Data Bus Width The microprocessor allows the connection of either an 8-bit or 16-bit wide data bus . The MPDB 8_16 input signal indicates which data bus width is being used . MPDB-8-16 = 0 assumes 8-bit data bus transfers, while MPDB 8_16 = 1 assumes 16-bit data bus transfers . The MPDB 8_16 input is supposed to be a static input. Since all internal registers of the TFEC0410G are 16 bits wide, an additional holding register is needed to facilitate an 8-bit data transfer. This implies that on an 8-bit data bus, two accesses are necessary to read or write the complete contents of an internal register. The internal holding register is 8 bits wide and resides at the address location 0x500 . It is connected to the upper byte of the internal data bus that connects to the registers . To write an internal register, a first access needs to write the upper byte of the 16-bit data to the holding register. During a second write, the lower byte of the data together with the contents of the holding register gets written to the address location specified . Similarly, in read mode, the upper byte of the register that was specified by the address gets loaded in the holding register, while the lower byte is visible on the external data bus . During a second read access, the upper byte can be made available on the data bus by reading the holding register. Table 147 . Hold Register Summary Function 8-Bit Mode Hold Register 38.7 Register Name (First Occurrence) I DEV-HOLD (R/W) Register Bits I DEV HOLD Qty. I 1 1st Addr (hex) I 0x500 Transfer Error Acknowledge (Mode 1 and Mode 2 Only) The TFEC0410G contains a bus time-out counter. It will terminate the device access if an internal data acknowledgment is not received within 32 PCLK periods, in case of an access to an undefined address region. This interval is used since all valid internal accesses to the device will be completed in significantly less than 32 PCLK periods . The transfer error acknowledge output TEA_N will be driven low in the event of a bus time-out. This feature must be considered with respect to the external processor's ability to generate its own bus time-out. The output pin TEA_N is asserted in conjunction with TA-N, if the calculated parity value does not match the parity generated by the external microprocessor on a data transfer and the input MPPAREN is driven high. The device only supports odd parity. Agere Systems Inc. 171 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 38 38.8 Operational Description July 2002 Microprocessor Interface (continued) Interrupt Structure The interrupt structure of the TFEC0410G is designed to minimize the effort for software/firmware to isolate the interrupt source . The interrupt structure is comprised of different registers, depending on the consolidation level. At the lowest level (source level), there are the three following registers : . Alarm register (AR), typically of the write-1-clear (W1 C) type . . Interrupt mask (I M) register of the read/write (R/W) type. . Persistency alarm (PA) register of the read-only (RO) type. An alarm register latches a raw status alarm. This latched alarm may contribute to an interrupt if its corresponding interrupt mask bit is enabled. Individual latched alarms are consolidated into an interrupt status register (ISR). If any of the latched alarms that are consolidated into a bit of an ISR are set and unmasked, the ISR bit is set . The ISR bit may contribute to an interrupt if its corresponding interrupt mask bit is disabled . ISRs may be consolidated into a higher-level ISR in a similar fashion until all alarms are consolidated into the chip-level ISR . The alarm register that causes an interrupt can be determined by traversing the tree of ISRs, starting at the chip-level ISR, until the source alarm is found. The raw nonregistered interrupt source can also be accessed through an address in the address map where applicable. At the chip level, all high-priority interrupts, e.g., LOC, are grouped together into one ISR and all lower-level interrupts, e.g., bit error, etc ., are grouped into another ISR. There will be two dedicated device outputs, one for highpriority interrupts and one for low-priority interrupts . In the case that the microprocessor supports only one interrupt input, the low-priority ISR can be mapped into one maskable bit of the high-priority ISR and will be observable on that output pin . Note : Interrupts are masked when the corresponding bit in the mask register is 0. If the mask register bit is 1, the interrupt is enabled. 38.9 Interrupt Alarm and Interrupt Persistency Registers An alarm is persistent if it has been asserted continuously (i .e., the alarm has not been negated from the time it was asserted to the time it was read by software) . An alarm is not persistent if it is negated one or more times from the point at which it was asserted to the point at which it was read by software . The persistency register monitors the state of an alarm point, and indicates to software whether the alarm is persistent. The following timing diagram (Figure 54) indicates the operation of the persistency register relative to the raw status alarm, and its corresponding interrupt alarm register. It also describes the software interaction with respect to its attempt to clear the alarm and its interpretation . At the rising edge of the raw alarm point, the corresponding interrupt alarm and persistency alarm register are set . The falling edge of the raw alarm causes the persistency alarm register to be reset (cleared) . Any subsequent assertion of the raw alarm does not cause the persistency alarm register to be asserted . It remains reset until the interrupt alarm register is cleared (after the raw alarm is negated and the interrupt alarm register is cleared) . Once the interrupt alarm register is cleared, its corresponding persistency alarm register reset is released. The persistency register is now able to be set on the next assertion of the raw alarm point. Note : For the raw alarm to be reliably latched by PCLK, it needs to be stable for at least 10 clock cycles of a 78 MHz/83 MHz internal clock . 172 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 38 with Strong/Weak FEC and Digital Wrapper Microprocessor Interface (continued) 38.9 Interrupt Alarm and Interrupt Persistency Registers (continued) SOFTWARE ATTEMPTS TO CLEAR INTERRUPT ALARM REGISTER; SINCE RAW ALARM IS ACTIVE, NOTHING HAPPENS . ; SOFTWARE CLEARS INTERRUPT ALARM REGISTER AFTER WRITE ; PERSISTENCY REGISTER IS NOW RELEASED TO BE SET AGAIN . RAW ALARM/ALARM STATE (RO) ; II . I I u INTERRUPT ALARM REGISTER (R/W1 C) PERSISTENCY REGISTER (RO) RAW ALARM EVENT GETS LATCHED INTO INTERRUPT ALARM AND PERSISTENCY REGISTER. -L RAW ALARM GETS INACTIVE WHICH CLEARS PERSISTENCY REGISTER. RAW ALARM BECOMES ACTIVE AGAIN ; PERSISTENCY REGISTER STAYS CLEARED TO INDICATE TO SOFTWARE THAT RAW ALARM WAS NOT PERSISTENT SINCE INTERRUPT ALARM REGISTER WAS SET. Note : All above registers can be read at any time by software to have the interrupt status evaluated without any impact to their state . Figure 54. Persistency Register Operation 38.10 Performance Monitor (PM) Clock The PM CLK signal is sent to all blocks for performance monitoring (collecting statistics) . PM_CLK can come from an external pin, an internal 1 s timer, or be controlled by software, depending on the PM mode DEV_PMMODE[1 :0] bits. The external PM_CLK pin is a bidirectional signal controlled by the DEV_PMCLK_IOCTL bit. This bit defaults to 0, making the pin an input . Table 148 . PMCLK Configuration and Interrupt Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) PMCLK Configuration PMCLK Configuration PM Counter Preload Value Software Reset for MPU Registers PMCLK Interrupt Alarm PMCLK Interrupt Alarm Mask DEV PMCLK CFG (R/W) DEV_PMCLK_CFG (R/W) DEV_PMCLK_PRELD (R/W) DEV_MPUREG_SWRST (R/W) DEV_PMCLK_ALARM (W1 C) DEV PMCLK MASK (R/W) DEV PMMODE DEV_PMCLK_IOCTL DEV_PMCLK_PRELD DEV_PM_TRIG_SWRST 1 1 1 1 0x100 0x100 0x101 0x300 DEV_PMCLK_A DEV PMCLK M 1 1 0x113 Ox4A Agere Systems Inc. 173 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 38 Operational Description July 2002 Microprocessor Interface (continued) 38.10 Performance Monitor (PM) Clock (continued) Table 149 . PMCLK Counter Register Summary Function Receive Performance Monitoring Register [4 :0] Receive REI-L Performance Monitoring [20 :16] Receive REI-L Performance Monitoring [15 :0] Receive CV-L Performance Monitoring [23 :16] Receive CV-L Performance Monitoring [15 :0] Receive CV-L Performance Monitoring [23 :16] Receive CV-L Performance Monitoring [15 :0] Receive CV-S Performance Monitoring [15 :0] Transmit PM Register [4 :0] Transmit CV-L Performance Monitoring [23 :16] Transmit CV-L Performance Monitoring [15 :0] Transmit CV-S Performance Monitoring [15 :0] DW BIP-0 Counter [26 :16] DW 131 P-0 Counter [15 :0] DW BIP-1 Counter [26 :16] DW 131 P-1 Counter [15 :0] DW BEI-0 Counter [26 :16] DW BEI-0 Counter [15 :0] DW BEI-1 Counter [26 :16] DW BEI-1 Counter [15 :0] 38.11 Register Name Qty. OHP RX PM OHP_RX_REI_U_PM OHP_RX_REI_L_PM OHP RX POST CVL U PM OHP_RX_POST_CVL_L_PM OHP_RX_PRE_CVL_U_PM OHP RX PRE CVL L PM OHP_RX_CVS_PM OHP_TX_PM OHP TX CVL U PM OHP_TX_CVL_L_PM OHP_TX_CVS_PM DW RX CNT BIP00 DW-RX-CNT-BIP01 DW-RX-CNT-BIP10 DW RX CNT BIP11 DW_RX_CNT_BEI00 DW-RX-CNT-BE101 DW RX CNT BE110 DW RX CNT BE111 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1st Addr (hex) Ox 132C 0x1338 0x1339 0x1341 0x1342 Ox134A 0x13413 0x1353 0x1394 Ox139C 0x139D Ox 13A5 0x2328 0x2329 0x2331 0x2332 Ox233A 0x23313 0x2343 1 0x2344 General Purpose Input/Output (GPIO) The programmable I/O general purpose input/output (GPIO) consists of 48 device pins that can be used for internal or external signal observation . These pins can be configured to be either inputs or outputs, depending on the DEV_GPIO_CFG[47 :0] bits. These pins are useful for board designers who need the ability to monitor or control signals on their boards. If a GPIO pin is configured for input, it can be programmed to generate either a level-sensitive interrupt, a positive edge detect interrupt, a negative edge detect interrupt, or both edges detect interrupt contributing to the composite external interrupt. The raw value on this pin can be read from the DEV_GPI STATE[47:0] bits. The interrupt alarm register is DEV_GPI_ALARM and the corresponding mask and persistency registers are DEV_GPI MASK and DEV GPI PERSIST, respectively. If a GPIO pin is configured for output, different internal signals can be monitored depending on the four select bits for that pin in the DEV_GPO_SEL[0-3] registers . Note that only the lower 16 GPIO pins can be used to monitor internal signals, while the other GPIO pins are connected to an internal register permanently. Select Bits = 0000: The value provisioned in the DEV_GPO_VAL[47 :0] bits will appear on the device pin immediately. 174 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 38 with Strong/Weak FEC and Digital Wrapper Microprocessor Interface (continued) 38.11 General Purpose Input/Output (GPIO) (continued) Select Bits = 0001 : The value of an alarm status signal will be visible at the pin according to the assignment in Table 150 . Note that pins 16-47 are undefined in this case. Table 150 . GPIO Pin Assignment when Select Bits = 0001 GPIO Pin Internal Signal 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice I Slice 3, 2, 1, 0, 3, 2, 1, 0, 3, 2, 1, 0, 3, 2, 1, 0, SONFEC Tx composite alarm . SONFEC Tx composite alarm . SONFEC Tx composite alarm . SONFEC Tx composite alarm . DWFEC Tx composite alarm . DWFEC Tx composite alarm . DWFEC Tx composite alarm . DWFEC Tx composite alarms. SONFEC Rx composite alarm . SONFEC Rx composite alarm . SONFEC Rx composite alarm . SONFEC Rx composite alarm . DWFEC Rx composite alarm. DWFEC Rx composite alarm. DWFEC Rx composite alarm. DWFEC Rx composite alarms. Select Bits = 0010: The value of the transmit and receive phase detector reference and variable signals will be visible at the pin according to the assignment in Table 151 . Note that pins 16-47 are undefined in this case. Table 151 . GPIO Pin Assignment when Select Bits = 0010 GPIO Pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Internal Signal Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice Slice I Slice Agere Systems Inc. 3-Phase 2-Phase 1-Phase 0-Phase 3-Phase 2-Phase 1-Phase 0-Phase 3-Phase 2-Phase 1-Phase 0-Phase 3-Phase 2-Phase 1-Phase 0-Phase detector Tx variable signal (44 .434 MHz). detector Tx variable signal (44 .434 MHz). detector Tx variable signal (44 .434 MHz). detector Tx variable signal (44 .434 MHz). detector Tx reference signal (44 .434 MHz). detector Tx reference signal (44 .434 MHz). detector Tx reference signal (44 .434 MHz). detector Tx reference signal (44 .434 MHz). detector Rx variable signal (44 .434 MHz). detector Rx variable signal (44 .434 MHz). detector Rx variable signal (44 .434 MHz). detector Rx variable signal (44 .434 MHz). detector Rx reference signal (44 .434 MHz). detector Rx reference signal (44 .434 MHz). detector Rx reference signal (44 .434 MHz). detector Rx reference signal (44 .434 MHz). 175 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 38 Operational Description July 2002 Microprocessor Interface (continued) 38.11 General Purpose Input/Output (GPIO) (continued) Select Bits = 0011 : The value of an alarm status signal will be visible at the pin according to the assignment in Table 152 . Note that pins 16-47 are undefined in this case. Table 152 . GPIO Pin Assignment when Select Bits = 0011 GPIO Pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Internal Signal Logic 0. Logic 0. Logic 0. Logic 0. Logic 0. Logic 0. Logic 0. Logic 0. Slice 3-SONFEC Tx free-running 8 kHz signal . Slice 2-SONFEC Tx free-running 8 kHz signal . Slice 1-SONFEC Tx free-running 8 kHz signal . Slice 0-SONFEC Tx free-running 8 kHz signal . Slice 3-DWFEC Tx free-running 8 kHz signal . Slice 2-DWFEC Tx free-running 8 kHz signal . Slice 1-DWFEC Tx free-running 8 kHz signal . I Slice 0-DWFEC Tx free-running 8 kHz signal . Select Bits = Others : Logic 0. 176 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 38 38.11 with Strong/Weak FEC and Digital Wrapper Microprocessor Interface (continued) General Purpose Input/Output (GPIO) (continued) Table 153 . GPIO Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) GPIO Configuration 0 (for GPI pins 47:32) GPIO Configuration 1 (for GPI pins 31 :16) GPIO Configuration 2 (for GPI pins 15:0) GPI Interrupt Polarity Configuration 0 (for GPI pins 47:32) GPI Interrupt Polarity Configuration 1 (for GPI pins 31 :16) GPI Interrupt Polarity Configuration 2 (for GPI pins 15:0) GPI Interrupt Type Configuration 0 (for GPI pins 7:0) GPI Interrupt Type Configuration 1 (for GPI pins 15:8) GPI Interrupt Type Configuration 2 (for GPI pins 23:16) GPI Interrupt Type Configuration 3 (for GPI pins 31 :24) GPI Interrupt Type Configuration 4 (for GPI pins 39:32) GPI Interrupt Type Configuration 5 (for GPI pins 47:40) GPO Output Value 0 (for GPO pins 47:32) GPO Output Value 1 (for GPO pins 31 :16) GPO Output Value 2 (for GPO pins 15:0) GPO Selection 0 (for GPO pins 3:0) GPO Selection 1 (for GPO pins 7:4) DEV_GPI CFG0 (R/W) DEV_GPIO DIRO 1 0x120 DEV_GPI CFG1 (R/W) DEV_GPIO DIR1 1 0x121 DEV_GPI CFG2 (R/W) DEV_GPIO DIR2 1 0x122 DEV_GPI INT_POLO (R/W) DEV_GPI INT_POLO 1 0x123 DEV_GPI INT_POL1 (R/W) DEV_GPI INT_POL1 1 0x124 DEV_GPI INT_POL2 (R/W) DEV_GPI INT_POL2 1 0x125 DEV_GPI INT TYPO (R/W) DEV_GPI[7 :0] INT TYP[1 :0] 1 0x126 DEV_GPI-INT TYP1 (R/W) DEV_GPI[15:8] INT TYP[1 :0] 1 0x127 DEV_GPI-INT TYP2 (R/W) DEV_GPI[23:16] INT TYP[1 :0] 1 0x128 DEV_GPI-INT TYP3 (R/W) DEV_GPI[31 :24] INT TYP[1 :0] 1 0x129 DEV_GPI-INT TYP4 (R/W) DEV_GPI[39:32] INT TYP[1 :0] 1 0x12A DEV_GPI-INT TYP5 (R/W) DEV_GPI[47:40] INT TYP[1 :0] 1 0x1213 DEV_GPO VAL0 (R/W) DEV_GPO VAL0 1 0x12C DEV_GPO VAL1 (R/W) DEV_GPO VAL1 1 0x12D DEV_GPO VAL2 (R/W) DEV_GPO VAL2 1 0x12E DEV_GPO SEL0 (R/W) DEV_GPO[3 :0] SEL[3 :0] 1 0x12F DEV_GPO SEL1 (R/W) DEV_GPO[7 :4] SEL[3 :0] 1 0x130 Agere Systems Inc. 177 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 38 38.11 Microprocessor Interface (continued) General Purpose Input/Output (GPIO) (continued) Table 153. GPIO Register Summary (continued) Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) GPO Selection 2 (for GPO pins 11 :8) GPO Selection 3 (for GPO pins 15:12) GPI Interrupt Alarm 0 (for GPI pins 47:32) GPI Interrupt Alarm 1 (for GPI pins 31 :16) GPI Interrupt Alarm 2 (for GPI pins 15:0) GPI Interrupt Mask 0 (for GPI pins 47:32) GPI Interrupt Mask 1 (for GPI pins 31 :16) GPI Interrupt Mask 2 (for GPI pins 15:0) GPI Interrupt Persistency 0 (for GPI pins 47:32) GPI Interrupt Persistency 1 (for GPI pins 31 :16) GPI Interrupt Persistency 2 (for GPI pins 15:0) GPI Interrupt Raw State 0 (for GPI pins 47:32) GPI Interrupt Raw State 1 (for GPI pins 31 :16) GPI Interrupt Raw State 2 (for GPI pins 15:0) DEV_GPO SEL2 (R/W) DEV_GPO[11 :8] SEL[3 :0] 1 0x131 DEV_GPO SEL3 (R/W) DEV_GPO[15:12] SEL[3 :0] 1 0x132 DEV_GPI ALARMO (W1 C) DEV_GPI AO 1 0x18 DEV_GPI ALARM1 (W1C) DEV_GPI A1 1 0x19 DEV_GPI ALARM2 (W1C) DEV_GPI A2 1 0x1A DEV_GPI-MASKO (R/W) DEV_GPI MO 1 0x47 DEV_GPI-MASK1 (R/W) DEV_GPI M1 1 0x48 DEV_GPI-MASK2 (R/W) DEV_GPI M2 1 0x49 DEV_GPI PERSISTO (RO) DEV_GPI-PO 1 0x74 DEV_GPI PERSIST1 (RO) DEV_GPI-P1 1 0x75 DEV_GPI PERSIST2 (RO) DEV_GPI-P2 1 0x76 DEV_GPI STATEO (RO) DEV_GPIO 1 0x94 DEV_GPI STATE1 (RO) DEV_GP11 1 0x95 DEV_GPI STATE2 (RO) DEV-GP12 1 0x96 178 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 39 with Strong/Weak FEC and Digital Wrapper TFEC Primary Clock Inputs The following table lists the possible TFEC modes and the clocks (primary inputs) needed for each mode. The first column (Mode) lists all the commonly used modes of the device . For each of these modes there is a reference (hyperlink) to the figures in the data sheet listed in the second column (Figure Number), if one exists . The receive line clock primary input (RCLKLI 3-2-1-0), as well as the total receive line rate (Rx-Line Bandwidth), are listed in columns 3 and 4, respectively . The same listing is repeated for receive system, transmit line, and transmit system in subsequent columns. In regenerator mode, loopback is on the system side; for weak FEC, this loopback could be before or after the elastic store on the system side. Only commonly used modes are listed below. The bidirectional mode does not use the elastic store in DWFEC . Abbreviations used are listed below : Strong : Weak : x: p: Strong FEC only, can be FEC or digital wrapper mode. Weak FEC only. Clock input need not be present . Clock input needs to be present . Table 154 . TFEC Clock Setup Mode Figure ~ RCLKLI Rx-Line RCLKSI Number 3-2-1-0 Bandwidth 3-2-1-0 Tx-Line TCLKSI Tx-System Rx-System TCLKLI Bandwidth 3-2-1-0 Bandwidth 3-2-1-0 Bandwidth Terminal [Rx/Tx Symmetric ; 16 Bits at 622 MHz/666 MHz] Strong 10 Gbits/s 12/14 x-x-x-p 1 x 10 .666 x-x-x-p 1 x 09 .953 x-x-x-p 1 x 10 .666 x-x-x-p 2 12/14 p-p-p-p 4 x 2 4 x 2 .488 4 x 2 .666 Strong .5 Gbits/s .666 p-p-p-p p-p-p-p p-p-p-p Bidirectional x-x-x-p 1 x 1 x 1 x 10 .666 x-x-x-p Strong 10 Gbits/s 16 10 .666 10 .666 4 x 2.666 4 x 2 .666 4 x 2 .666 Strong Bidirectional 2.5 Gbits/s 16 p-p-p-p p-p-p-p 17 x-x-x-p 1 x 1 x 1 x 9 .953 x-x-x-p Weak 10 Gbits/s 9.953 9 .953 2 17 p-p-p-p 4 x 2 4 x 2 4 x 2 Weak .5 Gbits/s .488 .488 .488 p-p-p-p 19/21 x-x-x-p 1 x 10 .666 x-x-x-p 1 x 9 .953 x-x-x-p 1 x 10 .666 x-x-x-p Strong and Weak 10 Gbits/s 19/21 p-p-p-p 4 x 2.666 4 x 2 .488 4 x 2 .666 Strong and Weak 2 .5 Gbits/s p-p-p-p p-p-p-p p-p-p-p [Rx/Tx Internal ; 622 Regenerator Symmetric, Loopback on the System 16 Bits at MHz/666 MHz] x-x-x-p 1 x 10 .666 x-x-x-p 1 x 10 .666 Strong 10 Gbits/s 13/15 2 4 x 2 4 x 2 .666 Strong .5 Gbits/s 13/15 p-p-p-p .666 p-p-p-p x-x-x-p 1 x 10 .666 1 x 10 .666 Strong Bidirectional 10 Gbits/s 4 x 2.666 4 x 2 .666 Strong Bidirectional 2.5 Gbits/s p-p-p-p x-x-x-p 1 x 9.953 1 x 9 .953 Weak 10 Gbits/s before LB ES 18 4 x 2.488 4 x 2 .488 Weak 2 .5 Gbits/s before LB ES 18 p-p-p-p x-x-x-p 1 x 10 .666 x-x-x-p 1 x 9 .953 Strong and Weak 10 Gbits/s 20 4 x 2.666 4 x 2 .488 Strong and Weak 2 .5 Gbits/s 20 p-p-p-p p-p-p-p Multiplex Mode Terminal [Weak FEC Only, 2 .5 Gbits/s to 10 Gbits/s/10 Gbits/s to 2 .5 Gbits/s ; 16 Bits at 622 MHz/666 22 x-x-x-p 1 x 9.953 4 x 2 .488 1 x 9 .953 x-x-x-p 10GLine_2G5System 22 x-x-x-p 1 x x-x-x-p 4 x 2 x-x-x-p 1 x Strong 10GLine_2G5System 10 .666 .488 10 .666 x-x-x-p Single 2 .5 Gbits/s Terminal [16 Bits at 155 MHz/166 MHz] x-x-x-p 1 x 2.666 x-x-x-p 1 x 2 .488 x-x-x-p 1 x 2 .666 x-x-x-p Strong 2 .5 Gbits/s 23 Bidirectional 2 x-x-x-p 1 x 2 1 x 2 1 x 2 x-x-x-p Strong .5 Gbits/s 23 .666 .666 .666 2 x-x-x-p 1 x 2 1 x 2 1 x 2 x-x-x-p Weak .5 Gbits/s 23 .488 .488 .488 2 x-x-x-p 1 x 2 x-x-x-p 1 x 2 x-x-x-p 1 x 2 x-x-x-p Strong and Weak .5 Gbits/s 23 .666 .488 .666 Single 2 .5 Gbits/s Regenerator [16 Bits at 155 MHz/166 MHz] x-x-x-p 1 x 2.666 x-x-x-p 1 x 2 .666 Strong 2 .5 Gbits/s 23 Bidirectional 2 x-x-x-p 1 x 2 1 x 2 .666 Strong .5 Gbits/s 23 .666 x-x-x-p 1 x 2.488 1 x 2 .488 Weak 2 .5 Gbits/s 23 I I 1 x 2 .666 1 Strong and Weak 2 .5 Gbits/s I 23 I x-x-x-p I 1 x 2.666 1 x-x-x-p I - Agere Systems Inc. 1 x 9 .953 4 x 2 .488 1 x 10 .666 4 x 2 .666 1 x 9 .953 4 x 2 .488 1 x 9 .953 4 x 2 .488 MHz] 4 x 2 .488 4 x 2 .488 1 1 1 1 x x x x 2 .488 2 .666 2 .488 2 .488 - 179 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 40 Operational Description July 2002 TFEC Clock Multiplexers The clock multiplexers listed below refer to Figure 24 on page 30. The values shown below are those for DEV_CTL CLKMUXn_Sm . When programming the clock multiplexer registers, the clock inversion control bit should be set to 0x0 (no inversion) under all conditions . 40.1 Clock Multiplexers and Register Bits Selection . Clock MUX A: DEV CTL CLKMUXO Sn [10 :8] . Clock MUX B: DEV CTL CLKMUX4 Sn [02 :0] . Clock MUX C: DEV CTL CLKMUXO Sn [02 :0] . Clock MUX D: DEV CTL CLKMUX1 Sn [10 :8] . Clock MUX E: DEV CTL CLKMUX1 Sn [02 :0] . Clock MUX F: DEV CTL CLKMUX2 Sn [10 :8] . Clock MUX G : DEV CTL CLKMUX2 Sn [02 :0] . Clock MUX H : DEV CTL CLKMUX3 Sn [10 :8] . Clock MUX I : DEV CTL CLKMUX4 Sn [10 :8] . Clock MUX J : DEV CTL CLKMUX3 Sn [02 :0] 40.2 Clock Selection .0x00: Ground . 0x01 : Transmit System Clock . 0x02: Receive System Clock . 0x03: Transmit Line Clock . 0x04: Receive Line Clock 180 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 40 40.2 with Strong/Weak FEC and Digital Wrapper TFEC Clock Multiplexers (continued) Clock Selection (continued) Table 155 . TFEC Clock Multiplexers Programming Mode Figure Number A B C D E F Terminal [Rx/Tx Symmetric; 1 6 Bits at 622 MHz/6 66 MHz] 12/14 0x03 0x03 0x03 0x01 0x00 0x04 12/14 0x03 0x03 0x03 0x01 0x00 0x04 Strong Bidirectional 10 Gbits/s 16 0x01 0x01 0x01 0x01 0x00 0x04 Bidirectional 2 Strong .5 Gbits/s 16 0x01 0x01 0x01 0x01 0x00 0x04 Weak 10 Gbits/s 17 0x01 0x01 0x00 0x00 0x01 0x00 17 Weak 2 .5 Gbits/s 0x01 0x01 0x00 0x00 0x01 0x00 Strong 10 Gbits/s Strong 2 .5 Gbits/s 0x03 0x01 0x01 G H I 0x02 0x00 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x04 ~ J 0x02 0x02 0x02 0x04 0x04 0x04 0x04 0x04 0x04 0x00 0x04 0x04 0x04 0x04 0x02 0x02 0x02 0x02 Strong and Weak 10 Gbits/s Strong and Weak 2 .5 Gbits/s 19/21 19/21 0x03 0x03 Strong 10 Gbits/s Strong 2.5 Gbits/s Strong Bidirectional 10 Gbits/s Strong Bidirectional 2.5 Gbits/s 13/15 13/15 0x04 0x04 0x04 0x02 0x04 0x04 0x04 0x02 0x00 0x04 0x00 0x04 0x02 0x02 0x00 0x00 0x00 0x00 0x00 0x00 18 18 0x04 0x04 0x00 0x00 0x04 0x04 0x00 0x00 0x04 0x00 0x04 0x00 0x00 0x04 0x00 0x04 0x00 0x00 0x00 0x00 0x03 0x03 0x03 0x01 0x01 0x04 0x02 0x02 0x02 Regenerator [Rx/Tx Symmetric, Internal Loopback on the System ; 16 Bits at 622 MHz/666 MHz] - Weak 10 Gbits/s Weak 2 .5 Gbits/s 0x04 0x04 0x04 0x00 0x04 0x04 0x04 0x00 0x00 0x04 0x00 0x04 0x00 0x00 0x00 0x00 Strong and Weak 10 Gbits/s before LB ES 20 0x04 0x04 0x04 0x02 0x02 0x04 0x02 0x02 Strong and Weak 2 .5 Gbits/s before LB ES 20 0x04 0x04 0x04 0x02 0x02 0x04 0x02 0x02 Multiplex Mode Terminal [Weak FEC Only, 2 .5 Gbits/s To 10 Gbits/s/10 Gbits/s To 2 .5 Gbits/s; 16 Bits at 622 MHz/666 MHz] 10GLine 2G5System 22 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x04 Strong 10GLine 2G5System 22 0x03 0x03 0x03 0x01 0x01 0x04 0x02 0x02 Strong 2 .5 Gbits/s Strong Bidirectional 2.5 Gbits/s Weak 2 .5 Gbits/s Single 2.5 Gbits/s Terminal [1 6 Bits at 155 MHz/166 MHz] 23 23 23 Strong and Weak 2 .5 Gbits/s 0x03 0x03 0x03 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x04 0x00 0x04 0x01 0x00 23 0x03 0x03 0x03 0x01 0x01 0x04 Single 2 .5 Gbits/s Regenerator [16 Bi ts at 155 MHz/166 MHz] Strong 2.5 Gbits/s 23 0x04 0x04 0x04 0x02 0x00 0x04 Strong Bidirectional 2.5 Gbits/s 23 0x04 0x04 0x04 0x00 0x00 0x04 Weak 2 .5 Gbits/s Strong and Weak 2 .5 Gbits/s I 23 23 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x04 0x02 0x02 0x02 0x00 0x00 0x00 0x00 0x04 0x02 0x02 0x04 0x04 0x04 0x04 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x02 0x02 0x02 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x04 0x00 0x00 I 0x04 I 0x04 I 0x04 I 0x02 I 0x02 I 0x04 I 0x02 I 0x02 I 0x00 I 0x00 1 . For clock multiplexers A and J, in 10 Gbits/s mode, only slice 0 needs to be programmed . Agere Systems Inc. 181 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 41 Operational Description July 2002 TFEC Data Multiplexers The data multiplexers listed below refers to Figure 24 on page 30. The values shown below are those for DEV CTL DMUX Sm . 41 .1 Data Multiplexers and Register Bits Selection . Data MUX K: DEV CTL-DMUX Sn [5:4] . Data MUX L: DEV CTL-DMUX Sn [7:6] . Data MUX M: DEV CTL-DMUX Sn [8] . Data MUX N: DEV CTL-DMUX Sn [3] . Data MUX O: DEV CTL-DMUX Sn [2] . Data MUX P: DEV CTL-DMUX Sn [1 :0] Table 156 . TFEC Data Multiplexer Programming A value of OxXX indicates a do not care condition . It could be set to 0x00. Mode Figure Number K L M N O P Terminal [Rx/Tx Symmetric, 16 Bits at 622 MHz/666 MHz] 12/14 Oxxx Oxxx Strong 10 Gbits/s 0x00 0x01 0x00 0x01 Strong 2 .5 Gbits/s 12/14 0x00 0x01 Oxxx Oxxx 0x00 0x01 Oxxx Oxxx Strong Bidirectional 10 Gbits/s 16 0x00 0x01 0x01 0x01 Strong Bidirectional 2 .5 Gbits/s 16 0x00 0x01 Oxxx Oxxx 0x01 0x01 17 Oxxx Oxxx Weak 10 Gbits/s 0x01 0x00 0x01 0x00 Weak 2.5 Gbits/s 17 0x01 Oxxx 0x00 0x01 Oxxx 0x00 19/21 OxXX Strong and Weak 10 Gbits/s 0x00 0x00 0x00 0x00 0x00 Strong and Weak 2.5 Gbits/s 19/21 0x00 0x00 0x00 0x00 OxXX 0x00 Regenerator [Rx/Tx Symmetric, Internal Loopback on the System ; 16 Bits at 622 M Hz/666 MHz] Strong 10 Gbits/s 13/15 0x00 0x02 OxXX OxXX OxXX OxXX Strong 2 .5 Gbits/si 13/15 0x00 0x02 OxXX OxXX OxXX OxXX Strong Bidirectional 10 Gbits/s 0x00 Oxxx Oxxx Oxxx Oxxx Oxxx Strong Bidirectional 2 .5 Gbits/s 0x00 Oxxx Oxxx Oxxx Oxxx Oxxx Weak 10 Gbits/s 18 0x01 Oxxx Oxxx 0x01 Oxxx Oxxx 2 Oxxx Oxxx Oxxx Oxxx Weak .5 Gbits/s 18 0x01 0x01 Strong and Weak 10 Gbits/s 20 0x00 0x00 Oxxx 0x00 Oxxx Oxxx Strong and Weak 2 .5 Gbits/s3 I 20 I 0x00 I 0x00 I Oxxx I 0x00 I Oxxx I Oxxx Notes : 1 . Loopback assumes at data MUX L . 2 . Loopback assumes after DW inside DWFEC . 3 . Loopback assumes inside SONFEC . 182 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 41 with Strong/Weak FEC and Digital Wrapper TFEC Data Multiplexers (continued) Table 156 . TFEC Data Multiplexer Programming (continued) A value of OxXX indicates a do not care condition . It could be set to 0x00. Mode Figure Number K L M N O P Multiplex Mode Terminal [Weak FEC Only, 2.5 Gbits/s to 10 Gbits/s/10 Gbits/s to 2.5 Gbits/s ; 16 Bits at 622 MHz/666 MHz] 10GLine 2G5System 22 0x01 OxXX 0x00 0x01 OxXX 0x00 Strong 10GLine 2G5System 22 0x00 0x00 0x00 0x00 OxXX 0x00 Single 2 .5 Gbits/s Terminal [16 Bits at 155 MHz/166 MHz] Strong 2 .5 Gbits/s 23 0x00 0x01 OXXX OXXX 0x00 0x01 Strong Bidirectional 2 .5 Gbits/s 23 0x00 0x01 OXXX OXXX 0x01 0x01 Weak 2.5 Gbits/s 23 0x01 OXXX 0x00 0x01 OXXX 0x00 Strong and Weak 2.5 Gbits/s 23 0x00 0x00 0x00 0x00 OXXX 0x00 Single 2.5 Gbits/s Regenerator [1 6 Bits at 155 M Hz/166 MHz] Strong 2 .5 Gbits/s OxXX OxXX OxXX OxXX 23 0x00 0x02 Strong Bidirectional 2 .5 Gbits/s 23 0x00 OXXX OXXX OXXX OXXX OXXX Weak 2.5 Gbits/s 23 0x01 OXXX OXXX 0x01 OXXX OXXX Strong and Weak 2.5 Gbits/s3 I 23 I 0x00 I 0x00 I OXXX I 0x00 I OXXX I OXXX 1 . Loopback assumes at data MUX L. 2. Loopback assumes after DW inside DWFEC. 3. Loopback assumes before data MUX M, inside SONFEC. 42 TFEC Phase Detectors 42.1 Clock Division Select . 0x0: 622 MHz clock, division by 14 or 79. . 0x1 : 666 MHz clock, division by 15 or 85. 42.2 Clock Selection .0x00: Ground . 0x01 : Transmit System Clock . 0x02 : Transmit Line Clock . 0x03: Receive System Clock . 0x04: Receive Line Clock Agere Systems Inc. 183 AdLib OCR Evaluation Operational Description July 2002 TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 42 42.2 TFEC Phase Detectors (continued) Clock Selection (continued) Table 157 . TFEC Phase Detectors Programming The polarity of the phase detectors is programmed to no inversion by default . Mode Figure Number RCLKLI RCLKSI Receive PD Controls Variable Div Sel Reference Div Sel TCLKLI TCLKSI Transmit PD Controls Variable Div Sel Reference &v Sel Terminal [Rx/Tx Symmetric; 16 Bits at 622 MHz/666 MHz] Strong 10 Gbits/s 12/14 666 MHz 622 MHz 0x0 0x03 0x1 0x04 666 MHz 622 MHz 0x1 0x02 0x0 0x01 Strong 2 .5 Gbits/s 12/14 666 MHz 622 MHz 0x0 0x03 0x1 0x04 666 MHz 622 MHz 0x1 0x02 0x0 0x01 Strong Bidirectional 10 Gbits/s 16 666 MHz 666 MHz Strong Bidirectional 2 .5 Gbits/s 16 666 MHz 666 MHz Weak 10 Gbits/s 17 622 MHz 622 MHz Weak 2 .5 Gbits/s 17 622 MHz 622 MHz Strong and Weak 10 Gbits/s 19/21 666 MHz 622 MHz 0x0 0x03 0x1 0x04 666 MHz 622 MHz 0x1 0x02 0x0 0x01 Strong and Weak 2 .5 Gbits/s 19/21 666 MHz 622 MHz 0x0 0x03 0x1 0x04 666 MHz 622 MHz 0x1 0x02 0x0 0x01 Regenerator [Rx/Tx Symmetric, Internal Loopback on the System ; 16 Bits at 622 MHz/666 MHz] Strong 10 Gbits/s 13/15 666 MHz 622 MHz 0x0 0x03 0x1 0x04 Strong 2 .5 Gbits/s 13/15 666 MHz 622 MHz 0x0 0x03 0x1 0x04 Strong Bidirectional 10 Gbits/s 666 MHz Strong Bidirectional 2 .5 Gbits/s 666 MHz Weak 10 Gbits/s before LB ES 18 622 MHz Weak 2 .5 Gbits/s before LB ES 18 622 MHz Weak 10 Gbits/s through LB ES 18 622 MHz 622 MHz 0x0 0x02 0x0 0x04 Weak 2 .5 Gbits/s through LB ES 18 622 MHz 622 MHz 0x0 0x02 0x0 0x04 Strong and Weak 10 Gbits/s 20 666 MHz 622 MHz 0x0 0x03 0x1 0x04 before LB ES Strong and Weak 2 .5 Gbits/s 20 666 MHz 622 MHz 0x0 0x03 0x1 0x04 before LB ES Strong and Weak 10 Gbits/s 20 666 MHz 622 MHz 0x0 0x03 0x1 0x04 622 MHz 0x0 0x02 0x1 0x04 through LB ES Strong and Weak 2 .5 Gbits/s 20 666 MHz 622 MHz 0x0 0x03 0x1 0x04 622 MHz 0x0 0x02 0x1 0x04 through LB ES ~i Multiplex Mode Terminal [Weak FEC Only, 2 .5 Gbits/s To 10 Gbits/s/10 Gbits/s To 2 .5 Gbits/s; 16 Bits at 622 MHz/666 MHz] 10GLine 2G5System 22 622 MHz 622 MHz Strong 10GLine_2G5System 22 666 MHz 622 MHz 0x0 0x03 0x1 0x04 666 MHz 622 MHz 0x1 0x02 0x0 0x01 Single 2 .5 Gbits/s Terminal [16 Bits at 155 MHz/166 MHz] Strong 2 .5 Gbits/s 23 166 MHz 155 MHz 0x0 0x03 0x1 0x04 166 MHz 155 MHz 0x1 0x02 0x0 0x01 Strong Bidirectional 2 .5 Gbits/s 23 166 MHz 166 MHz Weak 2 .5 Gbits/s 23 155 MHz 155 MHz Strong and Weak 2 .5 Gbits/s 23 166 MHz 155 MHz 0x0 0x03 0x1 0x04 166 MHz 155 MHz 0x1 0x02 0x0 0x01 Single 2 .5 Gbits/s Regenerator [16 Bits at 155 MHz/166 MHz] Strong 2 .5 Gbits/s 23 166 MHz 155 MHz 0x0 0x03 0x1 0x04 Strong Bidirectional 2 .5 Gbits/s 23 166 MHz Weak 2 .5 Gbits/s before LB ES 23 155 MHz Weak 2 .5 Gbits/s through LB ES 23 155 MHz 155 MHz 0x0 0x02 0x0 0x04 Strong and Weak 2 .5 Gbits/s 23 166 MHz 155 MHz 0x0 0x03 0x1 0x04 before LB ES Strong and Weak 2 .5 Gbits/s 23 166 MHz 155 MHz 0x0 0x03 0x1 0x04 155 MHz 0x0 0x02 0x1 0x04 through LB ES 184 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 43 with Strong/Weak FEC and Digital Wrapper TFEC Loopbacks The valid loopback configurations of TFEC are listed below. Refer to Figure 24 on page 30. The high-speed interface loopbacks are at 78 MHz or 83 MHz . These loopbacks are essentially loops through the high-speed multiplexer and demultiplexer blocks which could be operated at either of these clock frequencies . In all these modes, if an elastic store is present, any other clock could be used as long as its frequency matches that of the clock on the other side of the elastic store. The settings shown below are to be considered as guidelines only. As an example, it is possible to initiate two loopbacks inside the device, one within DWFEC (RDW2TDW LB) and another within SONFEC (TLINE2RLINE-LB), simultaneously . Such combinations are not listed in Table 158 . The primary input TFRMLI can only be used if the TCLKLI is present. However, TCLKLI could be used directly or as a substitute for any other clock via RCLKSI if the use of TFRMLI is desired . In 10 Gbits/s mode, only slice 0 of clock multiplexers A and J needs to be programmed. Table 158 . TFEC Loopback Programming Loopback (Active Signal) Primary Clocks Clock Multiplexers A/B C D E F G Data Multiplexers H I/J K L M N Receive High-Speed Interface [at 78 MHz/83 MHz] Loopbacks (DWFEC and SONFEC are disabled) RCLKLI 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 OxXX Oxxx Oxxx Receive DWFEC Only Loopbacks (SONFEC is Disabled) RDW2TDW_LB RCLKLI 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x00 0x00 OxXX OxXX OxXX RES2TES_LB RCLKLI 0x04 0x04 0x02 0x00 0x04 0x02 0x00 0x00 0x00 0x02 OxXX OxXX RCLKSI Receive SONFEC Only Loopbacks (DWFEC Disabled) RSYS2TSYS_LB RCLKLI 0x04 0x00 0x00 0x04 0x00 0x00 1 044 1 0x00 0x01 Oxxx Oxxx 0x01 Receive DWFEC and SONFEC Loopbacks RSYS2TSYS_LB RCLKLI 0x03 0x03 0x02 0x02 0x04 0x02 0x02 0x00 0x00 0x00 OxXX 0x00 RCLKSI TCLKLI Transmit High-Speed Interface [at 78 MHz/83 MHz] Loopbacks (DWFEC and SONFEC are Disabled) T2RF_LB TCLKSI 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 OxXX OxXx Oxxx Oxxx Transmit SONFEC Only Loopbacks (DWFEC is Disabled) TLINE2RLINE_LB TCLKSI 0x00 0x00 0x00 0x01 0x00 0x00 0x01 0x01 OxXX 0xxx 0x00 Oxxx Transmit DWFEC Only Loopbacks (SONFEC is Disabled) TDW2RDW_LB TCLKSI 0x00 0x01 0x00 0x00 0x01 0x00 0x00 0x01 OxXX 0x01 OxXX OxXX TDW2RDW_LB TCLKSI 0x00 0x03 0x01 0x00 0x03 0x02 0x00 0x02 Oxxx 0x01 Oxxx Oxxx TCLKLI RCLKSI TRSEN2RRSDE_LB TCLKSI 0x00 0x01 0x00 0x00 0x01 0x00 0x00 0x01 Oxxx 0x01 Oxxx Oxxx TRSEN2RRSDE_LB TCLKSI 0x00 0x03 0x01 0x00 0x03 0x02 0x00 0x02 OxXX 0x01 OxXX OxXX TCLKLI RCLKSI Transmit DWFEC and SONFEC Loopbacks TDW2RDW_LB TCLKSI 0x00 0x03 0x01 0x01 0x03 0x02 0x02 0x02 OxXX 0x00 0x00 0x00 TCLKLI RCLKSI TRSEN2RRSDE_LB TCLKSI 0x00 0x03 0x01 0x01 0x03 0x02 0x02 0x02 OxXX 0x00 0x00 0x00 TCLKLI RCLKSI R2TF LB O P oxXX OxXX OxXX OxXx OxXX Oxxx Oxxx Oxxx OxXx Oxxx Oxxx 0x02 Oxxx 0x00 0x01 0x00 0x01 0x01 0x01 0x00 0x01 0x01 OxXX 0x00 OxXX 0x00 1 . This loopback assumes DWES is bypassed (bidirectional mode); TFRMLI cannot be used to generate FEC/DW frames. 2. This loopback assumes DWES is present; TFRMLI could be used to generate FEC/DW frames. Agere Systems Inc. 185 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 44 Operational Description July 2002 TFEC Valid Modes The following truth table illustrates possible Rx/Tx modes in the TFEC0410G. Any combinations of these modes could be used. However care must be taken to set up the clocks in these modes. Refer to the Section 40, TFEC Clock Multiplexers, on page 180 to see the following settings: . DWFEC: Strong FEC (FEC/DW Mode) . SONFEC : Weak FEC . DWES: DWFEC Elastic Store 44.1 General Conditions on Primary Clock Inputs . Both RCLKLI and TCLKSI need to be present in all modes, except loopback/regenerator modes. . If DWFEC is used along with SONFEC and/or DWES, then both TCLKLI and RCLKSI need to be present . . If DWFEC is used with no DWES or SONFEC, then no other clocks need be present . . In case of multiplexing (10 Gbits/s H 2 .5 Gbits/s), all four 2 .5 Gbits/s signals are to be bit synchronous to the same clock via TCLKSI[0] . SYSTEM LINE 1 x 10 .666 1 x 09.953 4 x 02 .666 4 x 02.488 1 x 10 .666 DWFEC-NO DWES DWFEC + DWES DWFEC + SONFEC INVALID DWFEC + SONFEC 1 x 09 .953 INVALID SONFEC INVALID SONFEC 4 x 02 .666 INVALID INVALID DWFEC-NO DWES DWFEC + DWES DWFEC + SONFEC 4 x 02 .488 INVALID SONFEC [TxONLY] INVALID SONFEC Figure 55. TFEC Rx/Tx Possible Modes 186 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 45 45.1 with Strong/Weak FEC and Digital Wrapper Outline Diagram 792-Pin PBGAM1TH 40.00 0.20 o .0o 38 .70 o .os 35 .35 MAX Al BALL CORNER En r Al BALL PAD INDICATOR rJ 40 .00 0 .20 AVAILABLE MARKING AREA 00 .05 38 .70 o .os 35.35 I MAX 17 .72 1 J OL----7----J~ 4 x 45 CHAMFER - 8 x 4 .33 COUNTRY OF ORIGIN INDICATOR 1 .170 .05 f14 0.500 .10 I 30 TYP SOLDER BALL 0 .06 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 3937353331 2927252321 19171513 11 9 7 5 3 1 - .00 Al BALL / CORNER A 000000 000000 000000 I 000000 000000 000000 000000 000000 000000 I 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 I 000000 090960 I} - 096090 000000 000000 000000 000000 000000 000000 000000 I 000000 000000 000000 000000 000000 000000 I 000000 000000 000000 000000 000000 000000 I 000000 000000 000000 000000 000000 000000 I 000000 00000000000000000000m0000000000000000000 0 000000000000000000000000000000000000000 0000000 . . . . . . . 00 .00 00000000000000 % 000 0000000000000000000 00 00 00 00 0000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 J .00 Agere Systems Inc. 2 .28 0.21 000000000000000000000000000000000000000 0000000000000000000%0000000000000000000 0000000000000000000~0000000000000000000 000000000000000000000000000000000000000 0000000000000000000000000f0000000000000000000000000 0000000000000000000 0000000000000000000 000000 1 .00 000000 SEATING PLANE 0 .20 C G L R U D F H K M P T V - Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 0 .50 R, 3 PLACES 187 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 46 List of Acronyms A ADM AIS AIS-L API APLL AR AU Add/Drop Multiplexer Alarm Indication Signal Line Alarm Indication Signal Application Program Interface Analog Phase Locked Loop Alarm Register Administrative Unit (SDH naming for frames) B B1 , B2 , B3 BAR BCH BDI BDI-O BDI-P BEI BER BI BIM BIP BIP-8 BIST bit BLI BLSR Bits/s BS C2 CBR CDR CM CMEP CMF CML CMOH CMR CMS CMV CNTD COR CORBA COW CPT CPU 188 Hardware Design Guide July 2002 Error Count Bits Base Address Register Bose-Chaudhuri-Hocquenguem (weak FEC cyclic code) Backward Defect Indication Backward Defect Indication Overhead Backward Defect Indication Payload Backward Error Indication Bit Error Rate Backward Indication Byte Interleaved Multiplexer Bit Interleaved Parity Bit Interleaved Parity Level 8 Built-In Self-Test Binary Digit Backward Line Indication Bidirectional Line Switch Ring Bits Per Second Boundary Scan C Expected Payload Label Bit Constant Bit Rate Clock Data Recovery Common Mode or Configuration Management or Connection Monitoring Connection Monitoring End Point Common-Mode Failure Current-Mode Logic Connection Monitoring Overhead Common Mode Rejection Current-Mode Switching Common-Mode Voltage Continuous N-Times Detect Clear on Read Common Object Request Broker Architecture Clear on Write Cell Pointer Table Central Processing Unit CRC CV CV-L CV-P CV-S Cyclic Redundancy Check or Cyclic Redundancy Code Coding Violation Line Coding Violation Path Coding Violation Section Coding Violation D DCC DLL DPLL DRAM DSP DW DWAC DWDM DWSFEC Data Communications Channel Delay-Locked Loop Dedicated Phase-Locked Loop Dynamic Random Access Memory Digital Signal Processor Digital Wrapper Digital Wrapper Access Channel Dense Wavelength Division Multiplexing Digital Wrapper Enhanced Forward Error Correction E EFEC ES ESD ESF ESI EVT EXTEST ExTI Enhanced Forward Error Correction Errored Second or Elastic Store Electrostatic Discharge Extended Superframe End System Identifier Egress VC Table External Test Expected Trace Identifier F FAE FAS FCBGA FCS FDI FDI-O FDI-P FE FEBE FEC FIFO FM FPGA FS FSI FSM FTFL Field Application Engineer Frame Alignment Signal Flip-Chip Ball-Grid Array Frame Check Sequence Forward Defect Indication Forward Defect Indication Overhead Forward Defect Indication Payload Framing (bit) Error Far-End Block Error Forward Error Correction First In, First Out Frequency Modulation Field Programmable Gate Array Fixed Stuff FEC Status Indicator Finite State Machine Fault Type and Fault Location Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Hardware Design Guide July 2002 46 with Strong/Weak FEC and Digital Wrapper List of Acronyms (continued) L G GbE GND GPI GPIO GPO GRST GSR Gigabit Ethernet Ground General Purpose Input General Purpose Input/Output General Purpose Output Global Reset Global Set/Reset H H1, H2 HDLC HEC HSI HW SONET Signal Payload Pointer Bits High-Level Data Link Control Header Error Correction or Header Error Control High-Speed Interface Hardware I I/O IaDl IAE IDI IrDl IRQ ISR ITU Input/Output Intra-Domain Interface Incoming Alignment Error Initial Domain Identifier Inter-Domain Interface Interrupt Request Interrupt Status Register International Telecommunications Union J J1 JEDEC JC JTAG Trace Byte Joint Electronic Devices Engineering Council Stuff Control Byte Joint Test Access Group IaDl LAN LAPI LB LCK LED LOC LOF LOFA LOH LOL LOM LOP LOS LOTC IrDl LSB LSN LTE LV LVDS Intradomain Interface Local Area Network Low-Level Application Programming Interface Loopback Locked Light Emitting Diode Loss of Clock Loss of Frame Loss of Frame Alignment Line Overhead Loss of Lock Loss of Multiframe Alignment Loss of Pointer Loss of Signal Loss of Transmit Clock Interdomain Interface Least Significant Bit/Byte Least Significant Nibble Line Terminating Equipment Low Voltage Low-Voltage Differential Signal WAS MPI MPIF MS MSB MSI MSN MUTEX MUX Multiframe Alignment Signal Microprocessor Interface Master Processor Interface Multiplex Section Most Significant Bit/Byte Multiplex Structure Identifier Most Significant Nibble Mutual Exclusion Multiplex or Multiplexor K K1, K2 APS Bits of SONET Signal Agere Systems Inc. N NJO Negative Justification Offset (Negative Justification Byte) NRZ Nonreturn to Zero NSA Non-Service Affecting N-Time Detect A received value remains the same for N consecutive frames . 189 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper 46 Hardware Design Guide July 2002 List of Acronyms (continued) Q OA&M OCh OCI ODUk OH OHP OHPI OHPM OMSn OMS OMU ONNI OOA OOF OOM OOS OPU OSC OSI OTH OTM OTM-0 OTN OTS OTSn OTUk Operations Administration and Maintenance Optical Channel (single) Open Connection Indication Optical Channel Data Unit Overhead Overhead Processor Overhead Processor Insertion Overhead Processor Monitoring Optical Multiplex Section Overhead Optical Multiplexing Section Optical Multiplexing Unit Optical Transport Network Node Interface Out of Alignment Out of Frame Out of Multiframe Alignment Optical Transport Module Overhead Signal Optical Channel Payload Unit Optical Supervisory Channel Open System Interconnect Optical Transport Hierarchy Optical Transport Module Optical Transport Module of Order 0 Optical Transport Network Optical Transmission Section Optical Transmission Section Overhead Optical Channel Transport Unit PPLL PRAM PRBS PSI Programmable Phase-Locked Loop Pointer Random Access Memory Pseudo-Random Bit Sequence Payload Structure Identifier QoS Quality of Service R/W RAI RDI RDI-L REI REI-L RES RN RO RS RW Rx RZ Read/Write Remote Alarm Indication Remote Defect Indicator Line Remote Defect Indication Remote Error Indication Line Remote Error Indication Reserved Random Number Read Only Reed Solomon (strong FEC) Read/Write Receive Return to Zero P PA PBGA PBGAM PCLK PD PDI PHY PJO PLL PM PMCLK PMOH PN PNZ POAC POH POS P-P PP 190 Persistency Alarm Plastic Ball Grid Array Plastic Ball Grid Array Multilayer Microprocessor Clock Phase Detector Payload Defect Indication Physical Layer Positive Justification Offset Byte Phase-Locked Loop Performance Monitoring Performance Monitoring Clock Path Monitoring Overhead Pseudo-Random Noise Sequence or Pseudo-Random Number (i.e., PN29) Positive/Negative/Zero Path Overhead Access Channel Path Overhead Packet-Over-SONET/SDH Peak to Peak Pointer Processor Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Hardware Design Guide July 2002 46 List of Acronyms (continued) S SA SCLK SD SDH SEF SERDES SF SFI SFI-4 SM SNMP SNR SOH SONET SONFEC SPA SPE SPIF STAT STE SWI Service Affecting System Clock Signal Degrade Synchronous Digital Hierarchy Severely Errored Frame Serializer/Deserializer Signal Fail SERDES Framer Interface SERDES Framer Interface Level 4 Section Monitoring Simple Network Management Protocol Signal-to-Noise Ratio Section Overhead Synchronous Optical Network SONET Forward Error Correction Selected Packet Available SONET Payload Envelope Slave Processor Interface Status Indication Section Terminating Equipment Software Interrupt T TA TA TBD TC Tc TCK TCM TCMOH TDI TDM TDMX TDO TEA TFEC TIM Tj TMS TOAC TOH Tprop TRSTN TS TSI TSM with Strong/Weak FEC and Digital Wrapper Transfer Acknowledge Ambient Temperature To Be Determined Temperature Coefficient or Time Constant or Tandem Connection Case Temperature Test Clock Tandem Connection Monitoring Tandem Connection Monitoring Overhead Test Data In Time Division Multiplexer Transpose DeMultiplexer Test Data Out Transfer Error Acknowledge Transmission Forward Error Correcting Trace Identifier Mismatch Junction Temperature Test Mode Select Transport Overhead Access Channel Transport Overhead Propagation Time Test Reset (Active Low) Time Slot or Tributary Slot Time-Slot Interchange Tributary Slot Multiplexing Agere Systems Inc. TTI Tx Trail Trace Identifier Transmit V UNEQ UNI UPSR UTOPIA Unequipped User-Network Interface Unidirectional Path Switch Ring Universal Test and Operations Physical Interface for ATM VBR VC VCI VCO VP VPI VT VTG V Variable Bit Rate Virtual Channel Virtual Connection Indicator Voltage-Controlled Oscillator Virtual Path Virtual Path Indicator Virtual Tributary Virtual Tributary Group W1C WDM WRR Write One Clear Wavelength Division Multiplexing Weighted Round Robin XPIF External Processor Interface zo Section Overhead Bit 191 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 List of Objects Object Page A ADDRESS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .169, 170 AIS_CONDINSERT _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .68 ALGN_INH .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .131 APS BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 B BCH_ALARM_S0 . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_CLR_LIMIT-10 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_CLR_LIMIT-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_CLR_LIMIT-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_CLR_LIMIT-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_CLR_LIMIT-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_CLR_LIMIT-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_CLR_LIMIT_9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_10 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_3 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_4 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_5 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_6 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_7 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_8 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_UNIT_9 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_10 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_3 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_4 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_5 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_6 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_7 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_8 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_DT_VAL_9 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_REPORT . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_SET_LIMIT-3 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_SET_LIMIT-4 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_SET_LIMIT-5 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_SET_LIMIT-6 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_SET_LIMIT-7 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_SET_LIMIT-8 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BER_SET_LIMIT _9 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERCLR10 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERCLR4 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERCLR5 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERCLR6 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERCLR7 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERCLR8 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERCLR9 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT10 . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT3 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT4 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT5 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT6 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT7 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT8 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERDT9 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERSET3 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERSET4 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERSET5 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERSET6 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_BERSET7 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH BERSET8 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 192 Object Page BCH BERSET9 . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 127 BCH_DEC_EXTRACT . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 BCH_DEC_FSI . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH_DEC_FSI_A . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH_DEC_FSI_M . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH_DEC_FSI_P . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH_DEC_MODE . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 125 BCH_ENC_INSERT . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 122 BCH_ENC_MODE . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 122 BCH_ERR_BITBLK . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BCH_ERR_BITCNT_L . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BCH_ERR_BITCNT_L_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BCH_ERR_BITCNT_U .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BCH_ERR_BITCNT_U_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BCH_ERR_BLKCNT_L_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BCH ERR BLKCNT_USO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BCH ERR PROV SO . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 126, 127 BCH_ERR_RPT _SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 127 BCH_MASK_SO . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 127 BCH_PERSIST_SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_PROV_SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 BCH_RX_ALARM_SO . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH_RX_BER_SD . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 127 BCH_RX_BER_SD_DET . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_RX_BER_SD_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 127 BCH_RX_BER_SD_DET_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_RX_BER_SD _DET_ P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 127 BCH_RX_BER_SF . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_RX_BER_SF_DET . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 127 BCH_RX_BER_SF_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_RX_BER_SF_DET_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_RX_BER_SF_DET_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 BCH_RX_MASK_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH_RX_PERSIST_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH RX_STATE_SO . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 BCH RXPROV SO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 125 BCH_STATE_SO . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 127 BCH_TX_ALARM_SO . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TX_MASK_SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 123 BCH_TX_PERSIST_SO . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TX_STATE_SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 123 BCH_TXERR_COL . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TXERR_FINISH . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TXERR_FINISH_A . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 BCH_TXERR_FINISH_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 123 BCH_TXERR_FINISH_P . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 BCH_TXERR_MASK_L . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 BCH_TXERR_MASK_U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TXERR_MASKL_SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 BCH_TXERR_MASKU_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TXERR_REPEAT . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 BCH_TXERR_REPEAT_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 123 BCH_TXERR_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 123 BCH_TXERR_ROWCOL _SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TXERR_SKIP . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TXERR_SKIP-SO . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 BCH_TXERR_START . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 BCH_TXERR_START_SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 BCH_UNC_BLKCNT_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 126 BCH_UNC_BLKCNT_U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 BDI Tx . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 46 BDI TxL . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 46,47 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 with Strong/Weak FEC and Digital Wrapper List of Objects (continued) Object BEI RxL BEI TxL BIP RxL BIP TxL BYPASS Page . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .48, 49, 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 46,47 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 48, 49, 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 46,47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 131 C CS- N . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 169,170 D DATA . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 169,170 DESCRM DIS . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 132 DEV CTL CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 170,180 DEV_CTL_CLKMUXO . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 180 DEV_CTL_CLKMUX1 . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 180 DEV_CTL_CLKMUX2 . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 180 DEV_CTL_CLKMUX3 . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 180 DEV_CTL_CLKMUX4 . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 180 DEV_CTL_DMUX . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .182 DEV_CTL_LPBK_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 33 DEV_CTL_RX_PH DET_SO . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 34 DEV_CTL_TX_PHDET_SO . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 34 DEV_DP_SWRST_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 32 DEV_DWFEC_DAT_SWRST . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .32 DEV DWFEC MPU SWRST . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 32 DEV DWFEC PCLK PDN . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 33,170 DEV_DWFEC_RX_LOC_INH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .36 DEV_DWFEC_RX_LOF_INH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .36 DEV_DWFEC_RX_LOS_INH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .36 DEV_DWFEC_RX_OOF_INH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 36 DEV_DWFEC_TX_LOC_INH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .36 DEV_DWFEC_TX_LOF_INH . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .36 DEV_DWFEC_TX_LOS_INH . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 36 DEV_DWFEC_TXOOF_INH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .36 DEV_GPI_AO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_Al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_ALARM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .174 DEV_GPI_ALARMO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_ALARM 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_ALARM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_CFGO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_CFG1 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_CFG2 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_POLO . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_POL1 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_POL2 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_TYPO . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_TYP1 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_TYP2 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_TYP3 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INT_TYP4 . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_INTTYP5 _ . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 177 DEV_GPI_MO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_M 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 178 DEV_GPI_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 DEV GPI MASKO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .178 Agere Systems Inc. Object Page DEV GPI MASK1 . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV GPI MASK2 . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEVGPI P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV GPI P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI_P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI_PERSIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 DEV_GPI_PERSISTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI_PERSIST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI_PERSIST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI_STATE . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .174 DEV_GPI_STATEO . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI_STATE1 . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI_STATE2 . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPIO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPI1 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV-GPI2 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPIO_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 DEV_GPIO_DIRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_GPIO_DIR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_GPIO_DIR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_GPO_SEL . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .174 DEV_GPO_SELO . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_GPO_SEL1 . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_GPO_SEL2 . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPO_SEL3 . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .178 DEV_GPO_VAL . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .174 DEV_GPO_VALO . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_GPO_VAL1 . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_GPO_VAL2 . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .177 DEV_HOLD . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 DEV_IDO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 DEV_ID1 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 DEV_ID2 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 DEV_ID3 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 DEV_ID4 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 DEV LOC ALARM_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..31 DEV LOC LINE RXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31, 36, 44 DEV_LOC_LINE_RXCLK_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DEV LOC LINE RXCLK_P . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .31 DEV LOC LINE TXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .31, 36, 44 DEV_LOC_LINE_TXCLK_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..31 DEV_LOC_LINE_TXCLK _P . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .31 DEV_LOC_MASK_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..31 DEV_LOC_PERSIST_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..31 DEV LOC STATE_SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..31 DEV LOC SYS RXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31, 36 DEV_LOC_SYS_RXCLK_M . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DEV LOC SYS RXCLK_P . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DEV LOC SYS TXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .31, 36 DEV_LOC_SYS_TXCLK_M . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .31 DEV_LOC_SYS_TXCLK _P . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..31 DEV_LTIM_REF_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DEV_LTIM_REF_SEL_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DEV MPU_REG_SWRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..32 DEV MPUREG SWRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .32, 173 DEV_PDN_CLKIN_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DEV PDN_DWACOSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DEV PDN_ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33, 170 DEV_PDN_IN_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DEV_PDN_OUT_SO . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..33 DEV PDN TOACO SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 193 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 List of Objects (continued) Object Page DEV_PHDET_RX_POL . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_RX_REFDIV . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_RX_REFSEL . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_RX_VARDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_RX_VARSEL . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_TX_POL . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_TX_REFDIV . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_TX_REFSEL . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_TX_VARDIV . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PHDET_TX_VARSEL . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .34 DEV_PM_TRIG _SWRST . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_PMCLK_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_PMCLK_ALARM . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_PMCLK_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .173 DEV_PMCLK_IOCTL . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_PMCLK_M . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_PMCLK_MASK . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_PMCLK_PRELD . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_PMMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 DEV_RCLKLI_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. .33 DEV_RCLKSI_PDN . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RCLKSO_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RDLI_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RDSO_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .33 DEV_RDW_CS_PDN . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RDW_DATO_PDN . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RDW2TDW_LB . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RSYS2TSYS_LB . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RTOAC_CS_PDN . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RTOAC_DAT_PDN . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_RX_ALRMSTAT_INH_SO . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SCRATCH . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .168 DEV_SONFEC_DAT_SWRST . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .32 DEV_SONFEC MPU SWRST . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .32 DEV SONFEC PCLK PDN . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .33, 170 DEV_SONFEC_RX_LOC_INH . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SONFEC_RX_LOF_INH . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SONFEC_RX_LOS_INH . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SONFEC_RX_OOF_INH . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SONFEC_TX_LOC_INH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SONFEC_TX_LOF_INH . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SONFEC_TX_LOS_INH . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_SONFEC_TX_OOF_INH . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 DEV_TCLKLI_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .33 DEV_TCLKLO_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .33 DEV_TCLKSI_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .33 DEV_TDLO_PDN . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_TDSI_PDN . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_TDW_CS_PDN . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_TDW2RDW_LB . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_TFRMLI_PDN . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_TLINE2RLINE_LB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_TRSEN2RRSDE_LB . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .33 DEV_TTOAC_PDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. .33 DEV_TX_ALRMSTATINHSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 36 DEV_VER . . . .. . . . . . . . . . . . ._. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 DS N . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 DW ALARM SO . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .73, 75, 95, 96, 98, 100, 102 DW ALARM V2 SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71, 81, 99, 103, 105 DW_DWAC_RX_CTL_SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .106 DW_DWAC_RX_CTL_V2_SO . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .106 DW DWAC TX CTL SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .80 194 Object Page DW ES RXDATA . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61,94 DW ES_RXSYNC . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DW MASK SO . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 73, 75, 95, 96, 98, 100, 102 DW MASK-V2-SO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 81, 99, 103, 105 DW PERSIST 2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70, 73, 75, 98, 100, 102 DW PERSIST V2 SO . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 81, 99, 103, 105 DW PRBS ALARM-SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DW PRBS CTL SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80,110 DW PRBSCTLV2 SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81,111 DW_PRBS_MASK_S0 . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DW_PRBS_PERSIST-SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 110 DW_PRBS_STATE -SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DW_RS_TXDATA . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 DW_RX_BEI2_BIT_BLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DW RX BEI2_DISABLE . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 104 DW RX_Bill STAT . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49,103 DW RX_Bill STAT NEW A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49,103 DW_RX_Bill _STAT_NEW_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DW RX Bill STAT_NEW_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DW RX_BI12 STAT . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50,105 DW RX_BI12STAT NEW A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50,105 DW_RX_BI12_STAT_NEW_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DW_RX_BI12_STAT_NEWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DW_RX_BIP2_BIT_BLK . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 104 DW_RX_BIP2_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 104 DW_RX_CNT_BEI00 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BEI00SO _ . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 98 DW_RX_CNT_BE101 . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BE101_SO . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 98 DW_RX_CNT_BEI10 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BEI10_SO . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 100 DW_RX_CNT_BEI11 . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BEI11_SO . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 100 DW RX CNT BEI20_V2 SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DW RX_CNT BEI21_V2 SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 DW_RX_CN_BIP00 T . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BIP00_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 DW-RX-CNT-BIP01 . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BIP01_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 DW-RX-CNT-BIP10 . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BIP10_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DW_RX_CNT_BIPl 1 . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DW_RX_CNT_BIP11_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DW_RX_CNT_BIP20_V2_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DW_RX_CNT_BIP21_V2 _SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DW_RX_CNT_PRBS . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 DW RX CNT_PRBS_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DW RX_CTL AIS 2 SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 102,103 DW RX_CTL AISV2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 108,109 DW RX CTL AISBYTE_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 102 DW RX_CTL BII SO . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 98,100 DW RX CTL B112 V2 2_S0 . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 104 DW RX_CTL BIICNTD SO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98,100 DWRX_CTL BIP SO . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97,99 DW RX CTL CNTD V2_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DW RX_CTL OH V2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 103, 108, 109 DW RX CTL OHO_2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .95 DW RX_CTL OH1_2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .95 DW RX_CTL OH2 2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .96 DW RX CTL OH3 2_SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .96 DW RX_CTL TOP SO . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 95, 97, 98, 99, 100, 108 DW RX_CTL V2 SO . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 99, 104, 108, 111 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 with Strong/Weak FEC and Digital Wrapper List of Objects (continued) Object Page DW RX_MON V2 S0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .103, 105 DW_RX_NO_FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 111 DW RX VAL OH01 SO . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .95 DW RX_VAL OH23 SO . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .95, 96 DWRXAIS APSINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .49, 50, 109 DW RXAISCLRCNTD . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .49, 103 DW RXAIS COND . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .47, 66, 76, 107 DW RXAISDET . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .49, 50, 102, 103, 107 DWRXAIS DET A . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 102 DW RXAISDET M . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 102 DW RXAIS DET_P . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 102 DW RXAIS DETINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .49, 107, 108 DW RXAISFRM . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 49,103 DW RXAIS FTFLINH . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .49, 50, 77, 108 DWRXAISGCCINH . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .49, 50, 77, 109 DW RXAIS_INS . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .49, 107, 108 DW RXAIS ROW . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .49, 103 DWRXAISSETCNTD . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 49,102 DW RXAIS TCMINH . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .49, 50, 109 DW RXAISTCMSTAT_ IAEINH . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 109 DW RXBDI0 CNTD . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .48, 98 DW RXBDI0 DET .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .48, 98 DW RXBDI0 DET A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 98 DWRXBDI0DET M . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .98 DW RXBDI0 DET P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 98 DW RXBDI1 CNTD . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .49, 100 DWRXBDI1 DET .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .49, 100 DW RXBDI1 DET A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 100 DW_RXBDI1_DET_M . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 100 DW RXBDI1 DET_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 100 DW RXBDI2 CNTD . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 50,105 DW RXBDI2 DET .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .50, 105 DWRXBDI2DET A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 105 DW_RXBDI2-DET-M . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 105 DW_RXBDI2-DET-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 105 DW_RXBEI0_BIT_BLK . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .98 DW_RXBEI0_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .98 DW RXBE100_ECNT . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 98 DW RXBE101_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .48, 98 DW RXBEI1 BIT BLK . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 100 DW_RXBEI1_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 100 DW RXBE110_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 100 DW RXBE111_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .49, 100 DW RXBE120_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 104 DW RXBE121_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 50,104 DW_RXBI10_FRM . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 98 DW_RXBI10_ROW .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .98 DW_RXBII1_FRM . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 100 DW RXBII1_ROW .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 100 DW RXB111-STAT CNTD . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .49, 103 DW_RXB112-FRM . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 104 DW RXB112 ROW .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 104 DW RXB112 STAT CNTD . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 50,105 DW_RXBIP0_BIT_BLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 97 DW_RXBIP0_DISABLE . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .97 DW_RXBIP0_FRM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 97 DW_RXBIP0_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 97 DW RXBIP00_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 97 DW RXBIP01_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .48, 97 DW_RXBIP1_BIT_BLK . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .99 DW RXBIP1 DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .99 Agere Systems Inc. Object Page DW RXBIP1 FRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 DW_RXBIP1_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..99 DW RXBIP10-ECNT . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..99 DW RXBIP11_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 99 DW RXBIP2 FRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 DW RXBIP2 ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 DW RXBIP20 ECNT . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .104 DW RXBIP21 ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50, 104 DW RXFIX COND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 66, 76, 107 DW RXFIX DET . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .49, 50, 102, 103, 107 DW RXFIX DET A . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 DW RXFIX DET M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 DW RXFIX DET P . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 DW RXFIX DETINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107, 108 DW RXFIX INS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107, 108 DW RXFIX VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 102, 107 DW RXIAEO CNTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48, 99 DW RXIAEO DET . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 48, 99 DW RXIAEO DET A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 DW RXIAEO DET M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 DW RXIAEO DET P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 DW RXLCK FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 DW RXLOCAISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 107, 108 DW RXLOF AISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 107, 108 DW RXLOSAISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 107, 108 DW RXOA12 MFAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48, 108 DW RXOCI COND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 66, 76, 107 DW RXOCI DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 49, 50, 102, 103, 107 DW_RXOCI_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 DW RXOCI DET M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 DW RXOCI DET P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 DW RXOCI DETINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 107, 108 DW RXOCI_INS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 107, 108 DW_RXOHO_CNTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW_RXOHO_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 DW_RXOHO_DET_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW_RXOHO_FRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOHO ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOH0 VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOH0123 GRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48, 49, 50, 94, 95 DW_RXOH1_CNTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 DW RXOH1_DET A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOH1_DET M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOH1_FRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 DW RXOH1_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW_RXOH1_VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW_RXOH2_CNTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 DW_RXOH2_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOH2 DET_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOH2 FRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 DW_RXOH2_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..96 DW RXOH2 VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..95 DW RXOH3 CNTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 DW_RXOH3_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..96 DW_RXOH3_DET_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..96 DW_RXOH3_FRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 DW_RXOH3_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..96 DW RXOH3 VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..96 DW RXOOF AISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 107, 108 DW_RXPRBS_29_31_PAT . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .110 DW RXPRBS ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 195 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 List of Objects (continued) Object Page DW_RXPRBS_INS . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .111 DW_RXPRBS_INS_1 BERRINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .111 DW_RXPRBS_INS_29_31PAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 DW_RXPRBS_INS_INV . . ._ . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .111 DW_RXPRBS_INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 DW_RXPRBS_SYNC . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .110 DW_RXPRBS_SYNC_A . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .110 DW_RXPRBS_SYNC_M . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .110 DW_RXPRBS_SYNC_P . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .110 DW_RXPRBSDATA . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .110 DW_RXPRBSDATA_EN . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .110 DW RXSD AISINH . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .49, 107, 108 DW RXSF AISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .49, 107, 108 DW STATE 2 SO . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .70, 73, 75, 98, 100, 102 DWSTATE V2 SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 81, 99, 105 DW_TX_CBPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .82 DW_TX_CNT_PRBS_V2_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 81 DW_TX_CTL_AIS_2_SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 78 DW_TX_CTL_AIS_V2_SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 78 DW_TX_CTL_BDIOINH_2_SO . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 70 DW_TX_CTL_BDIl INH_V2_SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 73 DW TX CTL BDI2INHV2SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .75 DW TX CTL BII SO . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 69, 72 DWTXCTLBIIV2_SO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .74 DW TX CTL BIP SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .69, 72 DW_TX CTL BIP_V2_SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .74 DW TX CTL OA12 PAT SO . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .62, 78 DW_TX_CTL_OA12-SO . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 62 DW_TX_CTL_OHO_2_SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 64 DW_TX_CTL_OH1_2_SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 64 DW_TX_CTL_OH2_2_SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 64 DW TX CTL OH3 2 SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .64 DW TX CTL TOP 2 SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .61, 62, 64, 78, 80, 82 DW TX CTL TOP V2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .62, 71, 74, 76, 78, 82 DW_TX_ES_FRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. .61 DW_TX_NO_FS . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .82 DW TX_PASSTHRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .61 DW TXAIS APSINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .47, 77, 78 DWTXAISFTFLINH . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .47, 78 DW TXAIS GCCINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .47, 78 DW TXAIS_INS . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .47, 78 DWTXAIS TCMINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .47, 77, 78 DW TXAISTCMSTAT_IAEINH . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .68, 78 DW_TXAIS_TCMSTAT_IAEINHO . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . .. .44 DW TXBDI AISINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW TXBDI DET . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 66,106 DW_TXBDI_FIXINH . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW_TXBDI_INS . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW_TXBDI_LOCINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW_TXBDI_LOFINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. .66 DW_TXBDI_LOSINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW_TXBDI_OCIINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .66 DW_TXBDI_OOFINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW_TXBDI_SDINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW_TXBDI_SFINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .66 DW_TXBDI_TIMERINH . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .66 DW TXBDIO AISINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .70 DW TXBDIO DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .46, 48, 67, 70 DW_TXBDIO_DET_A . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .70 DW_TXBDIO_DET_M . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .70 DW_TXBDIO_DET_P . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .70 DW TXBDIO FIXINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .70 196 Object Page DW TXBDIO_INH . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67,70 DW TXBDIO_INS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66, 67, 70 DW_TXBDIO_LOCINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 70 DW_TXBDIO_LOFINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .70 DW_TXBDIO_LOSINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 70 DW_TXBDIO_OCIINH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DW_TXBDIO_OOFINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 DW_TXBDIO_SDINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 DW_TXBDIO_SFINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DW_TXBDIO_TIMERINH . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .70 DW TXBDI1_AISINH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DW TXBDI1_DET . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 49, 73 DW TXBDIl DET A . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 73 DW TXBDIl DET M . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .73 DWTXBDIl DET P . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 73 DW_TXBDI1_FIXINH . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DW TXBDI1_INH . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DW TXBDI1_INS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66,73 DW_TXBDI1_LOCINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 73 DW_TXBDI1_LOFINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .73 DW_TXBDI1_LOSINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 73 DW TXBDI1_OCIINH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DW TXBDI1_OOFINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DWTXBDI1_SDINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DW TXBDI1_SFINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DW TXBDIl TIMERINH . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .73 DW TXBDI2 AISINH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 DW TXBDI2 DET . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 50, 75 DW-TXBDI2-DET-A . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 75 DW-TXBDI2-DET-M . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .75 DW-TXBDI2-DET-P . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 75 DW TXBDI2-FIXINH . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DW TXBDI2-INH . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 DW TXBDI2-INS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66,75 DW_TXBDI2-LOCINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 75 DW_TXBDI2-LOFINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .75 DW TXBDI2 LOSINH . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 75 DW TXBDI2 OCIINH . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DWTXBDI2OOFINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 DW TXBDI2 SDINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 DW TXBDI2 SFINH . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DWTXBDI2TIMERINH . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .75 DW TXBEIO ERRINS . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DW_TXBEIO_INS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 DW TXBEI1_ERRINS . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DW TXBEI1_INS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 DW_TXBEI2_ERRINS . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DW_TXBEI2_INS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 DW_TXBI10_FRM . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 DW_TXBI10_ROW . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 DW_TXB111_FRM . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .72 DW TXB111_ROW . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 DW TXB111_STAT_INS . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . 47,74 DW_TXB112_FRM . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .74 DW TXB112 ROW . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 DW TXB112 STAT_INS . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . 47,76 DWTXBIPO ERRINS . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DW TXBIPO FRM . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DW TXBIPO INS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 68,69 DW_TXBIPO_ROW . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DW_TXBIP1_ERRINS . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DW TXBIP1 FRM . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 with Strong/Weak FEC and Digital Wrapper List of Objects (continued) Object Page DW_TXBIP1_INS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 72 DW_TXBIP1_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .72 DW_TXBIP2_ERRINS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .74 DW_TXBIP2_FRM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .74 DW_TXBIP2_INS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 74 DW_TXBIP2_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .74 DW TXDEFAULT . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .62 DW TXFIX INS . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .47, 78 DWTXFIXVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .47, 78 DW_TXIAE_DET . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 67 DW_TXIAE_INS . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 67 DW_TXIAE_LOFINH . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 67 DW TXIAE OOFINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .67 DW TXIAEO DET . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 48, 68, 71 DW_TXIAEO_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .71 DW_TXIAEO_DET_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 DW TXIAEO DET_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .71 DW TXIAEO INH .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .46, 67, 71 DW TXIAEO INS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 46, 71 DW TXIAEO LOFINH . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .46, 71 DWTXIAEOOOFINH . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 46, 71 DW TXLCK FIX . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .47, 78 DW TXLOCAISINH . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .47, 76, 78 DWTXLOF AISINH . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .47, 76, 78 DW TXLOSAISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .47, 76, 78 DW TXMFAS INS .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .46, 62 DWTXMFA_SYNC S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 62 DW TXOA1 VAL . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 46,62 DW TXOA12 INS .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .46, 62 DWTXOA12WAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .46, 47, 77, 78 DW TXOA12 PAIR . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 77 DW TXOA12 PAIRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .46, 62 DWTXOA2 VAL . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 46,62 DW TXOCI_INS . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .47, 78 DW_TXOHO_FRM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOHO_INS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOHO_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOHO_VAL . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH1_FRM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH1_INS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH1_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH1_VAL . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH2_FRM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH2_INS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH2_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH2_VAL . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH3_FRM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH3_INS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW_TXOH3_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW TXOH3 VAL . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .64 DW TXOOF AISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .47, 76, 78 DW_TXPRBS_1 BERRINS . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 80 DW_TXPRBS-29-31-PAT . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 80 DW_TXPRBS_ECNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 81 DW_TXPRBS_INS .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 80 DW_TXPRBS_INV .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 80 DW_TXPRBS_MON_29_31PAT . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .81 DW_TXPRBS_MON_INV . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 81 DW_TXPRBS_SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 DW_TXPRBS_SYNC_A . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .81 DW TXPRBS SYNC M . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 81 Agere Systems Inc. Object Page DW TXPRBS_SYNC_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 DW TXRXCOND AISINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 76, 78 DWTXRXCONDFIXINH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 76, 78 DW TXRXCOND OCIINH . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .47, 76, 78 DWAC DW_TXDATA_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 DWAC RXBDIO OVWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .48, 106 DWAC RXBD11 OVWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .49, 106 DWAC RXBD12 OVWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .50, 106 DWAC RXBE10 OVWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48, 106 DWAC RXBE11 OVWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 106 DWAC RXBE12 OVWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50, 106 DWAC RXIAEO OVWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48, 106 DWACTXINS . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .80 DWFEC MODEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DWFEC_MODE1_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DWFEC_MUX_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 DWFEC_RST_MON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..32 DWFEC RX_10G 2G5 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .40, 41 DWFEC RX_16 64 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .40, 41 DWFEC RX_FEC DW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 41 DWFEC RX_RST MON SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 DWFEC RX_RST MON Sl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 DWFEC RX_RST MON S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 DWFEC RX_RST MONS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 DWFEC RX78CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..30 DWFEC RX83DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DWFEC RXDATAO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DWFEC SYS RX83DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .94 DWFECTX_10G 2G5 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .40, 41 DWFEC TX_16 64 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .40, 41 DWFECTX DMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DWFEC TX FEC DW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 41 DWFECTXRSTMON SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..32 DWFECTX RST MON Sl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..32 DWFEC_TX_RST_MON_S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..32 DWFEC_TX_RST_MON_S3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..32 DWFEC_TX78CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..30 DWFEC_TXDATAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..30 DWFEC TXDATAO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..30 E ES ALARM SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54, 112 ESCTL SO . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .54, 112 ES DW_TXDATA . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..61 ES MASK SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54, 112 ESRX_OVERFLW A . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .44, 112 ES_RX_OVERFLW_M . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .112 ES RX RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 ES RX_UNDRFLW A . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 112 ESRX_UNDRFLW_M . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 ES TX OVERFLW A . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 54 ES_TX_OVERFLW_M . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ES TX RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ES TX UNDRFLW A . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 54 ESTX UNDRFLW M . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 F FIFO MAX . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .131 197 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 List of Objects (continued) Object Page FIFO-MIN . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .131 FRM ALARM SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55, 59, 60, 86, 87, 88 FRM_DIS . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .56 FRM_DW_RX_LOF . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .107 FRM_DW_RX_OOF . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .107 FRM_DW_RXLOS . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .107 FRM_DW_TXDATA . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .61 FRM_DW_TXLOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .76 FRM_DW_TXLOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .76 FRM DW_TXOOF . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .76 FRM MASK SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55, 59, 60, 86, 87, 88 FRM PERSIST SO . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .55, 59, 60, 86, 87, 88 FRM RX_CTL LOF 2 SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .60, 88 FRM_RX_CTL_LOSDET_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 86 FRM_RX_CTL_OA12-PAT3SO . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 87 FRM_RX_CTL_OA12_SO . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 87 FRM_RX_CTL_OOF3SO _ . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 87 FRM RX_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM RXLOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 44, 66, 67, 88, 108 FRM_RXLOF_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .88 FRM_RXLOF_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .88 FRM_RXLOF_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .88 FRM_RXLOF_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .88 FRM RXLOF_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 88 FRM RXLOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36, 44, 66, 86, 108 FRM_RXLOS_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .86 FRM_RXLOS_DET . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .86 FRM_RXLOS_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .86 FRM_RXLOS_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .86 FRM_RXOA1_VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM_RXOA12_PAIRCLR . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM_RXOA12_PAIRS . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM_RXOA12_PAIRSET . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM RXOA2_VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 87 FRM RXOOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36, 44, 66, 67, 87, 108 FRM_RXOOF_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM_RXOOF_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. .87 FRM_RXOOF_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM_RXOOF_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM RXOOF_SET . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .87 FRM STATE SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55, 59, 60, 86, 87, 88 FRM_TX_CTL_LOSDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .55 FRM_TX_CTL_LOSDET_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 55 FRM_TX_CTL_OA12-PAT3SO . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 59 FRM_TX_CTL_OA12-SO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 59 FRM_TX_CTL_OOF_3_SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 59 FRM TX DISABLE . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .59 FRM TXLOF . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .36, 44, 60, 78 FRM_TXLOF_A . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 60 FRM_TXLOF_CLR . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .60 FRM_TXLOF_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .60 FRM_TXLOF_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .60 FRM TXLOF_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .60 FRM TXLOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36, 44, 55, 78 FRM_TXLOS_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .55 FRM_TXLOS_DET . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .55 FRM_TXLOS_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .55 FRM_TXLOS_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .55 FRM_TXOA1_VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .59 FRM_TXOA12-PAIRCLR . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .59 FRM_TXOA12-PAIRS . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .59 FRM TXOA12 PAIRSET . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .59 198 Object Page FRM TXOA2_VAL . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .59 FRM TXOOF . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 44, 59, 78 FRM_TXOOF_A . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 FRM_TXOOF_CLR . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 FRM_TXOOF_M . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 FRM_TXOOF_P . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 FRM TXOOF SET . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 59 G GLBL RESYNC . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 131 INTH N . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169,170 INTL N . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 169,170 L LINE_RX_DWFEC_CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LINE RX83CLK . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 30 LINE RX83LOC . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 66, 107, 108 LINE_RXDATAI . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 30 LINE_TX_DMUX . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 30 LINE_TX_DWFEC_CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LINE_TX_HS_CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .30 LINE_TX_HSCLK . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 LINE_TX_LS_CLKMUX . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LINE_TX_LSCLK . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LINE-TX83CLK . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .30 LINE TX83LOC . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76,78 LINE TXDATAO . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .30 M MPDB 8 16 . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 20, 167, 171 MPMODE AS . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 167,168 MPPAREN . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 171 MPTYPE_IM . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 167, 168 MPU DW FRM OA1 VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 56 MPU_DW_FRM_OA12_PAIRCLR . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 56 MPU_DW_FRM_OA12_PAIRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 MPU_DW_FRM_OA12_PAIRSET . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 56 MPU_DW_FRM_OA2_VAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 56 MPU_DW_FRM_OOF_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 MPU_DW_FRM_OOF_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 MPU_DW_R2T_LB . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MPU SONFEC TX 10G 2G5 . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 131 O OH ALARM RxL . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48, 49, 50 OH RxL . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48, 49, 50 OH TxL . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46,47 OHP_RX_AIS_RDI . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 OHP_RX_AISD_DIS . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 OHP_RX_B1CAL_DIS . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 166 OHP_RX_B1 CORRUPT_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 OHP_RX_B1MON_DIS . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..132 OHP_RX_B2CAL_DIS . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 OHP RX B2CORRUPT SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 with Strong/Weak FEC and Digital Wrapper List of Objects (continued) Object Page OHP_RX_CVS_PM . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 OHP_RX_CVS_PM_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .132 OHP RX DESCR_DIS . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 132 OHP RX_F1S1BYTE SO . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 144,147 OHP RX_F1S1DET SO . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 144,147 OHP_RX_FRM_DIS. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 OHP_RX_JOEXPO_SO . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 142 OHP_RX_JOEXP31_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .142 OHP_RX_JOSUSO_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .142 OHP_RX_JOSUS31_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .142 OHP_RX_K1 K2BYTESO _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 OHP RX LOS SO .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .130 OHP RX_MAINT SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .138, 139, 142 OHP RX_NSA 0 ALARM SO . . . . . . . . .. . . . . . . . . . . . . . . . . . . 130, 142, 146, 163 OHP RX_NSA0MASK SO . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 130, 142, 146, 163 OHP RX_NSA 0 PERSIST SO . . . . . .. . . . . . . . . . . . . . . . . . . 130, 142, 146, 163 OHP RX_NSA 0 STATE SO . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 130, 142, 146, 163 OHP RX_NSA_1 ALARM SO . . . . . . . . .. . . . . . . . . . . . . . . . . . . 142, 144, 146, 147 OHP RX_NSA_1 MASK SO . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 142, 144, 146, 147 OHP RX PM . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 OHP RX_PM SO . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 134, 146 OHP_RX_POST_B2MON_DIS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 OHP_RX_POST_CVL_L_PM . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .174 OHP_RX_POST_CVL_L_PM_SO . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 OHP_RX_POST_CVL_U_PM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 OHP_RX_POST_CVL_UPMSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 OHP_RX_PRBS_BER . ._ . . . . ._. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 170 OHP_RX_PRBS_BER_SO . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 OHP_RX_PRE_B2MON_DIS . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 OHP_RX_PRE_CVL_L_PM . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 OHP_RX_PRE_CVL_L_PM_SO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 OHP_RX_PRE_CVL_U_PM . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 OHP RX PRE_CVL_U_PM_SO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .135 OHP RX_PROV SO . . . 130, 132, 139, 140, 141, 1 46, 162, 163, 164, 166 OHP_RX_REI_L_PM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 174 OHP_RX_REI_L_PM_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 148 OHP_RX_REI_U_PM . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .174 OHP RX REI_U_PM SO . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .148 OHP RX_SA ALARM SO . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 134, 138 OHP RX_SA MASK SO . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 134, 138 OHP RX_SA PERSIST SO . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 134, 138 OHP RX_SA STATE SO . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 134, 138 OHP_RX_SCRM_DIS. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 165 OHP_RX_SDSF_CLR4 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 OHP_RX_SDSF_DT3 . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 OHP RX_SDSF_SET3 . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .138 OHP TX AIS RDI .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 115,117 OHP_TX_AIS_RDI_SO . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 158 OHP_TX_B2_BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 155 OHP_TX_B2MON_DIS . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 OHP_TX_CVL_L_PM . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .174 OHP_TX_CVL_L_PM_SO . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 OHP_TX_CVL_U_PM . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 OHP TX CVS_PM . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 174 OHP TX F1S1BYTE SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .154, 158 OHP_TX_JOBYTEO_SO . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 153 OHP_TX_JOBYTE31SO _ . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 153 OHP_TX_K1 K2 . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 117 OHP TX K1 K2BYTE SO . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 158 OHP TX LOH PROC DIS . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 150, 151, 158, 159 Agere Systems Inc. Object Page OHP_TX_Ml CORRUPT_ SO . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 OHP TX MAINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 OHP TX MAINT SO . . . . . . . . . . . . . . . . . . . .150, 152, 153, 154, 157, 158, 159 OHP TX NSA ALARM-SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .134 OHP TX NSA MASK-SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 OH_TX_NSA_PERSIST-SO P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 OHP_TX_NSASTATE -SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 OHP_TX_PM . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .174 OHP TX PM_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 OHP TX PROV SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150, 151, 152, 159, 162, 164 OHP TX SOH PROC DIS . . . . . . . . . . . .. . . . . . . . . . . . .150, 152, 153, 154, 155 OTUk AIS RxL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 OTUk AIS TxL . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..47 OTUk IAE TxL . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .46, 47 OTUkLCKRxL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 OTUk OCI RxL . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .50 OTUk SF . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..45 OTUkSF TxL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46, 47 P PARITY . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .169 PM_CLK . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .173 PUMP_DN . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 PUMP UP . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..34 R R2TF_LB . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .185 RCLKLI . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..34 RCLKSI . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..34 RDW2TDW LB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61, 185 REF_CLK . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..34 REF_PHS . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..34 RES2TES LB . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .185 RS ALARM SO . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84, 93 RS_BER_SD . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .107 RS_BER_SF .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .107 RS ERR BITBLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..90 RS-MASK-2-SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84, 93 RS-PERSIST . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CNT_OT01_ERRBITO_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 RS_RX_CNT_OTO1_ERRBIT1_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 RS_RX_CNT_1 TOO_ERRBITO_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 RS_RX_CNT_1 TOO_ERRBIT1SO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 RS_RX_CNT_BERREP_SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 93 RS_RX_CNT_ERRBITO_SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .90 RS_RX_CNT_ERRBIT1_SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .90 RS_RX_CNT_ERRBLKO_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 RS_RX_CNT_ERRBLK1_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 RS_RX_CTL_BERCLRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CTL_BERCLR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CTL_BERCLR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CTL_BERCLR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CTL_BERCLR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CTL_BERCLR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CTL_BERCLR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..93 RS_RX_CTL_BERDTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 RS_RX_CTL_BERDT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 RS RX CTL BERDT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 199 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 List of Objects (continued) Object Page RS_RX_CTL_BERDT3 . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERDT4 . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERDT5 . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERDT6 . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERDT7 . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERSETO . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERSET1 . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERSET2 . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERSET3 . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERSET4 . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RX_CTL_BERSET5 . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS RX CTL BERSET6 . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS RX_CTL TOP SO . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88, 89, 90, 93 RS_RX_DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .89 RS_RX_DSCR . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .88 RS_RX_DSCR_7_16_POL . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .88 RS_RX_ERRO_1T00_BITCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RX_ERRO_BITCNT . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RX_ERR00_OT01_BITCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RX_ERR01_OT01-BITCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RX_ERR1_1T00_BITCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RX_ERR1_BITCNT . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RX_UNCO_BLKCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RX_UNC1_BLKCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .90 RS_RXBER_CLRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_CLR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_CLR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_CLR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_CLR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_CLR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_CLR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIMEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIME1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIME2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIME3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIME4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIME5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIME6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_DETTIME7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS RXBER_REPORT . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS RXBER SD DET . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .44, 66, 93 RS_RXBER_SD_DET_A . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS_RXBER_SD_DET_M . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS_RXBER_SD_DET_P . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS_RXBER_SD_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .93 RS_RXBER_SETO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_SET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_SET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_SET3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_SET4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS_RXBER_SET5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 93 RS RXBER SET6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS RXBER SF DET . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .44, 66, 93 RS_RXBER_SF_DET_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS_RXBER_SF_DET_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS_RXBER_SF_DET_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .93 RS RXBER_SF_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .93 RS STATE SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84,93 RS_TX_CTL_ERRCOL_SO . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . 84 RS_TX_CTL_ERRMSKO_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 84 RS_TX_CTL_ERRMSK1_SO .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 84 RS TX CTL ERRREPT SO . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .84 200 Object Page RS TX CTL ERRSKIP_SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 RS TX CTL TOP SO . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . 82, 83, 84 RS_TX_ENC. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 RS_TX_SCR . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 RS_TX_SCR716POL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 RS_TXERR ._ . ._ . . . ._. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 84 RS_TXERR_A . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 RS_TXERR_COL . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 RS_TXERR_M . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 84 RS_TXERR_REPEAT . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 84 RS_TXERR_SKIP . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 RS TXERR START . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 RS TXERRO MASK . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 RS_TXERR1MASK _ . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 RST_N . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 170 RSYS2TSYS_LB . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 185 RTOAC_CLKO_4 . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 161 RTOAC_DATAO_4 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 161 RTOACSYNCO4 _ _ . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 161 RW N . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169,170 RX A1A2 INH . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140,141 RX AIS L . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 RX AIS L A . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 134,139 RX_AIS_L_M . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 RX_AIS_L_P . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 134 RX_AISD_MODE . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 RX_B1BIP_MODE . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 RX_B1CALC_MODE . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 RX_B1CORRUPT_ENB . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 RX_BlCORRUPT_FRM_CNT . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 RX_B1MON_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 RX_B2CORRUPT_ENB . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 RX_B2CORRUPTFRMCNT _ _ . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 RX_CVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 132 RX_DESCR_MODE . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 RX_DW_ALM . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 RX ENH FRMG ENB . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 RX ENH FRMG INS . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 140,141 RX_F1_BYTE . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 RX F1_NDET . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 RX F1_NEW A . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 144 RX_F1_NEW_M . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 144 RX_FRM_MODE . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 rx-hw inseamais . . . . . . . . . . 140, 1 41, 142, 143, 144, 145, 146, 147, 148 RX_INCONSISTENT_APS . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 RX_INCONSISTENT_APS_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 RX_INCONSISTENT_APS_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 RX_INCONSISTENT_APSP _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 RX_JO_EXP_0 . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 142 RX_JO_EXP_31 . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RX JO MISMATCH . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RX JO MISMATCH A . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 139,142 RX JO MISMATCH M .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RXJOMISMATCH_P . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 142 RX JO MODE . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141,142 RX_JO_NEW_A . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RX JO NEW_M . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RX JO SUS 0 . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RX JO SU-31 S . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 RX JO TYPE . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 141,142 RX_K_VAL_LIMIT_SEL . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 146 RX K1 BYTE . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 146 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 with Strong/Weak FEC and Digital Wrapper List of Objects (continued) Object Page RX_K1_NEW_A . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_K1_NEW_M . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .146 RX_K1K2CH_MISMATCH . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .146 RX_K1 K2CH_MISMATCH_A . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_K1K2CH_MISMATCH_M . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .146 RX_K1 K2CH_M ISMATCH_P . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_K2_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_K2_NEW_A . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX K2_NEW M . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .146 RX_LINE AIS DIS . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 116,139 RX_LINE AIS_INS . . . . . . . . . . . . . . 116, 139, 140, 144, 145, 146, 147, 148 RX_LINE_AIS_PM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 134 RX_LINE_RDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_LINE_RDI_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_LINE_RDI_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_LINE_RDI_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX_LINE_RDIPM . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 146 RX LOC_A . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 139 RX_LOF . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .36, 130 RX_LOF A . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 130,139 RX_LOFAIS DIS .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 116, 130, 139 RX_LOF_M . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX_LOF_P . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX LOF_PM . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX_LOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 36,130 RX_LOS A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 130,139 RX_LOS_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX_LOS_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX_LOS_P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX_LOS_PM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX_LOS_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 130 RX_OHP_MODE . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 139 RX_POST_B2MON _ MODE . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 RX_POST_CVL_L . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .135 RX_POST_CVL_U .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 RX_POST_SD_BERSEL . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 137 RX_POST_SF_A . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 139 RX_POST_SF_BER_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX_PRBS_BER_CNT . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 RX_PRBS_ENB . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 RX_PRBS_INV . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .163 RX_PRBS_MODE . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 RX_PRBS_OOS . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 RX_PRBS_OOS_A . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 RX_PRBS_OOS_M . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .163 RX_PRBS_OOS_P . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 RX_PRBS_TYPE . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 163 RX_PRE_B2MONMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 RX_PRE_CVL_L . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 RX_PRE_CVL_U . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 135 RX_PRE_SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX PRE SD A . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX_PRE SD BER SEL . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 137,138 RX_PRE_SD_M . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX_PRE_SD_P . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX_PRE_SD_SF_BIPSEL . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX_PRE_SF . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .138 RX_PRE_SF_A . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX_PRE_SF_BER _SEL . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX_PRE_SF_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 RX PRE SF P . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 138 Agere Systems Inc. Object Page RX_REIL_L . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 RX_REIL_U . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 RX_RST_MON-SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 RX_RST_MON_Sl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 RX_RST_MON_S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 RX_RST_MON_S3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 RX_S1_BYTE BYTE . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .147 RX_S1_NDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 RX S1_ NEW A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 RX S1_ NEW M . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .147 RX SCR MODE . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 RX_SDH_MODE . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 RX_SDSF_CLR_LIMIT_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 RX_SDSF_DT_UNIT_3 . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 RX_SDSF_DT_VAL_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 RX SDSFSETLIMIT _ _ _3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 RX SEF . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36, 130 RXSEF A . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130, 139 RX SEF AIS DIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116, 130, 139 RX SEF M . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 RXSEF P . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 RX SEF_PM . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .130 RX SF AIS DIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116, 139 RXSON ALM . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .36 RX TDMX DIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 RX TIM L AIS DIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116, 139 RX_TMX_DIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 RX TOAC_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 RxL AIS BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 49, 50 RxL BERSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .44, 45, 46, 47, 51 RxL BER SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 45, 46, 47, 51 RxL BIP . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46, 48, 50 RxL FIX BYTE . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .47, 49, 50 RxL IAE . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..51 RxL LOC . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 45, 46, 47, 51 RxL LOF . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 45, 46, 47, 51 RxL LOS . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 45, 46, 47, 51 RxL OCI BYTE . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 49, 50 RxLOOF . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .44, 45, 46, 47, 51 RxL PM(TCMi) OCI/LCK/AIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 RxL PM STAT AIS . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .45, 46, 47, 49, 50, 51 RxL PMSTATLCK . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .47, 49, 50, 51 RxL PM STAT OCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 49, 50, 51 RxL SM_IAE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 RxL TCMi STAT AIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45, 46, 47, 49, 50, 51 RxL TCMi STAT LCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 49, 50, 51 RxL TCMi STAT OCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 49, 50, 51 RxES S OVRFLW . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .44, 51 RxS EUNDRFLW S . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 51 S SONFEC_RST_MON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 SONFEC RX BYP_DMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SONFEC RX_BYPASS SO . . . . . . . . .130, 132, 134, 135, 164, 165, 166 SONFECRX DMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SONFEC RX_MODE . . . . . . . . . . . . . . . . . . .130, 132, 134, 135, 139, 165, 166 SONFECRX_TP BYPASS . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .133, 165 SONFEC_RXBYPDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..30 SONFEC RXDATAI . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .30 201 AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface with Strong/Weak FEC and Digital Wrapper Operational Description July 2002 List of Objects (continued) Object Page SONFEC RXDATAO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SONFEC TX BYPASS SO . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .135, 150 SONFECTX DMUX . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SONFEC TX MODE . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .135, 150 SONFEC-TX78CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SONFEC_TXDATAI . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 30 SONFEC_TXDATAO . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 30 SYS_RX_DMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RX_DWFEC_CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RX_HS_CLKMUX . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RX_HSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RX_LS_CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RX_LSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RX_SONFEC_CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RX78CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_RXDATAO . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 30 SYS_TX_DWFEC_CLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS_TX_SONFECCLKMUX . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 SYS TXDATAI . . . . ._ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .30 T T2RF_LB . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .185 TA N . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169, 170, 171 TCLKLI . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 34 TCLKSI . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . 34 TDW2RDWLB _ . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .185 TEA N . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .20, 169, 171 TLINE2RLINE_LB . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .185 TRSEN2RRSDELB _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .185 TS-N . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169, 170 TX 20FRM RDI DIS . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .117, 158 TX A1A2 INH . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .151, 152 TX_A2_ERR_INS . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .152 TX_AIS_L_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 TX_B2MON_ MODE . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .135 TX_CVL_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 TX_CVL_U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 TX_DW ALM . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 TX ENH FRMG_INS . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .151, 152 TX-F1_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 TX F1 INS . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 tx-hw insert_ais . . . . . . . . . . . . . . . . . . .150, 151, 154, 155, 156, 157, 158, 159 tx_hw_insert_rdi . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .157 TX_INV PTR_INS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .156, 157 TX_JO_EXP_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 TX_JO_EXP_31 . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .153 TX-JO_INS . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .153 TX_K1_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 TX K1 K2_BYPASS . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .158 TX K2 BYTE . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .117, 158 TX-LINE AIS DIS . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .115, 149 TX LINE AI SINS . . . . . . . . . . . . . . .115, 150, 151, 155, 156, 157, 158, 159 TX-LINE_RDI . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .134 TX-LINE_RDI_A . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .134 TX-LINE_RDI_M . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .134 TX-LINE_RDI_P . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .134 TX LINE RDI_PM . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .134 TX LINE UNEQ_INS . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .156, 157 TX_LOC_A . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .149 TX_LOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .36 TX LOF A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 202 Object Page TX LOF AIS DIS . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 115,149 TX LOS . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 36 TX LOS_A . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 149 TX M1_INS . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 TX_M1CORRUPT_EN . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 TX_M1CORRUPT_ENB . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 TX M1CORRUPT _ FRM _ CNT . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 TX NDF_INS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156,157 TXOHP MODE . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150,153 TX PRBS ENB . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 156,164 TX_PRBS_INV . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 164 TX PRBS MODE . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 TX PRBS TYPE . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 163,164 TX RDI L SEL . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157,158 TX_RDI_L_SELECT . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 TX_RST_MON-SO . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TX_RST_MON_Sl . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TX_RST_MON_S2 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TX_RST_MONS3 _ . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TX-S1-BYTE . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .158 TX-S1-INS . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 TX_SDH_MODE . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 TX_SEF . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .36 TX SEF A . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 149 TX SEF AIS DIS . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 115,149 TX SON ALM . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TX TOAC ENB . . 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 162 TX TOAC MODE . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 162 TxLOC L . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . 44, 47, 51 TxL LOF . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . 44, 47, 51 TxL LOS . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 47, 51 TxLOOF . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . 44, 47, 51 TxLOC . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 TxS CF . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TxES S OVRFLW . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 44,51 TxS EUNDRFLW S . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44,51 V V10G_MODE N . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 VAR_CLK . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .34 VAR PHS . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Agere Systems Inc. AdLib OCR Evaluation TFEC041OG 2.5/10 Gbits/s Optical Networking Interface Operational Description July 2002 47 with Strong/Weak FEC and Digital Wrapper Ordering Information Device Code TFEC041OG-3PBGA2 Agere Systems Inc. Package I 792-Pin PBGAM1TH Temperature I -40 C to 85 C Comcode (Ordering Number) I 700012029 203 AdLib OCR Evaluation Intel is a registered trademark of Intel Corporation . Motorola is a registered trademark of Motorola, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http ://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc ., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA : Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-2588112 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN : (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc . reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application . Agere, Agere Systems, and the Agere Logo are trademarks of Agere Systems Inc. Copyright (c) 2002 Agere Systems Inc . All Rights Reserved July 2002 DS02-232SONT a 'ere s 8 y tems s